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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include <linux/string.h>
29#include <linux/bitops.h>
30#include <drm/drmP.h>
31#include <drm/i915_drm.h>
32#include "i915_drv.h"
33
34/**
35 * DOC: buffer object tiling
36 *
37 * i915_gem_set_tiling() and i915_gem_get_tiling() is the userspace interface to
38 * declare fence register requirements.
39 *
40 * In principle GEM doesn't care at all about the internal data layout of an
41 * object, and hence it also doesn't care about tiling or swizzling. There's two
42 * exceptions:
43 *
44 * - For X and Y tiling the hardware provides detilers for CPU access, so called
45 * fences. Since there's only a limited amount of them the kernel must manage
46 * these, and therefore userspace must tell the kernel the object tiling if it
47 * wants to use fences for detiling.
48 * - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which
49 * depends upon the physical page frame number. When swapping such objects the
50 * page frame number might change and the kernel must be able to fix this up
51 * and hence now the tiling. Note that on a subset of platforms with
52 * asymmetric memory channel population the swizzling pattern changes in an
53 * unknown way, and for those the kernel simply forbids swapping completely.
54 *
55 * Since neither of this applies for new tiling layouts on modern platforms like
56 * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
57 * Anything else can be handled in userspace entirely without the kernel's
58 * invovlement.
59 */
60
61/* Check pitch constriants for all chips & tiling formats */
62static bool
63i915_tiling_ok(struct drm_i915_private *dev_priv,
64 int stride, int size, int tiling_mode)
65{
66 int tile_width;
67
68 /* Linear is always fine */
69 if (tiling_mode == I915_TILING_NONE)
70 return true;
71
72 if (tiling_mode > I915_TILING_LAST)
73 return false;
74
75 if (IS_GEN2(dev_priv) ||
76 (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev_priv)))
77 tile_width = 128;
78 else
79 tile_width = 512;
80
81 /* check maximum stride & object size */
82 /* i965+ stores the end address of the gtt mapping in the fence
83 * reg, so dont bother to check the size */
84 if (INTEL_GEN(dev_priv) >= 7) {
85 if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
86 return false;
87 } else if (INTEL_GEN(dev_priv) >= 4) {
88 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
89 return false;
90 } else {
91 if (stride > 8192)
92 return false;
93
94 if (IS_GEN3(dev_priv)) {
95 if (size > I830_FENCE_MAX_SIZE_VAL << 20)
96 return false;
97 } else {
98 if (size > I830_FENCE_MAX_SIZE_VAL << 19)
99 return false;
100 }
101 }
102
103 if (stride < tile_width)
104 return false;
105
106 /* 965+ just needs multiples of tile width */
107 if (INTEL_GEN(dev_priv) >= 4) {
108 if (stride & (tile_width - 1))
109 return false;
110 return true;
111 }
112
113 /* Pre-965 needs power of two tile widths */
114 if (stride & (stride - 1))
115 return false;
116
117 return true;
118}
119
120static bool i915_vma_fence_prepare(struct i915_vma *vma, int tiling_mode)
121{
122 struct drm_i915_private *dev_priv = to_i915(vma->vm->dev);
123 u32 size;
124
125 if (!i915_vma_is_map_and_fenceable(vma))
126 return true;
127
128 if (INTEL_GEN(dev_priv) == 3) {
129 if (vma->node.start & ~I915_FENCE_START_MASK)
130 return false;
131 } else {
132 if (vma->node.start & ~I830_FENCE_START_MASK)
133 return false;
134 }
135
136 size = i915_gem_get_ggtt_size(dev_priv, vma->size, tiling_mode);
137 if (vma->node.size < size)
138 return false;
139
140 if (vma->node.start & (size - 1))
141 return false;
142
143 return true;
144}
145
146/* Make the current GTT allocation valid for the change in tiling. */
147static int
148i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj, int tiling_mode)
149{
150 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
151 struct i915_vma *vma;
152 int ret;
153
154 if (tiling_mode == I915_TILING_NONE)
155 return 0;
156
157 if (INTEL_GEN(dev_priv) >= 4)
158 return 0;
159
160 list_for_each_entry(vma, &obj->vma_list, obj_link) {
161 if (i915_vma_fence_prepare(vma, tiling_mode))
162 continue;
163
164 ret = i915_vma_unbind(vma);
165 if (ret)
166 return ret;
167 }
168
169 return 0;
170}
171
172/**
173 * i915_gem_set_tiling - IOCTL handler to set tiling mode
174 * @dev: DRM device
175 * @data: data pointer for the ioctl
176 * @file: DRM file for the ioctl call
177 *
178 * Sets the tiling mode of an object, returning the required swizzling of
179 * bit 6 of addresses in the object.
180 *
181 * Called by the user via ioctl.
182 *
183 * Returns:
184 * Zero on success, negative errno on failure.
185 */
186int
187i915_gem_set_tiling(struct drm_device *dev, void *data,
188 struct drm_file *file)
189{
190 struct drm_i915_gem_set_tiling *args = data;
191 struct drm_i915_private *dev_priv = to_i915(dev);
192 struct drm_i915_gem_object *obj;
193 int err = 0;
194
195 /* Make sure we don't cross-contaminate obj->tiling_and_stride */
196 BUILD_BUG_ON(I915_TILING_LAST & STRIDE_MASK);
197
198 obj = i915_gem_object_lookup(file, args->handle);
199 if (!obj)
200 return -ENOENT;
201
202 if (!i915_tiling_ok(dev_priv,
203 args->stride, obj->base.size, args->tiling_mode)) {
204 i915_gem_object_put(obj);
205 return -EINVAL;
206 }
207
208 mutex_lock(&dev->struct_mutex);
209 if (obj->pin_display || obj->framebuffer_references) {
210 err = -EBUSY;
211 goto err;
212 }
213
214 if (args->tiling_mode == I915_TILING_NONE) {
215 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
216 args->stride = 0;
217 } else {
218 if (args->tiling_mode == I915_TILING_X)
219 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
220 else
221 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
222
223 /* Hide bit 17 swizzling from the user. This prevents old Mesa
224 * from aborting the application on sw fallbacks to bit 17,
225 * and we use the pread/pwrite bit17 paths to swizzle for it.
226 * If there was a user that was relying on the swizzle
227 * information for drm_intel_bo_map()ed reads/writes this would
228 * break it, but we don't have any of those.
229 */
230 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
231 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
232 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
233 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
234
235 /* If we can't handle the swizzling, make it untiled. */
236 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
237 args->tiling_mode = I915_TILING_NONE;
238 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
239 args->stride = 0;
240 }
241 }
242
243 if (args->tiling_mode != i915_gem_object_get_tiling(obj) ||
244 args->stride != i915_gem_object_get_stride(obj)) {
245 /* We need to rebind the object if its current allocation
246 * no longer meets the alignment restrictions for its new
247 * tiling mode. Otherwise we can just leave it alone, but
248 * need to ensure that any fence register is updated before
249 * the next fenced (either through the GTT or by the BLT unit
250 * on older GPUs) access.
251 *
252 * After updating the tiling parameters, we then flag whether
253 * we need to update an associated fence register. Note this
254 * has to also include the unfenced register the GPU uses
255 * whilst executing a fenced command for an untiled object.
256 */
257
258 err = i915_gem_object_fence_prepare(obj, args->tiling_mode);
259 if (!err) {
260 struct i915_vma *vma;
261
262 mutex_lock(&obj->mm.lock);
263 if (obj->mm.pages &&
264 obj->mm.madv == I915_MADV_WILLNEED &&
265 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
266 if (args->tiling_mode == I915_TILING_NONE) {
267 GEM_BUG_ON(!obj->mm.quirked);
268 __i915_gem_object_unpin_pages(obj);
269 obj->mm.quirked = false;
270 }
271 if (!i915_gem_object_is_tiled(obj)) {
272 GEM_BUG_ON(!obj->mm.quirked);
273 __i915_gem_object_pin_pages(obj);
274 obj->mm.quirked = true;
275 }
276 }
277 mutex_unlock(&obj->mm.lock);
278
279 list_for_each_entry(vma, &obj->vma_list, obj_link) {
280 if (!vma->fence)
281 continue;
282
283 vma->fence->dirty = true;
284 }
285 obj->tiling_and_stride =
286 args->stride | args->tiling_mode;
287
288 /* Force the fence to be reacquired for GTT access */
289 i915_gem_release_mmap(obj);
290 }
291 }
292 /* we have to maintain this existing ABI... */
293 args->stride = i915_gem_object_get_stride(obj);
294 args->tiling_mode = i915_gem_object_get_tiling(obj);
295
296 /* Try to preallocate memory required to save swizzling on put-pages */
297 if (i915_gem_object_needs_bit17_swizzle(obj)) {
298 if (obj->bit_17 == NULL) {
299 obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
300 sizeof(long), GFP_KERNEL);
301 }
302 } else {
303 kfree(obj->bit_17);
304 obj->bit_17 = NULL;
305 }
306
307err:
308 i915_gem_object_put(obj);
309 mutex_unlock(&dev->struct_mutex);
310
311 return err;
312}
313
314/**
315 * i915_gem_get_tiling - IOCTL handler to get tiling mode
316 * @dev: DRM device
317 * @data: data pointer for the ioctl
318 * @file: DRM file for the ioctl call
319 *
320 * Returns the current tiling mode and required bit 6 swizzling for the object.
321 *
322 * Called by the user via ioctl.
323 *
324 * Returns:
325 * Zero on success, negative errno on failure.
326 */
327int
328i915_gem_get_tiling(struct drm_device *dev, void *data,
329 struct drm_file *file)
330{
331 struct drm_i915_gem_get_tiling *args = data;
332 struct drm_i915_private *dev_priv = to_i915(dev);
333 struct drm_i915_gem_object *obj;
334 int err = -ENOENT;
335
336 rcu_read_lock();
337 obj = i915_gem_object_lookup_rcu(file, args->handle);
338 if (obj) {
339 args->tiling_mode =
340 READ_ONCE(obj->tiling_and_stride) & TILING_MASK;
341 err = 0;
342 }
343 rcu_read_unlock();
344 if (unlikely(err))
345 return err;
346
347 switch (args->tiling_mode) {
348 case I915_TILING_X:
349 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
350 break;
351 case I915_TILING_Y:
352 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
353 break;
354 default:
355 case I915_TILING_NONE:
356 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
357 break;
358 }
359
360 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
361 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
362 args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
363 else
364 args->phys_swizzle_mode = args->swizzle_mode;
365 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
366 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
367 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
368 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
369
370 return 0;
371}