1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2 */
   3/*
   4 *
   5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6 * All Rights Reserved.
   7 *
   8 * Permission is hereby granted, free of charge, to any person obtaining a
   9 * copy of this software and associated documentation files (the
  10 * "Software"), to deal in the Software without restriction, including
  11 * without limitation the rights to use, copy, modify, merge, publish,
  12 * distribute, sub license, and/or sell copies of the Software, and to
  13 * permit persons to whom the Software is furnished to do so, subject to
  14 * the following conditions:
  15 *
  16 * The above copyright notice and this permission notice (including the
  17 * next paragraph) shall be included in all copies or substantial portions
  18 * of the Software.
  19 *
  20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27 *
  28 */
  29
  30#include <linux/acpi.h>
  31#include <linux/device.h>
  32#include <linux/oom.h>
  33#include <linux/module.h>
  34#include <linux/pci.h>
  35#include <linux/pm.h>
  36#include <linux/pm_runtime.h>
  37#include <linux/pnp.h>
  38#include <linux/slab.h>
  39#include <linux/vgaarb.h>
  40#include <linux/vga_switcheroo.h>
  41#include <linux/vt.h>
  42#include <acpi/video.h>
  43
  44#include <drm/drmP.h>
  45#include <drm/drm_crtc_helper.h>
  46#include <drm/i915_drm.h>
  47
  48#include "i915_drv.h"
  49#include "i915_trace.h"
  50#include "i915_vgpu.h"
  51#include "intel_drv.h"
  52
  53static struct drm_driver driver;
  54
  55static unsigned int i915_load_fail_count;
  56
  57bool __i915_inject_load_failure(const char *func, int line)
  58{
  59	if (i915_load_fail_count >= i915.inject_load_failure)
  60		return false;
  61
  62	if (++i915_load_fail_count == i915.inject_load_failure) {
  63		DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  64			 i915.inject_load_failure, func, line);
  65		return true;
  66	}
  67
  68	return false;
  69}
  70
  71#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  72#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  73		    "providing the dmesg log by booting with drm.debug=0xf"
  74
  75void
  76__i915_printk(struct drm_i915_private *dev_priv, const char *level,
  77	      const char *fmt, ...)
  78{
  79	static bool shown_bug_once;
  80	struct device *kdev = dev_priv->drm.dev;
  81	bool is_error = level[1] <= KERN_ERR[1];
  82	bool is_debug = level[1] == KERN_DEBUG[1];
  83	struct va_format vaf;
  84	va_list args;
  85
  86	if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  87		return;
  88
  89	va_start(args, fmt);
  90
  91	vaf.fmt = fmt;
  92	vaf.va = &args;
  93
  94	dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
  95		   __builtin_return_address(0), &vaf);
  96
  97	if (is_error && !shown_bug_once) {
  98		dev_notice(kdev, "%s", FDO_BUG_MSG);
  99		shown_bug_once = true;
 100	}
 101
 102	va_end(args);
 103}
 104
 105static bool i915_error_injected(struct drm_i915_private *dev_priv)
 106{
 107	return i915.inject_load_failure &&
 108	       i915_load_fail_count == i915.inject_load_failure;
 109}
 110
 111#define i915_load_error(dev_priv, fmt, ...)				     \
 112	__i915_printk(dev_priv,						     \
 113		      i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 114		      fmt, ##__VA_ARGS__)
 115
 116
 117static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 118{
 119	enum intel_pch ret = PCH_NOP;
 120
 121	/*
 122	 * In a virtualized passthrough environment we can be in a
 123	 * setup where the ISA bridge is not able to be passed through.
 124	 * In this case, a south bridge can be emulated and we have to
 125	 * make an educated guess as to which PCH is really there.
 126	 */
 127
 128	if (IS_GEN5(dev_priv)) {
 129		ret = PCH_IBX;
 130		DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 131	} else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
 132		ret = PCH_CPT;
 133		DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 134	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 135		ret = PCH_LPT;
 136		DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 137	} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 138		ret = PCH_SPT;
 139		DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 140	}
 141
 142	return ret;
 143}
 144
 145static void intel_detect_pch(struct drm_device *dev)
 146{
 147	struct drm_i915_private *dev_priv = to_i915(dev);
 148	struct pci_dev *pch = NULL;
 149
 150	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 151	 * (which really amounts to a PCH but no South Display).
 152	 */
 153	if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 154		dev_priv->pch_type = PCH_NOP;
 155		return;
 156	}
 157
 158	/*
 159	 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 160	 * make graphics device passthrough work easy for VMM, that only
 161	 * need to expose ISA bridge to let driver know the real hardware
 162	 * underneath. This is a requirement from virtualization team.
 163	 *
 164	 * In some virtualized environments (e.g. XEN), there is irrelevant
 165	 * ISA bridge in the system. To work reliably, we should scan trhough
 166	 * all the ISA bridge devices and check for the first match, instead
 167	 * of only checking the first one.
 168	 */
 169	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 170		if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 171			unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 172			dev_priv->pch_id = id;
 173
 174			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 175				dev_priv->pch_type = PCH_IBX;
 176				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 177				WARN_ON(!IS_GEN5(dev_priv));
 178			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 179				dev_priv->pch_type = PCH_CPT;
 180				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 181				WARN_ON(!(IS_GEN6(dev_priv) ||
 182					IS_IVYBRIDGE(dev_priv)));
 183			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 184				/* PantherPoint is CPT compatible */
 185				dev_priv->pch_type = PCH_CPT;
 186				DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 187				WARN_ON(!(IS_GEN6(dev_priv) ||
 188					IS_IVYBRIDGE(dev_priv)));
 189			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 190				dev_priv->pch_type = PCH_LPT;
 191				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 192				WARN_ON(!IS_HASWELL(dev_priv) &&
 193					!IS_BROADWELL(dev_priv));
 194				WARN_ON(IS_HSW_ULT(dev_priv) ||
 195					IS_BDW_ULT(dev_priv));
 196			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 197				dev_priv->pch_type = PCH_LPT;
 198				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 199				WARN_ON(!IS_HASWELL(dev_priv) &&
 200					!IS_BROADWELL(dev_priv));
 201				WARN_ON(!IS_HSW_ULT(dev_priv) &&
 202					!IS_BDW_ULT(dev_priv));
 203			} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 204				dev_priv->pch_type = PCH_SPT;
 205				DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 206				WARN_ON(!IS_SKYLAKE(dev_priv) &&
 207					!IS_KABYLAKE(dev_priv));
 208			} else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 209				dev_priv->pch_type = PCH_SPT;
 210				DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 211				WARN_ON(!IS_SKYLAKE(dev_priv) &&
 212					!IS_KABYLAKE(dev_priv));
 213			} else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 214				dev_priv->pch_type = PCH_KBP;
 215				DRM_DEBUG_KMS("Found KabyPoint PCH\n");
 216				WARN_ON(!IS_SKYLAKE(dev_priv) &&
 217					!IS_KABYLAKE(dev_priv));
 218			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 219				   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 220				   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 221				    pch->subsystem_vendor ==
 222					    PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 223				    pch->subsystem_device ==
 224					    PCI_SUBDEVICE_ID_QEMU)) {
 225				dev_priv->pch_type =
 226					intel_virt_detect_pch(dev_priv);
 227			} else
 228				continue;
 229
 230			break;
 231		}
 232	}
 233	if (!pch)
 234		DRM_DEBUG_KMS("No PCH found.\n");
 235
 236	pci_dev_put(pch);
 237}
 238
 239static int i915_getparam(struct drm_device *dev, void *data,
 240			 struct drm_file *file_priv)
 241{
 242	struct drm_i915_private *dev_priv = to_i915(dev);
 243	struct pci_dev *pdev = dev_priv->drm.pdev;
 244	drm_i915_getparam_t *param = data;
 245	int value;
 246
 247	switch (param->param) {
 248	case I915_PARAM_IRQ_ACTIVE:
 249	case I915_PARAM_ALLOW_BATCHBUFFER:
 250	case I915_PARAM_LAST_DISPATCH:
 251	case I915_PARAM_HAS_EXEC_CONSTANTS:
 252		/* Reject all old ums/dri params. */
 253		return -ENODEV;
 254	case I915_PARAM_CHIPSET_ID:
 255		value = pdev->device;
 256		break;
 257	case I915_PARAM_REVISION:
 258		value = pdev->revision;
 259		break;
 260	case I915_PARAM_NUM_FENCES_AVAIL:
 261		value = dev_priv->num_fence_regs;
 262		break;
 263	case I915_PARAM_HAS_OVERLAY:
 264		value = dev_priv->overlay ? 1 : 0;
 265		break;
 266	case I915_PARAM_HAS_BSD:
 267		value = !!dev_priv->engine[VCS];
 268		break;
 269	case I915_PARAM_HAS_BLT:
 270		value = !!dev_priv->engine[BCS];
 271		break;
 272	case I915_PARAM_HAS_VEBOX:
 273		value = !!dev_priv->engine[VECS];
 274		break;
 275	case I915_PARAM_HAS_BSD2:
 276		value = !!dev_priv->engine[VCS2];
 277		break;
 278	case I915_PARAM_HAS_LLC:
 279		value = HAS_LLC(dev_priv);
 280		break;
 281	case I915_PARAM_HAS_WT:
 282		value = HAS_WT(dev_priv);
 283		break;
 284	case I915_PARAM_HAS_ALIASING_PPGTT:
 285		value = USES_PPGTT(dev_priv);
 286		break;
 287	case I915_PARAM_HAS_SEMAPHORES:
 288		value = i915.semaphores;
 289		break;
 290	case I915_PARAM_HAS_SECURE_BATCHES:
 291		value = capable(CAP_SYS_ADMIN);
 292		break;
 293	case I915_PARAM_CMD_PARSER_VERSION:
 294		value = i915_cmd_parser_get_version(dev_priv);
 295		break;
 296	case I915_PARAM_SUBSLICE_TOTAL:
 297		value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 298		if (!value)
 299			return -ENODEV;
 300		break;
 301	case I915_PARAM_EU_TOTAL:
 302		value = INTEL_INFO(dev_priv)->sseu.eu_total;
 303		if (!value)
 304			return -ENODEV;
 305		break;
 306	case I915_PARAM_HAS_GPU_RESET:
 307		value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 308		break;
 309	case I915_PARAM_HAS_RESOURCE_STREAMER:
 310		value = HAS_RESOURCE_STREAMER(dev_priv);
 311		break;
 312	case I915_PARAM_HAS_POOLED_EU:
 313		value = HAS_POOLED_EU(dev_priv);
 314		break;
 315	case I915_PARAM_MIN_EU_IN_POOL:
 316		value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 317		break;
 318	case I915_PARAM_MMAP_GTT_VERSION:
 319		/* Though we've started our numbering from 1, and so class all
 320		 * earlier versions as 0, in effect their value is undefined as
 321		 * the ioctl will report EINVAL for the unknown param!
 322		 */
 323		value = i915_gem_mmap_gtt_version();
 324		break;
 325	case I915_PARAM_HAS_SCHEDULER:
 326		value = dev_priv->engine[RCS] &&
 327			dev_priv->engine[RCS]->schedule;
 328		break;
 329	case I915_PARAM_MMAP_VERSION:
 330		/* Remember to bump this if the version changes! */
 331	case I915_PARAM_HAS_GEM:
 332	case I915_PARAM_HAS_PAGEFLIPPING:
 333	case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 334	case I915_PARAM_HAS_RELAXED_FENCING:
 335	case I915_PARAM_HAS_COHERENT_RINGS:
 336	case I915_PARAM_HAS_RELAXED_DELTA:
 337	case I915_PARAM_HAS_GEN7_SOL_RESET:
 338	case I915_PARAM_HAS_WAIT_TIMEOUT:
 339	case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 340	case I915_PARAM_HAS_PINNED_BATCHES:
 341	case I915_PARAM_HAS_EXEC_NO_RELOC:
 342	case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 343	case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 344	case I915_PARAM_HAS_EXEC_SOFTPIN:
 345		/* For the time being all of these are always true;
 346		 * if some supported hardware does not have one of these
 347		 * features this value needs to be provided from
 348		 * INTEL_INFO(), a feature macro, or similar.
 349		 */
 350		value = 1;
 351		break;
 352	default:
 353		DRM_DEBUG("Unknown parameter %d\n", param->param);
 354		return -EINVAL;
 355	}
 356
 357	if (put_user(value, param->value))
 358		return -EFAULT;
 359
 360	return 0;
 361}
 362
 363static int i915_get_bridge_dev(struct drm_device *dev)
 364{
 365	struct drm_i915_private *dev_priv = to_i915(dev);
 366
 367	dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 368	if (!dev_priv->bridge_dev) {
 369		DRM_ERROR("bridge device not found\n");
 370		return -1;
 371	}
 372	return 0;
 373}
 374
 375/* Allocate space for the MCH regs if needed, return nonzero on error */
 376static int
 377intel_alloc_mchbar_resource(struct drm_device *dev)
 378{
 379	struct drm_i915_private *dev_priv = to_i915(dev);
 380	int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 381	u32 temp_lo, temp_hi = 0;
 382	u64 mchbar_addr;
 383	int ret;
 384
 385	if (INTEL_GEN(dev_priv) >= 4)
 386		pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 387	pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 388	mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 389
 390	/* If ACPI doesn't have it, assume we need to allocate it ourselves */
 391#ifdef CONFIG_PNP
 392	if (mchbar_addr &&
 393	    pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 394		return 0;
 395#endif
 396
 397	/* Get some space for it */
 398	dev_priv->mch_res.name = "i915 MCHBAR";
 399	dev_priv->mch_res.flags = IORESOURCE_MEM;
 400	ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 401				     &dev_priv->mch_res,
 402				     MCHBAR_SIZE, MCHBAR_SIZE,
 403				     PCIBIOS_MIN_MEM,
 404				     0, pcibios_align_resource,
 405				     dev_priv->bridge_dev);
 406	if (ret) {
 407		DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 408		dev_priv->mch_res.start = 0;
 409		return ret;
 410	}
 411
 412	if (INTEL_GEN(dev_priv) >= 4)
 413		pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 414				       upper_32_bits(dev_priv->mch_res.start));
 415
 416	pci_write_config_dword(dev_priv->bridge_dev, reg,
 417			       lower_32_bits(dev_priv->mch_res.start));
 418	return 0;
 419}
 420
 421/* Setup MCHBAR if possible, return true if we should disable it again */
 422static void
 423intel_setup_mchbar(struct drm_device *dev)
 424{
 425	struct drm_i915_private *dev_priv = to_i915(dev);
 426	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 427	u32 temp;
 428	bool enabled;
 429
 430	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 431		return;
 432
 433	dev_priv->mchbar_need_disable = false;
 434
 435	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 436		pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 437		enabled = !!(temp & DEVEN_MCHBAR_EN);
 438	} else {
 439		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 440		enabled = temp & 1;
 441	}
 442
 443	/* If it's already enabled, don't have to do anything */
 444	if (enabled)
 445		return;
 446
 447	if (intel_alloc_mchbar_resource(dev))
 448		return;
 449
 450	dev_priv->mchbar_need_disable = true;
 451
 452	/* Space is allocated or reserved, so enable it. */
 453	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 454		pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 455				       temp | DEVEN_MCHBAR_EN);
 456	} else {
 457		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 458		pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 459	}
 460}
 461
 462static void
 463intel_teardown_mchbar(struct drm_device *dev)
 464{
 465	struct drm_i915_private *dev_priv = to_i915(dev);
 466	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 467
 468	if (dev_priv->mchbar_need_disable) {
 469		if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 470			u32 deven_val;
 471
 472			pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 473					      &deven_val);
 474			deven_val &= ~DEVEN_MCHBAR_EN;
 475			pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 476					       deven_val);
 477		} else {
 478			u32 mchbar_val;
 479
 480			pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 481					      &mchbar_val);
 482			mchbar_val &= ~1;
 483			pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 484					       mchbar_val);
 485		}
 486	}
 487
 488	if (dev_priv->mch_res.start)
 489		release_resource(&dev_priv->mch_res);
 490}
 491
 492/* true = enable decode, false = disable decoder */
 493static unsigned int i915_vga_set_decode(void *cookie, bool state)
 494{
 495	struct drm_device *dev = cookie;
 496
 497	intel_modeset_vga_set_state(to_i915(dev), state);
 498	if (state)
 499		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 500		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 501	else
 502		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 503}
 504
 505static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 506{
 507	struct drm_device *dev = pci_get_drvdata(pdev);
 508	pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 509
 510	if (state == VGA_SWITCHEROO_ON) {
 511		pr_info("switched on\n");
 512		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 513		/* i915 resume handler doesn't set to D0 */
 514		pci_set_power_state(pdev, PCI_D0);
 515		i915_resume_switcheroo(dev);
 516		dev->switch_power_state = DRM_SWITCH_POWER_ON;
 517	} else {
 518		pr_info("switched off\n");
 519		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 520		i915_suspend_switcheroo(dev, pmm);
 521		dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 522	}
 523}
 524
 525static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 526{
 527	struct drm_device *dev = pci_get_drvdata(pdev);
 528
 529	/*
 530	 * FIXME: open_count is protected by drm_global_mutex but that would lead to
 531	 * locking inversion with the driver load path. And the access here is
 532	 * completely racy anyway. So don't bother with locking for now.
 533	 */
 534	return dev->open_count == 0;
 535}
 536
 537static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 538	.set_gpu_state = i915_switcheroo_set_state,
 539	.reprobe = NULL,
 540	.can_switch = i915_switcheroo_can_switch,
 541};
 542
 543static void i915_gem_fini(struct drm_i915_private *dev_priv)
 544{
 545	mutex_lock(&dev_priv->drm.struct_mutex);
 546	i915_gem_cleanup_engines(&dev_priv->drm);
 547	i915_gem_context_fini(&dev_priv->drm);
 548	mutex_unlock(&dev_priv->drm.struct_mutex);
 549
 550	rcu_barrier();
 551	flush_work(&dev_priv->mm.free_work);
 552
 553	WARN_ON(!list_empty(&dev_priv->context_list));
 554}
 555
 556static int i915_load_modeset_init(struct drm_device *dev)
 557{
 558	struct drm_i915_private *dev_priv = to_i915(dev);
 559	struct pci_dev *pdev = dev_priv->drm.pdev;
 560	int ret;
 561
 562	if (i915_inject_load_failure())
 563		return -ENODEV;
 564
 565	ret = intel_bios_init(dev_priv);
 566	if (ret)
 567		DRM_INFO("failed to find VBIOS tables\n");
 568
 569	/* If we have > 1 VGA cards, then we need to arbitrate access
 570	 * to the common VGA resources.
 571	 *
 572	 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 573	 * then we do not take part in VGA arbitration and the
 574	 * vga_client_register() fails with -ENODEV.
 575	 */
 576	ret = vga_client_register(pdev, dev, NULL, i915_vga_set_decode);
 577	if (ret && ret != -ENODEV)
 578		goto out;
 579
 580	intel_register_dsm_handler();
 581
 582	ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 583	if (ret)
 584		goto cleanup_vga_client;
 585
 586	/* must happen before intel_power_domains_init_hw() on VLV/CHV */
 587	intel_update_rawclk(dev_priv);
 588
 589	intel_power_domains_init_hw(dev_priv, false);
 590
 591	intel_csr_ucode_init(dev_priv);
 592
 593	ret = intel_irq_install(dev_priv);
 594	if (ret)
 595		goto cleanup_csr;
 596
 597	intel_setup_gmbus(dev);
 598
 599	/* Important: The output setup functions called by modeset_init need
 600	 * working irqs for e.g. gmbus and dp aux transfers. */
 601	ret = intel_modeset_init(dev);
 602	if (ret)
 603		goto cleanup_irq;
 604
 605	intel_guc_init(dev);
 606
 607	ret = i915_gem_init(dev);
 608	if (ret)
 609		goto cleanup_irq;
 610
 611	intel_modeset_gem_init(dev);
 612
 613	if (INTEL_INFO(dev_priv)->num_pipes == 0)
 614		return 0;
 615
 616	ret = intel_fbdev_init(dev);
 617	if (ret)
 618		goto cleanup_gem;
 619
 620	/* Only enable hotplug handling once the fbdev is fully set up. */
 621	intel_hpd_init(dev_priv);
 622
 623	drm_kms_helper_poll_init(dev);
 624
 625	return 0;
 626
 627cleanup_gem:
 628	if (i915_gem_suspend(dev))
 629		DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 630	i915_gem_fini(dev_priv);
 631cleanup_irq:
 632	intel_guc_fini(dev);
 633	drm_irq_uninstall(dev);
 634	intel_teardown_gmbus(dev);
 635cleanup_csr:
 636	intel_csr_ucode_fini(dev_priv);
 637	intel_power_domains_fini(dev_priv);
 638	vga_switcheroo_unregister_client(pdev);
 639cleanup_vga_client:
 640	vga_client_register(pdev, NULL, NULL, NULL);
 641out:
 642	return ret;
 643}
 644
 645#if IS_ENABLED(CONFIG_FB)
 646static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 647{
 648	struct apertures_struct *ap;
 649	struct pci_dev *pdev = dev_priv->drm.pdev;
 650	struct i915_ggtt *ggtt = &dev_priv->ggtt;
 651	bool primary;
 652	int ret;
 653
 654	ap = alloc_apertures(1);
 655	if (!ap)
 656		return -ENOMEM;
 657
 658	ap->ranges[0].base = ggtt->mappable_base;
 659	ap->ranges[0].size = ggtt->mappable_end;
 660
 661	primary =
 662		pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 663
 664	ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 665
 666	kfree(ap);
 667
 668	return ret;
 669}
 670#else
 671static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 672{
 673	return 0;
 674}
 675#endif
 676
 677#if !defined(CONFIG_VGA_CONSOLE)
 678static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 679{
 680	return 0;
 681}
 682#elif !defined(CONFIG_DUMMY_CONSOLE)
 683static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 684{
 685	return -ENODEV;
 686}
 687#else
 688static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 689{
 690	int ret = 0;
 691
 692	DRM_INFO("Replacing VGA console driver\n");
 693
 694	console_lock();
 695	if (con_is_bound(&vga_con))
 696		ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 697	if (ret == 0) {
 698		ret = do_unregister_con_driver(&vga_con);
 699
 700		/* Ignore "already unregistered". */
 701		if (ret == -ENODEV)
 702			ret = 0;
 703	}
 704	console_unlock();
 705
 706	return ret;
 707}
 708#endif
 709
 710static void intel_init_dpio(struct drm_i915_private *dev_priv)
 711{
 712	/*
 713	 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 714	 * CHV x1 PHY (DP/HDMI D)
 715	 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 716	 */
 717	if (IS_CHERRYVIEW(dev_priv)) {
 718		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 719		DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 720	} else if (IS_VALLEYVIEW(dev_priv)) {
 721		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 722	}
 723}
 724
 725static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 726{
 727	/*
 728	 * The i915 workqueue is primarily used for batched retirement of
 729	 * requests (and thus managing bo) once the task has been completed
 730	 * by the GPU. i915_gem_retire_requests() is called directly when we
 731	 * need high-priority retirement, such as waiting for an explicit
 732	 * bo.
 733	 *
 734	 * It is also used for periodic low-priority events, such as
 735	 * idle-timers and recording error state.
 736	 *
 737	 * All tasks on the workqueue are expected to acquire the dev mutex
 738	 * so there is no point in running more than one instance of the
 739	 * workqueue at any time.  Use an ordered one.
 740	 */
 741	dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 742	if (dev_priv->wq == NULL)
 743		goto out_err;
 744
 745	dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 746	if (dev_priv->hotplug.dp_wq == NULL)
 747		goto out_free_wq;
 748
 749	return 0;
 750
 751out_free_wq:
 752	destroy_workqueue(dev_priv->wq);
 753out_err:
 754	DRM_ERROR("Failed to allocate workqueues.\n");
 755
 756	return -ENOMEM;
 757}
 758
 759static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 760{
 761	destroy_workqueue(dev_priv->hotplug.dp_wq);
 762	destroy_workqueue(dev_priv->wq);
 763}
 764
 765/*
 766 * We don't keep the workarounds for pre-production hardware, so we expect our
 767 * driver to fail on these machines in one way or another. A little warning on
 768 * dmesg may help both the user and the bug triagers.
 769 */
 770static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 771{
 772	if (IS_HSW_EARLY_SDV(dev_priv) ||
 773	    IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
 774		DRM_ERROR("This is a pre-production stepping. "
 775			  "It may not be fully functional.\n");
 776}
 777
 778/**
 779 * i915_driver_init_early - setup state not requiring device access
 780 * @dev_priv: device private
 781 *
 782 * Initialize everything that is a "SW-only" state, that is state not
 783 * requiring accessing the device or exposing the driver via kernel internal
 784 * or userspace interfaces. Example steps belonging here: lock initialization,
 785 * system memory allocation, setting up device specific attributes and
 786 * function hooks not requiring accessing the device.
 787 */
 788static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 789				  const struct pci_device_id *ent)
 790{
 791	const struct intel_device_info *match_info =
 792		(struct intel_device_info *)ent->driver_data;
 793	struct intel_device_info *device_info;
 794	int ret = 0;
 795
 796	if (i915_inject_load_failure())
 797		return -ENODEV;
 798
 799	/* Setup the write-once "constant" device info */
 800	device_info = mkwrite_device_info(dev_priv);
 801	memcpy(device_info, match_info, sizeof(*device_info));
 802	device_info->device_id = dev_priv->drm.pdev->device;
 803
 804	BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 805	device_info->gen_mask = BIT(device_info->gen - 1);
 806
 807	spin_lock_init(&dev_priv->irq_lock);
 808	spin_lock_init(&dev_priv->gpu_error.lock);
 809	mutex_init(&dev_priv->backlight_lock);
 810	spin_lock_init(&dev_priv->uncore.lock);
 811	spin_lock_init(&dev_priv->mm.object_stat_lock);
 812	spin_lock_init(&dev_priv->mmio_flip_lock);
 813	mutex_init(&dev_priv->sb_lock);
 814	mutex_init(&dev_priv->modeset_restore_lock);
 815	mutex_init(&dev_priv->av_mutex);
 816	mutex_init(&dev_priv->wm.wm_mutex);
 817	mutex_init(&dev_priv->pps_mutex);
 818
 819	i915_memcpy_init_early(dev_priv);
 820
 821	ret = i915_workqueues_init(dev_priv);
 822	if (ret < 0)
 823		return ret;
 824
 825	ret = intel_gvt_init(dev_priv);
 826	if (ret < 0)
 827		goto err_workqueues;
 828
 829	/* This must be called before any calls to HAS_PCH_* */
 830	intel_detect_pch(&dev_priv->drm);
 831
 832	intel_pm_setup(&dev_priv->drm);
 833	intel_init_dpio(dev_priv);
 834	intel_power_domains_init(dev_priv);
 835	intel_irq_init(dev_priv);
 836	intel_hangcheck_init(dev_priv);
 837	intel_init_display_hooks(dev_priv);
 838	intel_init_clock_gating_hooks(dev_priv);
 839	intel_init_audio_hooks(dev_priv);
 840	ret = i915_gem_load_init(&dev_priv->drm);
 841	if (ret < 0)
 842		goto err_gvt;
 843
 844	intel_display_crc_init(dev_priv);
 845
 846	intel_device_info_dump(dev_priv);
 847
 848	intel_detect_preproduction_hw(dev_priv);
 849
 850	return 0;
 851
 852err_gvt:
 853	intel_gvt_cleanup(dev_priv);
 854err_workqueues:
 855	i915_workqueues_cleanup(dev_priv);
 856	return ret;
 857}
 858
 859/**
 860 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 861 * @dev_priv: device private
 862 */
 863static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 864{
 865	i915_gem_load_cleanup(&dev_priv->drm);
 866	i915_workqueues_cleanup(dev_priv);
 867}
 868
 869static int i915_mmio_setup(struct drm_device *dev)
 870{
 871	struct drm_i915_private *dev_priv = to_i915(dev);
 872	struct pci_dev *pdev = dev_priv->drm.pdev;
 873	int mmio_bar;
 874	int mmio_size;
 875
 876	mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 877	/*
 878	 * Before gen4, the registers and the GTT are behind different BARs.
 879	 * However, from gen4 onwards, the registers and the GTT are shared
 880	 * in the same BAR, so we want to restrict this ioremap from
 881	 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 882	 * the register BAR remains the same size for all the earlier
 883	 * generations up to Ironlake.
 884	 */
 885	if (INTEL_GEN(dev_priv) < 5)
 886		mmio_size = 512 * 1024;
 887	else
 888		mmio_size = 2 * 1024 * 1024;
 889	dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 890	if (dev_priv->regs == NULL) {
 891		DRM_ERROR("failed to map registers\n");
 892
 893		return -EIO;
 894	}
 895
 896	/* Try to make sure MCHBAR is enabled before poking at it */
 897	intel_setup_mchbar(dev);
 898
 899	return 0;
 900}
 901
 902static void i915_mmio_cleanup(struct drm_device *dev)
 903{
 904	struct drm_i915_private *dev_priv = to_i915(dev);
 905	struct pci_dev *pdev = dev_priv->drm.pdev;
 906
 907	intel_teardown_mchbar(dev);
 908	pci_iounmap(pdev, dev_priv->regs);
 909}
 910
 911/**
 912 * i915_driver_init_mmio - setup device MMIO
 913 * @dev_priv: device private
 914 *
 915 * Setup minimal device state necessary for MMIO accesses later in the
 916 * initialization sequence. The setup here should avoid any other device-wide
 917 * side effects or exposing the driver via kernel internal or user space
 918 * interfaces.
 919 */
 920static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 921{
 922	struct drm_device *dev = &dev_priv->drm;
 923	int ret;
 924
 925	if (i915_inject_load_failure())
 926		return -ENODEV;
 927
 928	if (i915_get_bridge_dev(dev))
 929		return -EIO;
 930
 931	ret = i915_mmio_setup(dev);
 932	if (ret < 0)
 933		goto put_bridge;
 934
 935	intel_uncore_init(dev_priv);
 936
 937	return 0;
 938
 939put_bridge:
 940	pci_dev_put(dev_priv->bridge_dev);
 941
 942	return ret;
 943}
 944
 945/**
 946 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 947 * @dev_priv: device private
 948 */
 949static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 950{
 951	struct drm_device *dev = &dev_priv->drm;
 952
 953	intel_uncore_fini(dev_priv);
 954	i915_mmio_cleanup(dev);
 955	pci_dev_put(dev_priv->bridge_dev);
 956}
 957
 958static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 959{
 960	i915.enable_execlists =
 961		intel_sanitize_enable_execlists(dev_priv,
 962						i915.enable_execlists);
 963
 964	/*
 965	 * i915.enable_ppgtt is read-only, so do an early pass to validate the
 966	 * user's requested state against the hardware/driver capabilities.  We
 967	 * do this now so that we can print out any log messages once rather
 968	 * than every time we check intel_enable_ppgtt().
 969	 */
 970	i915.enable_ppgtt =
 971		intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
 972	DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
 973
 974	i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
 975	DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores));
 976}
 977
 978/**
 979 * i915_driver_init_hw - setup state requiring device access
 980 * @dev_priv: device private
 981 *
 982 * Setup state that requires accessing the device, but doesn't require
 983 * exposing the driver via kernel internal or userspace interfaces.
 984 */
 985static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 986{
 987	struct pci_dev *pdev = dev_priv->drm.pdev;
 988	int ret;
 989
 990	if (i915_inject_load_failure())
 991		return -ENODEV;
 992
 993	intel_device_info_runtime_init(dev_priv);
 994
 995	intel_sanitize_options(dev_priv);
 996
 997	ret = i915_ggtt_probe_hw(dev_priv);
 998	if (ret)
 999		return ret;
1000
1001	/* WARNING: Apparently we must kick fbdev drivers before vgacon,
1002	 * otherwise the vga fbdev driver falls over. */
1003	ret = i915_kick_out_firmware_fb(dev_priv);
1004	if (ret) {
1005		DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1006		goto out_ggtt;
1007	}
1008
1009	ret = i915_kick_out_vgacon(dev_priv);
1010	if (ret) {
1011		DRM_ERROR("failed to remove conflicting VGA console\n");
1012		goto out_ggtt;
1013	}
1014
1015	ret = i915_ggtt_init_hw(dev_priv);
1016	if (ret)
1017		return ret;
1018
1019	ret = i915_ggtt_enable_hw(dev_priv);
1020	if (ret) {
1021		DRM_ERROR("failed to enable GGTT\n");
1022		goto out_ggtt;
1023	}
1024
1025	pci_set_master(pdev);
1026
1027	/* overlay on gen2 is broken and can't address above 1G */
1028	if (IS_GEN2(dev_priv)) {
1029		ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1030		if (ret) {
1031			DRM_ERROR("failed to set DMA mask\n");
1032
1033			goto out_ggtt;
1034		}
1035	}
1036
1037	/* 965GM sometimes incorrectly writes to hardware status page (HWS)
1038	 * using 32bit addressing, overwriting memory if HWS is located
1039	 * above 4GB.
1040	 *
1041	 * The documentation also mentions an issue with undefined
1042	 * behaviour if any general state is accessed within a page above 4GB,
1043	 * which also needs to be handled carefully.
1044	 */
1045	if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv)) {
1046		ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1047
1048		if (ret) {
1049			DRM_ERROR("failed to set DMA mask\n");
1050
1051			goto out_ggtt;
1052		}
1053	}
1054
1055	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1056			   PM_QOS_DEFAULT_VALUE);
1057
1058	intel_uncore_sanitize(dev_priv);
1059
1060	intel_opregion_setup(dev_priv);
1061
1062	i915_gem_load_init_fences(dev_priv);
1063
1064	/* On the 945G/GM, the chipset reports the MSI capability on the
1065	 * integrated graphics even though the support isn't actually there
1066	 * according to the published specs.  It doesn't appear to function
1067	 * correctly in testing on 945G.
1068	 * This may be a side effect of MSI having been made available for PEG
1069	 * and the registers being closely associated.
1070	 *
1071	 * According to chipset errata, on the 965GM, MSI interrupts may
1072	 * be lost or delayed, but we use them anyways to avoid
1073	 * stuck interrupts on some machines.
1074	 */
1075	if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
1076		if (pci_enable_msi(pdev) < 0)
1077			DRM_DEBUG_DRIVER("can't enable MSI");
1078	}
1079
1080	return 0;
1081
1082out_ggtt:
1083	i915_ggtt_cleanup_hw(dev_priv);
1084
1085	return ret;
1086}
1087
1088/**
1089 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1090 * @dev_priv: device private
1091 */
1092static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1093{
1094	struct pci_dev *pdev = dev_priv->drm.pdev;
1095
1096	if (pdev->msi_enabled)
1097		pci_disable_msi(pdev);
1098
1099	pm_qos_remove_request(&dev_priv->pm_qos);
1100	i915_ggtt_cleanup_hw(dev_priv);
1101}
1102
1103/**
1104 * i915_driver_register - register the driver with the rest of the system
1105 * @dev_priv: device private
1106 *
1107 * Perform any steps necessary to make the driver available via kernel
1108 * internal or userspace interfaces.
1109 */
1110static void i915_driver_register(struct drm_i915_private *dev_priv)
1111{
1112	struct drm_device *dev = &dev_priv->drm;
1113
1114	i915_gem_shrinker_init(dev_priv);
1115
1116	/*
1117	 * Notify a valid surface after modesetting,
1118	 * when running inside a VM.
1119	 */
1120	if (intel_vgpu_active(dev_priv))
1121		I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1122
1123	/* Reveal our presence to userspace */
1124	if (drm_dev_register(dev, 0) == 0) {
1125		i915_debugfs_register(dev_priv);
1126		i915_guc_register(dev_priv);
1127		i915_setup_sysfs(dev_priv);
1128	} else
1129		DRM_ERROR("Failed to register driver for userspace access!\n");
1130
1131	if (INTEL_INFO(dev_priv)->num_pipes) {
1132		/* Must be done after probing outputs */
1133		intel_opregion_register(dev_priv);
1134		acpi_video_register();
1135	}
1136
1137	if (IS_GEN5(dev_priv))
1138		intel_gpu_ips_init(dev_priv);
1139
1140	i915_audio_component_init(dev_priv);
1141
1142	/*
1143	 * Some ports require correctly set-up hpd registers for detection to
1144	 * work properly (leading to ghost connected connector status), e.g. VGA
1145	 * on gm45.  Hence we can only set up the initial fbdev config after hpd
1146	 * irqs are fully enabled. We do it last so that the async config
1147	 * cannot run before the connectors are registered.
1148	 */
1149	intel_fbdev_initial_config_async(dev);
1150}
1151
1152/**
1153 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1154 * @dev_priv: device private
1155 */
1156static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1157{
1158	i915_audio_component_cleanup(dev_priv);
1159
1160	intel_gpu_ips_teardown();
1161	acpi_video_unregister();
1162	intel_opregion_unregister(dev_priv);
1163
1164	i915_teardown_sysfs(dev_priv);
1165	i915_guc_unregister(dev_priv);
1166	i915_debugfs_unregister(dev_priv);
1167	drm_dev_unregister(&dev_priv->drm);
1168
1169	i915_gem_shrinker_cleanup(dev_priv);
1170}
1171
1172/**
1173 * i915_driver_load - setup chip and create an initial config
1174 * @pdev: PCI device
1175 * @ent: matching PCI ID entry
1176 *
1177 * The driver load routine has to do several things:
1178 *   - drive output discovery via intel_modeset_init()
1179 *   - initialize the memory manager
1180 *   - allocate initial config memory
1181 *   - setup the DRM framebuffer with the allocated memory
1182 */
1183int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1184{
1185	struct drm_i915_private *dev_priv;
1186	int ret;
1187
1188	if (i915.nuclear_pageflip)
1189		driver.driver_features |= DRIVER_ATOMIC;
1190
1191	ret = -ENOMEM;
1192	dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1193	if (dev_priv)
1194		ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1195	if (ret) {
1196		dev_printk(KERN_ERR, &pdev->dev,
1197			   "[" DRM_NAME ":%s] allocation failed\n", __func__);
1198		kfree(dev_priv);
1199		return ret;
1200	}
1201
1202	dev_priv->drm.pdev = pdev;
1203	dev_priv->drm.dev_private = dev_priv;
1204
1205	ret = pci_enable_device(pdev);
1206	if (ret)
1207		goto out_free_priv;
1208
1209	pci_set_drvdata(pdev, &dev_priv->drm);
1210
1211	ret = i915_driver_init_early(dev_priv, ent);
1212	if (ret < 0)
1213		goto out_pci_disable;
1214
1215	intel_runtime_pm_get(dev_priv);
1216
1217	ret = i915_driver_init_mmio(dev_priv);
1218	if (ret < 0)
1219		goto out_runtime_pm_put;
1220
1221	ret = i915_driver_init_hw(dev_priv);
1222	if (ret < 0)
1223		goto out_cleanup_mmio;
1224
1225	/*
1226	 * TODO: move the vblank init and parts of modeset init steps into one
1227	 * of the i915_driver_init_/i915_driver_register functions according
1228	 * to the role/effect of the given init step.
1229	 */
1230	if (INTEL_INFO(dev_priv)->num_pipes) {
1231		ret = drm_vblank_init(&dev_priv->drm,
1232				      INTEL_INFO(dev_priv)->num_pipes);
1233		if (ret)
1234			goto out_cleanup_hw;
1235	}
1236
1237	ret = i915_load_modeset_init(&dev_priv->drm);
1238	if (ret < 0)
1239		goto out_cleanup_vblank;
1240
1241	i915_driver_register(dev_priv);
1242
1243	intel_runtime_pm_enable(dev_priv);
1244
1245	/* Everything is in place, we can now relax! */
1246	DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
1247		 driver.name, driver.major, driver.minor, driver.patchlevel,
1248		 driver.date, pci_name(pdev), dev_priv->drm.primary->index);
1249	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1250		DRM_INFO("DRM_I915_DEBUG enabled\n");
1251	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1252		DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1253
1254	intel_runtime_pm_put(dev_priv);
1255
1256	return 0;
1257
1258out_cleanup_vblank:
1259	drm_vblank_cleanup(&dev_priv->drm);
1260out_cleanup_hw:
1261	i915_driver_cleanup_hw(dev_priv);
1262out_cleanup_mmio:
1263	i915_driver_cleanup_mmio(dev_priv);
1264out_runtime_pm_put:
1265	intel_runtime_pm_put(dev_priv);
1266	i915_driver_cleanup_early(dev_priv);
1267out_pci_disable:
1268	pci_disable_device(pdev);
1269out_free_priv:
1270	i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1271	drm_dev_unref(&dev_priv->drm);
1272	return ret;
1273}
1274
1275void i915_driver_unload(struct drm_device *dev)
1276{
1277	struct drm_i915_private *dev_priv = to_i915(dev);
1278	struct pci_dev *pdev = dev_priv->drm.pdev;
1279
1280	intel_fbdev_fini(dev);
1281
1282	if (i915_gem_suspend(dev))
1283		DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1284
1285	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1286
1287	i915_driver_unregister(dev_priv);
1288
1289	drm_vblank_cleanup(dev);
1290
1291	intel_modeset_cleanup(dev);
1292
1293	/*
1294	 * free the memory space allocated for the child device
1295	 * config parsed from VBT
1296	 */
1297	if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1298		kfree(dev_priv->vbt.child_dev);
1299		dev_priv->vbt.child_dev = NULL;
1300		dev_priv->vbt.child_dev_num = 0;
1301	}
1302	kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1303	dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1304	kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1305	dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1306
1307	vga_switcheroo_unregister_client(pdev);
1308	vga_client_register(pdev, NULL, NULL, NULL);
1309
1310	intel_csr_ucode_fini(dev_priv);
1311
1312	/* Free error state after interrupts are fully disabled. */
1313	cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1314	i915_destroy_error_state(dev);
1315
1316	/* Flush any outstanding unpin_work. */
1317	drain_workqueue(dev_priv->wq);
1318
1319	intel_guc_fini(dev);
1320	i915_gem_fini(dev_priv);
1321	intel_fbc_cleanup_cfb(dev_priv);
1322
1323	intel_power_domains_fini(dev_priv);
1324
1325	i915_driver_cleanup_hw(dev_priv);
1326	i915_driver_cleanup_mmio(dev_priv);
1327
1328	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1329
1330	i915_driver_cleanup_early(dev_priv);
1331}
1332
1333static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1334{
1335	int ret;
1336
1337	ret = i915_gem_open(dev, file);
1338	if (ret)
1339		return ret;
1340
1341	return 0;
1342}
1343
1344/**
1345 * i915_driver_lastclose - clean up after all DRM clients have exited
1346 * @dev: DRM device
1347 *
1348 * Take care of cleaning up after all DRM clients have exited.  In the
1349 * mode setting case, we want to restore the kernel's initial mode (just
1350 * in case the last client left us in a bad state).
1351 *
1352 * Additionally, in the non-mode setting case, we'll tear down the GTT
1353 * and DMA structures, since the kernel won't be using them, and clea
1354 * up any GEM state.
1355 */
1356static void i915_driver_lastclose(struct drm_device *dev)
1357{
1358	intel_fbdev_restore_mode(dev);
1359	vga_switcheroo_process_delayed_switch();
1360}
1361
1362static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1363{
1364	mutex_lock(&dev->struct_mutex);
1365	i915_gem_context_close(dev, file);
1366	i915_gem_release(dev, file);
1367	mutex_unlock(&dev->struct_mutex);
1368}
1369
1370static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1371{
1372	struct drm_i915_file_private *file_priv = file->driver_priv;
1373
1374	kfree(file_priv);
1375}
1376
1377static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1378{
1379	struct drm_device *dev = &dev_priv->drm;
1380	struct intel_encoder *encoder;
1381
1382	drm_modeset_lock_all(dev);
1383	for_each_intel_encoder(dev, encoder)
1384		if (encoder->suspend)
1385			encoder->suspend(encoder);
1386	drm_modeset_unlock_all(dev);
1387}
1388
1389static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1390			      bool rpm_resume);
1391static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1392
1393static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1394{
1395#if IS_ENABLED(CONFIG_ACPI_SLEEP)
1396	if (acpi_target_system_state() < ACPI_STATE_S3)
1397		return true;
1398#endif
1399	return false;
1400}
1401
1402static int i915_drm_suspend(struct drm_device *dev)
1403{
1404	struct drm_i915_private *dev_priv = to_i915(dev);
1405	struct pci_dev *pdev = dev_priv->drm.pdev;
1406	pci_power_t opregion_target_state;
1407	int error;
1408
1409	/* ignore lid events during suspend */
1410	mutex_lock(&dev_priv->modeset_restore_lock);
1411	dev_priv->modeset_restore = MODESET_SUSPENDED;
1412	mutex_unlock(&dev_priv->modeset_restore_lock);
1413
1414	disable_rpm_wakeref_asserts(dev_priv);
1415
1416	/* We do a lot of poking in a lot of registers, make sure they work
1417	 * properly. */
1418	intel_display_set_init_power(dev_priv, true);
1419
1420	drm_kms_helper_poll_disable(dev);
1421
1422	pci_save_state(pdev);
1423
1424	error = i915_gem_suspend(dev);
1425	if (error) {
1426		dev_err(&pdev->dev,
1427			"GEM idle failed, resume might fail\n");
1428		goto out;
1429	}
1430
1431	intel_guc_suspend(dev);
1432
1433	intel_display_suspend(dev);
1434
1435	intel_dp_mst_suspend(dev);
1436
1437	intel_runtime_pm_disable_interrupts(dev_priv);
1438	intel_hpd_cancel_work(dev_priv);
1439
1440	intel_suspend_encoders(dev_priv);
1441
1442	intel_suspend_hw(dev_priv);
1443
1444	i915_gem_suspend_gtt_mappings(dev_priv);
1445
1446	i915_save_state(dev);
1447
1448	opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1449	intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1450
1451	intel_uncore_forcewake_reset(dev_priv, false);
1452	intel_opregion_unregister(dev_priv);
1453
1454	intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1455
1456	dev_priv->suspend_count++;
1457
1458	intel_csr_ucode_suspend(dev_priv);
1459
1460out:
1461	enable_rpm_wakeref_asserts(dev_priv);
1462
1463	return error;
1464}
1465
1466static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1467{
1468	struct drm_i915_private *dev_priv = to_i915(dev);
1469	struct pci_dev *pdev = dev_priv->drm.pdev;
1470	bool fw_csr;
1471	int ret;
1472
1473	disable_rpm_wakeref_asserts(dev_priv);
1474
1475	intel_display_set_init_power(dev_priv, false);
1476
1477	fw_csr = !IS_BROXTON(dev_priv) &&
1478		suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1479	/*
1480	 * In case of firmware assisted context save/restore don't manually
1481	 * deinit the power domains. This also means the CSR/DMC firmware will
1482	 * stay active, it will power down any HW resources as required and
1483	 * also enable deeper system power states that would be blocked if the
1484	 * firmware was inactive.
1485	 */
1486	if (!fw_csr)
1487		intel_power_domains_suspend(dev_priv);
1488
1489	ret = 0;
1490	if (IS_BROXTON(dev_priv))
1491		bxt_enable_dc9(dev_priv);
1492	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1493		hsw_enable_pc8(dev_priv);
1494	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1495		ret = vlv_suspend_complete(dev_priv);
1496
1497	if (ret) {
1498		DRM_ERROR("Suspend complete failed: %d\n", ret);
1499		if (!fw_csr)
1500			intel_power_domains_init_hw(dev_priv, true);
1501
1502		goto out;
1503	}
1504
1505	pci_disable_device(pdev);
1506	/*
1507	 * During hibernation on some platforms the BIOS may try to access
1508	 * the device even though it's already in D3 and hang the machine. So
1509	 * leave the device in D0 on those platforms and hope the BIOS will
1510	 * power down the device properly. The issue was seen on multiple old
1511	 * GENs with different BIOS vendors, so having an explicit blacklist
1512	 * is inpractical; apply the workaround on everything pre GEN6. The
1513	 * platforms where the issue was seen:
1514	 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1515	 * Fujitsu FSC S7110
1516	 * Acer Aspire 1830T
1517	 */
1518	if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1519		pci_set_power_state(pdev, PCI_D3hot);
1520
1521	dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1522
1523out:
1524	enable_rpm_wakeref_asserts(dev_priv);
1525
1526	return ret;
1527}
1528
1529int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1530{
1531	int error;
1532
1533	if (!dev) {
1534		DRM_ERROR("dev: %p\n", dev);
1535		DRM_ERROR("DRM not initialized, aborting suspend.\n");
1536		return -ENODEV;
1537	}
1538
1539	if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1540			 state.event != PM_EVENT_FREEZE))
1541		return -EINVAL;
1542
1543	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1544		return 0;
1545
1546	error = i915_drm_suspend(dev);
1547	if (error)
1548		return error;
1549
1550	return i915_drm_suspend_late(dev, false);
1551}
1552
1553static int i915_drm_resume(struct drm_device *dev)
1554{
1555	struct drm_i915_private *dev_priv = to_i915(dev);
1556	int ret;
1557
1558	disable_rpm_wakeref_asserts(dev_priv);
1559	intel_sanitize_gt_powersave(dev_priv);
1560
1561	ret = i915_ggtt_enable_hw(dev_priv);
1562	if (ret)
1563		DRM_ERROR("failed to re-enable GGTT\n");
1564
1565	intel_csr_ucode_resume(dev_priv);
1566
1567	i915_gem_resume(dev);
1568
1569	i915_restore_state(dev);
1570	intel_pps_unlock_regs_wa(dev_priv);
1571	intel_opregion_setup(dev_priv);
1572
1573	intel_init_pch_refclk(dev);
1574
1575	/*
1576	 * Interrupts have to be enabled before any batches are run. If not the
1577	 * GPU will hang. i915_gem_init_hw() will initiate batches to
1578	 * update/restore the context.
1579	 *
1580	 * drm_mode_config_reset() needs AUX interrupts.
1581	 *
1582	 * Modeset enabling in intel_modeset_init_hw() also needs working
1583	 * interrupts.
1584	 */
1585	intel_runtime_pm_enable_interrupts(dev_priv);
1586
1587	drm_mode_config_reset(dev);
1588
1589	mutex_lock(&dev->struct_mutex);
1590	if (i915_gem_init_hw(dev)) {
1591		DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1592		i915_gem_set_wedged(dev_priv);
1593	}
1594	mutex_unlock(&dev->struct_mutex);
1595
1596	intel_guc_resume(dev);
1597
1598	intel_modeset_init_hw(dev);
1599
1600	spin_lock_irq(&dev_priv->irq_lock);
1601	if (dev_priv->display.hpd_irq_setup)
1602		dev_priv->display.hpd_irq_setup(dev_priv);
1603	spin_unlock_irq(&dev_priv->irq_lock);
1604
1605	intel_dp_mst_resume(dev);
1606
1607	intel_display_resume(dev);
1608
1609	drm_kms_helper_poll_enable(dev);
1610
1611	/*
1612	 * ... but also need to make sure that hotplug processing
1613	 * doesn't cause havoc. Like in the driver load code we don't
1614	 * bother with the tiny race here where we might loose hotplug
1615	 * notifications.
1616	 * */
1617	intel_hpd_init(dev_priv);
1618
1619	intel_opregion_register(dev_priv);
1620
1621	intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1622
1623	mutex_lock(&dev_priv->modeset_restore_lock);
1624	dev_priv->modeset_restore = MODESET_DONE;
1625	mutex_unlock(&dev_priv->modeset_restore_lock);
1626
1627	intel_opregion_notify_adapter(dev_priv, PCI_D0);
1628
1629	intel_autoenable_gt_powersave(dev_priv);
1630
1631	enable_rpm_wakeref_asserts(dev_priv);
1632
1633	return 0;
1634}
1635
1636static int i915_drm_resume_early(struct drm_device *dev)
1637{
1638	struct drm_i915_private *dev_priv = to_i915(dev);
1639	struct pci_dev *pdev = dev_priv->drm.pdev;
1640	int ret;
1641
1642	/*
1643	 * We have a resume ordering issue with the snd-hda driver also
1644	 * requiring our device to be power up. Due to the lack of a
1645	 * parent/child relationship we currently solve this with an early
1646	 * resume hook.
1647	 *
1648	 * FIXME: This should be solved with a special hdmi sink device or
1649	 * similar so that power domains can be employed.
1650	 */
1651
1652	/*
1653	 * Note that we need to set the power state explicitly, since we
1654	 * powered off the device during freeze and the PCI core won't power
1655	 * it back up for us during thaw. Powering off the device during
1656	 * freeze is not a hard requirement though, and during the
1657	 * suspend/resume phases the PCI core makes sure we get here with the
1658	 * device powered on. So in case we change our freeze logic and keep
1659	 * the device powered we can also remove the following set power state
1660	 * call.
1661	 */
1662	ret = pci_set_power_state(pdev, PCI_D0);
1663	if (ret) {
1664		DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1665		goto out;
1666	}
1667
1668	/*
1669	 * Note that pci_enable_device() first enables any parent bridge
1670	 * device and only then sets the power state for this device. The
1671	 * bridge enabling is a nop though, since bridge devices are resumed
1672	 * first. The order of enabling power and enabling the device is
1673	 * imposed by the PCI core as described above, so here we preserve the
1674	 * same order for the freeze/thaw phases.
1675	 *
1676	 * TODO: eventually we should remove pci_disable_device() /
1677	 * pci_enable_enable_device() from suspend/resume. Due to how they
1678	 * depend on the device enable refcount we can't anyway depend on them
1679	 * disabling/enabling the device.
1680	 */
1681	if (pci_enable_device(pdev)) {
1682		ret = -EIO;
1683		goto out;
1684	}
1685
1686	pci_set_master(pdev);
1687
1688	disable_rpm_wakeref_asserts(dev_priv);
1689
1690	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1691		ret = vlv_resume_prepare(dev_priv, false);
1692	if (ret)
1693		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1694			  ret);
1695
1696	intel_uncore_early_sanitize(dev_priv, true);
1697
1698	if (IS_BROXTON(dev_priv)) {
1699		if (!dev_priv->suspended_to_idle)
1700			gen9_sanitize_dc_state(dev_priv);
1701		bxt_disable_dc9(dev_priv);
1702	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1703		hsw_disable_pc8(dev_priv);
1704	}
1705
1706	intel_uncore_sanitize(dev_priv);
1707
1708	if (IS_BROXTON(dev_priv) ||
1709	    !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1710		intel_power_domains_init_hw(dev_priv, true);
1711
1712	enable_rpm_wakeref_asserts(dev_priv);
1713
1714out:
1715	dev_priv->suspended_to_idle = false;
1716
1717	return ret;
1718}
1719
1720int i915_resume_switcheroo(struct drm_device *dev)
1721{
1722	int ret;
1723
1724	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1725		return 0;
1726
1727	ret = i915_drm_resume_early(dev);
1728	if (ret)
1729		return ret;
1730
1731	return i915_drm_resume(dev);
1732}
1733
1734static void disable_engines_irq(struct drm_i915_private *dev_priv)
1735{
1736	struct intel_engine_cs *engine;
1737	enum intel_engine_id id;
1738
1739	/* Ensure irq handler finishes, and not run again. */
1740	disable_irq(dev_priv->drm.irq);
1741	for_each_engine(engine, dev_priv, id)
1742		tasklet_kill(&engine->irq_tasklet);
1743}
1744
1745static void enable_engines_irq(struct drm_i915_private *dev_priv)
1746{
1747	enable_irq(dev_priv->drm.irq);
1748}
1749
1750/**
1751 * i915_reset - reset chip after a hang
1752 * @dev: drm device to reset
1753 *
1754 * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1755 * on failure.
1756 *
1757 * Caller must hold the struct_mutex.
1758 *
1759 * Procedure is fairly simple:
1760 *   - reset the chip using the reset reg
1761 *   - re-init context state
1762 *   - re-init hardware status page
1763 *   - re-init ring buffer
1764 *   - re-init interrupt state
1765 *   - re-init display
1766 */
1767void i915_reset(struct drm_i915_private *dev_priv)
1768{
1769	struct drm_device *dev = &dev_priv->drm;
1770	struct i915_gpu_error *error = &dev_priv->gpu_error;
1771	int ret;
1772
1773	lockdep_assert_held(&dev->struct_mutex);
1774
1775	if (!test_and_clear_bit(I915_RESET_IN_PROGRESS, &error->flags))
1776		return;
1777
1778	/* Clear any previous failed attempts at recovery. Time to try again. */
1779	__clear_bit(I915_WEDGED, &error->flags);
1780	error->reset_count++;
1781
1782	pr_notice("drm/i915: Resetting chip after gpu hang\n");
1783
1784	disable_engines_irq(dev_priv);
1785	ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1786	enable_engines_irq(dev_priv);
1787
1788	if (ret) {
1789		if (ret != -ENODEV)
1790			DRM_ERROR("Failed to reset chip: %i\n", ret);
1791		else
1792			DRM_DEBUG_DRIVER("GPU reset disabled\n");
1793		goto error;
1794	}
1795
1796	i915_gem_reset(dev_priv);
1797	intel_overlay_reset(dev_priv);
1798
1799	/* Ok, now get things going again... */
1800
1801	/*
1802	 * Everything depends on having the GTT running, so we need to start
1803	 * there.  Fortunately we don't need to do this unless we reset the
1804	 * chip at a PCI level.
1805	 *
1806	 * Next we need to restore the context, but we don't use those
1807	 * yet either...
1808	 *
1809	 * Ring buffer needs to be re-initialized in the KMS case, or if X
1810	 * was running at the time of the reset (i.e. we weren't VT
1811	 * switched away).
1812	 */
1813	ret = i915_gem_init_hw(dev);
1814	if (ret) {
1815		DRM_ERROR("Failed hw init on reset %d\n", ret);
1816		goto error;
1817	}
1818
1819wakeup:
1820	wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
1821	return;
1822
1823error:
1824	i915_gem_set_wedged(dev_priv);
1825	goto wakeup;
1826}
1827
1828static int i915_pm_suspend(struct device *kdev)
1829{
1830	struct pci_dev *pdev = to_pci_dev(kdev);
1831	struct drm_device *dev = pci_get_drvdata(pdev);
1832
1833	if (!dev) {
1834		dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1835		return -ENODEV;
1836	}
1837
1838	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1839		return 0;
1840
1841	return i915_drm_suspend(dev);
1842}
1843
1844static int i915_pm_suspend_late(struct device *kdev)
1845{
1846	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1847
1848	/*
1849	 * We have a suspend ordering issue with the snd-hda driver also
1850	 * requiring our device to be power up. Due to the lack of a
1851	 * parent/child relationship we currently solve this with an late
1852	 * suspend hook.
1853	 *
1854	 * FIXME: This should be solved with a special hdmi sink device or
1855	 * similar so that power domains can be employed.
1856	 */
1857	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1858		return 0;
1859
1860	return i915_drm_suspend_late(dev, false);
1861}
1862
1863static int i915_pm_poweroff_late(struct device *kdev)
1864{
1865	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1866
1867	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1868		return 0;
1869
1870	return i915_drm_suspend_late(dev, true);
1871}
1872
1873static int i915_pm_resume_early(struct device *kdev)
1874{
1875	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1876
1877	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1878		return 0;
1879
1880	return i915_drm_resume_early(dev);
1881}
1882
1883static int i915_pm_resume(struct device *kdev)
1884{
1885	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1886
1887	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1888		return 0;
1889
1890	return i915_drm_resume(dev);
1891}
1892
1893/* freeze: before creating the hibernation_image */
1894static int i915_pm_freeze(struct device *kdev)
1895{
1896	int ret;
1897
1898	ret = i915_pm_suspend(kdev);
1899	if (ret)
1900		return ret;
1901
1902	ret = i915_gem_freeze(kdev_to_i915(kdev));
1903	if (ret)
1904		return ret;
1905
1906	return 0;
1907}
1908
1909static int i915_pm_freeze_late(struct device *kdev)
1910{
1911	int ret;
1912
1913	ret = i915_pm_suspend_late(kdev);
1914	if (ret)
1915		return ret;
1916
1917	ret = i915_gem_freeze_late(kdev_to_i915(kdev));
1918	if (ret)
1919		return ret;
1920
1921	return 0;
1922}
1923
1924/* thaw: called after creating the hibernation image, but before turning off. */
1925static int i915_pm_thaw_early(struct device *kdev)
1926{
1927	return i915_pm_resume_early(kdev);
1928}
1929
1930static int i915_pm_thaw(struct device *kdev)
1931{
1932	return i915_pm_resume(kdev);
1933}
1934
1935/* restore: called after loading the hibernation image. */
1936static int i915_pm_restore_early(struct device *kdev)
1937{
1938	return i915_pm_resume_early(kdev);
1939}
1940
1941static int i915_pm_restore(struct device *kdev)
1942{
1943	return i915_pm_resume(kdev);
1944}
1945
1946/*
1947 * Save all Gunit registers that may be lost after a D3 and a subsequent
1948 * S0i[R123] transition. The list of registers needing a save/restore is
1949 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1950 * registers in the following way:
1951 * - Driver: saved/restored by the driver
1952 * - Punit : saved/restored by the Punit firmware
1953 * - No, w/o marking: no need to save/restore, since the register is R/O or
1954 *                    used internally by the HW in a way that doesn't depend
1955 *                    keeping the content across a suspend/resume.
1956 * - Debug : used for debugging
1957 *
1958 * We save/restore all registers marked with 'Driver', with the following
1959 * exceptions:
1960 * - Registers out of use, including also registers marked with 'Debug'.
1961 *   These have no effect on the driver's operation, so we don't save/restore
1962 *   them to reduce the overhead.
1963 * - Registers that are fully setup by an initialization function called from
1964 *   the resume path. For example many clock gating and RPS/RC6 registers.
1965 * - Registers that provide the right functionality with their reset defaults.
1966 *
1967 * TODO: Except for registers that based on the above 3 criteria can be safely
1968 * ignored, we save/restore all others, practically treating the HW context as
1969 * a black-box for the driver. Further investigation is needed to reduce the
1970 * saved/restored registers even further, by following the same 3 criteria.
1971 */
1972static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1973{
1974	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1975	int i;
1976
1977	/* GAM 0x4000-0x4770 */
1978	s->wr_watermark		= I915_READ(GEN7_WR_WATERMARK);
1979	s->gfx_prio_ctrl	= I915_READ(GEN7_GFX_PRIO_CTRL);
1980	s->arb_mode		= I915_READ(ARB_MODE);
1981	s->gfx_pend_tlb0	= I915_READ(GEN7_GFX_PEND_TLB0);
1982	s->gfx_pend_tlb1	= I915_READ(GEN7_GFX_PEND_TLB1);
1983
1984	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1985		s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1986
1987	s->media_max_req_count	= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1988	s->gfx_max_req_count	= I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1989
1990	s->render_hwsp		= I915_READ(RENDER_HWS_PGA_GEN7);
1991	s->ecochk		= I915_READ(GAM_ECOCHK);
1992	s->bsd_hwsp		= I915_READ(BSD_HWS_PGA_GEN7);
1993	s->blt_hwsp		= I915_READ(BLT_HWS_PGA_GEN7);
1994
1995	s->tlb_rd_addr		= I915_READ(GEN7_TLB_RD_ADDR);
1996
1997	/* MBC 0x9024-0x91D0, 0x8500 */
1998	s->g3dctl		= I915_READ(VLV_G3DCTL);
1999	s->gsckgctl		= I915_READ(VLV_GSCKGCTL);
2000	s->mbctl		= I915_READ(GEN6_MBCTL);
2001
2002	/* GCP 0x9400-0x9424, 0x8100-0x810C */
2003	s->ucgctl1		= I915_READ(GEN6_UCGCTL1);
2004	s->ucgctl3		= I915_READ(GEN6_UCGCTL3);
2005	s->rcgctl1		= I915_READ(GEN6_RCGCTL1);
2006	s->rcgctl2		= I915_READ(GEN6_RCGCTL2);
2007	s->rstctl		= I915_READ(GEN6_RSTCTL);
2008	s->misccpctl		= I915_READ(GEN7_MISCCPCTL);
2009
2010	/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2011	s->gfxpause		= I915_READ(GEN6_GFXPAUSE);
2012	s->rpdeuhwtc		= I915_READ(GEN6_RPDEUHWTC);
2013	s->rpdeuc		= I915_READ(GEN6_RPDEUC);
2014	s->ecobus		= I915_READ(ECOBUS);
2015	s->pwrdwnupctl		= I915_READ(VLV_PWRDWNUPCTL);
2016	s->rp_down_timeout	= I915_READ(GEN6_RP_DOWN_TIMEOUT);
2017	s->rp_deucsw		= I915_READ(GEN6_RPDEUCSW);
2018	s->rcubmabdtmr		= I915_READ(GEN6_RCUBMABDTMR);
2019	s->rcedata		= I915_READ(VLV_RCEDATA);
2020	s->spare2gh		= I915_READ(VLV_SPAREG2H);
2021
2022	/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2023	s->gt_imr		= I915_READ(GTIMR);
2024	s->gt_ier		= I915_READ(GTIER);
2025	s->pm_imr		= I915_READ(GEN6_PMIMR);
2026	s->pm_ier		= I915_READ(GEN6_PMIER);
2027
2028	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2029		s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2030
2031	/* GT SA CZ domain, 0x100000-0x138124 */
2032	s->tilectl		= I915_READ(TILECTL);
2033	s->gt_fifoctl		= I915_READ(GTFIFOCTL);
2034	s->gtlc_wake_ctrl	= I915_READ(VLV_GTLC_WAKE_CTRL);
2035	s->gtlc_survive		= I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2036	s->pmwgicz		= I915_READ(VLV_PMWGICZ);
2037
2038	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
2039	s->gu_ctl0		= I915_READ(VLV_GU_CTL0);
2040	s->gu_ctl1		= I915_READ(VLV_GU_CTL1);
2041	s->pcbr			= I915_READ(VLV_PCBR);
2042	s->clock_gate_dis2	= I915_READ(VLV_GUNIT_CLOCK_GATE2);
2043
2044	/*
2045	 * Not saving any of:
2046	 * DFT,		0x9800-0x9EC0
2047	 * SARB,	0xB000-0xB1FC
2048	 * GAC,		0x5208-0x524C, 0x14000-0x14C000
2049	 * PCI CFG
2050	 */
2051}
2052
2053static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2054{
2055	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2056	u32 val;
2057	int i;
2058
2059	/* GAM 0x4000-0x4770 */
2060	I915_WRITE(GEN7_WR_WATERMARK,	s->wr_watermark);
2061	I915_WRITE(GEN7_GFX_PRIO_CTRL,	s->gfx_prio_ctrl);
2062	I915_WRITE(ARB_MODE,		s->arb_mode | (0xffff << 16));
2063	I915_WRITE(GEN7_GFX_PEND_TLB0,	s->gfx_pend_tlb0);
2064	I915_WRITE(GEN7_GFX_PEND_TLB1,	s->gfx_pend_tlb1);
2065
2066	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2067		I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2068
2069	I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2070	I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2071
2072	I915_WRITE(RENDER_HWS_PGA_GEN7,	s->render_hwsp);
2073	I915_WRITE(GAM_ECOCHK,		s->ecochk);
2074	I915_WRITE(BSD_HWS_PGA_GEN7,	s->bsd_hwsp);
2075	I915_WRITE(BLT_HWS_PGA_GEN7,	s->blt_hwsp);
2076
2077	I915_WRITE(GEN7_TLB_RD_ADDR,	s->tlb_rd_addr);
2078
2079	/* MBC 0x9024-0x91D0, 0x8500 */
2080	I915_WRITE(VLV_G3DCTL,		s->g3dctl);
2081	I915_WRITE(VLV_GSCKGCTL,	s->gsckgctl);
2082	I915_WRITE(GEN6_MBCTL,		s->mbctl);
2083
2084	/* GCP 0x9400-0x9424, 0x8100-0x810C */
2085	I915_WRITE(GEN6_UCGCTL1,	s->ucgctl1);
2086	I915_WRITE(GEN6_UCGCTL3,	s->ucgctl3);
2087	I915_WRITE(GEN6_RCGCTL1,	s->rcgctl1);
2088	I915_WRITE(GEN6_RCGCTL2,	s->rcgctl2);
2089	I915_WRITE(GEN6_RSTCTL,		s->rstctl);
2090	I915_WRITE(GEN7_MISCCPCTL,	s->misccpctl);
2091
2092	/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2093	I915_WRITE(GEN6_GFXPAUSE,	s->gfxpause);
2094	I915_WRITE(GEN6_RPDEUHWTC,	s->rpdeuhwtc);
2095	I915_WRITE(GEN6_RPDEUC,		s->rpdeuc);
2096	I915_WRITE(ECOBUS,		s->ecobus);
2097	I915_WRITE(VLV_PWRDWNUPCTL,	s->pwrdwnupctl);
2098	I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2099	I915_WRITE(GEN6_RPDEUCSW,	s->rp_deucsw);
2100	I915_WRITE(GEN6_RCUBMABDTMR,	s->rcubmabdtmr);
2101	I915_WRITE(VLV_RCEDATA,		s->rcedata);
2102	I915_WRITE(VLV_SPAREG2H,	s->spare2gh);
2103
2104	/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2105	I915_WRITE(GTIMR,		s->gt_imr);
2106	I915_WRITE(GTIER,		s->gt_ier);
2107	I915_WRITE(GEN6_PMIMR,		s->pm_imr);
2108	I915_WRITE(GEN6_PMIER,		s->pm_ier);
2109
2110	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2111		I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2112
2113	/* GT SA CZ domain, 0x100000-0x138124 */
2114	I915_WRITE(TILECTL,			s->tilectl);
2115	I915_WRITE(GTFIFOCTL,			s->gt_fifoctl);
2116	/*
2117	 * Preserve the GT allow wake and GFX force clock bit, they are not
2118	 * be restored, as they are used to control the s0ix suspend/resume
2119	 * sequence by the caller.
2120	 */
2121	val = I915_READ(VLV_GTLC_WAKE_CTRL);
2122	val &= VLV_GTLC_ALLOWWAKEREQ;
2123	val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2124	I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2125
2126	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2127	val &= VLV_GFX_CLK_FORCE_ON_BIT;
2128	val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2129	I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2130
2131	I915_WRITE(VLV_PMWGICZ,			s->pmwgicz);
2132
2133	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
2134	I915_WRITE(VLV_GU_CTL0,			s->gu_ctl0);
2135	I915_WRITE(VLV_GU_CTL1,			s->gu_ctl1);
2136	I915_WRITE(VLV_PCBR,			s->pcbr);
2137	I915_WRITE(VLV_GUNIT_CLOCK_GATE2,	s->clock_gate_dis2);
2138}
2139
2140int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2141{
2142	u32 val;
2143	int err;
2144
2145	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2146	val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2147	if (force_on)
2148		val |= VLV_GFX_CLK_FORCE_ON_BIT;
2149	I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2150
2151	if (!force_on)
2152		return 0;
2153
2154	err = intel_wait_for_register(dev_priv,
2155				      VLV_GTLC_SURVIVABILITY_REG,
2156				      VLV_GFX_CLK_STATUS_BIT,
2157				      VLV_GFX_CLK_STATUS_BIT,
2158				      20);
2159	if (err)
2160		DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2161			  I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2162
2163	return err;
2164}
2165
2166static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2167{
2168	u32 val;
2169	int err = 0;
2170
2171	val = I915_READ(VLV_GTLC_WAKE_CTRL);
2172	val &= ~VLV_GTLC_ALLOWWAKEREQ;
2173	if (allow)
2174		val |= VLV_GTLC_ALLOWWAKEREQ;
2175	I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2176	POSTING_READ(VLV_GTLC_WAKE_CTRL);
2177
2178	err = intel_wait_for_register(dev_priv,
2179				      VLV_GTLC_PW_STATUS,
2180				      VLV_GTLC_ALLOWWAKEACK,
2181				      allow,
2182				      1);
2183	if (err)
2184		DRM_ERROR("timeout disabling GT waking\n");
2185
2186	return err;
2187}
2188
2189static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2190				 bool wait_for_on)
2191{
2192	u32 mask;
2193	u32 val;
2194	int err;
2195
2196	mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2197	val = wait_for_on ? mask : 0;
2198	if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
2199		return 0;
2200
2201	DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
2202		      onoff(wait_for_on),
2203		      I915_READ(VLV_GTLC_PW_STATUS));
2204
2205	/*
2206	 * RC6 transitioning can be delayed up to 2 msec (see
2207	 * valleyview_enable_rps), use 3 msec for safety.
2208	 */
2209	err = intel_wait_for_register(dev_priv,
2210				      VLV_GTLC_PW_STATUS, mask, val,
2211				      3);
2212	if (err)
2213		DRM_ERROR("timeout waiting for GT wells to go %s\n",
2214			  onoff(wait_for_on));
2215
2216	return err;
2217}
2218
2219static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2220{
2221	if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2222		return;
2223
2224	DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2225	I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2226}
2227
2228static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2229{
2230	u32 mask;
2231	int err;
2232
2233	/*
2234	 * Bspec defines the following GT well on flags as debug only, so
2235	 * don't treat them as hard failures.
2236	 */
2237	(void)vlv_wait_for_gt_wells(dev_priv, false);
2238
2239	mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2240	WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2241
2242	vlv_check_no_gt_access(dev_priv);
2243
2244	err = vlv_force_gfx_clock(dev_priv, true);
2245	if (err)
2246		goto err1;
2247
2248	err = vlv_allow_gt_wake(dev_priv, false);
2249	if (err)
2250		goto err2;
2251
2252	if (!IS_CHERRYVIEW(dev_priv))
2253		vlv_save_gunit_s0ix_state(dev_priv);
2254
2255	err = vlv_force_gfx_clock(dev_priv, false);
2256	if (err)
2257		goto err2;
2258
2259	return 0;
2260
2261err2:
2262	/* For safety always re-enable waking and disable gfx clock forcing */
2263	vlv_allow_gt_wake(dev_priv, true);
2264err1:
2265	vlv_force_gfx_clock(dev_priv, false);
2266
2267	return err;
2268}
2269
2270static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2271				bool rpm_resume)
2272{
2273	int err;
2274	int ret;
2275
2276	/*
2277	 * If any of the steps fail just try to continue, that's the best we
2278	 * can do at this point. Return the first error code (which will also
2279	 * leave RPM permanently disabled).
2280	 */
2281	ret = vlv_force_gfx_clock(dev_priv, true);
2282
2283	if (!IS_CHERRYVIEW(dev_priv))
2284		vlv_restore_gunit_s0ix_state(dev_priv);
2285
2286	err = vlv_allow_gt_wake(dev_priv, true);
2287	if (!ret)
2288		ret = err;
2289
2290	err = vlv_force_gfx_clock(dev_priv, false);
2291	if (!ret)
2292		ret = err;
2293
2294	vlv_check_no_gt_access(dev_priv);
2295
2296	if (rpm_resume)
2297		intel_init_clock_gating(dev_priv);
2298
2299	return ret;
2300}
2301
2302static int intel_runtime_suspend(struct device *kdev)
2303{
2304	struct pci_dev *pdev = to_pci_dev(kdev);
2305	struct drm_device *dev = pci_get_drvdata(pdev);
2306	struct drm_i915_private *dev_priv = to_i915(dev);
2307	int ret;
2308
2309	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2310		return -ENODEV;
2311
2312	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2313		return -ENODEV;
2314
2315	DRM_DEBUG_KMS("Suspending device\n");
2316
2317	disable_rpm_wakeref_asserts(dev_priv);
2318
2319	/*
2320	 * We are safe here against re-faults, since the fault handler takes
2321	 * an RPM reference.
2322	 */
2323	i915_gem_runtime_suspend(dev_priv);
2324
2325	intel_guc_suspend(dev);
2326
2327	intel_runtime_pm_disable_interrupts(dev_priv);
2328
2329	ret = 0;
2330	if (IS_BROXTON(dev_priv)) {
2331		bxt_display_core_uninit(dev_priv);
2332		bxt_enable_dc9(dev_priv);
2333	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2334		hsw_enable_pc8(dev_priv);
2335	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2336		ret = vlv_suspend_complete(dev_priv);
2337	}
2338
2339	if (ret) {
2340		DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2341		intel_runtime_pm_enable_interrupts(dev_priv);
2342
2343		enable_rpm_wakeref_asserts(dev_priv);
2344
2345		return ret;
2346	}
2347
2348	intel_uncore_forcewake_reset(dev_priv, false);
2349
2350	enable_rpm_wakeref_asserts(dev_priv);
2351	WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2352
2353	if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2354		DRM_ERROR("Unclaimed access detected prior to suspending\n");
2355
2356	dev_priv->pm.suspended = true;
2357
2358	/*
2359	 * FIXME: We really should find a document that references the arguments
2360	 * used below!
2361	 */
2362	if (IS_BROADWELL(dev_priv)) {
2363		/*
2364		 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2365		 * being detected, and the call we do at intel_runtime_resume()
2366		 * won't be able to restore them. Since PCI_D3hot matches the
2367		 * actual specification and appears to be working, use it.
2368		 */
2369		intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2370	} else {
2371		/*
2372		 * current versions of firmware which depend on this opregion
2373		 * notification have repurposed the D1 definition to mean
2374		 * "runtime suspended" vs. what you would normally expect (D3)
2375		 * to distinguish it from notifications that might be sent via
2376		 * the suspend path.
2377		 */
2378		intel_opregion_notify_adapter(dev_priv, PCI_D1);
2379	}
2380
2381	assert_forcewakes_inactive(dev_priv);
2382
2383	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2384		intel_hpd_poll_init(dev_priv);
2385
2386	DRM_DEBUG_KMS("Device suspended\n");
2387	return 0;
2388}
2389
2390static int intel_runtime_resume(struct device *kdev)
2391{
2392	struct pci_dev *pdev = to_pci_dev(kdev);
2393	struct drm_device *dev = pci_get_drvdata(pdev);
2394	struct drm_i915_private *dev_priv = to_i915(dev);
2395	int ret = 0;
2396
2397	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2398		return -ENODEV;
2399
2400	DRM_DEBUG_KMS("Resuming device\n");
2401
2402	WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2403	disable_rpm_wakeref_asserts(dev_priv);
2404
2405	intel_opregion_notify_adapter(dev_priv, PCI_D0);
2406	dev_priv->pm.suspended = false;
2407	if (intel_uncore_unclaimed_mmio(dev_priv))
2408		DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2409
2410	intel_guc_resume(dev);
2411
2412	if (IS_GEN6(dev_priv))
2413		intel_init_pch_refclk(dev);
2414
2415	if (IS_BROXTON(dev_priv)) {
2416		bxt_disable_dc9(dev_priv);
2417		bxt_display_core_init(dev_priv, true);
2418		if (dev_priv->csr.dmc_payload &&
2419		    (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2420			gen9_enable_dc5(dev_priv);
2421	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2422		hsw_disable_pc8(dev_priv);
2423	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2424		ret = vlv_resume_prepare(dev_priv, true);
2425	}
2426
2427	/*
2428	 * No point of rolling back things in case of an error, as the best
2429	 * we can do is to hope that things will still work (and disable RPM).
2430	 */
2431	i915_gem_init_swizzling(dev_priv);
2432	i915_gem_restore_fences(dev_priv);
2433
2434	intel_runtime_pm_enable_interrupts(dev_priv);
2435
2436	/*
2437	 * On VLV/CHV display interrupts are part of the display
2438	 * power well, so hpd is reinitialized from there. For
2439	 * everyone else do it here.
2440	 */
2441	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2442		intel_hpd_init(dev_priv);
2443
2444	enable_rpm_wakeref_asserts(dev_priv);
2445
2446	if (ret)
2447		DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2448	else
2449		DRM_DEBUG_KMS("Device resumed\n");
2450
2451	return ret;
2452}
2453
2454const struct dev_pm_ops i915_pm_ops = {
2455	/*
2456	 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2457	 * PMSG_RESUME]
2458	 */
2459	.suspend = i915_pm_suspend,
2460	.suspend_late = i915_pm_suspend_late,
2461	.resume_early = i915_pm_resume_early,
2462	.resume = i915_pm_resume,
2463
2464	/*
2465	 * S4 event handlers
2466	 * @freeze, @freeze_late    : called (1) before creating the
2467	 *                            hibernation image [PMSG_FREEZE] and
2468	 *                            (2) after rebooting, before restoring
2469	 *                            the image [PMSG_QUIESCE]
2470	 * @thaw, @thaw_early       : called (1) after creating the hibernation
2471	 *                            image, before writing it [PMSG_THAW]
2472	 *                            and (2) after failing to create or
2473	 *                            restore the image [PMSG_RECOVER]
2474	 * @poweroff, @poweroff_late: called after writing the hibernation
2475	 *                            image, before rebooting [PMSG_HIBERNATE]
2476	 * @restore, @restore_early : called after rebooting and restoring the
2477	 *                            hibernation image [PMSG_RESTORE]
2478	 */
2479	.freeze = i915_pm_freeze,
2480	.freeze_late = i915_pm_freeze_late,
2481	.thaw_early = i915_pm_thaw_early,
2482	.thaw = i915_pm_thaw,
2483	.poweroff = i915_pm_suspend,
2484	.poweroff_late = i915_pm_poweroff_late,
2485	.restore_early = i915_pm_restore_early,
2486	.restore = i915_pm_restore,
2487
2488	/* S0ix (via runtime suspend) event handlers */
2489	.runtime_suspend = intel_runtime_suspend,
2490	.runtime_resume = intel_runtime_resume,
2491};
2492
2493static const struct vm_operations_struct i915_gem_vm_ops = {
2494	.fault = i915_gem_fault,
2495	.open = drm_gem_vm_open,
2496	.close = drm_gem_vm_close,
2497};
2498
2499static const struct file_operations i915_driver_fops = {
2500	.owner = THIS_MODULE,
2501	.open = drm_open,
2502	.release = drm_release,
2503	.unlocked_ioctl = drm_ioctl,
2504	.mmap = drm_gem_mmap,
2505	.poll = drm_poll,
2506	.read = drm_read,
2507	.compat_ioctl = i915_compat_ioctl,
2508	.llseek = noop_llseek,
2509};
2510
2511static int
2512i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2513			  struct drm_file *file)
2514{
2515	return -ENODEV;
2516}
2517
2518static const struct drm_ioctl_desc i915_ioctls[] = {
2519	DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2520	DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2521	DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2522	DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2523	DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2524	DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2525	DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2526	DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2527	DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2528	DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2529	DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2530	DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2531	DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2532	DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2533	DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2534	DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2535	DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2536	DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2537	DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2538	DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2539	DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2540	DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2541	DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2542	DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2543	DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2544	DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2545	DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2546	DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2547	DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2548	DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2549	DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2550	DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2551	DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2552	DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2553	DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2554	DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
2555	DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
2556	DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2557	DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2558	DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2559	DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2560	DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2561	DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2562	DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2563	DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2564	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2565	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2566	DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2567	DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2568	DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2569	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2570	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2571};
2572
2573static struct drm_driver driver = {
2574	/* Don't use MTRRs here; the Xserver or userspace app should
2575	 * deal with them for Intel hardware.
2576	 */
2577	.driver_features =
2578	    DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2579	    DRIVER_RENDER | DRIVER_MODESET,
2580	.open = i915_driver_open,
2581	.lastclose = i915_driver_lastclose,
2582	.preclose = i915_driver_preclose,
2583	.postclose = i915_driver_postclose,
2584	.set_busid = drm_pci_set_busid,
2585
2586	.gem_close_object = i915_gem_close_object,
2587	.gem_free_object_unlocked = i915_gem_free_object,
2588	.gem_vm_ops = &i915_gem_vm_ops,
2589
2590	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2591	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2592	.gem_prime_export = i915_gem_prime_export,
2593	.gem_prime_import = i915_gem_prime_import,
2594
2595	.dumb_create = i915_gem_dumb_create,
2596	.dumb_map_offset = i915_gem_mmap_gtt,
2597	.dumb_destroy = drm_gem_dumb_destroy,
2598	.ioctls = i915_ioctls,
2599	.num_ioctls = ARRAY_SIZE(i915_ioctls),
2600	.fops = &i915_driver_fops,
2601	.name = DRIVER_NAME,
2602	.desc = DRIVER_DESC,
2603	.date = DRIVER_DATE,
2604	.major = DRIVER_MAJOR,
2605	.minor = DRIVER_MINOR,
2606	.patchlevel = DRIVER_PATCHLEVEL,
2607};