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1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_pm.h"
27#include "amdgpu_dpm.h"
28#include "amdgpu_atombios.h"
29#include "si/sid.h"
30#include "r600_dpm.h"
31#include "si_dpm.h"
32#include "atom.h"
33#include "../include/pptable.h"
34#include <linux/math64.h>
35#include <linux/seq_file.h>
36#include <linux/firmware.h>
37
38#define MC_CG_ARB_FREQ_F0 0x0a
39#define MC_CG_ARB_FREQ_F1 0x0b
40#define MC_CG_ARB_FREQ_F2 0x0c
41#define MC_CG_ARB_FREQ_F3 0x0d
42
43#define SMC_RAM_END 0x20000
44
45#define SCLK_MIN_DEEPSLEEP_FREQ 1350
46
47
48/* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
49#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
50#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
51#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
52#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
53#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
54#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
55
56#define BIOS_SCRATCH_4 0x5cd
57
58MODULE_FIRMWARE("radeon/tahiti_smc.bin");
59MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
60MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
61MODULE_FIRMWARE("radeon/verde_smc.bin");
62MODULE_FIRMWARE("radeon/verde_k_smc.bin");
63MODULE_FIRMWARE("radeon/oland_smc.bin");
64MODULE_FIRMWARE("radeon/oland_k_smc.bin");
65MODULE_FIRMWARE("radeon/hainan_smc.bin");
66MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
67MODULE_FIRMWARE("radeon/banks_k_2_smc.bin");
68
69union power_info {
70 struct _ATOM_POWERPLAY_INFO info;
71 struct _ATOM_POWERPLAY_INFO_V2 info_2;
72 struct _ATOM_POWERPLAY_INFO_V3 info_3;
73 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
74 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
75 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
76 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
77 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
78};
79
80union fan_info {
81 struct _ATOM_PPLIB_FANTABLE fan;
82 struct _ATOM_PPLIB_FANTABLE2 fan2;
83 struct _ATOM_PPLIB_FANTABLE3 fan3;
84};
85
86union pplib_clock_info {
87 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
88 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
89 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
90 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
91 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
92};
93
94static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
95{
96 R600_UTC_DFLT_00,
97 R600_UTC_DFLT_01,
98 R600_UTC_DFLT_02,
99 R600_UTC_DFLT_03,
100 R600_UTC_DFLT_04,
101 R600_UTC_DFLT_05,
102 R600_UTC_DFLT_06,
103 R600_UTC_DFLT_07,
104 R600_UTC_DFLT_08,
105 R600_UTC_DFLT_09,
106 R600_UTC_DFLT_10,
107 R600_UTC_DFLT_11,
108 R600_UTC_DFLT_12,
109 R600_UTC_DFLT_13,
110 R600_UTC_DFLT_14,
111};
112
113static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
114{
115 R600_DTC_DFLT_00,
116 R600_DTC_DFLT_01,
117 R600_DTC_DFLT_02,
118 R600_DTC_DFLT_03,
119 R600_DTC_DFLT_04,
120 R600_DTC_DFLT_05,
121 R600_DTC_DFLT_06,
122 R600_DTC_DFLT_07,
123 R600_DTC_DFLT_08,
124 R600_DTC_DFLT_09,
125 R600_DTC_DFLT_10,
126 R600_DTC_DFLT_11,
127 R600_DTC_DFLT_12,
128 R600_DTC_DFLT_13,
129 R600_DTC_DFLT_14,
130};
131
132static const struct si_cac_config_reg cac_weights_tahiti[] =
133{
134 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
135 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
136 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
137 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
138 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
139 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
140 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
141 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
142 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
143 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
144 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
145 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
146 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
147 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
148 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
149 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
150 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
151 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
152 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
153 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
154 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
155 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
156 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
157 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
158 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
159 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
160 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
161 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
162 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
163 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
164 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
165 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
166 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
167 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
168 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
169 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
170 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
171 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
172 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
173 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
174 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
175 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
176 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
177 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
178 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
179 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
180 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
181 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
182 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
183 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
184 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
185 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
186 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
187 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
188 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
189 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
190 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
191 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
192 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
193 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
194 { 0xFFFFFFFF }
195};
196
197static const struct si_cac_config_reg lcac_tahiti[] =
198{
199 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
200 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
201 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
202 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
203 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
204 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
205 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
206 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
207 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
208 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
209 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
210 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
211 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
212 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
213 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
214 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
215 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
216 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
217 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
218 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
219 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
220 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
221 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
222 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
223 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
224 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
225 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
226 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
227 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
228 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
229 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
230 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
231 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
232 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
233 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
234 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
235 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
236 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
237 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
238 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
239 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
240 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
241 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
242 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
243 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
244 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
245 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
246 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
247 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
248 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
249 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
250 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
251 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
252 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
253 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
254 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
255 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
256 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
257 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
258 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
259 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
260 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
261 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
262 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
263 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
264 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
265 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
266 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
267 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
268 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
269 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
270 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
271 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
272 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
273 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
274 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
275 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
276 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
277 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
278 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
279 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
280 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
281 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
282 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
283 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
284 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
285 { 0xFFFFFFFF }
286
287};
288
289static const struct si_cac_config_reg cac_override_tahiti[] =
290{
291 { 0xFFFFFFFF }
292};
293
294static const struct si_powertune_data powertune_data_tahiti =
295{
296 ((1 << 16) | 27027),
297 6,
298 0,
299 4,
300 95,
301 {
302 0UL,
303 0UL,
304 4521550UL,
305 309631529UL,
306 -1270850L,
307 4513710L,
308 40
309 },
310 595000000UL,
311 12,
312 {
313 0,
314 0,
315 0,
316 0,
317 0,
318 0,
319 0,
320 0
321 },
322 true
323};
324
325static const struct si_dte_data dte_data_tahiti =
326{
327 { 1159409, 0, 0, 0, 0 },
328 { 777, 0, 0, 0, 0 },
329 2,
330 54000,
331 127000,
332 25,
333 2,
334 10,
335 13,
336 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
337 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
338 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
339 85,
340 false
341};
342
343#if 0
344static const struct si_dte_data dte_data_tahiti_le =
345{
346 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
347 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
348 0x5,
349 0xAFC8,
350 0x64,
351 0x32,
352 1,
353 0,
354 0x10,
355 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
356 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
357 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
358 85,
359 true
360};
361#endif
362
363static const struct si_dte_data dte_data_tahiti_pro =
364{
365 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
366 { 0x0, 0x0, 0x0, 0x0, 0x0 },
367 5,
368 45000,
369 100,
370 0xA,
371 1,
372 0,
373 0x10,
374 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
375 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
376 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
377 90,
378 true
379};
380
381static const struct si_dte_data dte_data_new_zealand =
382{
383 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
384 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
385 0x5,
386 0xAFC8,
387 0x69,
388 0x32,
389 1,
390 0,
391 0x10,
392 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
393 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
394 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
395 85,
396 true
397};
398
399static const struct si_dte_data dte_data_aruba_pro =
400{
401 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
402 { 0x0, 0x0, 0x0, 0x0, 0x0 },
403 5,
404 45000,
405 100,
406 0xA,
407 1,
408 0,
409 0x10,
410 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
411 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
412 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
413 90,
414 true
415};
416
417static const struct si_dte_data dte_data_malta =
418{
419 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
420 { 0x0, 0x0, 0x0, 0x0, 0x0 },
421 5,
422 45000,
423 100,
424 0xA,
425 1,
426 0,
427 0x10,
428 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
429 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
430 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
431 90,
432 true
433};
434
435static const struct si_cac_config_reg cac_weights_pitcairn[] =
436{
437 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
438 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
439 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
440 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
441 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
442 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
443 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
444 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
445 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
446 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
447 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
448 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
449 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
450 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
451 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
452 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
453 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
454 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
455 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
456 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
457 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
458 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
459 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
460 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
461 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
462 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
463 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
464 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
465 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
466 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
467 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
468 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
469 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
470 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
471 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
472 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
473 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
474 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
475 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
476 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
477 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
478 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
479 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
480 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
481 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
482 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
483 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
484 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
485 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
486 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
487 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
488 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
489 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
490 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
491 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
492 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
493 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
494 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
495 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
496 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
497 { 0xFFFFFFFF }
498};
499
500static const struct si_cac_config_reg lcac_pitcairn[] =
501{
502 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
503 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
504 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
505 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
506 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
507 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
508 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
509 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
510 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
511 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
512 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
513 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
514 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
515 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
516 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
517 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
518 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
519 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
520 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
521 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
522 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
523 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
524 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
525 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
526 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
527 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
528 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
529 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
530 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
531 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
532 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
533 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
534 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
535 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
536 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
537 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
538 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
539 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
540 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
541 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
542 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
543 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
544 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
545 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
546 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
547 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
548 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
549 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
550 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
551 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
552 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
553 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
554 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
555 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
556 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
557 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
558 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
559 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
560 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
561 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
562 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
563 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
564 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
565 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
566 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
567 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
568 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
569 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
570 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
571 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
572 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
573 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
574 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
575 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
576 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
577 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
578 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
579 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
580 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
581 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
582 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
583 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
584 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
585 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
586 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
587 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
588 { 0xFFFFFFFF }
589};
590
591static const struct si_cac_config_reg cac_override_pitcairn[] =
592{
593 { 0xFFFFFFFF }
594};
595
596static const struct si_powertune_data powertune_data_pitcairn =
597{
598 ((1 << 16) | 27027),
599 5,
600 0,
601 6,
602 100,
603 {
604 51600000UL,
605 1800000UL,
606 7194395UL,
607 309631529UL,
608 -1270850L,
609 4513710L,
610 100
611 },
612 117830498UL,
613 12,
614 {
615 0,
616 0,
617 0,
618 0,
619 0,
620 0,
621 0,
622 0
623 },
624 true
625};
626
627static const struct si_dte_data dte_data_pitcairn =
628{
629 { 0, 0, 0, 0, 0 },
630 { 0, 0, 0, 0, 0 },
631 0,
632 0,
633 0,
634 0,
635 0,
636 0,
637 0,
638 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
639 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
640 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
641 0,
642 false
643};
644
645static const struct si_dte_data dte_data_curacao_xt =
646{
647 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
648 { 0x0, 0x0, 0x0, 0x0, 0x0 },
649 5,
650 45000,
651 100,
652 0xA,
653 1,
654 0,
655 0x10,
656 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
657 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
658 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
659 90,
660 true
661};
662
663static const struct si_dte_data dte_data_curacao_pro =
664{
665 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
666 { 0x0, 0x0, 0x0, 0x0, 0x0 },
667 5,
668 45000,
669 100,
670 0xA,
671 1,
672 0,
673 0x10,
674 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
675 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
676 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
677 90,
678 true
679};
680
681static const struct si_dte_data dte_data_neptune_xt =
682{
683 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
684 { 0x0, 0x0, 0x0, 0x0, 0x0 },
685 5,
686 45000,
687 100,
688 0xA,
689 1,
690 0,
691 0x10,
692 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
693 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
694 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
695 90,
696 true
697};
698
699static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
700{
701 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
702 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
703 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
704 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
705 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
706 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
707 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
708 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
709 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
710 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
711 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
712 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
713 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
714 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
715 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
716 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
717 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
718 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
719 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
720 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
721 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
722 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
723 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
724 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
725 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
726 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
727 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
728 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
729 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
730 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
731 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
732 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
733 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
734 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
735 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
736 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
737 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
738 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
739 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
740 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
741 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
742 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
743 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
744 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
746 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
747 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
748 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
749 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
750 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
751 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
752 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
753 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
754 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
755 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
756 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
757 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
758 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
759 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
760 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
761 { 0xFFFFFFFF }
762};
763
764static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
765{
766 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
767 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
768 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
769 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
770 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
771 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
772 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
773 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
774 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
775 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
776 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
777 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
778 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
779 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
780 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
781 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
782 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
783 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
784 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
785 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
786 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
787 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
788 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
789 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
790 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
791 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
792 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
793 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
794 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
795 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
796 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
797 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
798 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
799 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
800 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
801 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
802 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
803 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
804 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
805 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
806 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
807 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
808 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
809 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
810 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
811 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
812 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
813 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
814 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
815 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
816 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
817 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
818 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
819 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
820 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
821 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
822 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
823 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
824 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
825 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
826 { 0xFFFFFFFF }
827};
828
829static const struct si_cac_config_reg cac_weights_heathrow[] =
830{
831 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
832 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
833 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
834 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
835 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
836 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
837 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
838 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
839 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
840 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
841 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
842 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
843 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
844 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
845 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
846 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
847 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
848 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
849 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
850 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
851 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
852 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
853 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
854 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
855 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
856 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
857 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
858 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
859 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
860 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
861 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
862 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
863 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
864 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
865 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
866 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
867 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
868 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
869 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
870 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
871 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
872 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
873 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
874 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
876 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
877 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
878 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
879 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
880 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
881 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
882 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
883 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
884 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
885 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
886 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
887 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
888 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
889 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
890 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
891 { 0xFFFFFFFF }
892};
893
894static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
895{
896 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
897 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
898 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
899 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
900 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
901 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
902 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
903 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
904 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
905 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
906 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
907 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
908 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
909 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
910 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
911 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
912 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
913 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
914 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
915 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
916 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
917 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
918 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
919 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
920 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
921 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
922 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
923 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
924 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
925 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
926 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
927 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
928 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
929 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
930 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
931 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
932 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
933 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
934 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
935 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
936 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
937 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
938 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
939 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
940 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
941 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
942 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
943 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
944 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
945 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
946 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
947 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
948 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
949 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
950 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
951 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
952 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
953 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
954 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
955 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
956 { 0xFFFFFFFF }
957};
958
959static const struct si_cac_config_reg cac_weights_cape_verde[] =
960{
961 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
962 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
963 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
964 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
965 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
966 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
967 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
968 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
969 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
970 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
971 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
972 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
973 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
974 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
975 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
976 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
977 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
978 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
979 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
980 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
981 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
982 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
983 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
984 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
985 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
986 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
987 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
988 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
989 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
990 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
991 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
992 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
993 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
994 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
995 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
996 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
997 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
998 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
999 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1000 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1001 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1002 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1003 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1004 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1005 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1006 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1007 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1008 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1009 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1010 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1011 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1012 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1013 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1014 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1015 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1016 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1017 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1018 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1019 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1020 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1021 { 0xFFFFFFFF }
1022};
1023
1024static const struct si_cac_config_reg lcac_cape_verde[] =
1025{
1026 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1027 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1028 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1029 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1030 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1031 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1032 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1033 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1034 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1035 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1036 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1037 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1038 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1039 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1040 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1041 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1042 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1043 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1044 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1045 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1046 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1047 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1048 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1049 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1050 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1051 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1052 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1053 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1054 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1055 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1056 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1057 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1058 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1059 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1060 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1061 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1062 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1063 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1064 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1065 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1066 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1067 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1068 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1069 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1070 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1071 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1072 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1073 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1074 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1075 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1076 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1077 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1078 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1079 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1080 { 0xFFFFFFFF }
1081};
1082
1083static const struct si_cac_config_reg cac_override_cape_verde[] =
1084{
1085 { 0xFFFFFFFF }
1086};
1087
1088static const struct si_powertune_data powertune_data_cape_verde =
1089{
1090 ((1 << 16) | 0x6993),
1091 5,
1092 0,
1093 7,
1094 105,
1095 {
1096 0UL,
1097 0UL,
1098 7194395UL,
1099 309631529UL,
1100 -1270850L,
1101 4513710L,
1102 100
1103 },
1104 117830498UL,
1105 12,
1106 {
1107 0,
1108 0,
1109 0,
1110 0,
1111 0,
1112 0,
1113 0,
1114 0
1115 },
1116 true
1117};
1118
1119static const struct si_dte_data dte_data_cape_verde =
1120{
1121 { 0, 0, 0, 0, 0 },
1122 { 0, 0, 0, 0, 0 },
1123 0,
1124 0,
1125 0,
1126 0,
1127 0,
1128 0,
1129 0,
1130 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1131 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1132 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1133 0,
1134 false
1135};
1136
1137static const struct si_dte_data dte_data_venus_xtx =
1138{
1139 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1140 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1141 5,
1142 55000,
1143 0x69,
1144 0xA,
1145 1,
1146 0,
1147 0x3,
1148 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1149 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1150 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1151 90,
1152 true
1153};
1154
1155static const struct si_dte_data dte_data_venus_xt =
1156{
1157 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1158 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1159 5,
1160 55000,
1161 0x69,
1162 0xA,
1163 1,
1164 0,
1165 0x3,
1166 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1167 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1168 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1169 90,
1170 true
1171};
1172
1173static const struct si_dte_data dte_data_venus_pro =
1174{
1175 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1176 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1177 5,
1178 55000,
1179 0x69,
1180 0xA,
1181 1,
1182 0,
1183 0x3,
1184 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1185 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1186 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1187 90,
1188 true
1189};
1190
1191static const struct si_cac_config_reg cac_weights_oland[] =
1192{
1193 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1194 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1195 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1196 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1197 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1198 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1199 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1200 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1201 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1202 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1203 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1204 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1205 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1206 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1207 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1208 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1209 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1210 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1211 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1212 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1213 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1214 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1215 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1216 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1217 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1218 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1219 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1220 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1222 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1223 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1224 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1225 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1226 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1227 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1228 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1229 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1230 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1231 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1232 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1233 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1234 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1235 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1239 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1240 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1241 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1242 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1243 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1244 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1245 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1246 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1247 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1248 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1249 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1250 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1251 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1252 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1253 { 0xFFFFFFFF }
1254};
1255
1256static const struct si_cac_config_reg cac_weights_mars_pro[] =
1257{
1258 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1259 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1260 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1261 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1262 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1263 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1264 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1265 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1266 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1267 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1268 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1269 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1270 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1271 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1272 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1273 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1274 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1275 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1276 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1277 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1278 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1279 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1280 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1281 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1282 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1283 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1284 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1285 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1286 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1287 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1288 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1289 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1290 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1291 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1292 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1293 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1294 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1295 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1296 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1297 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1298 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1299 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1300 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1303 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1304 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1305 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1306 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1307 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1308 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1309 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1310 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1311 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1312 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1313 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1314 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1315 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1316 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1317 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1318 { 0xFFFFFFFF }
1319};
1320
1321static const struct si_cac_config_reg cac_weights_mars_xt[] =
1322{
1323 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1324 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1325 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1326 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1327 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1328 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1329 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1330 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1331 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1332 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1333 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1334 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1335 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1336 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1337 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1338 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1339 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1340 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1341 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1342 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1343 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1344 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1345 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1346 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1347 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1348 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1349 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1350 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1351 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1352 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1353 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1354 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1355 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1356 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1357 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1358 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1359 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1360 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1361 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1362 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1363 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1364 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1365 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1368 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1369 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1370 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1371 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1372 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1373 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1374 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1375 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1376 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1377 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1378 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1379 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1380 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1381 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1382 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1383 { 0xFFFFFFFF }
1384};
1385
1386static const struct si_cac_config_reg cac_weights_oland_pro[] =
1387{
1388 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1389 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1390 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1391 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1392 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1393 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1394 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1395 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1396 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1397 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1398 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1399 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1400 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1401 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1402 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1403 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1404 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1405 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1406 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1407 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1408 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1409 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1410 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1411 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1412 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1413 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1414 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1415 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1416 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1417 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1418 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1419 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1420 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1421 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1422 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1423 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1424 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1425 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1426 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1427 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1428 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1429 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1430 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1431 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1432 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1433 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1434 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1435 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1436 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1437 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1438 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1439 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1440 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1441 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1442 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1443 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1444 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1445 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1446 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1447 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1448 { 0xFFFFFFFF }
1449};
1450
1451static const struct si_cac_config_reg cac_weights_oland_xt[] =
1452{
1453 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1454 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1455 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1456 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1457 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1458 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1459 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1460 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1461 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1462 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1463 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1464 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1465 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1466 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1467 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1468 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1469 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1470 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1471 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1472 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1473 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1474 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1475 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1476 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1477 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1478 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1479 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1480 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1481 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1483 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1484 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1485 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1486 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1487 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1488 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1489 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1490 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1491 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1492 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1493 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1494 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1495 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1496 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1497 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1498 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1499 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1500 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1501 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1502 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1503 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1504 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1505 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1506 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1507 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1508 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1509 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1510 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1511 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1512 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1513 { 0xFFFFFFFF }
1514};
1515
1516static const struct si_cac_config_reg lcac_oland[] =
1517{
1518 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1519 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1520 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1521 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1522 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1523 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1524 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1525 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1526 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1527 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1528 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1529 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1530 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1531 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1532 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1533 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1534 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1535 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1536 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1537 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1538 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1539 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1540 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1541 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1542 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1543 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1544 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1545 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1546 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1547 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1548 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1549 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1550 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1551 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1552 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1553 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1554 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1555 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1556 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1557 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1558 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1559 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1560 { 0xFFFFFFFF }
1561};
1562
1563static const struct si_cac_config_reg lcac_mars_pro[] =
1564{
1565 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1566 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1567 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1568 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1569 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1570 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1571 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1572 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1573 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1574 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1575 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1576 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1577 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1578 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1579 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1580 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1581 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1582 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1583 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1584 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1585 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1586 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1587 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1588 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1589 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1590 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1591 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1592 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1593 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1594 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1595 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1596 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1597 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1598 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1599 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1600 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1601 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1602 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1603 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1604 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1605 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1606 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1607 { 0xFFFFFFFF }
1608};
1609
1610static const struct si_cac_config_reg cac_override_oland[] =
1611{
1612 { 0xFFFFFFFF }
1613};
1614
1615static const struct si_powertune_data powertune_data_oland =
1616{
1617 ((1 << 16) | 0x6993),
1618 5,
1619 0,
1620 7,
1621 105,
1622 {
1623 0UL,
1624 0UL,
1625 7194395UL,
1626 309631529UL,
1627 -1270850L,
1628 4513710L,
1629 100
1630 },
1631 117830498UL,
1632 12,
1633 {
1634 0,
1635 0,
1636 0,
1637 0,
1638 0,
1639 0,
1640 0,
1641 0
1642 },
1643 true
1644};
1645
1646static const struct si_powertune_data powertune_data_mars_pro =
1647{
1648 ((1 << 16) | 0x6993),
1649 5,
1650 0,
1651 7,
1652 105,
1653 {
1654 0UL,
1655 0UL,
1656 7194395UL,
1657 309631529UL,
1658 -1270850L,
1659 4513710L,
1660 100
1661 },
1662 117830498UL,
1663 12,
1664 {
1665 0,
1666 0,
1667 0,
1668 0,
1669 0,
1670 0,
1671 0,
1672 0
1673 },
1674 true
1675};
1676
1677static const struct si_dte_data dte_data_oland =
1678{
1679 { 0, 0, 0, 0, 0 },
1680 { 0, 0, 0, 0, 0 },
1681 0,
1682 0,
1683 0,
1684 0,
1685 0,
1686 0,
1687 0,
1688 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1689 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1690 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1691 0,
1692 false
1693};
1694
1695static const struct si_dte_data dte_data_mars_pro =
1696{
1697 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1698 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1699 5,
1700 55000,
1701 105,
1702 0xA,
1703 1,
1704 0,
1705 0x10,
1706 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1707 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1708 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1709 90,
1710 true
1711};
1712
1713static const struct si_dte_data dte_data_sun_xt =
1714{
1715 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1716 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1717 5,
1718 55000,
1719 105,
1720 0xA,
1721 1,
1722 0,
1723 0x10,
1724 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1725 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1726 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1727 90,
1728 true
1729};
1730
1731
1732static const struct si_cac_config_reg cac_weights_hainan[] =
1733{
1734 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1735 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1736 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1737 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1738 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1739 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1740 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1741 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1742 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1743 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1744 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1745 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1746 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1747 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1748 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1749 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1750 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1751 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1752 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1753 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1754 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1755 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1756 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1757 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1758 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1759 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1760 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1761 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1762 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1763 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1764 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1765 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1766 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1767 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1768 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1769 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1770 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1771 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1772 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1773 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1774 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1775 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1776 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1777 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1778 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1779 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1780 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1781 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1782 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1783 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1784 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1785 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1786 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1787 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1788 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1789 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1790 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1791 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1792 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1793 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1794 { 0xFFFFFFFF }
1795};
1796
1797static const struct si_powertune_data powertune_data_hainan =
1798{
1799 ((1 << 16) | 0x6993),
1800 5,
1801 0,
1802 9,
1803 105,
1804 {
1805 0UL,
1806 0UL,
1807 7194395UL,
1808 309631529UL,
1809 -1270850L,
1810 4513710L,
1811 100
1812 },
1813 117830498UL,
1814 12,
1815 {
1816 0,
1817 0,
1818 0,
1819 0,
1820 0,
1821 0,
1822 0,
1823 0
1824 },
1825 true
1826};
1827
1828static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1829static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1830static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1831static struct si_ps *si_get_ps(struct amdgpu_ps *rps);
1832
1833static int si_populate_voltage_value(struct amdgpu_device *adev,
1834 const struct atom_voltage_table *table,
1835 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1836static int si_get_std_voltage_value(struct amdgpu_device *adev,
1837 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1838 u16 *std_voltage);
1839static int si_write_smc_soft_register(struct amdgpu_device *adev,
1840 u16 reg_offset, u32 value);
1841static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1842 struct rv7xx_pl *pl,
1843 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1844static int si_calculate_sclk_params(struct amdgpu_device *adev,
1845 u32 engine_clock,
1846 SISLANDS_SMC_SCLK_VALUE *sclk);
1847
1848static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1849static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1850static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev);
1851static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1852
1853static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1854{
1855 struct si_power_info *pi = adev->pm.dpm.priv;
1856 return pi;
1857}
1858
1859static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1860 u16 v, s32 t, u32 ileakage, u32 *leakage)
1861{
1862 s64 kt, kv, leakage_w, i_leakage, vddc;
1863 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1864 s64 tmp;
1865
1866 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1867 vddc = div64_s64(drm_int2fixp(v), 1000);
1868 temperature = div64_s64(drm_int2fixp(t), 1000);
1869
1870 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1871 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1872 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1873 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1874 t_ref = drm_int2fixp(coeff->t_ref);
1875
1876 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1877 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1878 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1879 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1880
1881 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1882
1883 *leakage = drm_fixp2int(leakage_w * 1000);
1884}
1885
1886static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1887 const struct ni_leakage_coeffients *coeff,
1888 u16 v,
1889 s32 t,
1890 u32 i_leakage,
1891 u32 *leakage)
1892{
1893 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1894}
1895
1896static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1897 const u32 fixed_kt, u16 v,
1898 u32 ileakage, u32 *leakage)
1899{
1900 s64 kt, kv, leakage_w, i_leakage, vddc;
1901
1902 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1903 vddc = div64_s64(drm_int2fixp(v), 1000);
1904
1905 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1906 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1907 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1908
1909 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1910
1911 *leakage = drm_fixp2int(leakage_w * 1000);
1912}
1913
1914static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1915 const struct ni_leakage_coeffients *coeff,
1916 const u32 fixed_kt,
1917 u16 v,
1918 u32 i_leakage,
1919 u32 *leakage)
1920{
1921 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1922}
1923
1924
1925static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1926 struct si_dte_data *dte_data)
1927{
1928 u32 p_limit1 = adev->pm.dpm.tdp_limit;
1929 u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1930 u32 k = dte_data->k;
1931 u32 t_max = dte_data->max_t;
1932 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1933 u32 t_0 = dte_data->t0;
1934 u32 i;
1935
1936 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1937 dte_data->tdep_count = 3;
1938
1939 for (i = 0; i < k; i++) {
1940 dte_data->r[i] =
1941 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1942 (p_limit2 * (u32)100);
1943 }
1944
1945 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1946
1947 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1948 dte_data->tdep_r[i] = dte_data->r[4];
1949 }
1950 } else {
1951 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1952 }
1953}
1954
1955static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1956{
1957 struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1958
1959 return pi;
1960}
1961
1962static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1963{
1964 struct ni_power_info *pi = adev->pm.dpm.priv;
1965
1966 return pi;
1967}
1968
1969static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1970{
1971 struct si_ps *ps = aps->ps_priv;
1972
1973 return ps;
1974}
1975
1976static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1977{
1978 struct ni_power_info *ni_pi = ni_get_pi(adev);
1979 struct si_power_info *si_pi = si_get_pi(adev);
1980 bool update_dte_from_pl2 = false;
1981
1982 if (adev->asic_type == CHIP_TAHITI) {
1983 si_pi->cac_weights = cac_weights_tahiti;
1984 si_pi->lcac_config = lcac_tahiti;
1985 si_pi->cac_override = cac_override_tahiti;
1986 si_pi->powertune_data = &powertune_data_tahiti;
1987 si_pi->dte_data = dte_data_tahiti;
1988
1989 switch (adev->pdev->device) {
1990 case 0x6798:
1991 si_pi->dte_data.enable_dte_by_default = true;
1992 break;
1993 case 0x6799:
1994 si_pi->dte_data = dte_data_new_zealand;
1995 break;
1996 case 0x6790:
1997 case 0x6791:
1998 case 0x6792:
1999 case 0x679E:
2000 si_pi->dte_data = dte_data_aruba_pro;
2001 update_dte_from_pl2 = true;
2002 break;
2003 case 0x679B:
2004 si_pi->dte_data = dte_data_malta;
2005 update_dte_from_pl2 = true;
2006 break;
2007 case 0x679A:
2008 si_pi->dte_data = dte_data_tahiti_pro;
2009 update_dte_from_pl2 = true;
2010 break;
2011 default:
2012 if (si_pi->dte_data.enable_dte_by_default == true)
2013 DRM_ERROR("DTE is not enabled!\n");
2014 break;
2015 }
2016 } else if (adev->asic_type == CHIP_PITCAIRN) {
2017 si_pi->cac_weights = cac_weights_pitcairn;
2018 si_pi->lcac_config = lcac_pitcairn;
2019 si_pi->cac_override = cac_override_pitcairn;
2020 si_pi->powertune_data = &powertune_data_pitcairn;
2021
2022 switch (adev->pdev->device) {
2023 case 0x6810:
2024 case 0x6818:
2025 si_pi->dte_data = dte_data_curacao_xt;
2026 update_dte_from_pl2 = true;
2027 break;
2028 case 0x6819:
2029 case 0x6811:
2030 si_pi->dte_data = dte_data_curacao_pro;
2031 update_dte_from_pl2 = true;
2032 break;
2033 case 0x6800:
2034 case 0x6806:
2035 si_pi->dte_data = dte_data_neptune_xt;
2036 update_dte_from_pl2 = true;
2037 break;
2038 default:
2039 si_pi->dte_data = dte_data_pitcairn;
2040 break;
2041 }
2042 } else if (adev->asic_type == CHIP_VERDE) {
2043 si_pi->lcac_config = lcac_cape_verde;
2044 si_pi->cac_override = cac_override_cape_verde;
2045 si_pi->powertune_data = &powertune_data_cape_verde;
2046
2047 switch (adev->pdev->device) {
2048 case 0x683B:
2049 case 0x683F:
2050 case 0x6829:
2051 case 0x6835:
2052 si_pi->cac_weights = cac_weights_cape_verde_pro;
2053 si_pi->dte_data = dte_data_cape_verde;
2054 break;
2055 case 0x682C:
2056 si_pi->cac_weights = cac_weights_cape_verde_pro;
2057 si_pi->dte_data = dte_data_sun_xt;
2058 break;
2059 case 0x6825:
2060 case 0x6827:
2061 si_pi->cac_weights = cac_weights_heathrow;
2062 si_pi->dte_data = dte_data_cape_verde;
2063 break;
2064 case 0x6824:
2065 case 0x682D:
2066 si_pi->cac_weights = cac_weights_chelsea_xt;
2067 si_pi->dte_data = dte_data_cape_verde;
2068 break;
2069 case 0x682F:
2070 si_pi->cac_weights = cac_weights_chelsea_pro;
2071 si_pi->dte_data = dte_data_cape_verde;
2072 break;
2073 case 0x6820:
2074 si_pi->cac_weights = cac_weights_heathrow;
2075 si_pi->dte_data = dte_data_venus_xtx;
2076 break;
2077 case 0x6821:
2078 si_pi->cac_weights = cac_weights_heathrow;
2079 si_pi->dte_data = dte_data_venus_xt;
2080 break;
2081 case 0x6823:
2082 case 0x682B:
2083 case 0x6822:
2084 case 0x682A:
2085 si_pi->cac_weights = cac_weights_chelsea_pro;
2086 si_pi->dte_data = dte_data_venus_pro;
2087 break;
2088 default:
2089 si_pi->cac_weights = cac_weights_cape_verde;
2090 si_pi->dte_data = dte_data_cape_verde;
2091 break;
2092 }
2093 } else if (adev->asic_type == CHIP_OLAND) {
2094 si_pi->lcac_config = lcac_mars_pro;
2095 si_pi->cac_override = cac_override_oland;
2096 si_pi->powertune_data = &powertune_data_mars_pro;
2097 si_pi->dte_data = dte_data_mars_pro;
2098
2099 switch (adev->pdev->device) {
2100 case 0x6601:
2101 case 0x6621:
2102 case 0x6603:
2103 case 0x6605:
2104 si_pi->cac_weights = cac_weights_mars_pro;
2105 update_dte_from_pl2 = true;
2106 break;
2107 case 0x6600:
2108 case 0x6606:
2109 case 0x6620:
2110 case 0x6604:
2111 si_pi->cac_weights = cac_weights_mars_xt;
2112 update_dte_from_pl2 = true;
2113 break;
2114 case 0x6611:
2115 case 0x6613:
2116 case 0x6608:
2117 si_pi->cac_weights = cac_weights_oland_pro;
2118 update_dte_from_pl2 = true;
2119 break;
2120 case 0x6610:
2121 si_pi->cac_weights = cac_weights_oland_xt;
2122 update_dte_from_pl2 = true;
2123 break;
2124 default:
2125 si_pi->cac_weights = cac_weights_oland;
2126 si_pi->lcac_config = lcac_oland;
2127 si_pi->cac_override = cac_override_oland;
2128 si_pi->powertune_data = &powertune_data_oland;
2129 si_pi->dte_data = dte_data_oland;
2130 break;
2131 }
2132 } else if (adev->asic_type == CHIP_HAINAN) {
2133 si_pi->cac_weights = cac_weights_hainan;
2134 si_pi->lcac_config = lcac_oland;
2135 si_pi->cac_override = cac_override_oland;
2136 si_pi->powertune_data = &powertune_data_hainan;
2137 si_pi->dte_data = dte_data_sun_xt;
2138 update_dte_from_pl2 = true;
2139 } else {
2140 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2141 return;
2142 }
2143
2144 ni_pi->enable_power_containment = false;
2145 ni_pi->enable_cac = false;
2146 ni_pi->enable_sq_ramping = false;
2147 si_pi->enable_dte = false;
2148
2149 if (si_pi->powertune_data->enable_powertune_by_default) {
2150 ni_pi->enable_power_containment = true;
2151 ni_pi->enable_cac = true;
2152 if (si_pi->dte_data.enable_dte_by_default) {
2153 si_pi->enable_dte = true;
2154 if (update_dte_from_pl2)
2155 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2156
2157 }
2158 ni_pi->enable_sq_ramping = true;
2159 }
2160
2161 ni_pi->driver_calculate_cac_leakage = true;
2162 ni_pi->cac_configuration_required = true;
2163
2164 if (ni_pi->cac_configuration_required) {
2165 ni_pi->support_cac_long_term_average = true;
2166 si_pi->dyn_powertune_data.l2_lta_window_size =
2167 si_pi->powertune_data->l2_lta_window_size_default;
2168 si_pi->dyn_powertune_data.lts_truncate =
2169 si_pi->powertune_data->lts_truncate_default;
2170 } else {
2171 ni_pi->support_cac_long_term_average = false;
2172 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2173 si_pi->dyn_powertune_data.lts_truncate = 0;
2174 }
2175
2176 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2177}
2178
2179static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2180{
2181 return 1;
2182}
2183
2184static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2185{
2186 u32 xclk;
2187 u32 wintime;
2188 u32 cac_window;
2189 u32 cac_window_size;
2190
2191 xclk = amdgpu_asic_get_xclk(adev);
2192
2193 if (xclk == 0)
2194 return 0;
2195
2196 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2197 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2198
2199 wintime = (cac_window_size * 100) / xclk;
2200
2201 return wintime;
2202}
2203
2204static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2205{
2206 return power_in_watts;
2207}
2208
2209static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2210 bool adjust_polarity,
2211 u32 tdp_adjustment,
2212 u32 *tdp_limit,
2213 u32 *near_tdp_limit)
2214{
2215 u32 adjustment_delta, max_tdp_limit;
2216
2217 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2218 return -EINVAL;
2219
2220 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2221
2222 if (adjust_polarity) {
2223 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2224 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2225 } else {
2226 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2227 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit;
2228 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2229 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2230 else
2231 *near_tdp_limit = 0;
2232 }
2233
2234 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2235 return -EINVAL;
2236 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2237 return -EINVAL;
2238
2239 return 0;
2240}
2241
2242static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2243 struct amdgpu_ps *amdgpu_state)
2244{
2245 struct ni_power_info *ni_pi = ni_get_pi(adev);
2246 struct si_power_info *si_pi = si_get_pi(adev);
2247
2248 if (ni_pi->enable_power_containment) {
2249 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2250 PP_SIslands_PAPMParameters *papm_parm;
2251 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2252 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2253 u32 tdp_limit;
2254 u32 near_tdp_limit;
2255 int ret;
2256
2257 if (scaling_factor == 0)
2258 return -EINVAL;
2259
2260 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2261
2262 ret = si_calculate_adjusted_tdp_limits(adev,
2263 false, /* ??? */
2264 adev->pm.dpm.tdp_adjustment,
2265 &tdp_limit,
2266 &near_tdp_limit);
2267 if (ret)
2268 return ret;
2269
2270 smc_table->dpm2Params.TDPLimit =
2271 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2272 smc_table->dpm2Params.NearTDPLimit =
2273 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2274 smc_table->dpm2Params.SafePowerLimit =
2275 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2276
2277 ret = amdgpu_si_copy_bytes_to_smc(adev,
2278 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2279 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2280 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2281 sizeof(u32) * 3,
2282 si_pi->sram_end);
2283 if (ret)
2284 return ret;
2285
2286 if (si_pi->enable_ppm) {
2287 papm_parm = &si_pi->papm_parm;
2288 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2289 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2290 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2291 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2292 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2293 papm_parm->PlatformPowerLimit = 0xffffffff;
2294 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2295
2296 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2297 (u8 *)papm_parm,
2298 sizeof(PP_SIslands_PAPMParameters),
2299 si_pi->sram_end);
2300 if (ret)
2301 return ret;
2302 }
2303 }
2304 return 0;
2305}
2306
2307static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2308 struct amdgpu_ps *amdgpu_state)
2309{
2310 struct ni_power_info *ni_pi = ni_get_pi(adev);
2311 struct si_power_info *si_pi = si_get_pi(adev);
2312
2313 if (ni_pi->enable_power_containment) {
2314 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2315 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2316 int ret;
2317
2318 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2319
2320 smc_table->dpm2Params.NearTDPLimit =
2321 cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2322 smc_table->dpm2Params.SafePowerLimit =
2323 cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2324
2325 ret = amdgpu_si_copy_bytes_to_smc(adev,
2326 (si_pi->state_table_start +
2327 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2328 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2329 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2330 sizeof(u32) * 2,
2331 si_pi->sram_end);
2332 if (ret)
2333 return ret;
2334 }
2335
2336 return 0;
2337}
2338
2339static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2340 const u16 prev_std_vddc,
2341 const u16 curr_std_vddc)
2342{
2343 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2344 u64 prev_vddc = (u64)prev_std_vddc;
2345 u64 curr_vddc = (u64)curr_std_vddc;
2346 u64 pwr_efficiency_ratio, n, d;
2347
2348 if ((prev_vddc == 0) || (curr_vddc == 0))
2349 return 0;
2350
2351 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2352 d = prev_vddc * prev_vddc;
2353 pwr_efficiency_ratio = div64_u64(n, d);
2354
2355 if (pwr_efficiency_ratio > (u64)0xFFFF)
2356 return 0;
2357
2358 return (u16)pwr_efficiency_ratio;
2359}
2360
2361static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2362 struct amdgpu_ps *amdgpu_state)
2363{
2364 struct si_power_info *si_pi = si_get_pi(adev);
2365
2366 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2367 amdgpu_state->vclk && amdgpu_state->dclk)
2368 return true;
2369
2370 return false;
2371}
2372
2373struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2374{
2375 struct evergreen_power_info *pi = adev->pm.dpm.priv;
2376
2377 return pi;
2378}
2379
2380static int si_populate_power_containment_values(struct amdgpu_device *adev,
2381 struct amdgpu_ps *amdgpu_state,
2382 SISLANDS_SMC_SWSTATE *smc_state)
2383{
2384 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2385 struct ni_power_info *ni_pi = ni_get_pi(adev);
2386 struct si_ps *state = si_get_ps(amdgpu_state);
2387 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2388 u32 prev_sclk;
2389 u32 max_sclk;
2390 u32 min_sclk;
2391 u16 prev_std_vddc;
2392 u16 curr_std_vddc;
2393 int i;
2394 u16 pwr_efficiency_ratio;
2395 u8 max_ps_percent;
2396 bool disable_uvd_power_tune;
2397 int ret;
2398
2399 if (ni_pi->enable_power_containment == false)
2400 return 0;
2401
2402 if (state->performance_level_count == 0)
2403 return -EINVAL;
2404
2405 if (smc_state->levelCount != state->performance_level_count)
2406 return -EINVAL;
2407
2408 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2409
2410 smc_state->levels[0].dpm2.MaxPS = 0;
2411 smc_state->levels[0].dpm2.NearTDPDec = 0;
2412 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2413 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2414 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2415
2416 for (i = 1; i < state->performance_level_count; i++) {
2417 prev_sclk = state->performance_levels[i-1].sclk;
2418 max_sclk = state->performance_levels[i].sclk;
2419 if (i == 1)
2420 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2421 else
2422 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2423
2424 if (prev_sclk > max_sclk)
2425 return -EINVAL;
2426
2427 if ((max_ps_percent == 0) ||
2428 (prev_sclk == max_sclk) ||
2429 disable_uvd_power_tune)
2430 min_sclk = max_sclk;
2431 else if (i == 1)
2432 min_sclk = prev_sclk;
2433 else
2434 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2435
2436 if (min_sclk < state->performance_levels[0].sclk)
2437 min_sclk = state->performance_levels[0].sclk;
2438
2439 if (min_sclk == 0)
2440 return -EINVAL;
2441
2442 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2443 state->performance_levels[i-1].vddc, &vddc);
2444 if (ret)
2445 return ret;
2446
2447 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2448 if (ret)
2449 return ret;
2450
2451 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2452 state->performance_levels[i].vddc, &vddc);
2453 if (ret)
2454 return ret;
2455
2456 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2457 if (ret)
2458 return ret;
2459
2460 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2461 prev_std_vddc, curr_std_vddc);
2462
2463 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2464 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2465 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2466 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2467 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2468 }
2469
2470 return 0;
2471}
2472
2473static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2474 struct amdgpu_ps *amdgpu_state,
2475 SISLANDS_SMC_SWSTATE *smc_state)
2476{
2477 struct ni_power_info *ni_pi = ni_get_pi(adev);
2478 struct si_ps *state = si_get_ps(amdgpu_state);
2479 u32 sq_power_throttle, sq_power_throttle2;
2480 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2481 int i;
2482
2483 if (state->performance_level_count == 0)
2484 return -EINVAL;
2485
2486 if (smc_state->levelCount != state->performance_level_count)
2487 return -EINVAL;
2488
2489 if (adev->pm.dpm.sq_ramping_threshold == 0)
2490 return -EINVAL;
2491
2492 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2493 enable_sq_ramping = false;
2494
2495 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2496 enable_sq_ramping = false;
2497
2498 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2499 enable_sq_ramping = false;
2500
2501 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2502 enable_sq_ramping = false;
2503
2504 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2505 enable_sq_ramping = false;
2506
2507 for (i = 0; i < state->performance_level_count; i++) {
2508 sq_power_throttle = 0;
2509 sq_power_throttle2 = 0;
2510
2511 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2512 enable_sq_ramping) {
2513 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2514 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2515 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2516 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2517 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2518 } else {
2519 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2520 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2521 }
2522
2523 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2524 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2525 }
2526
2527 return 0;
2528}
2529
2530static int si_enable_power_containment(struct amdgpu_device *adev,
2531 struct amdgpu_ps *amdgpu_new_state,
2532 bool enable)
2533{
2534 struct ni_power_info *ni_pi = ni_get_pi(adev);
2535 PPSMC_Result smc_result;
2536 int ret = 0;
2537
2538 if (ni_pi->enable_power_containment) {
2539 if (enable) {
2540 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2541 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2542 if (smc_result != PPSMC_Result_OK) {
2543 ret = -EINVAL;
2544 ni_pi->pc_enabled = false;
2545 } else {
2546 ni_pi->pc_enabled = true;
2547 }
2548 }
2549 } else {
2550 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2551 if (smc_result != PPSMC_Result_OK)
2552 ret = -EINVAL;
2553 ni_pi->pc_enabled = false;
2554 }
2555 }
2556
2557 return ret;
2558}
2559
2560static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2561{
2562 struct si_power_info *si_pi = si_get_pi(adev);
2563 int ret = 0;
2564 struct si_dte_data *dte_data = &si_pi->dte_data;
2565 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2566 u32 table_size;
2567 u8 tdep_count;
2568 u32 i;
2569
2570 if (dte_data == NULL)
2571 si_pi->enable_dte = false;
2572
2573 if (si_pi->enable_dte == false)
2574 return 0;
2575
2576 if (dte_data->k <= 0)
2577 return -EINVAL;
2578
2579 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2580 if (dte_tables == NULL) {
2581 si_pi->enable_dte = false;
2582 return -ENOMEM;
2583 }
2584
2585 table_size = dte_data->k;
2586
2587 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2588 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2589
2590 tdep_count = dte_data->tdep_count;
2591 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2592 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2593
2594 dte_tables->K = cpu_to_be32(table_size);
2595 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2596 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2597 dte_tables->WindowSize = dte_data->window_size;
2598 dte_tables->temp_select = dte_data->temp_select;
2599 dte_tables->DTE_mode = dte_data->dte_mode;
2600 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2601
2602 if (tdep_count > 0)
2603 table_size--;
2604
2605 for (i = 0; i < table_size; i++) {
2606 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2607 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2608 }
2609
2610 dte_tables->Tdep_count = tdep_count;
2611
2612 for (i = 0; i < (u32)tdep_count; i++) {
2613 dte_tables->T_limits[i] = dte_data->t_limits[i];
2614 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2615 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2616 }
2617
2618 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2619 (u8 *)dte_tables,
2620 sizeof(Smc_SIslands_DTE_Configuration),
2621 si_pi->sram_end);
2622 kfree(dte_tables);
2623
2624 return ret;
2625}
2626
2627static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2628 u16 *max, u16 *min)
2629{
2630 struct si_power_info *si_pi = si_get_pi(adev);
2631 struct amdgpu_cac_leakage_table *table =
2632 &adev->pm.dpm.dyn_state.cac_leakage_table;
2633 u32 i;
2634 u32 v0_loadline;
2635
2636 if (table == NULL)
2637 return -EINVAL;
2638
2639 *max = 0;
2640 *min = 0xFFFF;
2641
2642 for (i = 0; i < table->count; i++) {
2643 if (table->entries[i].vddc > *max)
2644 *max = table->entries[i].vddc;
2645 if (table->entries[i].vddc < *min)
2646 *min = table->entries[i].vddc;
2647 }
2648
2649 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2650 return -EINVAL;
2651
2652 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2653
2654 if (v0_loadline > 0xFFFFUL)
2655 return -EINVAL;
2656
2657 *min = (u16)v0_loadline;
2658
2659 if ((*min > *max) || (*max == 0) || (*min == 0))
2660 return -EINVAL;
2661
2662 return 0;
2663}
2664
2665static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2666{
2667 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2668 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2669}
2670
2671static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2672 PP_SIslands_CacConfig *cac_tables,
2673 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2674 u16 t0, u16 t_step)
2675{
2676 struct si_power_info *si_pi = si_get_pi(adev);
2677 u32 leakage;
2678 unsigned int i, j;
2679 s32 t;
2680 u32 smc_leakage;
2681 u32 scaling_factor;
2682 u16 voltage;
2683
2684 scaling_factor = si_get_smc_power_scaling_factor(adev);
2685
2686 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2687 t = (1000 * (i * t_step + t0));
2688
2689 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2690 voltage = vddc_max - (vddc_step * j);
2691
2692 si_calculate_leakage_for_v_and_t(adev,
2693 &si_pi->powertune_data->leakage_coefficients,
2694 voltage,
2695 t,
2696 si_pi->dyn_powertune_data.cac_leakage,
2697 &leakage);
2698
2699 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2700
2701 if (smc_leakage > 0xFFFF)
2702 smc_leakage = 0xFFFF;
2703
2704 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2705 cpu_to_be16((u16)smc_leakage);
2706 }
2707 }
2708 return 0;
2709}
2710
2711static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2712 PP_SIslands_CacConfig *cac_tables,
2713 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2714{
2715 struct si_power_info *si_pi = si_get_pi(adev);
2716 u32 leakage;
2717 unsigned int i, j;
2718 u32 smc_leakage;
2719 u32 scaling_factor;
2720 u16 voltage;
2721
2722 scaling_factor = si_get_smc_power_scaling_factor(adev);
2723
2724 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2725 voltage = vddc_max - (vddc_step * j);
2726
2727 si_calculate_leakage_for_v(adev,
2728 &si_pi->powertune_data->leakage_coefficients,
2729 si_pi->powertune_data->fixed_kt,
2730 voltage,
2731 si_pi->dyn_powertune_data.cac_leakage,
2732 &leakage);
2733
2734 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2735
2736 if (smc_leakage > 0xFFFF)
2737 smc_leakage = 0xFFFF;
2738
2739 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2740 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2741 cpu_to_be16((u16)smc_leakage);
2742 }
2743 return 0;
2744}
2745
2746static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2747{
2748 struct ni_power_info *ni_pi = ni_get_pi(adev);
2749 struct si_power_info *si_pi = si_get_pi(adev);
2750 PP_SIslands_CacConfig *cac_tables = NULL;
2751 u16 vddc_max, vddc_min, vddc_step;
2752 u16 t0, t_step;
2753 u32 load_line_slope, reg;
2754 int ret = 0;
2755 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2756
2757 if (ni_pi->enable_cac == false)
2758 return 0;
2759
2760 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2761 if (!cac_tables)
2762 return -ENOMEM;
2763
2764 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2765 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2766 WREG32(CG_CAC_CTRL, reg);
2767
2768 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2769 si_pi->dyn_powertune_data.dc_pwr_value =
2770 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2771 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2772 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2773
2774 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2775
2776 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2777 if (ret)
2778 goto done_free;
2779
2780 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2781 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2782 t_step = 4;
2783 t0 = 60;
2784
2785 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2786 ret = si_init_dte_leakage_table(adev, cac_tables,
2787 vddc_max, vddc_min, vddc_step,
2788 t0, t_step);
2789 else
2790 ret = si_init_simplified_leakage_table(adev, cac_tables,
2791 vddc_max, vddc_min, vddc_step);
2792 if (ret)
2793 goto done_free;
2794
2795 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2796
2797 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2798 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2799 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2800 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2801 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2802 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2803 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2804 cac_tables->calculation_repeats = cpu_to_be32(2);
2805 cac_tables->dc_cac = cpu_to_be32(0);
2806 cac_tables->log2_PG_LKG_SCALE = 12;
2807 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2808 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2809 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2810
2811 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2812 (u8 *)cac_tables,
2813 sizeof(PP_SIslands_CacConfig),
2814 si_pi->sram_end);
2815
2816 if (ret)
2817 goto done_free;
2818
2819 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2820
2821done_free:
2822 if (ret) {
2823 ni_pi->enable_cac = false;
2824 ni_pi->enable_power_containment = false;
2825 }
2826
2827 kfree(cac_tables);
2828
2829 return ret;
2830}
2831
2832static int si_program_cac_config_registers(struct amdgpu_device *adev,
2833 const struct si_cac_config_reg *cac_config_regs)
2834{
2835 const struct si_cac_config_reg *config_regs = cac_config_regs;
2836 u32 data = 0, offset;
2837
2838 if (!config_regs)
2839 return -EINVAL;
2840
2841 while (config_regs->offset != 0xFFFFFFFF) {
2842 switch (config_regs->type) {
2843 case SISLANDS_CACCONFIG_CGIND:
2844 offset = SMC_CG_IND_START + config_regs->offset;
2845 if (offset < SMC_CG_IND_END)
2846 data = RREG32_SMC(offset);
2847 break;
2848 default:
2849 data = RREG32(config_regs->offset);
2850 break;
2851 }
2852
2853 data &= ~config_regs->mask;
2854 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2855
2856 switch (config_regs->type) {
2857 case SISLANDS_CACCONFIG_CGIND:
2858 offset = SMC_CG_IND_START + config_regs->offset;
2859 if (offset < SMC_CG_IND_END)
2860 WREG32_SMC(offset, data);
2861 break;
2862 default:
2863 WREG32(config_regs->offset, data);
2864 break;
2865 }
2866 config_regs++;
2867 }
2868 return 0;
2869}
2870
2871static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2872{
2873 struct ni_power_info *ni_pi = ni_get_pi(adev);
2874 struct si_power_info *si_pi = si_get_pi(adev);
2875 int ret;
2876
2877 if ((ni_pi->enable_cac == false) ||
2878 (ni_pi->cac_configuration_required == false))
2879 return 0;
2880
2881 ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2882 if (ret)
2883 return ret;
2884 ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2885 if (ret)
2886 return ret;
2887 ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2888 if (ret)
2889 return ret;
2890
2891 return 0;
2892}
2893
2894static int si_enable_smc_cac(struct amdgpu_device *adev,
2895 struct amdgpu_ps *amdgpu_new_state,
2896 bool enable)
2897{
2898 struct ni_power_info *ni_pi = ni_get_pi(adev);
2899 struct si_power_info *si_pi = si_get_pi(adev);
2900 PPSMC_Result smc_result;
2901 int ret = 0;
2902
2903 if (ni_pi->enable_cac) {
2904 if (enable) {
2905 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2906 if (ni_pi->support_cac_long_term_average) {
2907 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2908 if (smc_result != PPSMC_Result_OK)
2909 ni_pi->support_cac_long_term_average = false;
2910 }
2911
2912 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2913 if (smc_result != PPSMC_Result_OK) {
2914 ret = -EINVAL;
2915 ni_pi->cac_enabled = false;
2916 } else {
2917 ni_pi->cac_enabled = true;
2918 }
2919
2920 if (si_pi->enable_dte) {
2921 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2922 if (smc_result != PPSMC_Result_OK)
2923 ret = -EINVAL;
2924 }
2925 }
2926 } else if (ni_pi->cac_enabled) {
2927 if (si_pi->enable_dte)
2928 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2929
2930 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2931
2932 ni_pi->cac_enabled = false;
2933
2934 if (ni_pi->support_cac_long_term_average)
2935 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2936 }
2937 }
2938 return ret;
2939}
2940
2941static int si_init_smc_spll_table(struct amdgpu_device *adev)
2942{
2943 struct ni_power_info *ni_pi = ni_get_pi(adev);
2944 struct si_power_info *si_pi = si_get_pi(adev);
2945 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2946 SISLANDS_SMC_SCLK_VALUE sclk_params;
2947 u32 fb_div, p_div;
2948 u32 clk_s, clk_v;
2949 u32 sclk = 0;
2950 int ret = 0;
2951 u32 tmp;
2952 int i;
2953
2954 if (si_pi->spll_table_start == 0)
2955 return -EINVAL;
2956
2957 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2958 if (spll_table == NULL)
2959 return -ENOMEM;
2960
2961 for (i = 0; i < 256; i++) {
2962 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2963 if (ret)
2964 break;
2965 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2966 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2967 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2968 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2969
2970 fb_div &= ~0x00001FFF;
2971 fb_div >>= 1;
2972 clk_v >>= 6;
2973
2974 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2975 ret = -EINVAL;
2976 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2977 ret = -EINVAL;
2978 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2979 ret = -EINVAL;
2980 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2981 ret = -EINVAL;
2982
2983 if (ret)
2984 break;
2985
2986 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2987 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2988 spll_table->freq[i] = cpu_to_be32(tmp);
2989
2990 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2991 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2992 spll_table->ss[i] = cpu_to_be32(tmp);
2993
2994 sclk += 512;
2995 }
2996
2997
2998 if (!ret)
2999 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
3000 (u8 *)spll_table,
3001 sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
3002 si_pi->sram_end);
3003
3004 if (ret)
3005 ni_pi->enable_power_containment = false;
3006
3007 kfree(spll_table);
3008
3009 return ret;
3010}
3011
3012struct si_dpm_quirk {
3013 u32 chip_vendor;
3014 u32 chip_device;
3015 u32 subsys_vendor;
3016 u32 subsys_device;
3017 u32 max_sclk;
3018 u32 max_mclk;
3019};
3020
3021/* cards with dpm stability problems */
3022static struct si_dpm_quirk si_dpm_quirk_list[] = {
3023 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
3024 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
3025 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
3026 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
3027 { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
3028 { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
3029 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
3030 { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
3031 { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
3032 { 0, 0, 0, 0 },
3033};
3034
3035static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3036 u16 vce_voltage)
3037{
3038 u16 highest_leakage = 0;
3039 struct si_power_info *si_pi = si_get_pi(adev);
3040 int i;
3041
3042 for (i = 0; i < si_pi->leakage_voltage.count; i++){
3043 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3044 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3045 }
3046
3047 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3048 return highest_leakage;
3049
3050 return vce_voltage;
3051}
3052
3053static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3054 u32 evclk, u32 ecclk, u16 *voltage)
3055{
3056 u32 i;
3057 int ret = -EINVAL;
3058 struct amdgpu_vce_clock_voltage_dependency_table *table =
3059 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3060
3061 if (((evclk == 0) && (ecclk == 0)) ||
3062 (table && (table->count == 0))) {
3063 *voltage = 0;
3064 return 0;
3065 }
3066
3067 for (i = 0; i < table->count; i++) {
3068 if ((evclk <= table->entries[i].evclk) &&
3069 (ecclk <= table->entries[i].ecclk)) {
3070 *voltage = table->entries[i].v;
3071 ret = 0;
3072 break;
3073 }
3074 }
3075
3076 /* if no match return the highest voltage */
3077 if (ret)
3078 *voltage = table->entries[table->count - 1].v;
3079
3080 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3081
3082 return ret;
3083}
3084
3085static bool si_dpm_vblank_too_short(struct amdgpu_device *adev)
3086{
3087
3088 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3089 /* we never hit the non-gddr5 limit so disable it */
3090 u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3091
3092 if (vblank_time < switch_limit)
3093 return true;
3094 else
3095 return false;
3096
3097}
3098
3099static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3100 u32 arb_freq_src, u32 arb_freq_dest)
3101{
3102 u32 mc_arb_dram_timing;
3103 u32 mc_arb_dram_timing2;
3104 u32 burst_time;
3105 u32 mc_cg_config;
3106
3107 switch (arb_freq_src) {
3108 case MC_CG_ARB_FREQ_F0:
3109 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
3110 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3111 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3112 break;
3113 case MC_CG_ARB_FREQ_F1:
3114 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
3115 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3116 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3117 break;
3118 case MC_CG_ARB_FREQ_F2:
3119 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
3120 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3121 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3122 break;
3123 case MC_CG_ARB_FREQ_F3:
3124 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
3125 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3126 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3127 break;
3128 default:
3129 return -EINVAL;
3130 }
3131
3132 switch (arb_freq_dest) {
3133 case MC_CG_ARB_FREQ_F0:
3134 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3135 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3136 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3137 break;
3138 case MC_CG_ARB_FREQ_F1:
3139 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3140 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3141 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3142 break;
3143 case MC_CG_ARB_FREQ_F2:
3144 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3145 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3146 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3147 break;
3148 case MC_CG_ARB_FREQ_F3:
3149 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3150 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3151 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3152 break;
3153 default:
3154 return -EINVAL;
3155 }
3156
3157 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3158 WREG32(MC_CG_CONFIG, mc_cg_config);
3159 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3160
3161 return 0;
3162}
3163
3164static void ni_update_current_ps(struct amdgpu_device *adev,
3165 struct amdgpu_ps *rps)
3166{
3167 struct si_ps *new_ps = si_get_ps(rps);
3168 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3169 struct ni_power_info *ni_pi = ni_get_pi(adev);
3170
3171 eg_pi->current_rps = *rps;
3172 ni_pi->current_ps = *new_ps;
3173 eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3174 adev->pm.dpm.current_ps = &eg_pi->current_rps;
3175}
3176
3177static void ni_update_requested_ps(struct amdgpu_device *adev,
3178 struct amdgpu_ps *rps)
3179{
3180 struct si_ps *new_ps = si_get_ps(rps);
3181 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3182 struct ni_power_info *ni_pi = ni_get_pi(adev);
3183
3184 eg_pi->requested_rps = *rps;
3185 ni_pi->requested_ps = *new_ps;
3186 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3187 adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
3188}
3189
3190static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3191 struct amdgpu_ps *new_ps,
3192 struct amdgpu_ps *old_ps)
3193{
3194 struct si_ps *new_state = si_get_ps(new_ps);
3195 struct si_ps *current_state = si_get_ps(old_ps);
3196
3197 if ((new_ps->vclk == old_ps->vclk) &&
3198 (new_ps->dclk == old_ps->dclk))
3199 return;
3200
3201 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3202 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3203 return;
3204
3205 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3206}
3207
3208static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3209 struct amdgpu_ps *new_ps,
3210 struct amdgpu_ps *old_ps)
3211{
3212 struct si_ps *new_state = si_get_ps(new_ps);
3213 struct si_ps *current_state = si_get_ps(old_ps);
3214
3215 if ((new_ps->vclk == old_ps->vclk) &&
3216 (new_ps->dclk == old_ps->dclk))
3217 return;
3218
3219 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3220 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3221 return;
3222
3223 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3224}
3225
3226static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3227{
3228 unsigned int i;
3229
3230 for (i = 0; i < table->count; i++)
3231 if (voltage <= table->entries[i].value)
3232 return table->entries[i].value;
3233
3234 return table->entries[table->count - 1].value;
3235}
3236
3237static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3238 u32 max_clock, u32 requested_clock)
3239{
3240 unsigned int i;
3241
3242 if ((clocks == NULL) || (clocks->count == 0))
3243 return (requested_clock < max_clock) ? requested_clock : max_clock;
3244
3245 for (i = 0; i < clocks->count; i++) {
3246 if (clocks->values[i] >= requested_clock)
3247 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3248 }
3249
3250 return (clocks->values[clocks->count - 1] < max_clock) ?
3251 clocks->values[clocks->count - 1] : max_clock;
3252}
3253
3254static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3255 u32 max_mclk, u32 requested_mclk)
3256{
3257 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3258 max_mclk, requested_mclk);
3259}
3260
3261static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3262 u32 max_sclk, u32 requested_sclk)
3263{
3264 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3265 max_sclk, requested_sclk);
3266}
3267
3268static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3269 u32 *max_clock)
3270{
3271 u32 i, clock = 0;
3272
3273 if ((table == NULL) || (table->count == 0)) {
3274 *max_clock = clock;
3275 return;
3276 }
3277
3278 for (i = 0; i < table->count; i++) {
3279 if (clock < table->entries[i].clk)
3280 clock = table->entries[i].clk;
3281 }
3282 *max_clock = clock;
3283}
3284
3285static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3286 u32 clock, u16 max_voltage, u16 *voltage)
3287{
3288 u32 i;
3289
3290 if ((table == NULL) || (table->count == 0))
3291 return;
3292
3293 for (i= 0; i < table->count; i++) {
3294 if (clock <= table->entries[i].clk) {
3295 if (*voltage < table->entries[i].v)
3296 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3297 table->entries[i].v : max_voltage);
3298 return;
3299 }
3300 }
3301
3302 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3303}
3304
3305static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3306 const struct amdgpu_clock_and_voltage_limits *max_limits,
3307 struct rv7xx_pl *pl)
3308{
3309
3310 if ((pl->mclk == 0) || (pl->sclk == 0))
3311 return;
3312
3313 if (pl->mclk == pl->sclk)
3314 return;
3315
3316 if (pl->mclk > pl->sclk) {
3317 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3318 pl->sclk = btc_get_valid_sclk(adev,
3319 max_limits->sclk,
3320 (pl->mclk +
3321 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3322 adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3323 } else {
3324 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3325 pl->mclk = btc_get_valid_mclk(adev,
3326 max_limits->mclk,
3327 pl->sclk -
3328 adev->pm.dpm.dyn_state.sclk_mclk_delta);
3329 }
3330}
3331
3332static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3333 u16 max_vddc, u16 max_vddci,
3334 u16 *vddc, u16 *vddci)
3335{
3336 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3337 u16 new_voltage;
3338
3339 if ((0 == *vddc) || (0 == *vddci))
3340 return;
3341
3342 if (*vddc > *vddci) {
3343 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3344 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3345 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3346 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3347 }
3348 } else {
3349 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3350 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3351 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3352 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3353 }
3354 }
3355}
3356
3357static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev,
3358 u32 sys_mask,
3359 enum amdgpu_pcie_gen asic_gen,
3360 enum amdgpu_pcie_gen default_gen)
3361{
3362 switch (asic_gen) {
3363 case AMDGPU_PCIE_GEN1:
3364 return AMDGPU_PCIE_GEN1;
3365 case AMDGPU_PCIE_GEN2:
3366 return AMDGPU_PCIE_GEN2;
3367 case AMDGPU_PCIE_GEN3:
3368 return AMDGPU_PCIE_GEN3;
3369 default:
3370 if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
3371 return AMDGPU_PCIE_GEN3;
3372 else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
3373 return AMDGPU_PCIE_GEN2;
3374 else
3375 return AMDGPU_PCIE_GEN1;
3376 }
3377 return AMDGPU_PCIE_GEN1;
3378}
3379
3380static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3381 u32 *p, u32 *u)
3382{
3383 u32 b_c = 0;
3384 u32 i_c;
3385 u32 tmp;
3386
3387 i_c = (i * r_c) / 100;
3388 tmp = i_c >> p_b;
3389
3390 while (tmp) {
3391 b_c++;
3392 tmp >>= 1;
3393 }
3394
3395 *u = (b_c + 1) / 2;
3396 *p = i_c / (1 << (2 * (*u)));
3397}
3398
3399static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3400{
3401 u32 k, a, ah, al;
3402 u32 t1;
3403
3404 if ((fl == 0) || (fh == 0) || (fl > fh))
3405 return -EINVAL;
3406
3407 k = (100 * fh) / fl;
3408 t1 = (t * (k - 100));
3409 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3410 a = (a + 5) / 10;
3411 ah = ((a * t) + 5000) / 10000;
3412 al = a - ah;
3413
3414 *th = t - ah;
3415 *tl = t + al;
3416
3417 return 0;
3418}
3419
3420static bool r600_is_uvd_state(u32 class, u32 class2)
3421{
3422 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3423 return true;
3424 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3425 return true;
3426 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3427 return true;
3428 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3429 return true;
3430 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3431 return true;
3432 return false;
3433}
3434
3435static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3436{
3437 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3438}
3439
3440static void rv770_get_max_vddc(struct amdgpu_device *adev)
3441{
3442 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3443 u16 vddc;
3444
3445 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3446 pi->max_vddc = 0;
3447 else
3448 pi->max_vddc = vddc;
3449}
3450
3451static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3452{
3453 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3454 struct amdgpu_atom_ss ss;
3455
3456 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3457 ASIC_INTERNAL_ENGINE_SS, 0);
3458 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3459 ASIC_INTERNAL_MEMORY_SS, 0);
3460
3461 if (pi->sclk_ss || pi->mclk_ss)
3462 pi->dynamic_ss = true;
3463 else
3464 pi->dynamic_ss = false;
3465}
3466
3467
3468static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3469 struct amdgpu_ps *rps)
3470{
3471 struct si_ps *ps = si_get_ps(rps);
3472 struct amdgpu_clock_and_voltage_limits *max_limits;
3473 bool disable_mclk_switching = false;
3474 bool disable_sclk_switching = false;
3475 u32 mclk, sclk;
3476 u16 vddc, vddci, min_vce_voltage = 0;
3477 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3478 u32 max_sclk = 0, max_mclk = 0;
3479 int i;
3480 struct si_dpm_quirk *p = si_dpm_quirk_list;
3481
3482 /* limit all SI kickers */
3483 if (adev->asic_type == CHIP_PITCAIRN) {
3484 if ((adev->pdev->revision == 0x81) ||
3485 (adev->pdev->device == 0x6810) ||
3486 (adev->pdev->device == 0x6811) ||
3487 (adev->pdev->device == 0x6816) ||
3488 (adev->pdev->device == 0x6817) ||
3489 (adev->pdev->device == 0x6806))
3490 max_mclk = 120000;
3491 } else if (adev->asic_type == CHIP_HAINAN) {
3492 if ((adev->pdev->revision == 0x81) ||
3493 (adev->pdev->revision == 0x83) ||
3494 (adev->pdev->revision == 0xC3) ||
3495 (adev->pdev->device == 0x6664) ||
3496 (adev->pdev->device == 0x6665) ||
3497 (adev->pdev->device == 0x6667)) {
3498 max_sclk = 75000;
3499 }
3500 } else if (adev->asic_type == CHIP_OLAND) {
3501 if ((adev->pdev->revision == 0xC7) ||
3502 (adev->pdev->revision == 0x80) ||
3503 (adev->pdev->revision == 0x81) ||
3504 (adev->pdev->revision == 0x83) ||
3505 (adev->pdev->revision == 0x87) ||
3506 (adev->pdev->device == 0x6604) ||
3507 (adev->pdev->device == 0x6605)) {
3508 max_sclk = 75000;
3509 }
3510 }
3511 /* Apply dpm quirks */
3512 while (p && p->chip_device != 0) {
3513 if (adev->pdev->vendor == p->chip_vendor &&
3514 adev->pdev->device == p->chip_device &&
3515 adev->pdev->subsystem_vendor == p->subsys_vendor &&
3516 adev->pdev->subsystem_device == p->subsys_device) {
3517 max_sclk = p->max_sclk;
3518 max_mclk = p->max_mclk;
3519 break;
3520 }
3521 ++p;
3522 }
3523
3524 if (rps->vce_active) {
3525 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3526 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3527 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3528 &min_vce_voltage);
3529 } else {
3530 rps->evclk = 0;
3531 rps->ecclk = 0;
3532 }
3533
3534 if ((adev->pm.dpm.new_active_crtc_count > 1) ||
3535 si_dpm_vblank_too_short(adev))
3536 disable_mclk_switching = true;
3537
3538 if (rps->vclk || rps->dclk) {
3539 disable_mclk_switching = true;
3540 disable_sclk_switching = true;
3541 }
3542
3543 if (adev->pm.dpm.ac_power)
3544 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3545 else
3546 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3547
3548 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3549 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3550 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3551 }
3552 if (adev->pm.dpm.ac_power == false) {
3553 for (i = 0; i < ps->performance_level_count; i++) {
3554 if (ps->performance_levels[i].mclk > max_limits->mclk)
3555 ps->performance_levels[i].mclk = max_limits->mclk;
3556 if (ps->performance_levels[i].sclk > max_limits->sclk)
3557 ps->performance_levels[i].sclk = max_limits->sclk;
3558 if (ps->performance_levels[i].vddc > max_limits->vddc)
3559 ps->performance_levels[i].vddc = max_limits->vddc;
3560 if (ps->performance_levels[i].vddci > max_limits->vddci)
3561 ps->performance_levels[i].vddci = max_limits->vddci;
3562 }
3563 }
3564
3565 /* limit clocks to max supported clocks based on voltage dependency tables */
3566 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3567 &max_sclk_vddc);
3568 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3569 &max_mclk_vddci);
3570 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3571 &max_mclk_vddc);
3572
3573 for (i = 0; i < ps->performance_level_count; i++) {
3574 if (max_sclk_vddc) {
3575 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3576 ps->performance_levels[i].sclk = max_sclk_vddc;
3577 }
3578 if (max_mclk_vddci) {
3579 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3580 ps->performance_levels[i].mclk = max_mclk_vddci;
3581 }
3582 if (max_mclk_vddc) {
3583 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3584 ps->performance_levels[i].mclk = max_mclk_vddc;
3585 }
3586 if (max_mclk) {
3587 if (ps->performance_levels[i].mclk > max_mclk)
3588 ps->performance_levels[i].mclk = max_mclk;
3589 }
3590 if (max_sclk) {
3591 if (ps->performance_levels[i].sclk > max_sclk)
3592 ps->performance_levels[i].sclk = max_sclk;
3593 }
3594 }
3595
3596 /* XXX validate the min clocks required for display */
3597
3598 if (disable_mclk_switching) {
3599 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3600 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3601 } else {
3602 mclk = ps->performance_levels[0].mclk;
3603 vddci = ps->performance_levels[0].vddci;
3604 }
3605
3606 if (disable_sclk_switching) {
3607 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3608 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3609 } else {
3610 sclk = ps->performance_levels[0].sclk;
3611 vddc = ps->performance_levels[0].vddc;
3612 }
3613
3614 if (rps->vce_active) {
3615 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3616 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3617 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3618 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3619 }
3620
3621 /* adjusted low state */
3622 ps->performance_levels[0].sclk = sclk;
3623 ps->performance_levels[0].mclk = mclk;
3624 ps->performance_levels[0].vddc = vddc;
3625 ps->performance_levels[0].vddci = vddci;
3626
3627 if (disable_sclk_switching) {
3628 sclk = ps->performance_levels[0].sclk;
3629 for (i = 1; i < ps->performance_level_count; i++) {
3630 if (sclk < ps->performance_levels[i].sclk)
3631 sclk = ps->performance_levels[i].sclk;
3632 }
3633 for (i = 0; i < ps->performance_level_count; i++) {
3634 ps->performance_levels[i].sclk = sclk;
3635 ps->performance_levels[i].vddc = vddc;
3636 }
3637 } else {
3638 for (i = 1; i < ps->performance_level_count; i++) {
3639 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3640 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3641 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3642 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3643 }
3644 }
3645
3646 if (disable_mclk_switching) {
3647 mclk = ps->performance_levels[0].mclk;
3648 for (i = 1; i < ps->performance_level_count; i++) {
3649 if (mclk < ps->performance_levels[i].mclk)
3650 mclk = ps->performance_levels[i].mclk;
3651 }
3652 for (i = 0; i < ps->performance_level_count; i++) {
3653 ps->performance_levels[i].mclk = mclk;
3654 ps->performance_levels[i].vddci = vddci;
3655 }
3656 } else {
3657 for (i = 1; i < ps->performance_level_count; i++) {
3658 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3659 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3660 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3661 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3662 }
3663 }
3664
3665 for (i = 0; i < ps->performance_level_count; i++)
3666 btc_adjust_clock_combinations(adev, max_limits,
3667 &ps->performance_levels[i]);
3668
3669 for (i = 0; i < ps->performance_level_count; i++) {
3670 if (ps->performance_levels[i].vddc < min_vce_voltage)
3671 ps->performance_levels[i].vddc = min_vce_voltage;
3672 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3673 ps->performance_levels[i].sclk,
3674 max_limits->vddc, &ps->performance_levels[i].vddc);
3675 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3676 ps->performance_levels[i].mclk,
3677 max_limits->vddci, &ps->performance_levels[i].vddci);
3678 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3679 ps->performance_levels[i].mclk,
3680 max_limits->vddc, &ps->performance_levels[i].vddc);
3681 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3682 adev->clock.current_dispclk,
3683 max_limits->vddc, &ps->performance_levels[i].vddc);
3684 }
3685
3686 for (i = 0; i < ps->performance_level_count; i++) {
3687 btc_apply_voltage_delta_rules(adev,
3688 max_limits->vddc, max_limits->vddci,
3689 &ps->performance_levels[i].vddc,
3690 &ps->performance_levels[i].vddci);
3691 }
3692
3693 ps->dc_compatible = true;
3694 for (i = 0; i < ps->performance_level_count; i++) {
3695 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3696 ps->dc_compatible = false;
3697 }
3698}
3699
3700#if 0
3701static int si_read_smc_soft_register(struct amdgpu_device *adev,
3702 u16 reg_offset, u32 *value)
3703{
3704 struct si_power_info *si_pi = si_get_pi(adev);
3705
3706 return amdgpu_si_read_smc_sram_dword(adev,
3707 si_pi->soft_regs_start + reg_offset, value,
3708 si_pi->sram_end);
3709}
3710#endif
3711
3712static int si_write_smc_soft_register(struct amdgpu_device *adev,
3713 u16 reg_offset, u32 value)
3714{
3715 struct si_power_info *si_pi = si_get_pi(adev);
3716
3717 return amdgpu_si_write_smc_sram_dword(adev,
3718 si_pi->soft_regs_start + reg_offset,
3719 value, si_pi->sram_end);
3720}
3721
3722static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3723{
3724 bool ret = false;
3725 u32 tmp, width, row, column, bank, density;
3726 bool is_memory_gddr5, is_special;
3727
3728 tmp = RREG32(MC_SEQ_MISC0);
3729 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3730 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3731 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3732
3733 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3734 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3735
3736 tmp = RREG32(MC_ARB_RAMCFG);
3737 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3738 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3739 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3740
3741 density = (1 << (row + column - 20 + bank)) * width;
3742
3743 if ((adev->pdev->device == 0x6819) &&
3744 is_memory_gddr5 && is_special && (density == 0x400))
3745 ret = true;
3746
3747 return ret;
3748}
3749
3750static void si_get_leakage_vddc(struct amdgpu_device *adev)
3751{
3752 struct si_power_info *si_pi = si_get_pi(adev);
3753 u16 vddc, count = 0;
3754 int i, ret;
3755
3756 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3757 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3758
3759 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3760 si_pi->leakage_voltage.entries[count].voltage = vddc;
3761 si_pi->leakage_voltage.entries[count].leakage_index =
3762 SISLANDS_LEAKAGE_INDEX0 + i;
3763 count++;
3764 }
3765 }
3766 si_pi->leakage_voltage.count = count;
3767}
3768
3769static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3770 u32 index, u16 *leakage_voltage)
3771{
3772 struct si_power_info *si_pi = si_get_pi(adev);
3773 int i;
3774
3775 if (leakage_voltage == NULL)
3776 return -EINVAL;
3777
3778 if ((index & 0xff00) != 0xff00)
3779 return -EINVAL;
3780
3781 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3782 return -EINVAL;
3783
3784 if (index < SISLANDS_LEAKAGE_INDEX0)
3785 return -EINVAL;
3786
3787 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3788 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3789 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3790 return 0;
3791 }
3792 }
3793 return -EAGAIN;
3794}
3795
3796static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3797{
3798 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3799 bool want_thermal_protection;
3800 enum amdgpu_dpm_event_src dpm_event_src;
3801
3802 switch (sources) {
3803 case 0:
3804 default:
3805 want_thermal_protection = false;
3806 break;
3807 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
3808 want_thermal_protection = true;
3809 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
3810 break;
3811 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3812 want_thermal_protection = true;
3813 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
3814 break;
3815 case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3816 (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3817 want_thermal_protection = true;
3818 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3819 break;
3820 }
3821
3822 if (want_thermal_protection) {
3823 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3824 if (pi->thermal_protection)
3825 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3826 } else {
3827 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3828 }
3829}
3830
3831static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3832 enum amdgpu_dpm_auto_throttle_src source,
3833 bool enable)
3834{
3835 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3836
3837 if (enable) {
3838 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3839 pi->active_auto_throttle_sources |= 1 << source;
3840 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3841 }
3842 } else {
3843 if (pi->active_auto_throttle_sources & (1 << source)) {
3844 pi->active_auto_throttle_sources &= ~(1 << source);
3845 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3846 }
3847 }
3848}
3849
3850static void si_start_dpm(struct amdgpu_device *adev)
3851{
3852 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3853}
3854
3855static void si_stop_dpm(struct amdgpu_device *adev)
3856{
3857 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3858}
3859
3860static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3861{
3862 if (enable)
3863 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3864 else
3865 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3866
3867}
3868
3869#if 0
3870static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3871 u32 thermal_level)
3872{
3873 PPSMC_Result ret;
3874
3875 if (thermal_level == 0) {
3876 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3877 if (ret == PPSMC_Result_OK)
3878 return 0;
3879 else
3880 return -EINVAL;
3881 }
3882 return 0;
3883}
3884
3885static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3886{
3887 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3888}
3889#endif
3890
3891#if 0
3892static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3893{
3894 if (ac_power)
3895 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3896 0 : -EINVAL;
3897
3898 return 0;
3899}
3900#endif
3901
3902static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3903 PPSMC_Msg msg, u32 parameter)
3904{
3905 WREG32(SMC_SCRATCH0, parameter);
3906 return amdgpu_si_send_msg_to_smc(adev, msg);
3907}
3908
3909static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3910{
3911 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3912 return -EINVAL;
3913
3914 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3915 0 : -EINVAL;
3916}
3917
3918static int si_dpm_force_performance_level(struct amdgpu_device *adev,
3919 enum amdgpu_dpm_forced_level level)
3920{
3921 struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3922 struct si_ps *ps = si_get_ps(rps);
3923 u32 levels = ps->performance_level_count;
3924
3925 if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) {
3926 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3927 return -EINVAL;
3928
3929 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3930 return -EINVAL;
3931 } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) {
3932 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3933 return -EINVAL;
3934
3935 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3936 return -EINVAL;
3937 } else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) {
3938 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3939 return -EINVAL;
3940
3941 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3942 return -EINVAL;
3943 }
3944
3945 adev->pm.dpm.forced_level = level;
3946
3947 return 0;
3948}
3949
3950#if 0
3951static int si_set_boot_state(struct amdgpu_device *adev)
3952{
3953 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3954 0 : -EINVAL;
3955}
3956#endif
3957
3958static int si_set_sw_state(struct amdgpu_device *adev)
3959{
3960 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3961 0 : -EINVAL;
3962}
3963
3964static int si_halt_smc(struct amdgpu_device *adev)
3965{
3966 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3967 return -EINVAL;
3968
3969 return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3970 0 : -EINVAL;
3971}
3972
3973static int si_resume_smc(struct amdgpu_device *adev)
3974{
3975 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3976 return -EINVAL;
3977
3978 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3979 0 : -EINVAL;
3980}
3981
3982static void si_dpm_start_smc(struct amdgpu_device *adev)
3983{
3984 amdgpu_si_program_jump_on_start(adev);
3985 amdgpu_si_start_smc(adev);
3986 amdgpu_si_smc_clock(adev, true);
3987}
3988
3989static void si_dpm_stop_smc(struct amdgpu_device *adev)
3990{
3991 amdgpu_si_reset_smc(adev);
3992 amdgpu_si_smc_clock(adev, false);
3993}
3994
3995static int si_process_firmware_header(struct amdgpu_device *adev)
3996{
3997 struct si_power_info *si_pi = si_get_pi(adev);
3998 u32 tmp;
3999 int ret;
4000
4001 ret = amdgpu_si_read_smc_sram_dword(adev,
4002 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4003 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
4004 &tmp, si_pi->sram_end);
4005 if (ret)
4006 return ret;
4007
4008 si_pi->state_table_start = tmp;
4009
4010 ret = amdgpu_si_read_smc_sram_dword(adev,
4011 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4012 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
4013 &tmp, si_pi->sram_end);
4014 if (ret)
4015 return ret;
4016
4017 si_pi->soft_regs_start = tmp;
4018
4019 ret = amdgpu_si_read_smc_sram_dword(adev,
4020 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4021 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
4022 &tmp, si_pi->sram_end);
4023 if (ret)
4024 return ret;
4025
4026 si_pi->mc_reg_table_start = tmp;
4027
4028 ret = amdgpu_si_read_smc_sram_dword(adev,
4029 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4030 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
4031 &tmp, si_pi->sram_end);
4032 if (ret)
4033 return ret;
4034
4035 si_pi->fan_table_start = tmp;
4036
4037 ret = amdgpu_si_read_smc_sram_dword(adev,
4038 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4039 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
4040 &tmp, si_pi->sram_end);
4041 if (ret)
4042 return ret;
4043
4044 si_pi->arb_table_start = tmp;
4045
4046 ret = amdgpu_si_read_smc_sram_dword(adev,
4047 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4048 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
4049 &tmp, si_pi->sram_end);
4050 if (ret)
4051 return ret;
4052
4053 si_pi->cac_table_start = tmp;
4054
4055 ret = amdgpu_si_read_smc_sram_dword(adev,
4056 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4057 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
4058 &tmp, si_pi->sram_end);
4059 if (ret)
4060 return ret;
4061
4062 si_pi->dte_table_start = tmp;
4063
4064 ret = amdgpu_si_read_smc_sram_dword(adev,
4065 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4066 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4067 &tmp, si_pi->sram_end);
4068 if (ret)
4069 return ret;
4070
4071 si_pi->spll_table_start = tmp;
4072
4073 ret = amdgpu_si_read_smc_sram_dword(adev,
4074 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4075 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4076 &tmp, si_pi->sram_end);
4077 if (ret)
4078 return ret;
4079
4080 si_pi->papm_cfg_table_start = tmp;
4081
4082 return ret;
4083}
4084
4085static void si_read_clock_registers(struct amdgpu_device *adev)
4086{
4087 struct si_power_info *si_pi = si_get_pi(adev);
4088
4089 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4090 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4091 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4092 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
4093 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
4094 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
4095 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4096 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4097 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4098 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4099 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4100 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4101 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4102 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4103 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4104}
4105
4106static void si_enable_thermal_protection(struct amdgpu_device *adev,
4107 bool enable)
4108{
4109 if (enable)
4110 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
4111 else
4112 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
4113}
4114
4115static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4116{
4117 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
4118}
4119
4120#if 0
4121static int si_enter_ulp_state(struct amdgpu_device *adev)
4122{
4123 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4124
4125 udelay(25000);
4126
4127 return 0;
4128}
4129
4130static int si_exit_ulp_state(struct amdgpu_device *adev)
4131{
4132 int i;
4133
4134 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4135
4136 udelay(7000);
4137
4138 for (i = 0; i < adev->usec_timeout; i++) {
4139 if (RREG32(SMC_RESP_0) == 1)
4140 break;
4141 udelay(1000);
4142 }
4143
4144 return 0;
4145}
4146#endif
4147
4148static int si_notify_smc_display_change(struct amdgpu_device *adev,
4149 bool has_display)
4150{
4151 PPSMC_Msg msg = has_display ?
4152 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4153
4154 return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4155 0 : -EINVAL;
4156}
4157
4158static void si_program_response_times(struct amdgpu_device *adev)
4159{
4160 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
4161 u32 vddc_dly, acpi_dly, vbi_dly;
4162 u32 reference_clock;
4163
4164 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4165
4166 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
4167 backbias_response_time = (u32)adev->pm.dpm.backbias_response_time;
4168
4169 if (voltage_response_time == 0)
4170 voltage_response_time = 1000;
4171
4172 acpi_delay_time = 15000;
4173 vbi_time_out = 100000;
4174
4175 reference_clock = amdgpu_asic_get_xclk(adev);
4176
4177 vddc_dly = (voltage_response_time * reference_clock) / 100;
4178 acpi_dly = (acpi_delay_time * reference_clock) / 100;
4179 vbi_dly = (vbi_time_out * reference_clock) / 100;
4180
4181 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
4182 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
4183 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4184 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4185}
4186
4187static void si_program_ds_registers(struct amdgpu_device *adev)
4188{
4189 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4190 u32 tmp;
4191
4192 /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4193 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4194 tmp = 0x10;
4195 else
4196 tmp = 0x1;
4197
4198 if (eg_pi->sclk_deep_sleep) {
4199 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
4200 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
4201 ~AUTOSCALE_ON_SS_CLEAR);
4202 }
4203}
4204
4205static void si_program_display_gap(struct amdgpu_device *adev)
4206{
4207 u32 tmp, pipe;
4208 int i;
4209
4210 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4211 if (adev->pm.dpm.new_active_crtc_count > 0)
4212 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4213 else
4214 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4215
4216 if (adev->pm.dpm.new_active_crtc_count > 1)
4217 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4218 else
4219 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4220
4221 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4222
4223 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4224 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4225
4226 if ((adev->pm.dpm.new_active_crtc_count > 0) &&
4227 (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
4228 /* find the first active crtc */
4229 for (i = 0; i < adev->mode_info.num_crtc; i++) {
4230 if (adev->pm.dpm.new_active_crtcs & (1 << i))
4231 break;
4232 }
4233 if (i == adev->mode_info.num_crtc)
4234 pipe = 0;
4235 else
4236 pipe = i;
4237
4238 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4239 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4240 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4241 }
4242
4243 /* Setting this to false forces the performance state to low if the crtcs are disabled.
4244 * This can be a problem on PowerXpress systems or if you want to use the card
4245 * for offscreen rendering or compute if there are no crtcs enabled.
4246 */
4247 si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0);
4248}
4249
4250static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4251{
4252 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4253
4254 if (enable) {
4255 if (pi->sclk_ss)
4256 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
4257 } else {
4258 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
4259 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
4260 }
4261}
4262
4263static void si_setup_bsp(struct amdgpu_device *adev)
4264{
4265 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4266 u32 xclk = amdgpu_asic_get_xclk(adev);
4267
4268 r600_calculate_u_and_p(pi->asi,
4269 xclk,
4270 16,
4271 &pi->bsp,
4272 &pi->bsu);
4273
4274 r600_calculate_u_and_p(pi->pasi,
4275 xclk,
4276 16,
4277 &pi->pbsp,
4278 &pi->pbsu);
4279
4280
4281 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
4282 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
4283
4284 WREG32(CG_BSP, pi->dsp);
4285}
4286
4287static void si_program_git(struct amdgpu_device *adev)
4288{
4289 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
4290}
4291
4292static void si_program_tp(struct amdgpu_device *adev)
4293{
4294 int i;
4295 enum r600_td td = R600_TD_DFLT;
4296
4297 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4298 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
4299
4300 if (td == R600_TD_AUTO)
4301 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4302 else
4303 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4304
4305 if (td == R600_TD_UP)
4306 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4307
4308 if (td == R600_TD_DOWN)
4309 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
4310}
4311
4312static void si_program_tpp(struct amdgpu_device *adev)
4313{
4314 WREG32(CG_TPC, R600_TPC_DFLT);
4315}
4316
4317static void si_program_sstp(struct amdgpu_device *adev)
4318{
4319 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
4320}
4321
4322static void si_enable_display_gap(struct amdgpu_device *adev)
4323{
4324 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
4325
4326 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4327 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
4328 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
4329
4330 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
4331 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
4332 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
4333 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4334}
4335
4336static void si_program_vc(struct amdgpu_device *adev)
4337{
4338 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4339
4340 WREG32(CG_FTV, pi->vrc);
4341}
4342
4343static void si_clear_vc(struct amdgpu_device *adev)
4344{
4345 WREG32(CG_FTV, 0);
4346}
4347
4348static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4349{
4350 u8 mc_para_index;
4351
4352 if (memory_clock < 10000)
4353 mc_para_index = 0;
4354 else if (memory_clock >= 80000)
4355 mc_para_index = 0x0f;
4356 else
4357 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4358 return mc_para_index;
4359}
4360
4361static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4362{
4363 u8 mc_para_index;
4364
4365 if (strobe_mode) {
4366 if (memory_clock < 12500)
4367 mc_para_index = 0x00;
4368 else if (memory_clock > 47500)
4369 mc_para_index = 0x0f;
4370 else
4371 mc_para_index = (u8)((memory_clock - 10000) / 2500);
4372 } else {
4373 if (memory_clock < 65000)
4374 mc_para_index = 0x00;
4375 else if (memory_clock > 135000)
4376 mc_para_index = 0x0f;
4377 else
4378 mc_para_index = (u8)((memory_clock - 60000) / 5000);
4379 }
4380 return mc_para_index;
4381}
4382
4383static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4384{
4385 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4386 bool strobe_mode = false;
4387 u8 result = 0;
4388
4389 if (mclk <= pi->mclk_strobe_mode_threshold)
4390 strobe_mode = true;
4391
4392 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4393 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4394 else
4395 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4396
4397 if (strobe_mode)
4398 result |= SISLANDS_SMC_STROBE_ENABLE;
4399
4400 return result;
4401}
4402
4403static int si_upload_firmware(struct amdgpu_device *adev)
4404{
4405 struct si_power_info *si_pi = si_get_pi(adev);
4406
4407 amdgpu_si_reset_smc(adev);
4408 amdgpu_si_smc_clock(adev, false);
4409
4410 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4411}
4412
4413static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4414 const struct atom_voltage_table *table,
4415 const struct amdgpu_phase_shedding_limits_table *limits)
4416{
4417 u32 data, num_bits, num_levels;
4418
4419 if ((table == NULL) || (limits == NULL))
4420 return false;
4421
4422 data = table->mask_low;
4423
4424 num_bits = hweight32(data);
4425
4426 if (num_bits == 0)
4427 return false;
4428
4429 num_levels = (1 << num_bits);
4430
4431 if (table->count != num_levels)
4432 return false;
4433
4434 if (limits->count != (num_levels - 1))
4435 return false;
4436
4437 return true;
4438}
4439
4440static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4441 u32 max_voltage_steps,
4442 struct atom_voltage_table *voltage_table)
4443{
4444 unsigned int i, diff;
4445
4446 if (voltage_table->count <= max_voltage_steps)
4447 return;
4448
4449 diff = voltage_table->count - max_voltage_steps;
4450
4451 for (i= 0; i < max_voltage_steps; i++)
4452 voltage_table->entries[i] = voltage_table->entries[i + diff];
4453
4454 voltage_table->count = max_voltage_steps;
4455}
4456
4457static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4458 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4459 struct atom_voltage_table *voltage_table)
4460{
4461 u32 i;
4462
4463 if (voltage_dependency_table == NULL)
4464 return -EINVAL;
4465
4466 voltage_table->mask_low = 0;
4467 voltage_table->phase_delay = 0;
4468
4469 voltage_table->count = voltage_dependency_table->count;
4470 for (i = 0; i < voltage_table->count; i++) {
4471 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4472 voltage_table->entries[i].smio_low = 0;
4473 }
4474
4475 return 0;
4476}
4477
4478static int si_construct_voltage_tables(struct amdgpu_device *adev)
4479{
4480 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4481 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4482 struct si_power_info *si_pi = si_get_pi(adev);
4483 int ret;
4484
4485 if (pi->voltage_control) {
4486 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4487 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4488 if (ret)
4489 return ret;
4490
4491 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4492 si_trim_voltage_table_to_fit_state_table(adev,
4493 SISLANDS_MAX_NO_VREG_STEPS,
4494 &eg_pi->vddc_voltage_table);
4495 } else if (si_pi->voltage_control_svi2) {
4496 ret = si_get_svi2_voltage_table(adev,
4497 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4498 &eg_pi->vddc_voltage_table);
4499 if (ret)
4500 return ret;
4501 } else {
4502 return -EINVAL;
4503 }
4504
4505 if (eg_pi->vddci_control) {
4506 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4507 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4508 if (ret)
4509 return ret;
4510
4511 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4512 si_trim_voltage_table_to_fit_state_table(adev,
4513 SISLANDS_MAX_NO_VREG_STEPS,
4514 &eg_pi->vddci_voltage_table);
4515 }
4516 if (si_pi->vddci_control_svi2) {
4517 ret = si_get_svi2_voltage_table(adev,
4518 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4519 &eg_pi->vddci_voltage_table);
4520 if (ret)
4521 return ret;
4522 }
4523
4524 if (pi->mvdd_control) {
4525 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4526 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4527
4528 if (ret) {
4529 pi->mvdd_control = false;
4530 return ret;
4531 }
4532
4533 if (si_pi->mvdd_voltage_table.count == 0) {
4534 pi->mvdd_control = false;
4535 return -EINVAL;
4536 }
4537
4538 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4539 si_trim_voltage_table_to_fit_state_table(adev,
4540 SISLANDS_MAX_NO_VREG_STEPS,
4541 &si_pi->mvdd_voltage_table);
4542 }
4543
4544 if (si_pi->vddc_phase_shed_control) {
4545 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4546 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4547 if (ret)
4548 si_pi->vddc_phase_shed_control = false;
4549
4550 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4551 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4552 si_pi->vddc_phase_shed_control = false;
4553 }
4554
4555 return 0;
4556}
4557
4558static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4559 const struct atom_voltage_table *voltage_table,
4560 SISLANDS_SMC_STATETABLE *table)
4561{
4562 unsigned int i;
4563
4564 for (i = 0; i < voltage_table->count; i++)
4565 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4566}
4567
4568static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4569 SISLANDS_SMC_STATETABLE *table)
4570{
4571 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4572 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4573 struct si_power_info *si_pi = si_get_pi(adev);
4574 u8 i;
4575
4576 if (si_pi->voltage_control_svi2) {
4577 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4578 si_pi->svc_gpio_id);
4579 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4580 si_pi->svd_gpio_id);
4581 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4582 2);
4583 } else {
4584 if (eg_pi->vddc_voltage_table.count) {
4585 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4586 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4587 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4588
4589 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4590 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4591 table->maxVDDCIndexInPPTable = i;
4592 break;
4593 }
4594 }
4595 }
4596
4597 if (eg_pi->vddci_voltage_table.count) {
4598 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4599
4600 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4601 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4602 }
4603
4604
4605 if (si_pi->mvdd_voltage_table.count) {
4606 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4607
4608 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4609 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4610 }
4611
4612 if (si_pi->vddc_phase_shed_control) {
4613 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4614 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4615 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4616
4617 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4618 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4619
4620 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4621 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4622 } else {
4623 si_pi->vddc_phase_shed_control = false;
4624 }
4625 }
4626 }
4627
4628 return 0;
4629}
4630
4631static int si_populate_voltage_value(struct amdgpu_device *adev,
4632 const struct atom_voltage_table *table,
4633 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4634{
4635 unsigned int i;
4636
4637 for (i = 0; i < table->count; i++) {
4638 if (value <= table->entries[i].value) {
4639 voltage->index = (u8)i;
4640 voltage->value = cpu_to_be16(table->entries[i].value);
4641 break;
4642 }
4643 }
4644
4645 if (i >= table->count)
4646 return -EINVAL;
4647
4648 return 0;
4649}
4650
4651static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4652 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4653{
4654 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4655 struct si_power_info *si_pi = si_get_pi(adev);
4656
4657 if (pi->mvdd_control) {
4658 if (mclk <= pi->mvdd_split_frequency)
4659 voltage->index = 0;
4660 else
4661 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4662
4663 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4664 }
4665 return 0;
4666}
4667
4668static int si_get_std_voltage_value(struct amdgpu_device *adev,
4669 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4670 u16 *std_voltage)
4671{
4672 u16 v_index;
4673 bool voltage_found = false;
4674 *std_voltage = be16_to_cpu(voltage->value);
4675
4676 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4677 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4678 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4679 return -EINVAL;
4680
4681 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4682 if (be16_to_cpu(voltage->value) ==
4683 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4684 voltage_found = true;
4685 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4686 *std_voltage =
4687 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4688 else
4689 *std_voltage =
4690 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4691 break;
4692 }
4693 }
4694
4695 if (!voltage_found) {
4696 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4697 if (be16_to_cpu(voltage->value) <=
4698 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4699 voltage_found = true;
4700 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4701 *std_voltage =
4702 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4703 else
4704 *std_voltage =
4705 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4706 break;
4707 }
4708 }
4709 }
4710 } else {
4711 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4712 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4713 }
4714 }
4715
4716 return 0;
4717}
4718
4719static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4720 u16 value, u8 index,
4721 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4722{
4723 voltage->index = index;
4724 voltage->value = cpu_to_be16(value);
4725
4726 return 0;
4727}
4728
4729static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4730 const struct amdgpu_phase_shedding_limits_table *limits,
4731 u16 voltage, u32 sclk, u32 mclk,
4732 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4733{
4734 unsigned int i;
4735
4736 for (i = 0; i < limits->count; i++) {
4737 if ((voltage <= limits->entries[i].voltage) &&
4738 (sclk <= limits->entries[i].sclk) &&
4739 (mclk <= limits->entries[i].mclk))
4740 break;
4741 }
4742
4743 smc_voltage->phase_settings = (u8)i;
4744
4745 return 0;
4746}
4747
4748static int si_init_arb_table_index(struct amdgpu_device *adev)
4749{
4750 struct si_power_info *si_pi = si_get_pi(adev);
4751 u32 tmp;
4752 int ret;
4753
4754 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4755 &tmp, si_pi->sram_end);
4756 if (ret)
4757 return ret;
4758
4759 tmp &= 0x00FFFFFF;
4760 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4761
4762 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4763 tmp, si_pi->sram_end);
4764}
4765
4766static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4767{
4768 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4769}
4770
4771static int si_reset_to_default(struct amdgpu_device *adev)
4772{
4773 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4774 0 : -EINVAL;
4775}
4776
4777static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4778{
4779 struct si_power_info *si_pi = si_get_pi(adev);
4780 u32 tmp;
4781 int ret;
4782
4783 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4784 &tmp, si_pi->sram_end);
4785 if (ret)
4786 return ret;
4787
4788 tmp = (tmp >> 24) & 0xff;
4789
4790 if (tmp == MC_CG_ARB_FREQ_F0)
4791 return 0;
4792
4793 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4794}
4795
4796static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4797 u32 engine_clock)
4798{
4799 u32 dram_rows;
4800 u32 dram_refresh_rate;
4801 u32 mc_arb_rfsh_rate;
4802 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4803
4804 if (tmp >= 4)
4805 dram_rows = 16384;
4806 else
4807 dram_rows = 1 << (tmp + 10);
4808
4809 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4810 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4811
4812 return mc_arb_rfsh_rate;
4813}
4814
4815static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4816 struct rv7xx_pl *pl,
4817 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4818{
4819 u32 dram_timing;
4820 u32 dram_timing2;
4821 u32 burst_time;
4822
4823 arb_regs->mc_arb_rfsh_rate =
4824 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4825
4826 amdgpu_atombios_set_engine_dram_timings(adev,
4827 pl->sclk,
4828 pl->mclk);
4829
4830 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4831 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4832 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4833
4834 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4835 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4836 arb_regs->mc_arb_burst_time = (u8)burst_time;
4837
4838 return 0;
4839}
4840
4841static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4842 struct amdgpu_ps *amdgpu_state,
4843 unsigned int first_arb_set)
4844{
4845 struct si_power_info *si_pi = si_get_pi(adev);
4846 struct si_ps *state = si_get_ps(amdgpu_state);
4847 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4848 int i, ret = 0;
4849
4850 for (i = 0; i < state->performance_level_count; i++) {
4851 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4852 if (ret)
4853 break;
4854 ret = amdgpu_si_copy_bytes_to_smc(adev,
4855 si_pi->arb_table_start +
4856 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4857 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4858 (u8 *)&arb_regs,
4859 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4860 si_pi->sram_end);
4861 if (ret)
4862 break;
4863 }
4864
4865 return ret;
4866}
4867
4868static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4869 struct amdgpu_ps *amdgpu_new_state)
4870{
4871 return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4872 SISLANDS_DRIVER_STATE_ARB_INDEX);
4873}
4874
4875static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4876 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4877{
4878 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4879 struct si_power_info *si_pi = si_get_pi(adev);
4880
4881 if (pi->mvdd_control)
4882 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4883 si_pi->mvdd_bootup_value, voltage);
4884
4885 return 0;
4886}
4887
4888static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4889 struct amdgpu_ps *amdgpu_initial_state,
4890 SISLANDS_SMC_STATETABLE *table)
4891{
4892 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4893 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4894 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4895 struct si_power_info *si_pi = si_get_pi(adev);
4896 u32 reg;
4897 int ret;
4898
4899 table->initialState.levels[0].mclk.vDLL_CNTL =
4900 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4901 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4902 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4903 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4904 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4905 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4906 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4907 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4908 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4909 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4910 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4911 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4912 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4913 table->initialState.levels[0].mclk.vMPLL_SS =
4914 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4915 table->initialState.levels[0].mclk.vMPLL_SS2 =
4916 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4917
4918 table->initialState.levels[0].mclk.mclk_value =
4919 cpu_to_be32(initial_state->performance_levels[0].mclk);
4920
4921 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4922 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4923 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4924 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4925 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4926 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4927 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4928 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4929 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4930 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4931 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4932 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4933
4934 table->initialState.levels[0].sclk.sclk_value =
4935 cpu_to_be32(initial_state->performance_levels[0].sclk);
4936
4937 table->initialState.levels[0].arbRefreshState =
4938 SISLANDS_INITIAL_STATE_ARB_INDEX;
4939
4940 table->initialState.levels[0].ACIndex = 0;
4941
4942 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4943 initial_state->performance_levels[0].vddc,
4944 &table->initialState.levels[0].vddc);
4945
4946 if (!ret) {
4947 u16 std_vddc;
4948
4949 ret = si_get_std_voltage_value(adev,
4950 &table->initialState.levels[0].vddc,
4951 &std_vddc);
4952 if (!ret)
4953 si_populate_std_voltage_value(adev, std_vddc,
4954 table->initialState.levels[0].vddc.index,
4955 &table->initialState.levels[0].std_vddc);
4956 }
4957
4958 if (eg_pi->vddci_control)
4959 si_populate_voltage_value(adev,
4960 &eg_pi->vddci_voltage_table,
4961 initial_state->performance_levels[0].vddci,
4962 &table->initialState.levels[0].vddci);
4963
4964 if (si_pi->vddc_phase_shed_control)
4965 si_populate_phase_shedding_value(adev,
4966 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4967 initial_state->performance_levels[0].vddc,
4968 initial_state->performance_levels[0].sclk,
4969 initial_state->performance_levels[0].mclk,
4970 &table->initialState.levels[0].vddc);
4971
4972 si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
4973
4974 reg = CG_R(0xffff) | CG_L(0);
4975 table->initialState.levels[0].aT = cpu_to_be32(reg);
4976 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4977 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4978
4979 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4980 table->initialState.levels[0].strobeMode =
4981 si_get_strobe_mode_settings(adev,
4982 initial_state->performance_levels[0].mclk);
4983
4984 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4985 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4986 else
4987 table->initialState.levels[0].mcFlags = 0;
4988 }
4989
4990 table->initialState.levelCount = 1;
4991
4992 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4993
4994 table->initialState.levels[0].dpm2.MaxPS = 0;
4995 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4996 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4997 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4998 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4999
5000 reg = MIN_POWER_MASK | MAX_POWER_MASK;
5001 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5002
5003 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5004 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5005
5006 return 0;
5007}
5008
5009static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
5010 SISLANDS_SMC_STATETABLE *table)
5011{
5012 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5013 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5014 struct si_power_info *si_pi = si_get_pi(adev);
5015 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5016 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5017 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5018 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5019 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5020 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5021 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5022 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5023 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5024 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5025 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5026 u32 reg;
5027 int ret;
5028
5029 table->ACPIState = table->initialState;
5030
5031 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
5032
5033 if (pi->acpi_vddc) {
5034 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5035 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
5036 if (!ret) {
5037 u16 std_vddc;
5038
5039 ret = si_get_std_voltage_value(adev,
5040 &table->ACPIState.levels[0].vddc, &std_vddc);
5041 if (!ret)
5042 si_populate_std_voltage_value(adev, std_vddc,
5043 table->ACPIState.levels[0].vddc.index,
5044 &table->ACPIState.levels[0].std_vddc);
5045 }
5046 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
5047
5048 if (si_pi->vddc_phase_shed_control) {
5049 si_populate_phase_shedding_value(adev,
5050 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5051 pi->acpi_vddc,
5052 0,
5053 0,
5054 &table->ACPIState.levels[0].vddc);
5055 }
5056 } else {
5057 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5058 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
5059 if (!ret) {
5060 u16 std_vddc;
5061
5062 ret = si_get_std_voltage_value(adev,
5063 &table->ACPIState.levels[0].vddc, &std_vddc);
5064
5065 if (!ret)
5066 si_populate_std_voltage_value(adev, std_vddc,
5067 table->ACPIState.levels[0].vddc.index,
5068 &table->ACPIState.levels[0].std_vddc);
5069 }
5070 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev,
5071 si_pi->sys_pcie_mask,
5072 si_pi->boot_pcie_gen,
5073 AMDGPU_PCIE_GEN1);
5074
5075 if (si_pi->vddc_phase_shed_control)
5076 si_populate_phase_shedding_value(adev,
5077 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5078 pi->min_vddc_in_table,
5079 0,
5080 0,
5081 &table->ACPIState.levels[0].vddc);
5082 }
5083
5084 if (pi->acpi_vddc) {
5085 if (eg_pi->acpi_vddci)
5086 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5087 eg_pi->acpi_vddci,
5088 &table->ACPIState.levels[0].vddci);
5089 }
5090
5091 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5092 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5093
5094 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5095
5096 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5097 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5098
5099 table->ACPIState.levels[0].mclk.vDLL_CNTL =
5100 cpu_to_be32(dll_cntl);
5101 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
5102 cpu_to_be32(mclk_pwrmgt_cntl);
5103 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
5104 cpu_to_be32(mpll_ad_func_cntl);
5105 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
5106 cpu_to_be32(mpll_dq_func_cntl);
5107 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
5108 cpu_to_be32(mpll_func_cntl);
5109 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
5110 cpu_to_be32(mpll_func_cntl_1);
5111 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
5112 cpu_to_be32(mpll_func_cntl_2);
5113 table->ACPIState.levels[0].mclk.vMPLL_SS =
5114 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5115 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
5116 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5117
5118 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5119 cpu_to_be32(spll_func_cntl);
5120 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
5121 cpu_to_be32(spll_func_cntl_2);
5122 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5123 cpu_to_be32(spll_func_cntl_3);
5124 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
5125 cpu_to_be32(spll_func_cntl_4);
5126
5127 table->ACPIState.levels[0].mclk.mclk_value = 0;
5128 table->ACPIState.levels[0].sclk.sclk_value = 0;
5129
5130 si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
5131
5132 if (eg_pi->dynamic_ac_timing)
5133 table->ACPIState.levels[0].ACIndex = 0;
5134
5135 table->ACPIState.levels[0].dpm2.MaxPS = 0;
5136 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
5137 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
5138 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
5139 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5140
5141 reg = MIN_POWER_MASK | MAX_POWER_MASK;
5142 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5143
5144 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5145 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5146
5147 return 0;
5148}
5149
5150static int si_populate_ulv_state(struct amdgpu_device *adev,
5151 SISLANDS_SMC_SWSTATE *state)
5152{
5153 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5154 struct si_power_info *si_pi = si_get_pi(adev);
5155 struct si_ulv_param *ulv = &si_pi->ulv;
5156 u32 sclk_in_sr = 1350; /* ??? */
5157 int ret;
5158
5159 ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5160 &state->levels[0]);
5161 if (!ret) {
5162 if (eg_pi->sclk_deep_sleep) {
5163 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5164 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5165 else
5166 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5167 }
5168 if (ulv->one_pcie_lane_in_ulv)
5169 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5170 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5171 state->levels[0].ACIndex = 1;
5172 state->levels[0].std_vddc = state->levels[0].vddc;
5173 state->levelCount = 1;
5174
5175 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5176 }
5177
5178 return ret;
5179}
5180
5181static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5182{
5183 struct si_power_info *si_pi = si_get_pi(adev);
5184 struct si_ulv_param *ulv = &si_pi->ulv;
5185 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5186 int ret;
5187
5188 ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5189 &arb_regs);
5190 if (ret)
5191 return ret;
5192
5193 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5194 ulv->volt_change_delay);
5195
5196 ret = amdgpu_si_copy_bytes_to_smc(adev,
5197 si_pi->arb_table_start +
5198 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5199 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5200 (u8 *)&arb_regs,
5201 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5202 si_pi->sram_end);
5203
5204 return ret;
5205}
5206
5207static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5208{
5209 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5210
5211 pi->mvdd_split_frequency = 30000;
5212}
5213
5214static int si_init_smc_table(struct amdgpu_device *adev)
5215{
5216 struct si_power_info *si_pi = si_get_pi(adev);
5217 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5218 const struct si_ulv_param *ulv = &si_pi->ulv;
5219 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
5220 int ret;
5221 u32 lane_width;
5222 u32 vr_hot_gpio;
5223
5224 si_populate_smc_voltage_tables(adev, table);
5225
5226 switch (adev->pm.int_thermal_type) {
5227 case THERMAL_TYPE_SI:
5228 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5229 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5230 break;
5231 case THERMAL_TYPE_NONE:
5232 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5233 break;
5234 default:
5235 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5236 break;
5237 }
5238
5239 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5240 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5241
5242 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5243 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5244 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5245 }
5246
5247 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5248 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5249
5250 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5251 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5252
5253 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5254 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5255
5256 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5257 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5258 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5259 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5260 vr_hot_gpio);
5261 }
5262
5263 ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5264 if (ret)
5265 return ret;
5266
5267 ret = si_populate_smc_acpi_state(adev, table);
5268 if (ret)
5269 return ret;
5270
5271 table->driverState = table->initialState;
5272
5273 ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5274 SISLANDS_INITIAL_STATE_ARB_INDEX);
5275 if (ret)
5276 return ret;
5277
5278 if (ulv->supported && ulv->pl.vddc) {
5279 ret = si_populate_ulv_state(adev, &table->ULVState);
5280 if (ret)
5281 return ret;
5282
5283 ret = si_program_ulv_memory_timing_parameters(adev);
5284 if (ret)
5285 return ret;
5286
5287 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
5288 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5289
5290 lane_width = amdgpu_get_pcie_lanes(adev);
5291 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5292 } else {
5293 table->ULVState = table->initialState;
5294 }
5295
5296 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5297 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5298 si_pi->sram_end);
5299}
5300
5301static int si_calculate_sclk_params(struct amdgpu_device *adev,
5302 u32 engine_clock,
5303 SISLANDS_SMC_SCLK_VALUE *sclk)
5304{
5305 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5306 struct si_power_info *si_pi = si_get_pi(adev);
5307 struct atom_clock_dividers dividers;
5308 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5309 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5310 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5311 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5312 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5313 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5314 u64 tmp;
5315 u32 reference_clock = adev->clock.spll.reference_freq;
5316 u32 reference_divider;
5317 u32 fbdiv;
5318 int ret;
5319
5320 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5321 engine_clock, false, ÷rs);
5322 if (ret)
5323 return ret;
5324
5325 reference_divider = 1 + dividers.ref_div;
5326
5327 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5328 do_div(tmp, reference_clock);
5329 fbdiv = (u32) tmp;
5330
5331 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5332 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5333 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5334
5335 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5336 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5337
5338 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
5339 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
5340 spll_func_cntl_3 |= SPLL_DITHEN;
5341
5342 if (pi->sclk_ss) {
5343 struct amdgpu_atom_ss ss;
5344 u32 vco_freq = engine_clock * dividers.post_div;
5345
5346 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5347 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5348 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5349 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5350
5351 cg_spll_spread_spectrum &= ~CLK_S_MASK;
5352 cg_spll_spread_spectrum |= CLK_S(clk_s);
5353 cg_spll_spread_spectrum |= SSEN;
5354
5355 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
5356 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
5357 }
5358 }
5359
5360 sclk->sclk_value = engine_clock;
5361 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5362 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5363 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5364 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5365 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5366 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5367
5368 return 0;
5369}
5370
5371static int si_populate_sclk_value(struct amdgpu_device *adev,
5372 u32 engine_clock,
5373 SISLANDS_SMC_SCLK_VALUE *sclk)
5374{
5375 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5376 int ret;
5377
5378 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5379 if (!ret) {
5380 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5381 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5382 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5383 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5384 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5385 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5386 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5387 }
5388
5389 return ret;
5390}
5391
5392static int si_populate_mclk_value(struct amdgpu_device *adev,
5393 u32 engine_clock,
5394 u32 memory_clock,
5395 SISLANDS_SMC_MCLK_VALUE *mclk,
5396 bool strobe_mode,
5397 bool dll_state_on)
5398{
5399 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5400 struct si_power_info *si_pi = si_get_pi(adev);
5401 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5402 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5403 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5404 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5405 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5406 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5407 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5408 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5409 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5410 struct atom_mpll_param mpll_param;
5411 int ret;
5412
5413 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5414 if (ret)
5415 return ret;
5416
5417 mpll_func_cntl &= ~BWCTRL_MASK;
5418 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5419
5420 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5421 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5422 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5423
5424 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5425 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5426
5427 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5428 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5429 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5430 YCLK_POST_DIV(mpll_param.post_div);
5431 }
5432
5433 if (pi->mclk_ss) {
5434 struct amdgpu_atom_ss ss;
5435 u32 freq_nom;
5436 u32 tmp;
5437 u32 reference_clock = adev->clock.mpll.reference_freq;
5438
5439 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5440 freq_nom = memory_clock * 4;
5441 else
5442 freq_nom = memory_clock * 2;
5443
5444 tmp = freq_nom / reference_clock;
5445 tmp = tmp * tmp;
5446 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5447 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
5448 u32 clks = reference_clock * 5 / ss.rate;
5449 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5450
5451 mpll_ss1 &= ~CLKV_MASK;
5452 mpll_ss1 |= CLKV(clkv);
5453
5454 mpll_ss2 &= ~CLKS_MASK;
5455 mpll_ss2 |= CLKS(clks);
5456 }
5457 }
5458
5459 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5460 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5461
5462 if (dll_state_on)
5463 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5464 else
5465 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5466
5467 mclk->mclk_value = cpu_to_be32(memory_clock);
5468 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5469 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5470 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5471 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5472 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5473 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5474 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5475 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5476 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5477
5478 return 0;
5479}
5480
5481static void si_populate_smc_sp(struct amdgpu_device *adev,
5482 struct amdgpu_ps *amdgpu_state,
5483 SISLANDS_SMC_SWSTATE *smc_state)
5484{
5485 struct si_ps *ps = si_get_ps(amdgpu_state);
5486 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5487 int i;
5488
5489 for (i = 0; i < ps->performance_level_count - 1; i++)
5490 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5491
5492 smc_state->levels[ps->performance_level_count - 1].bSP =
5493 cpu_to_be32(pi->psp);
5494}
5495
5496static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5497 struct rv7xx_pl *pl,
5498 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5499{
5500 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5501 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5502 struct si_power_info *si_pi = si_get_pi(adev);
5503 int ret;
5504 bool dll_state_on;
5505 u16 std_vddc;
5506 bool gmc_pg = false;
5507
5508 if (eg_pi->pcie_performance_request &&
5509 (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))
5510 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5511 else
5512 level->gen2PCIE = (u8)pl->pcie_gen;
5513
5514 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5515 if (ret)
5516 return ret;
5517
5518 level->mcFlags = 0;
5519
5520 if (pi->mclk_stutter_mode_threshold &&
5521 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5522 !eg_pi->uvd_enabled &&
5523 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5524 (adev->pm.dpm.new_active_crtc_count <= 2)) {
5525 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5526
5527 if (gmc_pg)
5528 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5529 }
5530
5531 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5532 if (pl->mclk > pi->mclk_edc_enable_threshold)
5533 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5534
5535 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5536 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5537
5538 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5539
5540 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5541 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5542 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5543 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5544 else
5545 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5546 } else {
5547 dll_state_on = false;
5548 }
5549 } else {
5550 level->strobeMode = si_get_strobe_mode_settings(adev,
5551 pl->mclk);
5552
5553 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5554 }
5555
5556 ret = si_populate_mclk_value(adev,
5557 pl->sclk,
5558 pl->mclk,
5559 &level->mclk,
5560 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5561 if (ret)
5562 return ret;
5563
5564 ret = si_populate_voltage_value(adev,
5565 &eg_pi->vddc_voltage_table,
5566 pl->vddc, &level->vddc);
5567 if (ret)
5568 return ret;
5569
5570
5571 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5572 if (ret)
5573 return ret;
5574
5575 ret = si_populate_std_voltage_value(adev, std_vddc,
5576 level->vddc.index, &level->std_vddc);
5577 if (ret)
5578 return ret;
5579
5580 if (eg_pi->vddci_control) {
5581 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5582 pl->vddci, &level->vddci);
5583 if (ret)
5584 return ret;
5585 }
5586
5587 if (si_pi->vddc_phase_shed_control) {
5588 ret = si_populate_phase_shedding_value(adev,
5589 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5590 pl->vddc,
5591 pl->sclk,
5592 pl->mclk,
5593 &level->vddc);
5594 if (ret)
5595 return ret;
5596 }
5597
5598 level->MaxPoweredUpCU = si_pi->max_cu;
5599
5600 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5601
5602 return ret;
5603}
5604
5605static int si_populate_smc_t(struct amdgpu_device *adev,
5606 struct amdgpu_ps *amdgpu_state,
5607 SISLANDS_SMC_SWSTATE *smc_state)
5608{
5609 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5610 struct si_ps *state = si_get_ps(amdgpu_state);
5611 u32 a_t;
5612 u32 t_l, t_h;
5613 u32 high_bsp;
5614 int i, ret;
5615
5616 if (state->performance_level_count >= 9)
5617 return -EINVAL;
5618
5619 if (state->performance_level_count < 2) {
5620 a_t = CG_R(0xffff) | CG_L(0);
5621 smc_state->levels[0].aT = cpu_to_be32(a_t);
5622 return 0;
5623 }
5624
5625 smc_state->levels[0].aT = cpu_to_be32(0);
5626
5627 for (i = 0; i <= state->performance_level_count - 2; i++) {
5628 ret = r600_calculate_at(
5629 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5630 100 * R600_AH_DFLT,
5631 state->performance_levels[i + 1].sclk,
5632 state->performance_levels[i].sclk,
5633 &t_l,
5634 &t_h);
5635
5636 if (ret) {
5637 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5638 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5639 }
5640
5641 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5642 a_t |= CG_R(t_l * pi->bsp / 20000);
5643 smc_state->levels[i].aT = cpu_to_be32(a_t);
5644
5645 high_bsp = (i == state->performance_level_count - 2) ?
5646 pi->pbsp : pi->bsp;
5647 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5648 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5649 }
5650
5651 return 0;
5652}
5653
5654static int si_disable_ulv(struct amdgpu_device *adev)
5655{
5656 struct si_power_info *si_pi = si_get_pi(adev);
5657 struct si_ulv_param *ulv = &si_pi->ulv;
5658
5659 if (ulv->supported)
5660 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5661 0 : -EINVAL;
5662
5663 return 0;
5664}
5665
5666static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5667 struct amdgpu_ps *amdgpu_state)
5668{
5669 const struct si_power_info *si_pi = si_get_pi(adev);
5670 const struct si_ulv_param *ulv = &si_pi->ulv;
5671 const struct si_ps *state = si_get_ps(amdgpu_state);
5672 int i;
5673
5674 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5675 return false;
5676
5677 /* XXX validate against display requirements! */
5678
5679 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5680 if (adev->clock.current_dispclk <=
5681 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5682 if (ulv->pl.vddc <
5683 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5684 return false;
5685 }
5686 }
5687
5688 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5689 return false;
5690
5691 return true;
5692}
5693
5694static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5695 struct amdgpu_ps *amdgpu_new_state)
5696{
5697 const struct si_power_info *si_pi = si_get_pi(adev);
5698 const struct si_ulv_param *ulv = &si_pi->ulv;
5699
5700 if (ulv->supported) {
5701 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5702 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5703 0 : -EINVAL;
5704 }
5705 return 0;
5706}
5707
5708static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5709 struct amdgpu_ps *amdgpu_state,
5710 SISLANDS_SMC_SWSTATE *smc_state)
5711{
5712 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5713 struct ni_power_info *ni_pi = ni_get_pi(adev);
5714 struct si_power_info *si_pi = si_get_pi(adev);
5715 struct si_ps *state = si_get_ps(amdgpu_state);
5716 int i, ret;
5717 u32 threshold;
5718 u32 sclk_in_sr = 1350; /* ??? */
5719
5720 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5721 return -EINVAL;
5722
5723 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5724
5725 if (amdgpu_state->vclk && amdgpu_state->dclk) {
5726 eg_pi->uvd_enabled = true;
5727 if (eg_pi->smu_uvd_hs)
5728 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5729 } else {
5730 eg_pi->uvd_enabled = false;
5731 }
5732
5733 if (state->dc_compatible)
5734 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5735
5736 smc_state->levelCount = 0;
5737 for (i = 0; i < state->performance_level_count; i++) {
5738 if (eg_pi->sclk_deep_sleep) {
5739 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5740 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5741 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5742 else
5743 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5744 }
5745 }
5746
5747 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5748 &smc_state->levels[i]);
5749 smc_state->levels[i].arbRefreshState =
5750 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5751
5752 if (ret)
5753 return ret;
5754
5755 if (ni_pi->enable_power_containment)
5756 smc_state->levels[i].displayWatermark =
5757 (state->performance_levels[i].sclk < threshold) ?
5758 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5759 else
5760 smc_state->levels[i].displayWatermark = (i < 2) ?
5761 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5762
5763 if (eg_pi->dynamic_ac_timing)
5764 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5765 else
5766 smc_state->levels[i].ACIndex = 0;
5767
5768 smc_state->levelCount++;
5769 }
5770
5771 si_write_smc_soft_register(adev,
5772 SI_SMC_SOFT_REGISTER_watermark_threshold,
5773 threshold / 512);
5774
5775 si_populate_smc_sp(adev, amdgpu_state, smc_state);
5776
5777 ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5778 if (ret)
5779 ni_pi->enable_power_containment = false;
5780
5781 ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
5782 if (ret)
5783 ni_pi->enable_sq_ramping = false;
5784
5785 return si_populate_smc_t(adev, amdgpu_state, smc_state);
5786}
5787
5788static int si_upload_sw_state(struct amdgpu_device *adev,
5789 struct amdgpu_ps *amdgpu_new_state)
5790{
5791 struct si_power_info *si_pi = si_get_pi(adev);
5792 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
5793 int ret;
5794 u32 address = si_pi->state_table_start +
5795 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5796 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5797 ((new_state->performance_level_count - 1) *
5798 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5799 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5800
5801 memset(smc_state, 0, state_size);
5802
5803 ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5804 if (ret)
5805 return ret;
5806
5807 return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5808 state_size, si_pi->sram_end);
5809}
5810
5811static int si_upload_ulv_state(struct amdgpu_device *adev)
5812{
5813 struct si_power_info *si_pi = si_get_pi(adev);
5814 struct si_ulv_param *ulv = &si_pi->ulv;
5815 int ret = 0;
5816
5817 if (ulv->supported && ulv->pl.vddc) {
5818 u32 address = si_pi->state_table_start +
5819 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5820 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5821 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5822
5823 memset(smc_state, 0, state_size);
5824
5825 ret = si_populate_ulv_state(adev, smc_state);
5826 if (!ret)
5827 ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5828 state_size, si_pi->sram_end);
5829 }
5830
5831 return ret;
5832}
5833
5834static int si_upload_smc_data(struct amdgpu_device *adev)
5835{
5836 struct amdgpu_crtc *amdgpu_crtc = NULL;
5837 int i;
5838
5839 if (adev->pm.dpm.new_active_crtc_count == 0)
5840 return 0;
5841
5842 for (i = 0; i < adev->mode_info.num_crtc; i++) {
5843 if (adev->pm.dpm.new_active_crtcs & (1 << i)) {
5844 amdgpu_crtc = adev->mode_info.crtcs[i];
5845 break;
5846 }
5847 }
5848
5849 if (amdgpu_crtc == NULL)
5850 return 0;
5851
5852 if (amdgpu_crtc->line_time <= 0)
5853 return 0;
5854
5855 if (si_write_smc_soft_register(adev,
5856 SI_SMC_SOFT_REGISTER_crtc_index,
5857 amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
5858 return 0;
5859
5860 if (si_write_smc_soft_register(adev,
5861 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5862 amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5863 return 0;
5864
5865 if (si_write_smc_soft_register(adev,
5866 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5867 amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5868 return 0;
5869
5870 return 0;
5871}
5872
5873static int si_set_mc_special_registers(struct amdgpu_device *adev,
5874 struct si_mc_reg_table *table)
5875{
5876 u8 i, j, k;
5877 u32 temp_reg;
5878
5879 for (i = 0, j = table->last; i < table->last; i++) {
5880 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5881 return -EINVAL;
5882 switch (table->mc_reg_address[i].s1) {
5883 case MC_SEQ_MISC1:
5884 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5885 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5886 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5887 for (k = 0; k < table->num_entries; k++)
5888 table->mc_reg_table_entry[k].mc_data[j] =
5889 ((temp_reg & 0xffff0000)) |
5890 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5891 j++;
5892 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5893 return -EINVAL;
5894
5895 temp_reg = RREG32(MC_PMG_CMD_MRS);
5896 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5897 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5898 for (k = 0; k < table->num_entries; k++) {
5899 table->mc_reg_table_entry[k].mc_data[j] =
5900 (temp_reg & 0xffff0000) |
5901 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5902 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5903 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5904 }
5905 j++;
5906 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5907 return -EINVAL;
5908
5909 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5910 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5911 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5912 for (k = 0; k < table->num_entries; k++)
5913 table->mc_reg_table_entry[k].mc_data[j] =
5914 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5915 j++;
5916 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5917 return -EINVAL;
5918 }
5919 break;
5920 case MC_SEQ_RESERVE_M:
5921 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5922 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5923 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5924 for(k = 0; k < table->num_entries; k++)
5925 table->mc_reg_table_entry[k].mc_data[j] =
5926 (temp_reg & 0xffff0000) |
5927 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5928 j++;
5929 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5930 return -EINVAL;
5931 break;
5932 default:
5933 break;
5934 }
5935 }
5936
5937 table->last = j;
5938
5939 return 0;
5940}
5941
5942static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5943{
5944 bool result = true;
5945 switch (in_reg) {
5946 case MC_SEQ_RAS_TIMING:
5947 *out_reg = MC_SEQ_RAS_TIMING_LP;
5948 break;
5949 case MC_SEQ_CAS_TIMING:
5950 *out_reg = MC_SEQ_CAS_TIMING_LP;
5951 break;
5952 case MC_SEQ_MISC_TIMING:
5953 *out_reg = MC_SEQ_MISC_TIMING_LP;
5954 break;
5955 case MC_SEQ_MISC_TIMING2:
5956 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5957 break;
5958 case MC_SEQ_RD_CTL_D0:
5959 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5960 break;
5961 case MC_SEQ_RD_CTL_D1:
5962 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5963 break;
5964 case MC_SEQ_WR_CTL_D0:
5965 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5966 break;
5967 case MC_SEQ_WR_CTL_D1:
5968 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5969 break;
5970 case MC_PMG_CMD_EMRS:
5971 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5972 break;
5973 case MC_PMG_CMD_MRS:
5974 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5975 break;
5976 case MC_PMG_CMD_MRS1:
5977 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5978 break;
5979 case MC_SEQ_PMG_TIMING:
5980 *out_reg = MC_SEQ_PMG_TIMING_LP;
5981 break;
5982 case MC_PMG_CMD_MRS2:
5983 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5984 break;
5985 case MC_SEQ_WR_CTL_2:
5986 *out_reg = MC_SEQ_WR_CTL_2_LP;
5987 break;
5988 default:
5989 result = false;
5990 break;
5991 }
5992
5993 return result;
5994}
5995
5996static void si_set_valid_flag(struct si_mc_reg_table *table)
5997{
5998 u8 i, j;
5999
6000 for (i = 0; i < table->last; i++) {
6001 for (j = 1; j < table->num_entries; j++) {
6002 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
6003 table->valid_flag |= 1 << i;
6004 break;
6005 }
6006 }
6007 }
6008}
6009
6010static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
6011{
6012 u32 i;
6013 u16 address;
6014
6015 for (i = 0; i < table->last; i++)
6016 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
6017 address : table->mc_reg_address[i].s1;
6018
6019}
6020
6021static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
6022 struct si_mc_reg_table *si_table)
6023{
6024 u8 i, j;
6025
6026 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6027 return -EINVAL;
6028 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
6029 return -EINVAL;
6030
6031 for (i = 0; i < table->last; i++)
6032 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
6033 si_table->last = table->last;
6034
6035 for (i = 0; i < table->num_entries; i++) {
6036 si_table->mc_reg_table_entry[i].mclk_max =
6037 table->mc_reg_table_entry[i].mclk_max;
6038 for (j = 0; j < table->last; j++) {
6039 si_table->mc_reg_table_entry[i].mc_data[j] =
6040 table->mc_reg_table_entry[i].mc_data[j];
6041 }
6042 }
6043 si_table->num_entries = table->num_entries;
6044
6045 return 0;
6046}
6047
6048static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
6049{
6050 struct si_power_info *si_pi = si_get_pi(adev);
6051 struct atom_mc_reg_table *table;
6052 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
6053 u8 module_index = rv770_get_memory_module_index(adev);
6054 int ret;
6055
6056 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
6057 if (!table)
6058 return -ENOMEM;
6059
6060 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
6061 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
6062 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
6063 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
6064 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
6065 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
6066 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
6067 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
6068 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6069 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6070 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6071 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6072 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6073 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6074
6075 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6076 if (ret)
6077 goto init_mc_done;
6078
6079 ret = si_copy_vbios_mc_reg_table(table, si_table);
6080 if (ret)
6081 goto init_mc_done;
6082
6083 si_set_s0_mc_reg_index(si_table);
6084
6085 ret = si_set_mc_special_registers(adev, si_table);
6086 if (ret)
6087 goto init_mc_done;
6088
6089 si_set_valid_flag(si_table);
6090
6091init_mc_done:
6092 kfree(table);
6093
6094 return ret;
6095
6096}
6097
6098static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6099 SMC_SIslands_MCRegisters *mc_reg_table)
6100{
6101 struct si_power_info *si_pi = si_get_pi(adev);
6102 u32 i, j;
6103
6104 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6105 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6106 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6107 break;
6108 mc_reg_table->address[i].s0 =
6109 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6110 mc_reg_table->address[i].s1 =
6111 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6112 i++;
6113 }
6114 }
6115 mc_reg_table->last = (u8)i;
6116}
6117
6118static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6119 SMC_SIslands_MCRegisterSet *data,
6120 u32 num_entries, u32 valid_flag)
6121{
6122 u32 i, j;
6123
6124 for(i = 0, j = 0; j < num_entries; j++) {
6125 if (valid_flag & (1 << j)) {
6126 data->value[i] = cpu_to_be32(entry->mc_data[j]);
6127 i++;
6128 }
6129 }
6130}
6131
6132static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6133 struct rv7xx_pl *pl,
6134 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6135{
6136 struct si_power_info *si_pi = si_get_pi(adev);
6137 u32 i = 0;
6138
6139 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6140 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6141 break;
6142 }
6143
6144 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6145 --i;
6146
6147 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6148 mc_reg_table_data, si_pi->mc_reg_table.last,
6149 si_pi->mc_reg_table.valid_flag);
6150}
6151
6152static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6153 struct amdgpu_ps *amdgpu_state,
6154 SMC_SIslands_MCRegisters *mc_reg_table)
6155{
6156 struct si_ps *state = si_get_ps(amdgpu_state);
6157 int i;
6158
6159 for (i = 0; i < state->performance_level_count; i++) {
6160 si_convert_mc_reg_table_entry_to_smc(adev,
6161 &state->performance_levels[i],
6162 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6163 }
6164}
6165
6166static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6167 struct amdgpu_ps *amdgpu_boot_state)
6168{
6169 struct si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6170 struct si_power_info *si_pi = si_get_pi(adev);
6171 struct si_ulv_param *ulv = &si_pi->ulv;
6172 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6173
6174 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6175
6176 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6177
6178 si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6179
6180 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6181 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6182
6183 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6184 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6185 si_pi->mc_reg_table.last,
6186 si_pi->mc_reg_table.valid_flag);
6187
6188 if (ulv->supported && ulv->pl.vddc != 0)
6189 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6190 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6191 else
6192 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6193 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6194 si_pi->mc_reg_table.last,
6195 si_pi->mc_reg_table.valid_flag);
6196
6197 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6198
6199 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6200 (u8 *)smc_mc_reg_table,
6201 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6202}
6203
6204static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6205 struct amdgpu_ps *amdgpu_new_state)
6206{
6207 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
6208 struct si_power_info *si_pi = si_get_pi(adev);
6209 u32 address = si_pi->mc_reg_table_start +
6210 offsetof(SMC_SIslands_MCRegisters,
6211 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6212 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6213
6214 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6215
6216 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6217
6218 return amdgpu_si_copy_bytes_to_smc(adev, address,
6219 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6220 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6221 si_pi->sram_end);
6222}
6223
6224static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6225{
6226 if (enable)
6227 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
6228 else
6229 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
6230}
6231
6232static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6233 struct amdgpu_ps *amdgpu_state)
6234{
6235 struct si_ps *state = si_get_ps(amdgpu_state);
6236 int i;
6237 u16 pcie_speed, max_speed = 0;
6238
6239 for (i = 0; i < state->performance_level_count; i++) {
6240 pcie_speed = state->performance_levels[i].pcie_gen;
6241 if (max_speed < pcie_speed)
6242 max_speed = pcie_speed;
6243 }
6244 return max_speed;
6245}
6246
6247static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6248{
6249 u32 speed_cntl;
6250
6251 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
6252 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
6253
6254 return (u16)speed_cntl;
6255}
6256
6257static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6258 struct amdgpu_ps *amdgpu_new_state,
6259 struct amdgpu_ps *amdgpu_current_state)
6260{
6261 struct si_power_info *si_pi = si_get_pi(adev);
6262 enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6263 enum amdgpu_pcie_gen current_link_speed;
6264
6265 if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
6266 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6267 else
6268 current_link_speed = si_pi->force_pcie_gen;
6269
6270 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
6271 si_pi->pspp_notify_required = false;
6272 if (target_link_speed > current_link_speed) {
6273 switch (target_link_speed) {
6274#if defined(CONFIG_ACPI)
6275 case AMDGPU_PCIE_GEN3:
6276 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6277 break;
6278 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6279 if (current_link_speed == AMDGPU_PCIE_GEN2)
6280 break;
6281 case AMDGPU_PCIE_GEN2:
6282 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6283 break;
6284#endif
6285 default:
6286 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6287 break;
6288 }
6289 } else {
6290 if (target_link_speed < current_link_speed)
6291 si_pi->pspp_notify_required = true;
6292 }
6293}
6294
6295static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6296 struct amdgpu_ps *amdgpu_new_state,
6297 struct amdgpu_ps *amdgpu_current_state)
6298{
6299 struct si_power_info *si_pi = si_get_pi(adev);
6300 enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6301 u8 request;
6302
6303 if (si_pi->pspp_notify_required) {
6304 if (target_link_speed == AMDGPU_PCIE_GEN3)
6305 request = PCIE_PERF_REQ_PECI_GEN3;
6306 else if (target_link_speed == AMDGPU_PCIE_GEN2)
6307 request = PCIE_PERF_REQ_PECI_GEN2;
6308 else
6309 request = PCIE_PERF_REQ_PECI_GEN1;
6310
6311 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6312 (si_get_current_pcie_speed(adev) > 0))
6313 return;
6314
6315#if defined(CONFIG_ACPI)
6316 amdgpu_acpi_pcie_performance_request(adev, request, false);
6317#endif
6318 }
6319}
6320
6321#if 0
6322static int si_ds_request(struct amdgpu_device *adev,
6323 bool ds_status_on, u32 count_write)
6324{
6325 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6326
6327 if (eg_pi->sclk_deep_sleep) {
6328 if (ds_status_on)
6329 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6330 PPSMC_Result_OK) ?
6331 0 : -EINVAL;
6332 else
6333 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6334 PPSMC_Result_OK) ? 0 : -EINVAL;
6335 }
6336 return 0;
6337}
6338#endif
6339
6340static void si_set_max_cu_value(struct amdgpu_device *adev)
6341{
6342 struct si_power_info *si_pi = si_get_pi(adev);
6343
6344 if (adev->asic_type == CHIP_VERDE) {
6345 switch (adev->pdev->device) {
6346 case 0x6820:
6347 case 0x6825:
6348 case 0x6821:
6349 case 0x6823:
6350 case 0x6827:
6351 si_pi->max_cu = 10;
6352 break;
6353 case 0x682D:
6354 case 0x6824:
6355 case 0x682F:
6356 case 0x6826:
6357 si_pi->max_cu = 8;
6358 break;
6359 case 0x6828:
6360 case 0x6830:
6361 case 0x6831:
6362 case 0x6838:
6363 case 0x6839:
6364 case 0x683D:
6365 si_pi->max_cu = 10;
6366 break;
6367 case 0x683B:
6368 case 0x683F:
6369 case 0x6829:
6370 si_pi->max_cu = 8;
6371 break;
6372 default:
6373 si_pi->max_cu = 0;
6374 break;
6375 }
6376 } else {
6377 si_pi->max_cu = 0;
6378 }
6379}
6380
6381static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6382 struct amdgpu_clock_voltage_dependency_table *table)
6383{
6384 u32 i;
6385 int j;
6386 u16 leakage_voltage;
6387
6388 if (table) {
6389 for (i = 0; i < table->count; i++) {
6390 switch (si_get_leakage_voltage_from_leakage_index(adev,
6391 table->entries[i].v,
6392 &leakage_voltage)) {
6393 case 0:
6394 table->entries[i].v = leakage_voltage;
6395 break;
6396 case -EAGAIN:
6397 return -EINVAL;
6398 case -EINVAL:
6399 default:
6400 break;
6401 }
6402 }
6403
6404 for (j = (table->count - 2); j >= 0; j--) {
6405 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6406 table->entries[j].v : table->entries[j + 1].v;
6407 }
6408 }
6409 return 0;
6410}
6411
6412static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6413{
6414 int ret = 0;
6415
6416 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6417 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6418 if (ret)
6419 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
6420 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6421 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6422 if (ret)
6423 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
6424 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6425 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6426 if (ret)
6427 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
6428 return ret;
6429}
6430
6431static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6432 struct amdgpu_ps *amdgpu_new_state,
6433 struct amdgpu_ps *amdgpu_current_state)
6434{
6435 u32 lane_width;
6436 u32 new_lane_width =
6437 (amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6438 u32 current_lane_width =
6439 (amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6440
6441 if (new_lane_width != current_lane_width) {
6442 amdgpu_set_pcie_lanes(adev, new_lane_width);
6443 lane_width = amdgpu_get_pcie_lanes(adev);
6444 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6445 }
6446}
6447
6448static void si_dpm_setup_asic(struct amdgpu_device *adev)
6449{
6450 si_read_clock_registers(adev);
6451 si_enable_acpi_power_management(adev);
6452}
6453
6454static int si_thermal_enable_alert(struct amdgpu_device *adev,
6455 bool enable)
6456{
6457 u32 thermal_int = RREG32(CG_THERMAL_INT);
6458
6459 if (enable) {
6460 PPSMC_Result result;
6461
6462 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6463 WREG32(CG_THERMAL_INT, thermal_int);
6464 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6465 if (result != PPSMC_Result_OK) {
6466 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6467 return -EINVAL;
6468 }
6469 } else {
6470 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6471 WREG32(CG_THERMAL_INT, thermal_int);
6472 }
6473
6474 return 0;
6475}
6476
6477static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6478 int min_temp, int max_temp)
6479{
6480 int low_temp = 0 * 1000;
6481 int high_temp = 255 * 1000;
6482
6483 if (low_temp < min_temp)
6484 low_temp = min_temp;
6485 if (high_temp > max_temp)
6486 high_temp = max_temp;
6487 if (high_temp < low_temp) {
6488 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6489 return -EINVAL;
6490 }
6491
6492 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6493 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6494 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6495
6496 adev->pm.dpm.thermal.min_temp = low_temp;
6497 adev->pm.dpm.thermal.max_temp = high_temp;
6498
6499 return 0;
6500}
6501
6502static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6503{
6504 struct si_power_info *si_pi = si_get_pi(adev);
6505 u32 tmp;
6506
6507 if (si_pi->fan_ctrl_is_in_default_mode) {
6508 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6509 si_pi->fan_ctrl_default_mode = tmp;
6510 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6511 si_pi->t_min = tmp;
6512 si_pi->fan_ctrl_is_in_default_mode = false;
6513 }
6514
6515 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6516 tmp |= TMIN(0);
6517 WREG32(CG_FDO_CTRL2, tmp);
6518
6519 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6520 tmp |= FDO_PWM_MODE(mode);
6521 WREG32(CG_FDO_CTRL2, tmp);
6522}
6523
6524static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6525{
6526 struct si_power_info *si_pi = si_get_pi(adev);
6527 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6528 u32 duty100;
6529 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6530 u16 fdo_min, slope1, slope2;
6531 u32 reference_clock, tmp;
6532 int ret;
6533 u64 tmp64;
6534
6535 if (!si_pi->fan_table_start) {
6536 adev->pm.dpm.fan.ucode_fan_control = false;
6537 return 0;
6538 }
6539
6540 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6541
6542 if (duty100 == 0) {
6543 adev->pm.dpm.fan.ucode_fan_control = false;
6544 return 0;
6545 }
6546
6547 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6548 do_div(tmp64, 10000);
6549 fdo_min = (u16)tmp64;
6550
6551 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6552 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6553
6554 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6555 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6556
6557 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6558 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6559
6560 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6561 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6562 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
6563 fan_table.slope1 = cpu_to_be16(slope1);
6564 fan_table.slope2 = cpu_to_be16(slope2);
6565 fan_table.fdo_min = cpu_to_be16(fdo_min);
6566 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
6567 fan_table.hys_up = cpu_to_be16(1);
6568 fan_table.hys_slope = cpu_to_be16(1);
6569 fan_table.temp_resp_lim = cpu_to_be16(5);
6570 reference_clock = amdgpu_asic_get_xclk(adev);
6571
6572 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6573 reference_clock) / 1600);
6574 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6575
6576 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6577 fan_table.temp_src = (uint8_t)tmp;
6578
6579 ret = amdgpu_si_copy_bytes_to_smc(adev,
6580 si_pi->fan_table_start,
6581 (u8 *)(&fan_table),
6582 sizeof(fan_table),
6583 si_pi->sram_end);
6584
6585 if (ret) {
6586 DRM_ERROR("Failed to load fan table to the SMC.");
6587 adev->pm.dpm.fan.ucode_fan_control = false;
6588 }
6589
6590 return ret;
6591}
6592
6593static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6594{
6595 struct si_power_info *si_pi = si_get_pi(adev);
6596 PPSMC_Result ret;
6597
6598 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6599 if (ret == PPSMC_Result_OK) {
6600 si_pi->fan_is_controlled_by_smc = true;
6601 return 0;
6602 } else {
6603 return -EINVAL;
6604 }
6605}
6606
6607static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6608{
6609 struct si_power_info *si_pi = si_get_pi(adev);
6610 PPSMC_Result ret;
6611
6612 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6613
6614 if (ret == PPSMC_Result_OK) {
6615 si_pi->fan_is_controlled_by_smc = false;
6616 return 0;
6617 } else {
6618 return -EINVAL;
6619 }
6620}
6621
6622static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
6623 u32 *speed)
6624{
6625 u32 duty, duty100;
6626 u64 tmp64;
6627
6628 if (adev->pm.no_fan)
6629 return -ENOENT;
6630
6631 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6632 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6633
6634 if (duty100 == 0)
6635 return -EINVAL;
6636
6637 tmp64 = (u64)duty * 100;
6638 do_div(tmp64, duty100);
6639 *speed = (u32)tmp64;
6640
6641 if (*speed > 100)
6642 *speed = 100;
6643
6644 return 0;
6645}
6646
6647static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
6648 u32 speed)
6649{
6650 struct si_power_info *si_pi = si_get_pi(adev);
6651 u32 tmp;
6652 u32 duty, duty100;
6653 u64 tmp64;
6654
6655 if (adev->pm.no_fan)
6656 return -ENOENT;
6657
6658 if (si_pi->fan_is_controlled_by_smc)
6659 return -EINVAL;
6660
6661 if (speed > 100)
6662 return -EINVAL;
6663
6664 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6665
6666 if (duty100 == 0)
6667 return -EINVAL;
6668
6669 tmp64 = (u64)speed * duty100;
6670 do_div(tmp64, 100);
6671 duty = (u32)tmp64;
6672
6673 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6674 tmp |= FDO_STATIC_DUTY(duty);
6675 WREG32(CG_FDO_CTRL0, tmp);
6676
6677 return 0;
6678}
6679
6680static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
6681{
6682 if (mode) {
6683 /* stop auto-manage */
6684 if (adev->pm.dpm.fan.ucode_fan_control)
6685 si_fan_ctrl_stop_smc_fan_control(adev);
6686 si_fan_ctrl_set_static_mode(adev, mode);
6687 } else {
6688 /* restart auto-manage */
6689 if (adev->pm.dpm.fan.ucode_fan_control)
6690 si_thermal_start_smc_fan_control(adev);
6691 else
6692 si_fan_ctrl_set_default_mode(adev);
6693 }
6694}
6695
6696static u32 si_dpm_get_fan_control_mode(struct amdgpu_device *adev)
6697{
6698 struct si_power_info *si_pi = si_get_pi(adev);
6699 u32 tmp;
6700
6701 if (si_pi->fan_is_controlled_by_smc)
6702 return 0;
6703
6704 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6705 return (tmp >> FDO_PWM_MODE_SHIFT);
6706}
6707
6708#if 0
6709static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6710 u32 *speed)
6711{
6712 u32 tach_period;
6713 u32 xclk = amdgpu_asic_get_xclk(adev);
6714
6715 if (adev->pm.no_fan)
6716 return -ENOENT;
6717
6718 if (adev->pm.fan_pulses_per_revolution == 0)
6719 return -ENOENT;
6720
6721 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6722 if (tach_period == 0)
6723 return -ENOENT;
6724
6725 *speed = 60 * xclk * 10000 / tach_period;
6726
6727 return 0;
6728}
6729
6730static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6731 u32 speed)
6732{
6733 u32 tach_period, tmp;
6734 u32 xclk = amdgpu_asic_get_xclk(adev);
6735
6736 if (adev->pm.no_fan)
6737 return -ENOENT;
6738
6739 if (adev->pm.fan_pulses_per_revolution == 0)
6740 return -ENOENT;
6741
6742 if ((speed < adev->pm.fan_min_rpm) ||
6743 (speed > adev->pm.fan_max_rpm))
6744 return -EINVAL;
6745
6746 if (adev->pm.dpm.fan.ucode_fan_control)
6747 si_fan_ctrl_stop_smc_fan_control(adev);
6748
6749 tach_period = 60 * xclk * 10000 / (8 * speed);
6750 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6751 tmp |= TARGET_PERIOD(tach_period);
6752 WREG32(CG_TACH_CTRL, tmp);
6753
6754 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6755
6756 return 0;
6757}
6758#endif
6759
6760static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6761{
6762 struct si_power_info *si_pi = si_get_pi(adev);
6763 u32 tmp;
6764
6765 if (!si_pi->fan_ctrl_is_in_default_mode) {
6766 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6767 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6768 WREG32(CG_FDO_CTRL2, tmp);
6769
6770 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6771 tmp |= TMIN(si_pi->t_min);
6772 WREG32(CG_FDO_CTRL2, tmp);
6773 si_pi->fan_ctrl_is_in_default_mode = true;
6774 }
6775}
6776
6777static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6778{
6779 if (adev->pm.dpm.fan.ucode_fan_control) {
6780 si_fan_ctrl_start_smc_fan_control(adev);
6781 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6782 }
6783}
6784
6785static void si_thermal_initialize(struct amdgpu_device *adev)
6786{
6787 u32 tmp;
6788
6789 if (adev->pm.fan_pulses_per_revolution) {
6790 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6791 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
6792 WREG32(CG_TACH_CTRL, tmp);
6793 }
6794
6795 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6796 tmp |= TACH_PWM_RESP_RATE(0x28);
6797 WREG32(CG_FDO_CTRL2, tmp);
6798}
6799
6800static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6801{
6802 int ret;
6803
6804 si_thermal_initialize(adev);
6805 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6806 if (ret)
6807 return ret;
6808 ret = si_thermal_enable_alert(adev, true);
6809 if (ret)
6810 return ret;
6811 if (adev->pm.dpm.fan.ucode_fan_control) {
6812 ret = si_halt_smc(adev);
6813 if (ret)
6814 return ret;
6815 ret = si_thermal_setup_fan_table(adev);
6816 if (ret)
6817 return ret;
6818 ret = si_resume_smc(adev);
6819 if (ret)
6820 return ret;
6821 si_thermal_start_smc_fan_control(adev);
6822 }
6823
6824 return 0;
6825}
6826
6827static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6828{
6829 if (!adev->pm.no_fan) {
6830 si_fan_ctrl_set_default_mode(adev);
6831 si_fan_ctrl_stop_smc_fan_control(adev);
6832 }
6833}
6834
6835static int si_dpm_enable(struct amdgpu_device *adev)
6836{
6837 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6838 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6839 struct si_power_info *si_pi = si_get_pi(adev);
6840 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6841 int ret;
6842
6843 if (amdgpu_si_is_smc_running(adev))
6844 return -EINVAL;
6845 if (pi->voltage_control || si_pi->voltage_control_svi2)
6846 si_enable_voltage_control(adev, true);
6847 if (pi->mvdd_control)
6848 si_get_mvdd_configuration(adev);
6849 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6850 ret = si_construct_voltage_tables(adev);
6851 if (ret) {
6852 DRM_ERROR("si_construct_voltage_tables failed\n");
6853 return ret;
6854 }
6855 }
6856 if (eg_pi->dynamic_ac_timing) {
6857 ret = si_initialize_mc_reg_table(adev);
6858 if (ret)
6859 eg_pi->dynamic_ac_timing = false;
6860 }
6861 if (pi->dynamic_ss)
6862 si_enable_spread_spectrum(adev, true);
6863 if (pi->thermal_protection)
6864 si_enable_thermal_protection(adev, true);
6865 si_setup_bsp(adev);
6866 si_program_git(adev);
6867 si_program_tp(adev);
6868 si_program_tpp(adev);
6869 si_program_sstp(adev);
6870 si_enable_display_gap(adev);
6871 si_program_vc(adev);
6872 ret = si_upload_firmware(adev);
6873 if (ret) {
6874 DRM_ERROR("si_upload_firmware failed\n");
6875 return ret;
6876 }
6877 ret = si_process_firmware_header(adev);
6878 if (ret) {
6879 DRM_ERROR("si_process_firmware_header failed\n");
6880 return ret;
6881 }
6882 ret = si_initial_switch_from_arb_f0_to_f1(adev);
6883 if (ret) {
6884 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6885 return ret;
6886 }
6887 ret = si_init_smc_table(adev);
6888 if (ret) {
6889 DRM_ERROR("si_init_smc_table failed\n");
6890 return ret;
6891 }
6892 ret = si_init_smc_spll_table(adev);
6893 if (ret) {
6894 DRM_ERROR("si_init_smc_spll_table failed\n");
6895 return ret;
6896 }
6897 ret = si_init_arb_table_index(adev);
6898 if (ret) {
6899 DRM_ERROR("si_init_arb_table_index failed\n");
6900 return ret;
6901 }
6902 if (eg_pi->dynamic_ac_timing) {
6903 ret = si_populate_mc_reg_table(adev, boot_ps);
6904 if (ret) {
6905 DRM_ERROR("si_populate_mc_reg_table failed\n");
6906 return ret;
6907 }
6908 }
6909 ret = si_initialize_smc_cac_tables(adev);
6910 if (ret) {
6911 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6912 return ret;
6913 }
6914 ret = si_initialize_hardware_cac_manager(adev);
6915 if (ret) {
6916 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6917 return ret;
6918 }
6919 ret = si_initialize_smc_dte_tables(adev);
6920 if (ret) {
6921 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6922 return ret;
6923 }
6924 ret = si_populate_smc_tdp_limits(adev, boot_ps);
6925 if (ret) {
6926 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6927 return ret;
6928 }
6929 ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6930 if (ret) {
6931 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6932 return ret;
6933 }
6934 si_program_response_times(adev);
6935 si_program_ds_registers(adev);
6936 si_dpm_start_smc(adev);
6937 ret = si_notify_smc_display_change(adev, false);
6938 if (ret) {
6939 DRM_ERROR("si_notify_smc_display_change failed\n");
6940 return ret;
6941 }
6942 si_enable_sclk_control(adev, true);
6943 si_start_dpm(adev);
6944
6945 si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6946 si_thermal_start_thermal_controller(adev);
6947 ni_update_current_ps(adev, boot_ps);
6948
6949 return 0;
6950}
6951
6952static int si_set_temperature_range(struct amdgpu_device *adev)
6953{
6954 int ret;
6955
6956 ret = si_thermal_enable_alert(adev, false);
6957 if (ret)
6958 return ret;
6959 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6960 if (ret)
6961 return ret;
6962 ret = si_thermal_enable_alert(adev, true);
6963 if (ret)
6964 return ret;
6965
6966 return ret;
6967}
6968
6969static void si_dpm_disable(struct amdgpu_device *adev)
6970{
6971 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6972 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6973
6974 if (!amdgpu_si_is_smc_running(adev))
6975 return;
6976 si_thermal_stop_thermal_controller(adev);
6977 si_disable_ulv(adev);
6978 si_clear_vc(adev);
6979 if (pi->thermal_protection)
6980 si_enable_thermal_protection(adev, false);
6981 si_enable_power_containment(adev, boot_ps, false);
6982 si_enable_smc_cac(adev, boot_ps, false);
6983 si_enable_spread_spectrum(adev, false);
6984 si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6985 si_stop_dpm(adev);
6986 si_reset_to_default(adev);
6987 si_dpm_stop_smc(adev);
6988 si_force_switch_to_arb_f0(adev);
6989
6990 ni_update_current_ps(adev, boot_ps);
6991}
6992
6993static int si_dpm_pre_set_power_state(struct amdgpu_device *adev)
6994{
6995 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6996 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
6997 struct amdgpu_ps *new_ps = &requested_ps;
6998
6999 ni_update_requested_ps(adev, new_ps);
7000 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
7001
7002 return 0;
7003}
7004
7005static int si_power_control_set_level(struct amdgpu_device *adev)
7006{
7007 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
7008 int ret;
7009
7010 ret = si_restrict_performance_levels_before_switch(adev);
7011 if (ret)
7012 return ret;
7013 ret = si_halt_smc(adev);
7014 if (ret)
7015 return ret;
7016 ret = si_populate_smc_tdp_limits(adev, new_ps);
7017 if (ret)
7018 return ret;
7019 ret = si_populate_smc_tdp_limits_2(adev, new_ps);
7020 if (ret)
7021 return ret;
7022 ret = si_resume_smc(adev);
7023 if (ret)
7024 return ret;
7025 ret = si_set_sw_state(adev);
7026 if (ret)
7027 return ret;
7028 return 0;
7029}
7030
7031static int si_dpm_set_power_state(struct amdgpu_device *adev)
7032{
7033 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7034 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7035 struct amdgpu_ps *old_ps = &eg_pi->current_rps;
7036 int ret;
7037
7038 ret = si_disable_ulv(adev);
7039 if (ret) {
7040 DRM_ERROR("si_disable_ulv failed\n");
7041 return ret;
7042 }
7043 ret = si_restrict_performance_levels_before_switch(adev);
7044 if (ret) {
7045 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
7046 return ret;
7047 }
7048 if (eg_pi->pcie_performance_request)
7049 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
7050 ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
7051 ret = si_enable_power_containment(adev, new_ps, false);
7052 if (ret) {
7053 DRM_ERROR("si_enable_power_containment failed\n");
7054 return ret;
7055 }
7056 ret = si_enable_smc_cac(adev, new_ps, false);
7057 if (ret) {
7058 DRM_ERROR("si_enable_smc_cac failed\n");
7059 return ret;
7060 }
7061 ret = si_halt_smc(adev);
7062 if (ret) {
7063 DRM_ERROR("si_halt_smc failed\n");
7064 return ret;
7065 }
7066 ret = si_upload_sw_state(adev, new_ps);
7067 if (ret) {
7068 DRM_ERROR("si_upload_sw_state failed\n");
7069 return ret;
7070 }
7071 ret = si_upload_smc_data(adev);
7072 if (ret) {
7073 DRM_ERROR("si_upload_smc_data failed\n");
7074 return ret;
7075 }
7076 ret = si_upload_ulv_state(adev);
7077 if (ret) {
7078 DRM_ERROR("si_upload_ulv_state failed\n");
7079 return ret;
7080 }
7081 if (eg_pi->dynamic_ac_timing) {
7082 ret = si_upload_mc_reg_table(adev, new_ps);
7083 if (ret) {
7084 DRM_ERROR("si_upload_mc_reg_table failed\n");
7085 return ret;
7086 }
7087 }
7088 ret = si_program_memory_timing_parameters(adev, new_ps);
7089 if (ret) {
7090 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7091 return ret;
7092 }
7093 si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7094
7095 ret = si_resume_smc(adev);
7096 if (ret) {
7097 DRM_ERROR("si_resume_smc failed\n");
7098 return ret;
7099 }
7100 ret = si_set_sw_state(adev);
7101 if (ret) {
7102 DRM_ERROR("si_set_sw_state failed\n");
7103 return ret;
7104 }
7105 ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7106 if (eg_pi->pcie_performance_request)
7107 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7108 ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7109 if (ret) {
7110 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7111 return ret;
7112 }
7113 ret = si_enable_smc_cac(adev, new_ps, true);
7114 if (ret) {
7115 DRM_ERROR("si_enable_smc_cac failed\n");
7116 return ret;
7117 }
7118 ret = si_enable_power_containment(adev, new_ps, true);
7119 if (ret) {
7120 DRM_ERROR("si_enable_power_containment failed\n");
7121 return ret;
7122 }
7123
7124 ret = si_power_control_set_level(adev);
7125 if (ret) {
7126 DRM_ERROR("si_power_control_set_level failed\n");
7127 return ret;
7128 }
7129
7130 return 0;
7131}
7132
7133static void si_dpm_post_set_power_state(struct amdgpu_device *adev)
7134{
7135 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7136 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7137
7138 ni_update_current_ps(adev, new_ps);
7139}
7140
7141#if 0
7142void si_dpm_reset_asic(struct amdgpu_device *adev)
7143{
7144 si_restrict_performance_levels_before_switch(adev);
7145 si_disable_ulv(adev);
7146 si_set_boot_state(adev);
7147}
7148#endif
7149
7150static void si_dpm_display_configuration_changed(struct amdgpu_device *adev)
7151{
7152 si_program_display_gap(adev);
7153}
7154
7155
7156static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7157 struct amdgpu_ps *rps,
7158 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7159 u8 table_rev)
7160{
7161 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7162 rps->class = le16_to_cpu(non_clock_info->usClassification);
7163 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7164
7165 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7166 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7167 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7168 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7169 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7170 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7171 } else {
7172 rps->vclk = 0;
7173 rps->dclk = 0;
7174 }
7175
7176 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7177 adev->pm.dpm.boot_ps = rps;
7178 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7179 adev->pm.dpm.uvd_ps = rps;
7180}
7181
7182static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7183 struct amdgpu_ps *rps, int index,
7184 union pplib_clock_info *clock_info)
7185{
7186 struct rv7xx_power_info *pi = rv770_get_pi(adev);
7187 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7188 struct si_power_info *si_pi = si_get_pi(adev);
7189 struct si_ps *ps = si_get_ps(rps);
7190 u16 leakage_voltage;
7191 struct rv7xx_pl *pl = &ps->performance_levels[index];
7192 int ret;
7193
7194 ps->performance_level_count = index + 1;
7195
7196 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7197 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7198 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7199 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7200
7201 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7202 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7203 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7204 pl->pcie_gen = r600_get_pcie_gen_support(adev,
7205 si_pi->sys_pcie_mask,
7206 si_pi->boot_pcie_gen,
7207 clock_info->si.ucPCIEGen);
7208
7209 /* patch up vddc if necessary */
7210 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7211 &leakage_voltage);
7212 if (ret == 0)
7213 pl->vddc = leakage_voltage;
7214
7215 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7216 pi->acpi_vddc = pl->vddc;
7217 eg_pi->acpi_vddci = pl->vddci;
7218 si_pi->acpi_pcie_gen = pl->pcie_gen;
7219 }
7220
7221 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7222 index == 0) {
7223 /* XXX disable for A0 tahiti */
7224 si_pi->ulv.supported = false;
7225 si_pi->ulv.pl = *pl;
7226 si_pi->ulv.one_pcie_lane_in_ulv = false;
7227 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7228 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7229 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7230 }
7231
7232 if (pi->min_vddc_in_table > pl->vddc)
7233 pi->min_vddc_in_table = pl->vddc;
7234
7235 if (pi->max_vddc_in_table < pl->vddc)
7236 pi->max_vddc_in_table = pl->vddc;
7237
7238 /* patch up boot state */
7239 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7240 u16 vddc, vddci, mvdd;
7241 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7242 pl->mclk = adev->clock.default_mclk;
7243 pl->sclk = adev->clock.default_sclk;
7244 pl->vddc = vddc;
7245 pl->vddci = vddci;
7246 si_pi->mvdd_bootup_value = mvdd;
7247 }
7248
7249 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7250 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7251 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7252 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7253 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7254 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7255 }
7256}
7257
7258union pplib_power_state {
7259 struct _ATOM_PPLIB_STATE v1;
7260 struct _ATOM_PPLIB_STATE_V2 v2;
7261};
7262
7263static int si_parse_power_table(struct amdgpu_device *adev)
7264{
7265 struct amdgpu_mode_info *mode_info = &adev->mode_info;
7266 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7267 union pplib_power_state *power_state;
7268 int i, j, k, non_clock_array_index, clock_array_index;
7269 union pplib_clock_info *clock_info;
7270 struct _StateArray *state_array;
7271 struct _ClockInfoArray *clock_info_array;
7272 struct _NonClockInfoArray *non_clock_info_array;
7273 union power_info *power_info;
7274 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
7275 u16 data_offset;
7276 u8 frev, crev;
7277 u8 *power_state_offset;
7278 struct si_ps *ps;
7279
7280 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7281 &frev, &crev, &data_offset))
7282 return -EINVAL;
7283 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7284
7285 amdgpu_add_thermal_controller(adev);
7286
7287 state_array = (struct _StateArray *)
7288 (mode_info->atom_context->bios + data_offset +
7289 le16_to_cpu(power_info->pplib.usStateArrayOffset));
7290 clock_info_array = (struct _ClockInfoArray *)
7291 (mode_info->atom_context->bios + data_offset +
7292 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7293 non_clock_info_array = (struct _NonClockInfoArray *)
7294 (mode_info->atom_context->bios + data_offset +
7295 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7296
7297 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
7298 state_array->ucNumEntries, GFP_KERNEL);
7299 if (!adev->pm.dpm.ps)
7300 return -ENOMEM;
7301 power_state_offset = (u8 *)state_array->states;
7302 for (i = 0; i < state_array->ucNumEntries; i++) {
7303 u8 *idx;
7304 power_state = (union pplib_power_state *)power_state_offset;
7305 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7306 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7307 &non_clock_info_array->nonClockInfo[non_clock_array_index];
7308 ps = kzalloc(sizeof(struct si_ps), GFP_KERNEL);
7309 if (ps == NULL) {
7310 kfree(adev->pm.dpm.ps);
7311 return -ENOMEM;
7312 }
7313 adev->pm.dpm.ps[i].ps_priv = ps;
7314 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7315 non_clock_info,
7316 non_clock_info_array->ucEntrySize);
7317 k = 0;
7318 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7319 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7320 clock_array_index = idx[j];
7321 if (clock_array_index >= clock_info_array->ucNumEntries)
7322 continue;
7323 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7324 break;
7325 clock_info = (union pplib_clock_info *)
7326 ((u8 *)&clock_info_array->clockInfo[0] +
7327 (clock_array_index * clock_info_array->ucEntrySize));
7328 si_parse_pplib_clock_info(adev,
7329 &adev->pm.dpm.ps[i], k,
7330 clock_info);
7331 k++;
7332 }
7333 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7334 }
7335 adev->pm.dpm.num_ps = state_array->ucNumEntries;
7336
7337 /* fill in the vce power states */
7338 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
7339 u32 sclk, mclk;
7340 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7341 clock_info = (union pplib_clock_info *)
7342 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7343 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7344 sclk |= clock_info->si.ucEngineClockHigh << 16;
7345 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7346 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7347 adev->pm.dpm.vce_states[i].sclk = sclk;
7348 adev->pm.dpm.vce_states[i].mclk = mclk;
7349 }
7350
7351 return 0;
7352}
7353
7354static int si_dpm_init(struct amdgpu_device *adev)
7355{
7356 struct rv7xx_power_info *pi;
7357 struct evergreen_power_info *eg_pi;
7358 struct ni_power_info *ni_pi;
7359 struct si_power_info *si_pi;
7360 struct atom_clock_dividers dividers;
7361 int ret;
7362 u32 mask;
7363
7364 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7365 if (si_pi == NULL)
7366 return -ENOMEM;
7367 adev->pm.dpm.priv = si_pi;
7368 ni_pi = &si_pi->ni;
7369 eg_pi = &ni_pi->eg;
7370 pi = &eg_pi->rv7xx;
7371
7372 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
7373 if (ret)
7374 si_pi->sys_pcie_mask = 0;
7375 else
7376 si_pi->sys_pcie_mask = mask;
7377 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7378 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7379
7380 si_set_max_cu_value(adev);
7381
7382 rv770_get_max_vddc(adev);
7383 si_get_leakage_vddc(adev);
7384 si_patch_dependency_tables_based_on_leakage(adev);
7385
7386 pi->acpi_vddc = 0;
7387 eg_pi->acpi_vddci = 0;
7388 pi->min_vddc_in_table = 0;
7389 pi->max_vddc_in_table = 0;
7390
7391 ret = amdgpu_get_platform_caps(adev);
7392 if (ret)
7393 return ret;
7394
7395 ret = amdgpu_parse_extended_power_table(adev);
7396 if (ret)
7397 return ret;
7398
7399 ret = si_parse_power_table(adev);
7400 if (ret)
7401 return ret;
7402
7403 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7404 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
7405 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7406 amdgpu_free_extended_power_table(adev);
7407 return -ENOMEM;
7408 }
7409 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7410 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7411 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7412 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7413 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7414 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7415 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7416 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7417 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7418
7419 if (adev->pm.dpm.voltage_response_time == 0)
7420 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7421 if (adev->pm.dpm.backbias_response_time == 0)
7422 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7423
7424 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7425 0, false, ÷rs);
7426 if (ret)
7427 pi->ref_div = dividers.ref_div + 1;
7428 else
7429 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7430
7431 eg_pi->smu_uvd_hs = false;
7432
7433 pi->mclk_strobe_mode_threshold = 40000;
7434 if (si_is_special_1gb_platform(adev))
7435 pi->mclk_stutter_mode_threshold = 0;
7436 else
7437 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7438 pi->mclk_edc_enable_threshold = 40000;
7439 eg_pi->mclk_edc_wr_enable_threshold = 40000;
7440
7441 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7442
7443 pi->voltage_control =
7444 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7445 VOLTAGE_OBJ_GPIO_LUT);
7446 if (!pi->voltage_control) {
7447 si_pi->voltage_control_svi2 =
7448 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7449 VOLTAGE_OBJ_SVID2);
7450 if (si_pi->voltage_control_svi2)
7451 amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7452 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7453 }
7454
7455 pi->mvdd_control =
7456 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7457 VOLTAGE_OBJ_GPIO_LUT);
7458
7459 eg_pi->vddci_control =
7460 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7461 VOLTAGE_OBJ_GPIO_LUT);
7462 if (!eg_pi->vddci_control)
7463 si_pi->vddci_control_svi2 =
7464 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7465 VOLTAGE_OBJ_SVID2);
7466
7467 si_pi->vddc_phase_shed_control =
7468 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7469 VOLTAGE_OBJ_PHASE_LUT);
7470
7471 rv770_get_engine_memory_ss(adev);
7472
7473 pi->asi = RV770_ASI_DFLT;
7474 pi->pasi = CYPRESS_HASI_DFLT;
7475 pi->vrc = SISLANDS_VRC_DFLT;
7476
7477 pi->gfx_clock_gating = true;
7478
7479 eg_pi->sclk_deep_sleep = true;
7480 si_pi->sclk_deep_sleep_above_low = false;
7481
7482 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7483 pi->thermal_protection = true;
7484 else
7485 pi->thermal_protection = false;
7486
7487 eg_pi->dynamic_ac_timing = true;
7488
7489 eg_pi->light_sleep = true;
7490#if defined(CONFIG_ACPI)
7491 eg_pi->pcie_performance_request =
7492 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7493#else
7494 eg_pi->pcie_performance_request = false;
7495#endif
7496
7497 si_pi->sram_end = SMC_RAM_END;
7498
7499 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7500 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7501 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7502 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7503 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7504 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7505 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7506
7507 si_initialize_powertune_defaults(adev);
7508
7509 /* make sure dc limits are valid */
7510 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7511 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7512 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7513 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7514
7515 si_pi->fan_ctrl_is_in_default_mode = true;
7516
7517 return 0;
7518}
7519
7520static void si_dpm_fini(struct amdgpu_device *adev)
7521{
7522 int i;
7523
7524 if (adev->pm.dpm.ps)
7525 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7526 kfree(adev->pm.dpm.ps[i].ps_priv);
7527 kfree(adev->pm.dpm.ps);
7528 kfree(adev->pm.dpm.priv);
7529 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7530 amdgpu_free_extended_power_table(adev);
7531}
7532
7533static void si_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
7534 struct seq_file *m)
7535{
7536 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7537 struct amdgpu_ps *rps = &eg_pi->current_rps;
7538 struct si_ps *ps = si_get_ps(rps);
7539 struct rv7xx_pl *pl;
7540 u32 current_index =
7541 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7542 CURRENT_STATE_INDEX_SHIFT;
7543
7544 if (current_index >= ps->performance_level_count) {
7545 seq_printf(m, "invalid dpm profile %d\n", current_index);
7546 } else {
7547 pl = &ps->performance_levels[current_index];
7548 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7549 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7550 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7551 }
7552}
7553
7554static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7555 struct amdgpu_irq_src *source,
7556 unsigned type,
7557 enum amdgpu_interrupt_state state)
7558{
7559 u32 cg_thermal_int;
7560
7561 switch (type) {
7562 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7563 switch (state) {
7564 case AMDGPU_IRQ_STATE_DISABLE:
7565 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7566 cg_thermal_int |= THERM_INT_MASK_HIGH;
7567 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7568 break;
7569 case AMDGPU_IRQ_STATE_ENABLE:
7570 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7571 cg_thermal_int &= ~THERM_INT_MASK_HIGH;
7572 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7573 break;
7574 default:
7575 break;
7576 }
7577 break;
7578
7579 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7580 switch (state) {
7581 case AMDGPU_IRQ_STATE_DISABLE:
7582 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7583 cg_thermal_int |= THERM_INT_MASK_LOW;
7584 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7585 break;
7586 case AMDGPU_IRQ_STATE_ENABLE:
7587 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7588 cg_thermal_int &= ~THERM_INT_MASK_LOW;
7589 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7590 break;
7591 default:
7592 break;
7593 }
7594 break;
7595
7596 default:
7597 break;
7598 }
7599 return 0;
7600}
7601
7602static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7603 struct amdgpu_irq_src *source,
7604 struct amdgpu_iv_entry *entry)
7605{
7606 bool queue_thermal = false;
7607
7608 if (entry == NULL)
7609 return -EINVAL;
7610
7611 switch (entry->src_id) {
7612 case 230: /* thermal low to high */
7613 DRM_DEBUG("IH: thermal low to high\n");
7614 adev->pm.dpm.thermal.high_to_low = false;
7615 queue_thermal = true;
7616 break;
7617 case 231: /* thermal high to low */
7618 DRM_DEBUG("IH: thermal high to low\n");
7619 adev->pm.dpm.thermal.high_to_low = true;
7620 queue_thermal = true;
7621 break;
7622 default:
7623 break;
7624 }
7625
7626 if (queue_thermal)
7627 schedule_work(&adev->pm.dpm.thermal.work);
7628
7629 return 0;
7630}
7631
7632static int si_dpm_late_init(void *handle)
7633{
7634 int ret;
7635 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7636
7637 if (!amdgpu_dpm)
7638 return 0;
7639
7640 /* init the sysfs and debugfs files late */
7641 ret = amdgpu_pm_sysfs_init(adev);
7642 if (ret)
7643 return ret;
7644
7645 ret = si_set_temperature_range(adev);
7646 if (ret)
7647 return ret;
7648#if 0 //TODO ?
7649 si_dpm_powergate_uvd(adev, true);
7650#endif
7651 return 0;
7652}
7653
7654/**
7655 * si_dpm_init_microcode - load ucode images from disk
7656 *
7657 * @adev: amdgpu_device pointer
7658 *
7659 * Use the firmware interface to load the ucode images into
7660 * the driver (not loaded into hw).
7661 * Returns 0 on success, error on failure.
7662 */
7663static int si_dpm_init_microcode(struct amdgpu_device *adev)
7664{
7665 const char *chip_name;
7666 char fw_name[30];
7667 int err;
7668
7669 DRM_DEBUG("\n");
7670 switch (adev->asic_type) {
7671 case CHIP_TAHITI:
7672 chip_name = "tahiti";
7673 break;
7674 case CHIP_PITCAIRN:
7675 if ((adev->pdev->revision == 0x81) &&
7676 ((adev->pdev->device == 0x6810) ||
7677 (adev->pdev->device == 0x6811)))
7678 chip_name = "pitcairn_k";
7679 else
7680 chip_name = "pitcairn";
7681 break;
7682 case CHIP_VERDE:
7683 if (((adev->pdev->device == 0x6820) &&
7684 ((adev->pdev->revision == 0x81) ||
7685 (adev->pdev->revision == 0x83))) ||
7686 ((adev->pdev->device == 0x6821) &&
7687 ((adev->pdev->revision == 0x83) ||
7688 (adev->pdev->revision == 0x87))) ||
7689 ((adev->pdev->revision == 0x87) &&
7690 ((adev->pdev->device == 0x6823) ||
7691 (adev->pdev->device == 0x682b))))
7692 chip_name = "verde_k";
7693 else
7694 chip_name = "verde";
7695 break;
7696 case CHIP_OLAND:
7697 if (((adev->pdev->revision == 0x81) &&
7698 ((adev->pdev->device == 0x6600) ||
7699 (adev->pdev->device == 0x6604) ||
7700 (adev->pdev->device == 0x6605) ||
7701 (adev->pdev->device == 0x6610))) ||
7702 ((adev->pdev->revision == 0x83) &&
7703 (adev->pdev->device == 0x6610)))
7704 chip_name = "oland_k";
7705 else
7706 chip_name = "oland";
7707 break;
7708 case CHIP_HAINAN:
7709 if (((adev->pdev->revision == 0x81) &&
7710 (adev->pdev->device == 0x6660)) ||
7711 ((adev->pdev->revision == 0x83) &&
7712 ((adev->pdev->device == 0x6660) ||
7713 (adev->pdev->device == 0x6663) ||
7714 (adev->pdev->device == 0x6665) ||
7715 (adev->pdev->device == 0x6667))))
7716 chip_name = "hainan_k";
7717 else if ((adev->pdev->revision == 0xc3) &&
7718 (adev->pdev->device == 0x6665))
7719 chip_name = "banks_k_2";
7720 else
7721 chip_name = "hainan";
7722 break;
7723 default: BUG();
7724 }
7725
7726 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
7727 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
7728 if (err)
7729 goto out;
7730 err = amdgpu_ucode_validate(adev->pm.fw);
7731
7732out:
7733 if (err) {
7734 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
7735 err, fw_name);
7736 release_firmware(adev->pm.fw);
7737 adev->pm.fw = NULL;
7738 }
7739 return err;
7740
7741}
7742
7743static int si_dpm_sw_init(void *handle)
7744{
7745 int ret;
7746 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7747
7748 ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
7749 if (ret)
7750 return ret;
7751
7752 ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
7753 if (ret)
7754 return ret;
7755
7756 /* default to balanced state */
7757 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7758 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7759 adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
7760 adev->pm.default_sclk = adev->clock.default_sclk;
7761 adev->pm.default_mclk = adev->clock.default_mclk;
7762 adev->pm.current_sclk = adev->clock.default_sclk;
7763 adev->pm.current_mclk = adev->clock.default_mclk;
7764 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7765
7766 if (amdgpu_dpm == 0)
7767 return 0;
7768
7769 ret = si_dpm_init_microcode(adev);
7770 if (ret)
7771 return ret;
7772
7773 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7774 mutex_lock(&adev->pm.mutex);
7775 ret = si_dpm_init(adev);
7776 if (ret)
7777 goto dpm_failed;
7778 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7779 if (amdgpu_dpm == 1)
7780 amdgpu_pm_print_power_states(adev);
7781 mutex_unlock(&adev->pm.mutex);
7782 DRM_INFO("amdgpu: dpm initialized\n");
7783
7784 return 0;
7785
7786dpm_failed:
7787 si_dpm_fini(adev);
7788 mutex_unlock(&adev->pm.mutex);
7789 DRM_ERROR("amdgpu: dpm initialization failed\n");
7790 return ret;
7791}
7792
7793static int si_dpm_sw_fini(void *handle)
7794{
7795 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7796
7797 flush_work(&adev->pm.dpm.thermal.work);
7798
7799 mutex_lock(&adev->pm.mutex);
7800 amdgpu_pm_sysfs_fini(adev);
7801 si_dpm_fini(adev);
7802 mutex_unlock(&adev->pm.mutex);
7803
7804 return 0;
7805}
7806
7807static int si_dpm_hw_init(void *handle)
7808{
7809 int ret;
7810
7811 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7812
7813 if (!amdgpu_dpm)
7814 return 0;
7815
7816 mutex_lock(&adev->pm.mutex);
7817 si_dpm_setup_asic(adev);
7818 ret = si_dpm_enable(adev);
7819 if (ret)
7820 adev->pm.dpm_enabled = false;
7821 else
7822 adev->pm.dpm_enabled = true;
7823 mutex_unlock(&adev->pm.mutex);
7824
7825 return ret;
7826}
7827
7828static int si_dpm_hw_fini(void *handle)
7829{
7830 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7831
7832 if (adev->pm.dpm_enabled) {
7833 mutex_lock(&adev->pm.mutex);
7834 si_dpm_disable(adev);
7835 mutex_unlock(&adev->pm.mutex);
7836 }
7837
7838 return 0;
7839}
7840
7841static int si_dpm_suspend(void *handle)
7842{
7843 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7844
7845 if (adev->pm.dpm_enabled) {
7846 mutex_lock(&adev->pm.mutex);
7847 /* disable dpm */
7848 si_dpm_disable(adev);
7849 /* reset the power state */
7850 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7851 mutex_unlock(&adev->pm.mutex);
7852 }
7853 return 0;
7854}
7855
7856static int si_dpm_resume(void *handle)
7857{
7858 int ret;
7859 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7860
7861 if (adev->pm.dpm_enabled) {
7862 /* asic init will reset to the boot state */
7863 mutex_lock(&adev->pm.mutex);
7864 si_dpm_setup_asic(adev);
7865 ret = si_dpm_enable(adev);
7866 if (ret)
7867 adev->pm.dpm_enabled = false;
7868 else
7869 adev->pm.dpm_enabled = true;
7870 mutex_unlock(&adev->pm.mutex);
7871 if (adev->pm.dpm_enabled)
7872 amdgpu_pm_compute_clocks(adev);
7873 }
7874 return 0;
7875}
7876
7877static bool si_dpm_is_idle(void *handle)
7878{
7879 /* XXX */
7880 return true;
7881}
7882
7883static int si_dpm_wait_for_idle(void *handle)
7884{
7885 /* XXX */
7886 return 0;
7887}
7888
7889static int si_dpm_soft_reset(void *handle)
7890{
7891 return 0;
7892}
7893
7894static int si_dpm_set_clockgating_state(void *handle,
7895 enum amd_clockgating_state state)
7896{
7897 return 0;
7898}
7899
7900static int si_dpm_set_powergating_state(void *handle,
7901 enum amd_powergating_state state)
7902{
7903 return 0;
7904}
7905
7906/* get temperature in millidegrees */
7907static int si_dpm_get_temp(struct amdgpu_device *adev)
7908{
7909 u32 temp;
7910 int actual_temp = 0;
7911
7912 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
7913 CTF_TEMP_SHIFT;
7914
7915 if (temp & 0x200)
7916 actual_temp = 255;
7917 else
7918 actual_temp = temp & 0x1ff;
7919
7920 actual_temp = (actual_temp * 1000);
7921
7922 return actual_temp;
7923}
7924
7925static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low)
7926{
7927 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7928 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7929
7930 if (low)
7931 return requested_state->performance_levels[0].sclk;
7932 else
7933 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7934}
7935
7936static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low)
7937{
7938 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7939 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7940
7941 if (low)
7942 return requested_state->performance_levels[0].mclk;
7943 else
7944 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7945}
7946
7947static void si_dpm_print_power_state(struct amdgpu_device *adev,
7948 struct amdgpu_ps *rps)
7949{
7950 struct si_ps *ps = si_get_ps(rps);
7951 struct rv7xx_pl *pl;
7952 int i;
7953
7954 amdgpu_dpm_print_class_info(rps->class, rps->class2);
7955 amdgpu_dpm_print_cap_info(rps->caps);
7956 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7957 for (i = 0; i < ps->performance_level_count; i++) {
7958 pl = &ps->performance_levels[i];
7959 if (adev->asic_type >= CHIP_TAHITI)
7960 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7961 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7962 else
7963 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u\n",
7964 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
7965 }
7966 amdgpu_dpm_print_ps_status(adev, rps);
7967}
7968
7969static int si_dpm_early_init(void *handle)
7970{
7971
7972 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7973
7974 si_dpm_set_dpm_funcs(adev);
7975 si_dpm_set_irq_funcs(adev);
7976 return 0;
7977}
7978
7979static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1,
7980 const struct rv7xx_pl *si_cpl2)
7981{
7982 return ((si_cpl1->mclk == si_cpl2->mclk) &&
7983 (si_cpl1->sclk == si_cpl2->sclk) &&
7984 (si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
7985 (si_cpl1->vddc == si_cpl2->vddc) &&
7986 (si_cpl1->vddci == si_cpl2->vddci));
7987}
7988
7989static int si_check_state_equal(struct amdgpu_device *adev,
7990 struct amdgpu_ps *cps,
7991 struct amdgpu_ps *rps,
7992 bool *equal)
7993{
7994 struct si_ps *si_cps;
7995 struct si_ps *si_rps;
7996 int i;
7997
7998 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
7999 return -EINVAL;
8000
8001 si_cps = si_get_ps(cps);
8002 si_rps = si_get_ps(rps);
8003
8004 if (si_cps == NULL) {
8005 printk("si_cps is NULL\n");
8006 *equal = false;
8007 return 0;
8008 }
8009
8010 if (si_cps->performance_level_count != si_rps->performance_level_count) {
8011 *equal = false;
8012 return 0;
8013 }
8014
8015 for (i = 0; i < si_cps->performance_level_count; i++) {
8016 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
8017 &(si_rps->performance_levels[i]))) {
8018 *equal = false;
8019 return 0;
8020 }
8021 }
8022
8023 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
8024 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
8025 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
8026
8027 return 0;
8028}
8029
8030
8031const struct amd_ip_funcs si_dpm_ip_funcs = {
8032 .name = "si_dpm",
8033 .early_init = si_dpm_early_init,
8034 .late_init = si_dpm_late_init,
8035 .sw_init = si_dpm_sw_init,
8036 .sw_fini = si_dpm_sw_fini,
8037 .hw_init = si_dpm_hw_init,
8038 .hw_fini = si_dpm_hw_fini,
8039 .suspend = si_dpm_suspend,
8040 .resume = si_dpm_resume,
8041 .is_idle = si_dpm_is_idle,
8042 .wait_for_idle = si_dpm_wait_for_idle,
8043 .soft_reset = si_dpm_soft_reset,
8044 .set_clockgating_state = si_dpm_set_clockgating_state,
8045 .set_powergating_state = si_dpm_set_powergating_state,
8046};
8047
8048static const struct amdgpu_dpm_funcs si_dpm_funcs = {
8049 .get_temperature = &si_dpm_get_temp,
8050 .pre_set_power_state = &si_dpm_pre_set_power_state,
8051 .set_power_state = &si_dpm_set_power_state,
8052 .post_set_power_state = &si_dpm_post_set_power_state,
8053 .display_configuration_changed = &si_dpm_display_configuration_changed,
8054 .get_sclk = &si_dpm_get_sclk,
8055 .get_mclk = &si_dpm_get_mclk,
8056 .print_power_state = &si_dpm_print_power_state,
8057 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8058 .force_performance_level = &si_dpm_force_performance_level,
8059 .vblank_too_short = &si_dpm_vblank_too_short,
8060 .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8061 .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8062 .set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
8063 .get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
8064 .check_state_equal = &si_check_state_equal,
8065 .get_vce_clock_state = amdgpu_get_vce_clock_state,
8066};
8067
8068static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev)
8069{
8070 if (adev->pm.funcs == NULL)
8071 adev->pm.funcs = &si_dpm_funcs;
8072}
8073
8074static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8075 .set = si_dpm_set_interrupt_state,
8076 .process = si_dpm_process_interrupt,
8077};
8078
8079static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8080{
8081 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8082 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
8083}
8084
8085const struct amdgpu_ip_block_version si_dpm_ip_block =
8086{
8087 .type = AMD_IP_BLOCK_TYPE_SMC,
8088 .major = 6,
8089 .minor = 0,
8090 .rev = 0,
8091 .funcs = &si_dpm_ip_funcs,
8092};