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1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include <linux/irqdomain.h>
27#include <linux/pci.h>
28#include <linux/pm_domain.h>
29#include <linux/platform_device.h>
30#include <sound/designware_i2s.h>
31#include <sound/pcm.h>
32#include <linux/acpi.h>
33#include <linux/dmi.h>
34
35#include "amdgpu.h"
36#include "atom.h"
37#include "amdgpu_acp.h"
38
39#include "acp_gfx_if.h"
40
41#define ST_JADEITE 1
42#define ACP_TILE_ON_MASK 0x03
43#define ACP_TILE_OFF_MASK 0x02
44#define ACP_TILE_ON_RETAIN_REG_MASK 0x1f
45#define ACP_TILE_OFF_RETAIN_REG_MASK 0x20
46
47#define ACP_TILE_P1_MASK 0x3e
48#define ACP_TILE_P2_MASK 0x3d
49#define ACP_TILE_DSP0_MASK 0x3b
50#define ACP_TILE_DSP1_MASK 0x37
51
52#define ACP_TILE_DSP2_MASK 0x2f
53
54#define ACP_DMA_REGS_END 0x146c0
55#define ACP_I2S_PLAY_REGS_START 0x14840
56#define ACP_I2S_PLAY_REGS_END 0x148b4
57#define ACP_I2S_CAP_REGS_START 0x148b8
58#define ACP_I2S_CAP_REGS_END 0x1496c
59
60#define ACP_I2S_COMP1_CAP_REG_OFFSET 0xac
61#define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8
62#define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c
63#define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68
64#define ACP_BT_PLAY_REGS_START 0x14970
65#define ACP_BT_PLAY_REGS_END 0x14a24
66#define ACP_BT_COMP1_REG_OFFSET 0xac
67#define ACP_BT_COMP2_REG_OFFSET 0xa8
68
69#define mmACP_PGFSM_RETAIN_REG 0x51c9
70#define mmACP_PGFSM_CONFIG_REG 0x51ca
71#define mmACP_PGFSM_READ_REG_0 0x51cc
72
73#define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8
74#define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9
75#define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa
76#define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb
77
78#define mmACP_CONTROL 0x5131
79#define mmACP_STATUS 0x5133
80#define mmACP_SOFT_RESET 0x5134
81#define ACP_CONTROL__ClkEn_MASK 0x1
82#define ACP_SOFT_RESET__SoftResetAud_MASK 0x100
83#define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000
84#define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF
85#define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF
86
87#define ACP_TIMEOUT_LOOP 0x000000FF
88#define ACP_DEVS 4
89#define ACP_SRC_ID 162
90
91static unsigned long acp_machine_id;
92
93enum {
94 ACP_TILE_P1 = 0,
95 ACP_TILE_P2,
96 ACP_TILE_DSP0,
97 ACP_TILE_DSP1,
98 ACP_TILE_DSP2,
99};
100
101static int acp_sw_init(void *handle)
102{
103 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
104
105 adev->acp.parent = adev->dev;
106
107 adev->acp.cgs_device =
108 amdgpu_cgs_create_device(adev);
109 if (!adev->acp.cgs_device)
110 return -EINVAL;
111
112 return 0;
113}
114
115static int acp_sw_fini(void *handle)
116{
117 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
118
119 if (adev->acp.cgs_device)
120 amdgpu_cgs_destroy_device(adev->acp.cgs_device);
121
122 return 0;
123}
124
125struct acp_pm_domain {
126 void *adev;
127 struct generic_pm_domain gpd;
128};
129
130static int acp_poweroff(struct generic_pm_domain *genpd)
131{
132 struct acp_pm_domain *apd;
133 struct amdgpu_device *adev;
134
135 apd = container_of(genpd, struct acp_pm_domain, gpd);
136 adev = apd->adev;
137 /* call smu to POWER GATE ACP block
138 * smu will
139 * 1. turn off the acp clock
140 * 2. power off the acp tiles
141 * 3. check and enter ulv state
142 */
143 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
144 return 0;
145}
146
147static int acp_poweron(struct generic_pm_domain *genpd)
148{
149 struct acp_pm_domain *apd;
150 struct amdgpu_device *adev;
151
152 apd = container_of(genpd, struct acp_pm_domain, gpd);
153 adev = apd->adev;
154 /* call smu to UNGATE ACP block
155 * smu will
156 * 1. exit ulv
157 * 2. turn on acp clock
158 * 3. power on acp tiles
159 */
160 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
161 return 0;
162}
163
164static int acp_genpd_add_device(struct device *dev, void *data)
165{
166 struct generic_pm_domain *gpd = data;
167 int ret;
168
169 ret = pm_genpd_add_device(gpd, dev);
170 if (ret)
171 dev_err(dev, "Failed to add dev to genpd %d\n", ret);
172
173 return ret;
174}
175
176static int acp_genpd_remove_device(struct device *dev, void *data)
177{
178 int ret;
179
180 ret = pm_genpd_remove_device(dev);
181 if (ret)
182 dev_err(dev, "Failed to remove dev from genpd %d\n", ret);
183
184 /* Continue to remove */
185 return 0;
186}
187
188static int acp_quirk_cb(const struct dmi_system_id *id)
189{
190 acp_machine_id = ST_JADEITE;
191 return 1;
192}
193
194static const struct dmi_system_id acp_quirk_table[] = {
195 {
196 .callback = acp_quirk_cb,
197 .matches = {
198 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMD"),
199 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Jadeite"),
200 }
201 },
202 {
203 .callback = acp_quirk_cb,
204 .matches = {
205 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "IP3 Technology CO.,Ltd."),
206 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ASN1D"),
207 },
208 },
209 {
210 .callback = acp_quirk_cb,
211 .matches = {
212 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Standard"),
213 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ASN10"),
214 },
215 },
216 {}
217};
218
219/**
220 * acp_hw_init - start and test ACP block
221 *
222 * @handle: handle used to pass amdgpu_device pointer
223 *
224 */
225static int acp_hw_init(void *handle)
226{
227 int r;
228 u64 acp_base;
229 u32 val = 0;
230 u32 count = 0;
231 struct i2s_platform_data *i2s_pdata = NULL;
232
233 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
234
235 const struct amdgpu_ip_block *ip_block =
236 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);
237
238 if (!ip_block)
239 return -EINVAL;
240
241 r = amd_acp_hw_init(adev->acp.cgs_device,
242 ip_block->version->major, ip_block->version->minor);
243 /* -ENODEV means board uses AZ rather than ACP */
244 if (r == -ENODEV) {
245 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
246 return 0;
247 } else if (r) {
248 return r;
249 }
250
251 if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289)
252 return -EINVAL;
253
254 acp_base = adev->rmmio_base;
255 adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL);
256 if (!adev->acp.acp_genpd)
257 return -ENOMEM;
258
259 adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
260 adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
261 adev->acp.acp_genpd->gpd.power_on = acp_poweron;
262 adev->acp.acp_genpd->adev = adev;
263
264 pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false);
265 dmi_check_system(acp_quirk_table);
266 switch (acp_machine_id) {
267 case ST_JADEITE:
268 {
269 adev->acp.acp_cell = kcalloc(2, sizeof(struct mfd_cell),
270 GFP_KERNEL);
271 if (!adev->acp.acp_cell) {
272 r = -ENOMEM;
273 goto failure;
274 }
275
276 adev->acp.acp_res = kcalloc(3, sizeof(struct resource), GFP_KERNEL);
277 if (!adev->acp.acp_res) {
278 r = -ENOMEM;
279 goto failure;
280 }
281
282 i2s_pdata = kcalloc(1, sizeof(struct i2s_platform_data), GFP_KERNEL);
283 if (!i2s_pdata) {
284 r = -ENOMEM;
285 goto failure;
286 }
287
288 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
289 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
290 i2s_pdata[0].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;
291 i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
292 i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
293 i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
294
295 adev->acp.acp_res[0].name = "acp2x_dma";
296 adev->acp.acp_res[0].flags = IORESOURCE_MEM;
297 adev->acp.acp_res[0].start = acp_base;
298 adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END;
299
300 adev->acp.acp_res[1].name = "acp2x_dw_i2s_play_cap";
301 adev->acp.acp_res[1].flags = IORESOURCE_MEM;
302 adev->acp.acp_res[1].start = acp_base + ACP_I2S_CAP_REGS_START;
303 adev->acp.acp_res[1].end = acp_base + ACP_I2S_CAP_REGS_END;
304
305 adev->acp.acp_res[2].name = "acp2x_dma_irq";
306 adev->acp.acp_res[2].flags = IORESOURCE_IRQ;
307 adev->acp.acp_res[2].start = amdgpu_irq_create_mapping(adev, 162);
308 adev->acp.acp_res[2].end = adev->acp.acp_res[2].start;
309
310 adev->acp.acp_cell[0].name = "acp_audio_dma";
311 adev->acp.acp_cell[0].num_resources = 3;
312 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
313 adev->acp.acp_cell[0].platform_data = &adev->asic_type;
314 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
315
316 adev->acp.acp_cell[1].name = "designware-i2s";
317 adev->acp.acp_cell[1].num_resources = 1;
318 adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1];
319 adev->acp.acp_cell[1].platform_data = &i2s_pdata[0];
320 adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data);
321 r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell, 2);
322 if (r)
323 goto failure;
324 r = device_for_each_child(adev->acp.parent, &adev->acp.acp_genpd->gpd,
325 acp_genpd_add_device);
326 if (r)
327 goto failure;
328 break;
329 }
330 default:
331 adev->acp.acp_cell = kcalloc(ACP_DEVS, sizeof(struct mfd_cell),
332 GFP_KERNEL);
333
334 if (!adev->acp.acp_cell) {
335 r = -ENOMEM;
336 goto failure;
337 }
338
339 adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL);
340 if (!adev->acp.acp_res) {
341 r = -ENOMEM;
342 goto failure;
343 }
344
345 i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL);
346 if (!i2s_pdata) {
347 r = -ENOMEM;
348 goto failure;
349 }
350
351 switch (adev->asic_type) {
352 case CHIP_STONEY:
353 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
354 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
355 break;
356 default:
357 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
358 }
359 i2s_pdata[0].cap = DWC_I2S_PLAY;
360 i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
361 i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
362 i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
363 switch (adev->asic_type) {
364 case CHIP_STONEY:
365 i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
366 DW_I2S_QUIRK_COMP_PARAM1 |
367 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
368 break;
369 default:
370 i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
371 DW_I2S_QUIRK_COMP_PARAM1;
372 }
373
374 i2s_pdata[1].cap = DWC_I2S_RECORD;
375 i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;
376 i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
377 i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
378
379 i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
380 switch (adev->asic_type) {
381 case CHIP_STONEY:
382 i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
383 break;
384 default:
385 break;
386 }
387
388 i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;
389 i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000;
390 i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;
391 i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;
392
393 adev->acp.acp_res[0].name = "acp2x_dma";
394 adev->acp.acp_res[0].flags = IORESOURCE_MEM;
395 adev->acp.acp_res[0].start = acp_base;
396 adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END;
397
398 adev->acp.acp_res[1].name = "acp2x_dw_i2s_play";
399 adev->acp.acp_res[1].flags = IORESOURCE_MEM;
400 adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START;
401 adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END;
402
403 adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap";
404 adev->acp.acp_res[2].flags = IORESOURCE_MEM;
405 adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START;
406 adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END;
407
408 adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap";
409 adev->acp.acp_res[3].flags = IORESOURCE_MEM;
410 adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START;
411 adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END;
412
413 adev->acp.acp_res[4].name = "acp2x_dma_irq";
414 adev->acp.acp_res[4].flags = IORESOURCE_IRQ;
415 adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162);
416 adev->acp.acp_res[4].end = adev->acp.acp_res[4].start;
417
418 adev->acp.acp_cell[0].name = "acp_audio_dma";
419 adev->acp.acp_cell[0].num_resources = 5;
420 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
421 adev->acp.acp_cell[0].platform_data = &adev->asic_type;
422 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
423
424 adev->acp.acp_cell[1].name = "designware-i2s";
425 adev->acp.acp_cell[1].num_resources = 1;
426 adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1];
427 adev->acp.acp_cell[1].platform_data = &i2s_pdata[0];
428 adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data);
429
430 adev->acp.acp_cell[2].name = "designware-i2s";
431 adev->acp.acp_cell[2].num_resources = 1;
432 adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2];
433 adev->acp.acp_cell[2].platform_data = &i2s_pdata[1];
434 adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data);
435
436 adev->acp.acp_cell[3].name = "designware-i2s";
437 adev->acp.acp_cell[3].num_resources = 1;
438 adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3];
439 adev->acp.acp_cell[3].platform_data = &i2s_pdata[2];
440 adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data);
441
442 r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell, ACP_DEVS);
443 if (r)
444 goto failure;
445
446 r = device_for_each_child(adev->acp.parent, &adev->acp.acp_genpd->gpd,
447 acp_genpd_add_device);
448 if (r)
449 goto failure;
450 }
451
452 /* Assert Soft reset of ACP */
453 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
454
455 val |= ACP_SOFT_RESET__SoftResetAud_MASK;
456 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
457
458 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
459 while (true) {
460 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
461 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
462 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
463 break;
464 if (--count == 0) {
465 dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
466 r = -ETIMEDOUT;
467 goto failure;
468 }
469 udelay(100);
470 }
471 /* Enable clock to ACP and wait until the clock is enabled */
472 val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
473 val = val | ACP_CONTROL__ClkEn_MASK;
474 cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
475
476 count = ACP_CLOCK_EN_TIME_OUT_VALUE;
477
478 while (true) {
479 val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
480 if (val & (u32) 0x1)
481 break;
482 if (--count == 0) {
483 dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
484 r = -ETIMEDOUT;
485 goto failure;
486 }
487 udelay(100);
488 }
489 /* Deassert the SOFT RESET flags */
490 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
491 val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
492 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
493 return 0;
494
495failure:
496 kfree(i2s_pdata);
497 kfree(adev->acp.acp_res);
498 kfree(adev->acp.acp_cell);
499 kfree(adev->acp.acp_genpd);
500 return r;
501}
502
503/**
504 * acp_hw_fini - stop the hardware block
505 *
506 * @handle: handle used to pass amdgpu_device pointer
507 *
508 */
509static int acp_hw_fini(void *handle)
510{
511 u32 val = 0;
512 u32 count = 0;
513 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
514
515 /* return early if no ACP */
516 if (!adev->acp.acp_genpd) {
517 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
518 return 0;
519 }
520
521 /* Assert Soft reset of ACP */
522 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
523
524 val |= ACP_SOFT_RESET__SoftResetAud_MASK;
525 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
526
527 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
528 while (true) {
529 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
530 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
531 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
532 break;
533 if (--count == 0) {
534 dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
535 return -ETIMEDOUT;
536 }
537 udelay(100);
538 }
539 /* Disable ACP clock */
540 val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
541 val &= ~ACP_CONTROL__ClkEn_MASK;
542 cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
543
544 count = ACP_CLOCK_EN_TIME_OUT_VALUE;
545
546 while (true) {
547 val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
548 if (val & (u32) 0x1)
549 break;
550 if (--count == 0) {
551 dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
552 return -ETIMEDOUT;
553 }
554 udelay(100);
555 }
556
557 device_for_each_child(adev->acp.parent, NULL,
558 acp_genpd_remove_device);
559
560 mfd_remove_devices(adev->acp.parent);
561 kfree(adev->acp.acp_res);
562 kfree(adev->acp.acp_genpd);
563 kfree(adev->acp.acp_cell);
564
565 return 0;
566}
567
568static int acp_suspend(void *handle)
569{
570 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
571
572 /* power up on suspend */
573 if (!adev->acp.acp_cell)
574 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
575 return 0;
576}
577
578static int acp_resume(void *handle)
579{
580 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
581
582 /* power down again on resume */
583 if (!adev->acp.acp_cell)
584 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
585 return 0;
586}
587
588static int acp_early_init(void *handle)
589{
590 return 0;
591}
592
593static bool acp_is_idle(void *handle)
594{
595 return true;
596}
597
598static int acp_wait_for_idle(void *handle)
599{
600 return 0;
601}
602
603static int acp_soft_reset(void *handle)
604{
605 return 0;
606}
607
608static int acp_set_clockgating_state(void *handle,
609 enum amd_clockgating_state state)
610{
611 return 0;
612}
613
614static int acp_set_powergating_state(void *handle,
615 enum amd_powergating_state state)
616{
617 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
618 bool enable = (state == AMD_PG_STATE_GATE);
619
620 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable);
621
622 return 0;
623}
624
625static const struct amd_ip_funcs acp_ip_funcs = {
626 .name = "acp_ip",
627 .early_init = acp_early_init,
628 .late_init = NULL,
629 .sw_init = acp_sw_init,
630 .sw_fini = acp_sw_fini,
631 .hw_init = acp_hw_init,
632 .hw_fini = acp_hw_fini,
633 .suspend = acp_suspend,
634 .resume = acp_resume,
635 .is_idle = acp_is_idle,
636 .wait_for_idle = acp_wait_for_idle,
637 .soft_reset = acp_soft_reset,
638 .set_clockgating_state = acp_set_clockgating_state,
639 .set_powergating_state = acp_set_powergating_state,
640};
641
642const struct amdgpu_ip_block_version acp_ip_block = {
643 .type = AMD_IP_BLOCK_TYPE_ACP,
644 .major = 2,
645 .minor = 2,
646 .rev = 0,
647 .funcs = &acp_ip_funcs,
648};
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include <linux/irqdomain.h>
27#include <linux/pm_domain.h>
28#include <linux/platform_device.h>
29#include <sound/designware_i2s.h>
30#include <sound/pcm.h>
31
32#include "amdgpu.h"
33#include "atom.h"
34#include "amdgpu_acp.h"
35
36#include "acp_gfx_if.h"
37
38#define ACP_TILE_ON_MASK 0x03
39#define ACP_TILE_OFF_MASK 0x02
40#define ACP_TILE_ON_RETAIN_REG_MASK 0x1f
41#define ACP_TILE_OFF_RETAIN_REG_MASK 0x20
42
43#define ACP_TILE_P1_MASK 0x3e
44#define ACP_TILE_P2_MASK 0x3d
45#define ACP_TILE_DSP0_MASK 0x3b
46#define ACP_TILE_DSP1_MASK 0x37
47
48#define ACP_TILE_DSP2_MASK 0x2f
49
50#define ACP_DMA_REGS_END 0x146c0
51#define ACP_I2S_PLAY_REGS_START 0x14840
52#define ACP_I2S_PLAY_REGS_END 0x148b4
53#define ACP_I2S_CAP_REGS_START 0x148b8
54#define ACP_I2S_CAP_REGS_END 0x1496c
55
56#define ACP_I2S_COMP1_CAP_REG_OFFSET 0xac
57#define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8
58#define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c
59#define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68
60
61#define mmACP_PGFSM_RETAIN_REG 0x51c9
62#define mmACP_PGFSM_CONFIG_REG 0x51ca
63#define mmACP_PGFSM_READ_REG_0 0x51cc
64
65#define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8
66#define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9
67#define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa
68#define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb
69
70#define ACP_TIMEOUT_LOOP 0x000000FF
71#define ACP_DEVS 3
72#define ACP_SRC_ID 162
73
74enum {
75 ACP_TILE_P1 = 0,
76 ACP_TILE_P2,
77 ACP_TILE_DSP0,
78 ACP_TILE_DSP1,
79 ACP_TILE_DSP2,
80};
81
82static int acp_sw_init(void *handle)
83{
84 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
85
86 adev->acp.parent = adev->dev;
87
88 adev->acp.cgs_device =
89 amdgpu_cgs_create_device(adev);
90 if (!adev->acp.cgs_device)
91 return -EINVAL;
92
93 return 0;
94}
95
96static int acp_sw_fini(void *handle)
97{
98 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
99
100 if (adev->acp.cgs_device)
101 amdgpu_cgs_destroy_device(adev->acp.cgs_device);
102
103 return 0;
104}
105
106/* power off a tile/block within ACP */
107static int acp_suspend_tile(void *cgs_dev, int tile)
108{
109 u32 val = 0;
110 u32 count = 0;
111
112 if ((tile < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) {
113 pr_err("Invalid ACP tile : %d to suspend\n", tile);
114 return -1;
115 }
116
117 val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile);
118 val &= ACP_TILE_ON_MASK;
119
120 if (val == 0x0) {
121 val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG);
122 val = val | (1 << tile);
123 cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val);
124 cgs_write_register(cgs_dev, mmACP_PGFSM_CONFIG_REG,
125 0x500 + tile);
126
127 count = ACP_TIMEOUT_LOOP;
128 while (true) {
129 val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0
130 + tile);
131 val = val & ACP_TILE_ON_MASK;
132 if (val == ACP_TILE_OFF_MASK)
133 break;
134 if (--count == 0) {
135 pr_err("Timeout reading ACP PGFSM status\n");
136 return -ETIMEDOUT;
137 }
138 udelay(100);
139 }
140
141 val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG);
142
143 val |= ACP_TILE_OFF_RETAIN_REG_MASK;
144 cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val);
145 }
146 return 0;
147}
148
149/* power on a tile/block within ACP */
150static int acp_resume_tile(void *cgs_dev, int tile)
151{
152 u32 val = 0;
153 u32 count = 0;
154
155 if ((tile < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) {
156 pr_err("Invalid ACP tile to resume\n");
157 return -1;
158 }
159
160 val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile);
161 val = val & ACP_TILE_ON_MASK;
162
163 if (val != 0x0) {
164 cgs_write_register(cgs_dev, mmACP_PGFSM_CONFIG_REG,
165 0x600 + tile);
166 count = ACP_TIMEOUT_LOOP;
167 while (true) {
168 val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0
169 + tile);
170 val = val & ACP_TILE_ON_MASK;
171 if (val == 0x0)
172 break;
173 if (--count == 0) {
174 pr_err("Timeout reading ACP PGFSM status\n");
175 return -ETIMEDOUT;
176 }
177 udelay(100);
178 }
179 val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG);
180 if (tile == ACP_TILE_P1)
181 val = val & (ACP_TILE_P1_MASK);
182 else if (tile == ACP_TILE_P2)
183 val = val & (ACP_TILE_P2_MASK);
184
185 cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val);
186 }
187 return 0;
188}
189
190struct acp_pm_domain {
191 void *cgs_dev;
192 struct generic_pm_domain gpd;
193};
194
195static int acp_poweroff(struct generic_pm_domain *genpd)
196{
197 int i, ret;
198 struct acp_pm_domain *apd;
199
200 apd = container_of(genpd, struct acp_pm_domain, gpd);
201 if (apd != NULL) {
202 /* Donot return abruptly if any of power tile fails to suspend.
203 * Log it and continue powering off other tile
204 */
205 for (i = 4; i >= 0 ; i--) {
206 ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_P1 + i);
207 if (ret)
208 pr_err("ACP tile %d tile suspend failed\n", i);
209 }
210 }
211 return 0;
212}
213
214static int acp_poweron(struct generic_pm_domain *genpd)
215{
216 int i, ret;
217 struct acp_pm_domain *apd;
218
219 apd = container_of(genpd, struct acp_pm_domain, gpd);
220 if (apd != NULL) {
221 for (i = 0; i < 2; i++) {
222 ret = acp_resume_tile(apd->cgs_dev, ACP_TILE_P1 + i);
223 if (ret) {
224 pr_err("ACP tile %d resume failed\n", i);
225 break;
226 }
227 }
228
229 /* Disable DSPs which are not going to be used */
230 for (i = 0; i < 3; i++) {
231 ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_DSP0 + i);
232 /* Continue suspending other DSP, even if one fails */
233 if (ret)
234 pr_err("ACP DSP %d suspend failed\n", i);
235 }
236 }
237 return 0;
238}
239
240static struct device *get_mfd_cell_dev(const char *device_name, int r)
241{
242 char auto_dev_name[25];
243 struct device *dev;
244
245 snprintf(auto_dev_name, sizeof(auto_dev_name),
246 "%s.%d.auto", device_name, r);
247 dev = bus_find_device_by_name(&platform_bus_type, NULL, auto_dev_name);
248 dev_info(dev, "device %s added to pm domain\n", auto_dev_name);
249
250 return dev;
251}
252
253/**
254 * acp_hw_init - start and test ACP block
255 *
256 * @adev: amdgpu_device pointer
257 *
258 */
259static int acp_hw_init(void *handle)
260{
261 int r, i;
262 uint64_t acp_base;
263 struct device *dev;
264 struct i2s_platform_data *i2s_pdata;
265
266 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
267
268 const struct amdgpu_ip_block *ip_block =
269 amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);
270
271 if (!ip_block)
272 return -EINVAL;
273
274 r = amd_acp_hw_init(adev->acp.cgs_device,
275 ip_block->version->major, ip_block->version->minor);
276 /* -ENODEV means board uses AZ rather than ACP */
277 if (r == -ENODEV)
278 return 0;
279 else if (r)
280 return r;
281
282 r = cgs_get_pci_resource(adev->acp.cgs_device, CGS_RESOURCE_TYPE_MMIO,
283 0x5289, 0, &acp_base);
284 if (r == -ENODEV)
285 return 0;
286 else if (r)
287 return r;
288
289 adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL);
290 if (adev->acp.acp_genpd == NULL)
291 return -ENOMEM;
292
293 adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
294 adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
295 adev->acp.acp_genpd->gpd.power_on = acp_poweron;
296
297
298 adev->acp.acp_genpd->cgs_dev = adev->acp.cgs_device;
299
300 pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false);
301
302 adev->acp.acp_cell = kzalloc(sizeof(struct mfd_cell) * ACP_DEVS,
303 GFP_KERNEL);
304
305 if (adev->acp.acp_cell == NULL)
306 return -ENOMEM;
307
308 adev->acp.acp_res = kzalloc(sizeof(struct resource) * 4, GFP_KERNEL);
309
310 if (adev->acp.acp_res == NULL) {
311 kfree(adev->acp.acp_cell);
312 return -ENOMEM;
313 }
314
315 i2s_pdata = kzalloc(sizeof(struct i2s_platform_data) * 2, GFP_KERNEL);
316 if (i2s_pdata == NULL) {
317 kfree(adev->acp.acp_res);
318 kfree(adev->acp.acp_cell);
319 return -ENOMEM;
320 }
321
322 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
323 i2s_pdata[0].cap = DWC_I2S_PLAY;
324 i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
325 i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
326 i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
327
328 i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
329 DW_I2S_QUIRK_COMP_PARAM1;
330 i2s_pdata[1].cap = DWC_I2S_RECORD;
331 i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;
332 i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
333 i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
334
335 adev->acp.acp_res[0].name = "acp2x_dma";
336 adev->acp.acp_res[0].flags = IORESOURCE_MEM;
337 adev->acp.acp_res[0].start = acp_base;
338 adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END;
339
340 adev->acp.acp_res[1].name = "acp2x_dw_i2s_play";
341 adev->acp.acp_res[1].flags = IORESOURCE_MEM;
342 adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START;
343 adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END;
344
345 adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap";
346 adev->acp.acp_res[2].flags = IORESOURCE_MEM;
347 adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START;
348 adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END;
349
350 adev->acp.acp_res[3].name = "acp2x_dma_irq";
351 adev->acp.acp_res[3].flags = IORESOURCE_IRQ;
352 adev->acp.acp_res[3].start = amdgpu_irq_create_mapping(adev, 162);
353 adev->acp.acp_res[3].end = adev->acp.acp_res[3].start;
354
355 adev->acp.acp_cell[0].name = "acp_audio_dma";
356 adev->acp.acp_cell[0].num_resources = 4;
357 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
358
359 adev->acp.acp_cell[1].name = "designware-i2s";
360 adev->acp.acp_cell[1].num_resources = 1;
361 adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1];
362 adev->acp.acp_cell[1].platform_data = &i2s_pdata[0];
363 adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data);
364
365 adev->acp.acp_cell[2].name = "designware-i2s";
366 adev->acp.acp_cell[2].num_resources = 1;
367 adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2];
368 adev->acp.acp_cell[2].platform_data = &i2s_pdata[1];
369 adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data);
370
371 r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell,
372 ACP_DEVS);
373 if (r)
374 return r;
375
376 for (i = 0; i < ACP_DEVS ; i++) {
377 dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
378 r = pm_genpd_add_device(&adev->acp.acp_genpd->gpd, dev);
379 if (r) {
380 dev_err(dev, "Failed to add dev to genpd\n");
381 return r;
382 }
383 }
384
385 return 0;
386}
387
388/**
389 * acp_hw_fini - stop the hardware block
390 *
391 * @adev: amdgpu_device pointer
392 *
393 */
394static int acp_hw_fini(void *handle)
395{
396 int i, ret;
397 struct device *dev;
398 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
399
400 /* return early if no ACP */
401 if (!adev->acp.acp_genpd)
402 return 0;
403
404 for (i = 0; i < ACP_DEVS ; i++) {
405 dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
406 ret = pm_genpd_remove_device(&adev->acp.acp_genpd->gpd, dev);
407 /* If removal fails, dont giveup and try rest */
408 if (ret)
409 dev_err(dev, "remove dev from genpd failed\n");
410 }
411
412 mfd_remove_devices(adev->acp.parent);
413 kfree(adev->acp.acp_res);
414 kfree(adev->acp.acp_genpd);
415 kfree(adev->acp.acp_cell);
416
417 return 0;
418}
419
420static int acp_suspend(void *handle)
421{
422 return 0;
423}
424
425static int acp_resume(void *handle)
426{
427 return 0;
428}
429
430static int acp_early_init(void *handle)
431{
432 return 0;
433}
434
435static bool acp_is_idle(void *handle)
436{
437 return true;
438}
439
440static int acp_wait_for_idle(void *handle)
441{
442 return 0;
443}
444
445static int acp_soft_reset(void *handle)
446{
447 return 0;
448}
449
450static int acp_set_clockgating_state(void *handle,
451 enum amd_clockgating_state state)
452{
453 return 0;
454}
455
456static int acp_set_powergating_state(void *handle,
457 enum amd_powergating_state state)
458{
459 return 0;
460}
461
462static const struct amd_ip_funcs acp_ip_funcs = {
463 .name = "acp_ip",
464 .early_init = acp_early_init,
465 .late_init = NULL,
466 .sw_init = acp_sw_init,
467 .sw_fini = acp_sw_fini,
468 .hw_init = acp_hw_init,
469 .hw_fini = acp_hw_fini,
470 .suspend = acp_suspend,
471 .resume = acp_resume,
472 .is_idle = acp_is_idle,
473 .wait_for_idle = acp_wait_for_idle,
474 .soft_reset = acp_soft_reset,
475 .set_clockgating_state = acp_set_clockgating_state,
476 .set_powergating_state = acp_set_powergating_state,
477};
478
479const struct amdgpu_ip_block_version acp_ip_block =
480{
481 .type = AMD_IP_BLOCK_TYPE_ACP,
482 .major = 2,
483 .minor = 2,
484 .rev = 0,
485 .funcs = &acp_ip_funcs,
486};