1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * Copyright 2016,2017 IBM Corporation.
  4 */
  5#ifndef _ASM_POWERPC_XIVE_H
  6#define _ASM_POWERPC_XIVE_H
  7
  8#include <asm/opal-api.h>
  9
 10#define XIVE_INVALID_VP	0xffffffff
 11
 12#ifdef CONFIG_PPC_XIVE
 13
 14/*
 15 * Thread Interrupt Management Area (TIMA)
 16 *
 17 * This is a global MMIO region divided in 4 pages of varying access
 18 * permissions, providing access to per-cpu interrupt management
 19 * functions. It always identifies the CPU doing the access based
 20 * on the PowerBus initiator ID, thus we always access via the
 21 * same offset regardless of where the code is executing
 22 */
 23extern void __iomem *xive_tima;
 24extern unsigned long xive_tima_os;
 25
 26/*
 27 * Offset in the TM area of our current execution level (provided by
 28 * the backend)
 29 */
 30extern u32 xive_tima_offset;
 31
 32/*
 33 * Per-irq data (irq_get_handler_data for normal IRQs), IPIs
 34 * have it stored in the xive_cpu structure. We also cache
 35 * for normal interrupts the current target CPU.
 36 *
 37 * This structure is setup by the backend for each interrupt.
 38 */
 39struct xive_irq_data {
 40	u64 flags;
 41	u64 eoi_page;
 42	void __iomem *eoi_mmio;
 43	u64 trig_page;
 44	void __iomem *trig_mmio;
 45	u32 esb_shift;
 46	int src_chip;
 47	u32 hw_irq;
 48
 49	/* Setup/used by frontend */
 50	int target;
 51	/*
 52	 * saved_p means that there is a queue entry for this interrupt
 53	 * in some CPU's queue (not including guest vcpu queues), even
 54	 * if P is not set in the source ESB.
 55	 * stale_p means that there is no queue entry for this interrupt
 56	 * in some CPU's queue, even if P is set in the source ESB.
 57	 */
 58	bool saved_p;
 59	bool stale_p;
 60};
 61#define XIVE_IRQ_FLAG_STORE_EOI	0x01
 62#define XIVE_IRQ_FLAG_LSI	0x02
 63/* #define XIVE_IRQ_FLAG_SHIFT_BUG	0x04 */ /* P9 DD1.0 workaround */
 64/* #define XIVE_IRQ_FLAG_MASK_FW	0x08 */ /* P9 DD1.0 workaround */
 65/* #define XIVE_IRQ_FLAG_EOI_FW	0x10 */ /* P9 DD1.0 workaround */
 66#define XIVE_IRQ_FLAG_H_INT_ESB	0x20
 67
 68/* Special flag set by KVM for excalation interrupts */
 69#define XIVE_IRQ_FLAG_NO_EOI	0x80
 70
 71#define XIVE_INVALID_CHIP_ID	-1
 72
 73/* A queue tracking structure in a CPU */
 74struct xive_q {
 75	__be32 			*qpage;
 76	u32			msk;
 77	u32			idx;
 78	u32			toggle;
 79	u64			eoi_phys;
 80	u32			esc_irq;
 81	atomic_t		count;
 82	atomic_t		pending_count;
 83	u64			guest_qaddr;
 84	u32			guest_qshift;
 85};
 86
 87/* Global enable flags for the XIVE support */
 88extern bool __xive_enabled;
 89
 90static inline bool xive_enabled(void) { return __xive_enabled; }
 91
 92bool xive_spapr_init(void);
 93bool xive_native_init(void);
 94void xive_smp_probe(void);
 95int  xive_smp_prepare_cpu(unsigned int cpu);
 96void xive_smp_setup_cpu(void);
 97void xive_smp_disable_cpu(void);
 98void xive_teardown_cpu(void);
 99void xive_shutdown(void);
100void xive_flush_interrupt(void);
101
102/* xmon hook */
103void xmon_xive_do_dump(int cpu);
104int xmon_xive_get_irq_config(u32 hw_irq, struct irq_data *d);
105void xmon_xive_get_irq_all(void);
106
107/* APIs used by KVM */
108u32 xive_native_default_eq_shift(void);
109u32 xive_native_alloc_vp_block(u32 max_vcpus);
110void xive_native_free_vp_block(u32 vp_base);
111int xive_native_populate_irq_data(u32 hw_irq,
112				  struct xive_irq_data *data);
113void xive_cleanup_irq_data(struct xive_irq_data *xd);
114void xive_irq_free_data(unsigned int virq);
115void xive_native_free_irq(u32 irq);
116int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
117
118int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
119				__be32 *qpage, u32 order, bool can_escalate);
120void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio);
121
122void xive_native_sync_source(u32 hw_irq);
123void xive_native_sync_queue(u32 hw_irq);
124bool is_xive_irq(struct irq_chip *chip);
125int xive_native_enable_vp(u32 vp_id, bool single_escalation);
126int xive_native_disable_vp(u32 vp_id);
127int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id);
128bool xive_native_has_single_escalation(void);
129bool xive_native_has_save_restore(void);
130
131int xive_native_get_queue_info(u32 vp_id, uint32_t prio,
132			       u64 *out_qpage,
133			       u64 *out_qsize,
134			       u64 *out_qeoi_page,
135			       u32 *out_escalate_irq,
136			       u64 *out_qflags);
137
138int xive_native_get_queue_state(u32 vp_id, uint32_t prio, u32 *qtoggle,
139				u32 *qindex);
140int xive_native_set_queue_state(u32 vp_id, uint32_t prio, u32 qtoggle,
141				u32 qindex);
142int xive_native_get_vp_state(u32 vp_id, u64 *out_state);
143bool xive_native_has_queue_state_support(void);
144extern u32 xive_native_alloc_irq_on_chip(u32 chip_id);
145
146static inline u32 xive_native_alloc_irq(void)
147{
148	return xive_native_alloc_irq_on_chip(OPAL_XIVE_ANY_CHIP);
149}
150
151#else
152
153static inline bool xive_enabled(void) { return false; }
154
155static inline bool xive_spapr_init(void) { return false; }
156static inline bool xive_native_init(void) { return false; }
157static inline void xive_smp_probe(void) { }
158static inline int  xive_smp_prepare_cpu(unsigned int cpu) { return -EINVAL; }
159static inline void xive_smp_setup_cpu(void) { }
160static inline void xive_smp_disable_cpu(void) { }
161static inline void xive_shutdown(void) { }
162static inline void xive_flush_interrupt(void) { }
163
164static inline u32 xive_native_alloc_vp_block(u32 max_vcpus) { return XIVE_INVALID_VP; }
165static inline void xive_native_free_vp_block(u32 vp_base) { }
166
167#endif
168
169#endif /* _ASM_POWERPC_XIVE_H */