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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * (C) Copyright 2005 Tundra Semiconductor Corp.
4 * Alex Bounine, <alexandreb at tundra.com).
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 */
9
10/*
11 * definitions for interrupt controller initialization and external interrupt
12 * demultiplexing on TSI108EMU/SVB boards.
13 */
14
15#ifndef _ASM_POWERPC_TSI108_IRQ_H
16#define _ASM_POWERPC_TSI108_IRQ_H
17
18/*
19 * Tsi108 interrupts
20 */
21#ifndef TSI108_IRQ_REG_BASE
22#define TSI108_IRQ_REG_BASE 0
23#endif
24
25#define TSI108_IRQ(x) (TSI108_IRQ_REG_BASE + (x))
26
27#define TSI108_MAX_VECTORS (36 + 4) /* 36 sources + PCI INT demux */
28#define MAX_TASK_PRIO 0xF
29
30#define TSI108_IRQ_SPURIOUS (TSI108_MAX_VECTORS)
31
32#define DEFAULT_PRIO_LVL 10 /* initial priority level */
33
34/* Interrupt vectors assignment to external and internal
35 * sources of requests. */
36
37/* EXTERNAL INTERRUPT SOURCES */
38
39#define IRQ_TSI108_EXT_INT0 TSI108_IRQ(0) /* External Source at INT[0] */
40#define IRQ_TSI108_EXT_INT1 TSI108_IRQ(1) /* External Source at INT[1] */
41#define IRQ_TSI108_EXT_INT2 TSI108_IRQ(2) /* External Source at INT[2] */
42#define IRQ_TSI108_EXT_INT3 TSI108_IRQ(3) /* External Source at INT[3] */
43
44/* INTERNAL INTERRUPT SOURCES */
45
46#define IRQ_TSI108_RESERVED0 TSI108_IRQ(4) /* Reserved IRQ */
47#define IRQ_TSI108_RESERVED1 TSI108_IRQ(5) /* Reserved IRQ */
48#define IRQ_TSI108_RESERVED2 TSI108_IRQ(6) /* Reserved IRQ */
49#define IRQ_TSI108_RESERVED3 TSI108_IRQ(7) /* Reserved IRQ */
50#define IRQ_TSI108_DMA0 TSI108_IRQ(8) /* DMA0 */
51#define IRQ_TSI108_DMA1 TSI108_IRQ(9) /* DMA1 */
52#define IRQ_TSI108_DMA2 TSI108_IRQ(10) /* DMA2 */
53#define IRQ_TSI108_DMA3 TSI108_IRQ(11) /* DMA3 */
54#define IRQ_TSI108_UART0 TSI108_IRQ(12) /* UART0 */
55#define IRQ_TSI108_UART1 TSI108_IRQ(13) /* UART1 */
56#define IRQ_TSI108_I2C TSI108_IRQ(14) /* I2C */
57#define IRQ_TSI108_GPIO TSI108_IRQ(15) /* GPIO */
58#define IRQ_TSI108_GIGE0 TSI108_IRQ(16) /* GIGE0 */
59#define IRQ_TSI108_GIGE1 TSI108_IRQ(17) /* GIGE1 */
60#define IRQ_TSI108_RESERVED4 TSI108_IRQ(18) /* Reserved IRQ */
61#define IRQ_TSI108_HLP TSI108_IRQ(19) /* HLP */
62#define IRQ_TSI108_SDRAM TSI108_IRQ(20) /* SDC */
63#define IRQ_TSI108_PROC_IF TSI108_IRQ(21) /* Processor IF */
64#define IRQ_TSI108_RESERVED5 TSI108_IRQ(22) /* Reserved IRQ */
65#define IRQ_TSI108_PCI TSI108_IRQ(23) /* PCI/X block */
66
67#define IRQ_TSI108_MBOX0 TSI108_IRQ(24) /* Mailbox 0 register */
68#define IRQ_TSI108_MBOX1 TSI108_IRQ(25) /* Mailbox 1 register */
69#define IRQ_TSI108_MBOX2 TSI108_IRQ(26) /* Mailbox 2 register */
70#define IRQ_TSI108_MBOX3 TSI108_IRQ(27) /* Mailbox 3 register */
71
72#define IRQ_TSI108_DBELL0 TSI108_IRQ(28) /* Doorbell 0 */
73#define IRQ_TSI108_DBELL1 TSI108_IRQ(29) /* Doorbell 1 */
74#define IRQ_TSI108_DBELL2 TSI108_IRQ(30) /* Doorbell 2 */
75#define IRQ_TSI108_DBELL3 TSI108_IRQ(31) /* Doorbell 3 */
76
77#define IRQ_TSI108_TIMER0 TSI108_IRQ(32) /* Global Timer 0 */
78#define IRQ_TSI108_TIMER1 TSI108_IRQ(33) /* Global Timer 1 */
79#define IRQ_TSI108_TIMER2 TSI108_IRQ(34) /* Global Timer 2 */
80#define IRQ_TSI108_TIMER3 TSI108_IRQ(35) /* Global Timer 3 */
81
82/*
83 * PCI bus INTA# - INTD# lines demultiplexor
84 */
85#define IRQ_PCI_INTAD_BASE TSI108_IRQ(36)
86#define IRQ_PCI_INTA (IRQ_PCI_INTAD_BASE + 0)
87#define IRQ_PCI_INTB (IRQ_PCI_INTAD_BASE + 1)
88#define IRQ_PCI_INTC (IRQ_PCI_INTAD_BASE + 2)
89#define IRQ_PCI_INTD (IRQ_PCI_INTAD_BASE + 3)
90#define NUM_PCI_IRQS (4)
91
92/* number of entries in vector dispatch table */
93#define IRQ_TSI108_TAB_SIZE (TSI108_MAX_VECTORS + 1)
94
95/* Mapping of MPIC outputs to processors' interrupt pins */
96
97#define IDIR_INT_OUT0 0x1
98#define IDIR_INT_OUT1 0x2
99#define IDIR_INT_OUT2 0x4
100#define IDIR_INT_OUT3 0x8
101
102/*---------------------------------------------------------------
103 * IRQ line configuration parameters */
104
105/* Interrupt delivery modes */
106typedef enum {
107 TSI108_IRQ_DIRECTED,
108 TSI108_IRQ_DISTRIBUTED,
109} TSI108_IRQ_MODE;
110#endif /* _ASM_POWERPC_TSI108_IRQ_H */
1/*
2 * (C) Copyright 2005 Tundra Semiconductor Corp.
3 * Alex Bounine, <alexandreb at tundra.com).
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * definitions for interrupt controller initialization and external interrupt
26 * demultiplexing on TSI108EMU/SVB boards.
27 */
28
29#ifndef _ASM_POWERPC_TSI108_IRQ_H
30#define _ASM_POWERPC_TSI108_IRQ_H
31
32/*
33 * Tsi108 interrupts
34 */
35#ifndef TSI108_IRQ_REG_BASE
36#define TSI108_IRQ_REG_BASE 0
37#endif
38
39#define TSI108_IRQ(x) (TSI108_IRQ_REG_BASE + (x))
40
41#define TSI108_MAX_VECTORS (36 + 4) /* 36 sources + PCI INT demux */
42#define MAX_TASK_PRIO 0xF
43
44#define TSI108_IRQ_SPURIOUS (TSI108_MAX_VECTORS)
45
46#define DEFAULT_PRIO_LVL 10 /* initial priority level */
47
48/* Interrupt vectors assignment to external and internal
49 * sources of requests. */
50
51/* EXTERNAL INTERRUPT SOURCES */
52
53#define IRQ_TSI108_EXT_INT0 TSI108_IRQ(0) /* External Source at INT[0] */
54#define IRQ_TSI108_EXT_INT1 TSI108_IRQ(1) /* External Source at INT[1] */
55#define IRQ_TSI108_EXT_INT2 TSI108_IRQ(2) /* External Source at INT[2] */
56#define IRQ_TSI108_EXT_INT3 TSI108_IRQ(3) /* External Source at INT[3] */
57
58/* INTERNAL INTERRUPT SOURCES */
59
60#define IRQ_TSI108_RESERVED0 TSI108_IRQ(4) /* Reserved IRQ */
61#define IRQ_TSI108_RESERVED1 TSI108_IRQ(5) /* Reserved IRQ */
62#define IRQ_TSI108_RESERVED2 TSI108_IRQ(6) /* Reserved IRQ */
63#define IRQ_TSI108_RESERVED3 TSI108_IRQ(7) /* Reserved IRQ */
64#define IRQ_TSI108_DMA0 TSI108_IRQ(8) /* DMA0 */
65#define IRQ_TSI108_DMA1 TSI108_IRQ(9) /* DMA1 */
66#define IRQ_TSI108_DMA2 TSI108_IRQ(10) /* DMA2 */
67#define IRQ_TSI108_DMA3 TSI108_IRQ(11) /* DMA3 */
68#define IRQ_TSI108_UART0 TSI108_IRQ(12) /* UART0 */
69#define IRQ_TSI108_UART1 TSI108_IRQ(13) /* UART1 */
70#define IRQ_TSI108_I2C TSI108_IRQ(14) /* I2C */
71#define IRQ_TSI108_GPIO TSI108_IRQ(15) /* GPIO */
72#define IRQ_TSI108_GIGE0 TSI108_IRQ(16) /* GIGE0 */
73#define IRQ_TSI108_GIGE1 TSI108_IRQ(17) /* GIGE1 */
74#define IRQ_TSI108_RESERVED4 TSI108_IRQ(18) /* Reserved IRQ */
75#define IRQ_TSI108_HLP TSI108_IRQ(19) /* HLP */
76#define IRQ_TSI108_SDRAM TSI108_IRQ(20) /* SDC */
77#define IRQ_TSI108_PROC_IF TSI108_IRQ(21) /* Processor IF */
78#define IRQ_TSI108_RESERVED5 TSI108_IRQ(22) /* Reserved IRQ */
79#define IRQ_TSI108_PCI TSI108_IRQ(23) /* PCI/X block */
80
81#define IRQ_TSI108_MBOX0 TSI108_IRQ(24) /* Mailbox 0 register */
82#define IRQ_TSI108_MBOX1 TSI108_IRQ(25) /* Mailbox 1 register */
83#define IRQ_TSI108_MBOX2 TSI108_IRQ(26) /* Mailbox 2 register */
84#define IRQ_TSI108_MBOX3 TSI108_IRQ(27) /* Mailbox 3 register */
85
86#define IRQ_TSI108_DBELL0 TSI108_IRQ(28) /* Doorbell 0 */
87#define IRQ_TSI108_DBELL1 TSI108_IRQ(29) /* Doorbell 1 */
88#define IRQ_TSI108_DBELL2 TSI108_IRQ(30) /* Doorbell 2 */
89#define IRQ_TSI108_DBELL3 TSI108_IRQ(31) /* Doorbell 3 */
90
91#define IRQ_TSI108_TIMER0 TSI108_IRQ(32) /* Global Timer 0 */
92#define IRQ_TSI108_TIMER1 TSI108_IRQ(33) /* Global Timer 1 */
93#define IRQ_TSI108_TIMER2 TSI108_IRQ(34) /* Global Timer 2 */
94#define IRQ_TSI108_TIMER3 TSI108_IRQ(35) /* Global Timer 3 */
95
96/*
97 * PCI bus INTA# - INTD# lines demultiplexor
98 */
99#define IRQ_PCI_INTAD_BASE TSI108_IRQ(36)
100#define IRQ_PCI_INTA (IRQ_PCI_INTAD_BASE + 0)
101#define IRQ_PCI_INTB (IRQ_PCI_INTAD_BASE + 1)
102#define IRQ_PCI_INTC (IRQ_PCI_INTAD_BASE + 2)
103#define IRQ_PCI_INTD (IRQ_PCI_INTAD_BASE + 3)
104#define NUM_PCI_IRQS (4)
105
106/* number of entries in vector dispatch table */
107#define IRQ_TSI108_TAB_SIZE (TSI108_MAX_VECTORS + 1)
108
109/* Mapping of MPIC outputs to processors' interrupt pins */
110
111#define IDIR_INT_OUT0 0x1
112#define IDIR_INT_OUT1 0x2
113#define IDIR_INT_OUT2 0x4
114#define IDIR_INT_OUT3 0x8
115
116/*---------------------------------------------------------------
117 * IRQ line configuration parameters */
118
119/* Interrupt delivery modes */
120typedef enum {
121 TSI108_IRQ_DIRECTED,
122 TSI108_IRQ_DISTRIBUTED,
123} TSI108_IRQ_MODE;
124#endif /* _ASM_POWERPC_TSI108_IRQ_H */