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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2022-2023 Intel Corporation
4 *
5 * High level display driver entry points. This is a layer between top level
6 * driver code and low level display functionality; no low level display code or
7 * details here.
8 */
9
10#include <linux/vga_switcheroo.h>
11#include <acpi/video.h>
12#include <drm/display/drm_dp_mst_helper.h>
13#include <drm/drm_atomic_helper.h>
14#include <drm/drm_mode_config.h>
15#include <drm/drm_privacy_screen_consumer.h>
16#include <drm/drm_probe_helper.h>
17#include <drm/drm_vblank.h>
18
19#include "i915_drv.h"
20#include "i9xx_wm.h"
21#include "intel_acpi.h"
22#include "intel_atomic.h"
23#include "intel_audio.h"
24#include "intel_bios.h"
25#include "intel_bw.h"
26#include "intel_cdclk.h"
27#include "intel_color.h"
28#include "intel_crtc.h"
29#include "intel_display_debugfs.h"
30#include "intel_display_driver.h"
31#include "intel_display_irq.h"
32#include "intel_display_power.h"
33#include "intel_display_types.h"
34#include "intel_display_wa.h"
35#include "intel_dkl_phy.h"
36#include "intel_dmc.h"
37#include "intel_dp.h"
38#include "intel_dp_tunnel.h"
39#include "intel_dpll.h"
40#include "intel_dpll_mgr.h"
41#include "intel_fb.h"
42#include "intel_fbc.h"
43#include "intel_fbdev.h"
44#include "intel_fdi.h"
45#include "intel_gmbus.h"
46#include "intel_hdcp.h"
47#include "intel_hotplug.h"
48#include "intel_hti.h"
49#include "intel_modeset_lock.h"
50#include "intel_modeset_setup.h"
51#include "intel_opregion.h"
52#include "intel_overlay.h"
53#include "intel_plane_initial.h"
54#include "intel_pmdemand.h"
55#include "intel_pps.h"
56#include "intel_quirks.h"
57#include "intel_vga.h"
58#include "intel_wm.h"
59#include "skl_watermark.h"
60
61bool intel_display_driver_probe_defer(struct pci_dev *pdev)
62{
63 struct drm_privacy_screen *privacy_screen;
64
65 /*
66 * apple-gmux is needed on dual GPU MacBook Pro
67 * to probe the panel if we're the inactive GPU.
68 */
69 if (vga_switcheroo_client_probe_defer(pdev))
70 return true;
71
72 /* If the LCD panel has a privacy-screen, wait for it */
73 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL);
74 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER)
75 return true;
76
77 drm_privacy_screen_put(privacy_screen);
78
79 return false;
80}
81
82void intel_display_driver_init_hw(struct drm_i915_private *i915)
83{
84 struct intel_cdclk_state *cdclk_state;
85
86 if (!HAS_DISPLAY(i915))
87 return;
88
89 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state);
90
91 intel_update_cdclk(i915);
92 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK");
93 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw;
94
95 intel_display_wa_apply(i915);
96}
97
98static const struct drm_mode_config_funcs intel_mode_funcs = {
99 .fb_create = intel_user_framebuffer_create,
100 .get_format_info = intel_fb_get_format_info,
101 .output_poll_changed = intel_fbdev_output_poll_changed,
102 .mode_valid = intel_mode_valid,
103 .atomic_check = intel_atomic_check,
104 .atomic_commit = intel_atomic_commit,
105 .atomic_state_alloc = intel_atomic_state_alloc,
106 .atomic_state_clear = intel_atomic_state_clear,
107 .atomic_state_free = intel_atomic_state_free,
108};
109
110static const struct drm_mode_config_helper_funcs intel_mode_config_funcs = {
111 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
112};
113
114static void intel_mode_config_init(struct drm_i915_private *i915)
115{
116 struct drm_mode_config *mode_config = &i915->drm.mode_config;
117
118 drm_mode_config_init(&i915->drm);
119 INIT_LIST_HEAD(&i915->display.global.obj_list);
120
121 mode_config->min_width = 0;
122 mode_config->min_height = 0;
123
124 mode_config->preferred_depth = 24;
125 mode_config->prefer_shadow = 1;
126
127 mode_config->funcs = &intel_mode_funcs;
128 mode_config->helper_private = &intel_mode_config_funcs;
129
130 mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915);
131
132 /*
133 * Maximum framebuffer dimensions, chosen to match
134 * the maximum render engine surface size on gen4+.
135 */
136 if (DISPLAY_VER(i915) >= 7) {
137 mode_config->max_width = 16384;
138 mode_config->max_height = 16384;
139 } else if (DISPLAY_VER(i915) >= 4) {
140 mode_config->max_width = 8192;
141 mode_config->max_height = 8192;
142 } else if (DISPLAY_VER(i915) == 3) {
143 mode_config->max_width = 4096;
144 mode_config->max_height = 4096;
145 } else {
146 mode_config->max_width = 2048;
147 mode_config->max_height = 2048;
148 }
149
150 if (IS_I845G(i915) || IS_I865G(i915)) {
151 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
152 mode_config->cursor_height = 1023;
153 } else if (IS_I830(i915) || IS_I85X(i915) ||
154 IS_I915G(i915) || IS_I915GM(i915)) {
155 mode_config->cursor_width = 64;
156 mode_config->cursor_height = 64;
157 } else {
158 mode_config->cursor_width = 256;
159 mode_config->cursor_height = 256;
160 }
161}
162
163static void intel_mode_config_cleanup(struct drm_i915_private *i915)
164{
165 intel_atomic_global_obj_cleanup(i915);
166 drm_mode_config_cleanup(&i915->drm);
167}
168
169static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
170{
171 struct intel_plane *plane;
172
173 for_each_intel_plane(&dev_priv->drm, plane) {
174 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv,
175 plane->pipe);
176
177 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
178 }
179}
180
181void intel_display_driver_early_probe(struct drm_i915_private *i915)
182{
183 if (!HAS_DISPLAY(i915))
184 return;
185
186 spin_lock_init(&i915->display.fb_tracking.lock);
187 mutex_init(&i915->display.backlight.lock);
188 mutex_init(&i915->display.audio.mutex);
189 mutex_init(&i915->display.wm.wm_mutex);
190 mutex_init(&i915->display.pps.mutex);
191 mutex_init(&i915->display.hdcp.hdcp_mutex);
192
193 intel_display_irq_init(i915);
194 intel_dkl_phy_init(i915);
195 intel_color_init_hooks(i915);
196 intel_init_cdclk_hooks(i915);
197 intel_audio_hooks_init(i915);
198 intel_dpll_init_clock_hook(i915);
199 intel_init_display_hooks(i915);
200 intel_fdi_init_hook(i915);
201}
202
203/* part #1: call before irq install */
204int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
205{
206 int ret;
207
208 if (i915_inject_probe_failure(i915))
209 return -ENODEV;
210
211 if (HAS_DISPLAY(i915)) {
212 ret = drm_vblank_init(&i915->drm,
213 INTEL_NUM_PIPES(i915));
214 if (ret)
215 return ret;
216 }
217
218 intel_bios_init(i915);
219
220 ret = intel_vga_register(i915);
221 if (ret)
222 goto cleanup_bios;
223
224 /* FIXME: completely on the wrong abstraction layer */
225 ret = intel_power_domains_init(i915);
226 if (ret < 0)
227 goto cleanup_vga;
228
229 intel_pmdemand_init_early(i915);
230
231 intel_power_domains_init_hw(i915, false);
232
233 if (!HAS_DISPLAY(i915))
234 return 0;
235
236 intel_dmc_init(i915);
237
238 i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0);
239 i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI |
240 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
241
242 intel_mode_config_init(i915);
243
244 ret = intel_cdclk_init(i915);
245 if (ret)
246 goto cleanup_vga_client_pw_domain_dmc;
247
248 ret = intel_color_init(i915);
249 if (ret)
250 goto cleanup_vga_client_pw_domain_dmc;
251
252 ret = intel_dbuf_init(i915);
253 if (ret)
254 goto cleanup_vga_client_pw_domain_dmc;
255
256 ret = intel_bw_init(i915);
257 if (ret)
258 goto cleanup_vga_client_pw_domain_dmc;
259
260 ret = intel_pmdemand_init(i915);
261 if (ret)
262 goto cleanup_vga_client_pw_domain_dmc;
263
264 intel_init_quirks(i915);
265
266 intel_fbc_init(i915);
267
268 return 0;
269
270cleanup_vga_client_pw_domain_dmc:
271 intel_dmc_fini(i915);
272 intel_power_domains_driver_remove(i915);
273cleanup_vga:
274 intel_vga_unregister(i915);
275cleanup_bios:
276 intel_bios_driver_remove(i915);
277
278 return ret;
279}
280
281static void set_display_access(struct drm_i915_private *i915,
282 bool any_task_allowed,
283 struct task_struct *allowed_task)
284{
285 struct drm_modeset_acquire_ctx ctx;
286 int err;
287
288 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, err) {
289 err = drm_modeset_lock_all_ctx(&i915->drm, &ctx);
290 if (err)
291 continue;
292
293 i915->display.access.any_task_allowed = any_task_allowed;
294 i915->display.access.allowed_task = allowed_task;
295 }
296
297 drm_WARN_ON(&i915->drm, err);
298}
299
300/**
301 * intel_display_driver_enable_user_access - Enable display HW access for all threads
302 * @i915: i915 device instance
303 *
304 * Enable the display HW access for all threads. Examples for such accesses
305 * are modeset commits and connector probing.
306 *
307 * This function should be called during driver loading and system resume once
308 * all the HW initialization steps are done.
309 */
310void intel_display_driver_enable_user_access(struct drm_i915_private *i915)
311{
312 set_display_access(i915, true, NULL);
313
314 intel_hpd_enable_detection_work(i915);
315}
316
317/**
318 * intel_display_driver_disable_user_access - Disable display HW access for user threads
319 * @i915: i915 device instance
320 *
321 * Disable the display HW access for user threads. Examples for such accesses
322 * are modeset commits and connector probing. For the current thread the
323 * access is still enabled, which should only perform HW init/deinit
324 * programming (as the initial modeset during driver loading or the disabling
325 * modeset during driver unloading and system suspend/shutdown). This function
326 * should be followed by calling either intel_display_driver_enable_user_access()
327 * after completing the HW init programming or
328 * intel_display_driver_suspend_access() after completing the HW deinit
329 * programming.
330 *
331 * This function should be called during driver loading/unloading and system
332 * suspend/shutdown before starting the HW init/deinit programming.
333 */
334void intel_display_driver_disable_user_access(struct drm_i915_private *i915)
335{
336 intel_hpd_disable_detection_work(i915);
337
338 set_display_access(i915, false, current);
339}
340
341/**
342 * intel_display_driver_suspend_access - Suspend display HW access for all threads
343 * @i915: i915 device instance
344 *
345 * Disable the display HW access for all threads. Examples for such accesses
346 * are modeset commits and connector probing. This call should be either
347 * followed by calling intel_display_driver_resume_access(), or the driver
348 * should be unloaded/shutdown.
349 *
350 * This function should be called during driver unloading and system
351 * suspend/shutdown after completing the HW deinit programming.
352 */
353void intel_display_driver_suspend_access(struct drm_i915_private *i915)
354{
355 set_display_access(i915, false, NULL);
356}
357
358/**
359 * intel_display_driver_resume_access - Resume display HW access for the resume thread
360 * @i915: i915 device instance
361 *
362 * Enable the display HW access for the current resume thread, keeping the
363 * access disabled for all other (user) threads. Examples for such accesses
364 * are modeset commits and connector probing. The resume thread should only
365 * perform HW init programming (as the restoring modeset). This function
366 * should be followed by calling intel_display_driver_enable_user_access(),
367 * after completing the HW init programming steps.
368 *
369 * This function should be called during system resume before starting the HW
370 * init steps.
371 */
372void intel_display_driver_resume_access(struct drm_i915_private *i915)
373{
374 set_display_access(i915, false, current);
375}
376
377/**
378 * intel_display_driver_check_access - Check if the current thread has disaplay HW access
379 * @i915: i915 device instance
380 *
381 * Check whether the current thread has display HW access, print a debug
382 * message if it doesn't. Such accesses are modeset commits and connector
383 * probing. If the function returns %false any HW access should be prevented.
384 *
385 * Returns %true if the current thread has display HW access, %false
386 * otherwise.
387 */
388bool intel_display_driver_check_access(struct drm_i915_private *i915)
389{
390 char comm[TASK_COMM_LEN];
391 char current_task[TASK_COMM_LEN + 16];
392 char allowed_task[TASK_COMM_LEN + 16] = "none";
393
394 if (i915->display.access.any_task_allowed ||
395 i915->display.access.allowed_task == current)
396 return true;
397
398 snprintf(current_task, sizeof(current_task), "%s[%d]",
399 get_task_comm(comm, current),
400 task_pid_vnr(current));
401
402 if (i915->display.access.allowed_task)
403 snprintf(allowed_task, sizeof(allowed_task), "%s[%d]",
404 get_task_comm(comm, i915->display.access.allowed_task),
405 task_pid_vnr(i915->display.access.allowed_task));
406
407 drm_dbg_kms(&i915->drm,
408 "Reject display access from task %s (allowed to %s)\n",
409 current_task, allowed_task);
410
411 return false;
412}
413
414/* part #2: call after irq install, but before gem init */
415int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
416{
417 struct drm_device *dev = &i915->drm;
418 enum pipe pipe;
419 int ret;
420
421 if (!HAS_DISPLAY(i915))
422 return 0;
423
424 intel_wm_init(i915);
425
426 intel_panel_sanitize_ssc(i915);
427
428 intel_pps_setup(i915);
429
430 intel_gmbus_setup(i915);
431
432 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
433 INTEL_NUM_PIPES(i915),
434 INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
435
436 for_each_pipe(i915, pipe) {
437 ret = intel_crtc_init(i915, pipe);
438 if (ret)
439 goto err_mode_config;
440 }
441
442 intel_plane_possible_crtcs_init(i915);
443 intel_shared_dpll_init(i915);
444 intel_fdi_pll_freq_update(i915);
445
446 intel_update_czclk(i915);
447 intel_display_driver_init_hw(i915);
448 intel_dpll_update_ref_clks(i915);
449
450 if (i915->display.cdclk.max_cdclk_freq == 0)
451 intel_update_max_cdclk(i915);
452
453 intel_hti_init(i915);
454
455 /* Just disable it once at startup */
456 intel_vga_disable(i915);
457 intel_setup_outputs(i915);
458
459 ret = intel_dp_tunnel_mgr_init(i915);
460 if (ret)
461 goto err_hdcp;
462
463 intel_display_driver_disable_user_access(i915);
464
465 drm_modeset_lock_all(dev);
466 intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx);
467 intel_acpi_assign_connector_fwnodes(i915);
468 drm_modeset_unlock_all(dev);
469
470 intel_initial_plane_config(i915);
471
472 /*
473 * Make sure hardware watermarks really match the state we read out.
474 * Note that we need to do this after reconstructing the BIOS fb's
475 * since the watermark calculation done here will use pstate->fb.
476 */
477 if (!HAS_GMCH(i915))
478 ilk_wm_sanitize(i915);
479
480 return 0;
481
482err_hdcp:
483 intel_hdcp_component_fini(i915);
484err_mode_config:
485 intel_mode_config_cleanup(i915);
486
487 return ret;
488}
489
490/* part #3: call after gem init */
491int intel_display_driver_probe(struct drm_i915_private *i915)
492{
493 int ret;
494
495 if (!HAS_DISPLAY(i915))
496 return 0;
497
498 /*
499 * This will bind stuff into ggtt, so it needs to be done after
500 * the BIOS fb takeover and whatever else magic ggtt reservations
501 * happen during gem/ggtt init.
502 */
503 intel_hdcp_component_init(i915);
504
505 /*
506 * Force all active planes to recompute their states. So that on
507 * mode_setcrtc after probe, all the intel_plane_state variables
508 * are already calculated and there is no assert_plane warnings
509 * during bootup.
510 */
511 ret = intel_initial_commit(&i915->drm);
512 if (ret)
513 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret);
514
515 intel_overlay_setup(i915);
516
517 ret = intel_fbdev_init(&i915->drm);
518 if (ret)
519 return ret;
520
521 /* Only enable hotplug handling once the fbdev is fully set up. */
522 intel_hpd_init(i915);
523
524 skl_watermark_ipc_init(i915);
525
526 return 0;
527}
528
529void intel_display_driver_register(struct drm_i915_private *i915)
530{
531 struct drm_printer p = drm_dbg_printer(&i915->drm, DRM_UT_KMS,
532 "i915 display info:");
533
534 if (!HAS_DISPLAY(i915))
535 return;
536
537 /* Must be done after probing outputs */
538 intel_opregion_register(i915);
539 intel_acpi_video_register(i915);
540
541 intel_audio_init(i915);
542
543 intel_display_driver_enable_user_access(i915);
544
545 intel_display_debugfs_register(i915);
546
547 /*
548 * Some ports require correctly set-up hpd registers for
549 * detection to work properly (leading to ghost connected
550 * connector status), e.g. VGA on gm45. Hence we can only set
551 * up the initial fbdev config after hpd irqs are fully
552 * enabled. We do it last so that the async config cannot run
553 * before the connectors are registered.
554 */
555 intel_fbdev_initial_config_async(i915);
556
557 /*
558 * We need to coordinate the hotplugs with the asynchronous
559 * fbdev configuration, for which we use the
560 * fbdev->async_cookie.
561 */
562 drm_kms_helper_poll_init(&i915->drm);
563 intel_hpd_poll_disable(i915);
564
565 intel_display_device_info_print(DISPLAY_INFO(i915),
566 DISPLAY_RUNTIME_INFO(i915), &p);
567}
568
569/* part #1: call before irq uninstall */
570void intel_display_driver_remove(struct drm_i915_private *i915)
571{
572 if (!HAS_DISPLAY(i915))
573 return;
574
575 flush_workqueue(i915->display.wq.flip);
576 flush_workqueue(i915->display.wq.modeset);
577
578 /*
579 * MST topology needs to be suspended so we don't have any calls to
580 * fbdev after it's finalized. MST will be destroyed later as part of
581 * drm_mode_config_cleanup()
582 */
583 intel_dp_mst_suspend(i915);
584}
585
586/* part #2: call after irq uninstall */
587void intel_display_driver_remove_noirq(struct drm_i915_private *i915)
588{
589 if (!HAS_DISPLAY(i915))
590 return;
591
592 intel_display_driver_suspend_access(i915);
593
594 /*
595 * Due to the hpd irq storm handling the hotplug work can re-arm the
596 * poll handlers. Hence disable polling after hpd handling is shut down.
597 */
598 intel_hpd_poll_fini(i915);
599
600 /* poll work can call into fbdev, hence clean that up afterwards */
601 intel_fbdev_fini(i915);
602
603 intel_unregister_dsm_handler();
604
605 /* flush any delayed tasks or pending work */
606 flush_workqueue(i915->unordered_wq);
607
608 intel_hdcp_component_fini(i915);
609
610 intel_mode_config_cleanup(i915);
611
612 intel_dp_tunnel_mgr_cleanup(i915);
613
614 intel_overlay_cleanup(i915);
615
616 intel_gmbus_teardown(i915);
617
618 destroy_workqueue(i915->display.wq.flip);
619 destroy_workqueue(i915->display.wq.modeset);
620
621 intel_fbc_cleanup(i915);
622}
623
624/* part #3: call after gem init */
625void intel_display_driver_remove_nogem(struct drm_i915_private *i915)
626{
627 intel_dmc_fini(i915);
628
629 intel_power_domains_driver_remove(i915);
630
631 intel_vga_unregister(i915);
632
633 intel_bios_driver_remove(i915);
634}
635
636void intel_display_driver_unregister(struct drm_i915_private *i915)
637{
638 if (!HAS_DISPLAY(i915))
639 return;
640
641 intel_fbdev_unregister(i915);
642 /*
643 * After flushing the fbdev (incl. a late async config which
644 * will have delayed queuing of a hotplug event), then flush
645 * the hotplug events.
646 */
647 drm_kms_helper_poll_fini(&i915->drm);
648
649 intel_display_driver_disable_user_access(i915);
650
651 intel_audio_deinit(i915);
652
653 drm_atomic_helper_shutdown(&i915->drm);
654
655 acpi_video_unregister();
656 intel_opregion_unregister(i915);
657}
658
659/*
660 * turn all crtc's off, but do not adjust state
661 * This has to be paired with a call to intel_modeset_setup_hw_state.
662 */
663int intel_display_driver_suspend(struct drm_i915_private *i915)
664{
665 struct drm_atomic_state *state;
666 int ret;
667
668 if (!HAS_DISPLAY(i915))
669 return 0;
670
671 state = drm_atomic_helper_suspend(&i915->drm);
672 ret = PTR_ERR_OR_ZERO(state);
673 if (ret)
674 drm_err(&i915->drm, "Suspending crtc's failed with %i\n",
675 ret);
676 else
677 i915->display.restore.modeset_state = state;
678 return ret;
679}
680
681int
682__intel_display_driver_resume(struct drm_i915_private *i915,
683 struct drm_atomic_state *state,
684 struct drm_modeset_acquire_ctx *ctx)
685{
686 struct drm_crtc_state *crtc_state;
687 struct drm_crtc *crtc;
688 int ret, i;
689
690 intel_modeset_setup_hw_state(i915, ctx);
691 intel_vga_redisable(i915);
692
693 if (!state)
694 return 0;
695
696 /*
697 * We've duplicated the state, pointers to the old state are invalid.
698 *
699 * Don't attempt to use the old state until we commit the duplicated state.
700 */
701 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
702 /*
703 * Force recalculation even if we restore
704 * current state. With fast modeset this may not result
705 * in a modeset when the state is compatible.
706 */
707 crtc_state->mode_changed = true;
708 }
709
710 /* ignore any reset values/BIOS leftovers in the WM registers */
711 if (!HAS_GMCH(i915))
712 to_intel_atomic_state(state)->skip_intermediate_wm = true;
713
714 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
715
716 drm_WARN_ON(&i915->drm, ret == -EDEADLK);
717
718 return ret;
719}
720
721void intel_display_driver_resume(struct drm_i915_private *i915)
722{
723 struct drm_atomic_state *state = i915->display.restore.modeset_state;
724 struct drm_modeset_acquire_ctx ctx;
725 int ret;
726
727 if (!HAS_DISPLAY(i915))
728 return;
729
730 i915->display.restore.modeset_state = NULL;
731 if (state)
732 state->acquire_ctx = &ctx;
733
734 drm_modeset_acquire_init(&ctx, 0);
735
736 while (1) {
737 ret = drm_modeset_lock_all_ctx(&i915->drm, &ctx);
738 if (ret != -EDEADLK)
739 break;
740
741 drm_modeset_backoff(&ctx);
742 }
743
744 if (!ret)
745 ret = __intel_display_driver_resume(i915, state, &ctx);
746
747 skl_watermark_ipc_update(i915);
748 drm_modeset_drop_locks(&ctx);
749 drm_modeset_acquire_fini(&ctx);
750
751 if (ret)
752 drm_err(&i915->drm,
753 "Restoring old state failed with %i\n", ret);
754 if (state)
755 drm_atomic_state_put(state);
756}