1/*
   2 * Copyright 2018 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#include <linux/string_helpers.h>
  27#include <linux/uaccess.h>
  28
  29#include "dc.h"
  30#include "amdgpu.h"
  31#include "amdgpu_dm.h"
  32#include "amdgpu_dm_debugfs.h"
  33#include "dm_helpers.h"
  34#include "dmub/dmub_srv.h"
  35#include "resource.h"
  36#include "dsc.h"
  37#include "link_hwss.h"
  38#include "dc/dc_dmub_srv.h"
  39#include "link/protocols/link_dp_capability.h"
  40#include "inc/hw/dchubbub.h"
  41
  42#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
  43#include "amdgpu_dm_psr.h"
  44#endif
  45
  46struct dmub_debugfs_trace_header {
  47	uint32_t entry_count;
  48	uint32_t reserved[3];
  49};
  50
  51struct dmub_debugfs_trace_entry {
  52	uint32_t trace_code;
  53	uint32_t tick_count;
  54	uint32_t param0;
  55	uint32_t param1;
  56};
  57
  58static const char *const mst_progress_status[] = {
  59	"probe",
  60	"remote_edid",
  61	"allocate_new_payload",
  62	"clear_allocated_payload",
  63};
  64
  65/* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
  66 *
  67 * Function takes in attributes passed to debugfs write entry
  68 * and writes into param array.
  69 * The user passes max_param_num to identify maximum number of
  70 * parameters that could be parsed.
  71 *
  72 */
  73static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,
  74					  long *param, const char __user *buf,
  75					  int max_param_num,
  76					  uint8_t *param_nums)
  77{
  78	char *wr_buf_ptr = NULL;
  79	uint32_t wr_buf_count = 0;
  80	int r;
  81	char *sub_str = NULL;
  82	const char delimiter[3] = {' ', '\n', '\0'};
  83	uint8_t param_index = 0;
  84
  85	*param_nums = 0;
  86
  87	wr_buf_ptr = wr_buf;
  88
  89	/* r is bytes not be copied */
  90	if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) {
  91		DRM_DEBUG_DRIVER("user data could not be read successfully\n");
  92		return -EFAULT;
  93	}
  94
  95	/* check number of parameters. isspace could not differ space and \n */
  96	while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {
  97		/* skip space*/
  98		while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
  99			wr_buf_ptr++;
 100			wr_buf_count++;
 101			}
 102
 103		if (wr_buf_count == wr_buf_size)
 104			break;
 105
 106		/* skip non-space*/
 107		while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {
 108			wr_buf_ptr++;
 109			wr_buf_count++;
 110		}
 111
 112		(*param_nums)++;
 113
 114		if (wr_buf_count == wr_buf_size)
 115			break;
 116	}
 117
 118	if (*param_nums > max_param_num)
 119		*param_nums = max_param_num;
 120
 121	wr_buf_ptr = wr_buf; /* reset buf pointer */
 122	wr_buf_count = 0; /* number of char already checked */
 123
 124	while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
 125		wr_buf_ptr++;
 126		wr_buf_count++;
 127	}
 128
 129	while (param_index < *param_nums) {
 130		/* after strsep, wr_buf_ptr will be moved to after space */
 131		sub_str = strsep(&wr_buf_ptr, delimiter);
 132
 133		r = kstrtol(sub_str, 16, &(param[param_index]));
 134
 135		if (r)
 136			DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
 137
 138		param_index++;
 139	}
 140
 141	return 0;
 142}
 143
 144/* function description
 145 * get/ set DP configuration: lane_count, link_rate, spread_spectrum
 146 *
 147 * valid lane count value: 1, 2, 4
 148 * valid link rate value:
 149 * 06h = 1.62Gbps per lane
 150 * 0Ah = 2.7Gbps per lane
 151 * 0Ch = 3.24Gbps per lane
 152 * 14h = 5.4Gbps per lane
 153 * 1Eh = 8.1Gbps per lane
 154 *
 155 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
 156 *
 157 * --- to get dp configuration
 158 *
 159 * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 160 *
 161 * It will list current, verified, reported, preferred dp configuration.
 162 * current -- for current video mode
 163 * verified --- maximum configuration which pass link training
 164 * reported --- DP rx report caps (DPCD register offset 0, 1 2)
 165 * preferred --- user force settings
 166 *
 167 * --- set (or force) dp configuration
 168 *
 169 * echo <lane_count>  <link_rate> > link_settings
 170 *
 171 * for example, to force to  2 lane, 2.7GHz,
 172 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings
 173 *
 174 * spread_spectrum could not be changed dynamically.
 175 *
 176 * in case invalid lane count, link rate are force, no hw programming will be
 177 * done. please check link settings after force operation to see if HW get
 178 * programming.
 179 *
 180 * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 181 *
 182 * check current and preferred settings.
 183 *
 184 */
 185static ssize_t dp_link_settings_read(struct file *f, char __user *buf,
 186				 size_t size, loff_t *pos)
 187{
 188	struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 189	struct dc_link *link = connector->dc_link;
 190	char *rd_buf = NULL;
 191	char *rd_buf_ptr = NULL;
 192	const uint32_t rd_buf_size = 100;
 193	uint32_t result = 0;
 194	uint8_t str_len = 0;
 195	int r;
 196
 197	if (*pos & 3 || size & 3)
 198		return -EINVAL;
 199
 200	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 201	if (!rd_buf)
 202		return 0;
 203
 204	rd_buf_ptr = rd_buf;
 205
 206	str_len = strlen("Current:  %d  0x%x  %d  ");
 207	snprintf(rd_buf_ptr, str_len, "Current:  %d  0x%x  %d  ",
 208			link->cur_link_settings.lane_count,
 209			link->cur_link_settings.link_rate,
 210			link->cur_link_settings.link_spread);
 211	rd_buf_ptr += str_len;
 212
 213	str_len = strlen("Verified:  %d  0x%x  %d  ");
 214	snprintf(rd_buf_ptr, str_len, "Verified:  %d  0x%x  %d  ",
 215			link->verified_link_cap.lane_count,
 216			link->verified_link_cap.link_rate,
 217			link->verified_link_cap.link_spread);
 218	rd_buf_ptr += str_len;
 219
 220	str_len = strlen("Reported:  %d  0x%x  %d  ");
 221	snprintf(rd_buf_ptr, str_len, "Reported:  %d  0x%x  %d  ",
 222			link->reported_link_cap.lane_count,
 223			link->reported_link_cap.link_rate,
 224			link->reported_link_cap.link_spread);
 225	rd_buf_ptr += str_len;
 226
 227	str_len = strlen("Preferred:  %d  0x%x  %d  ");
 228	snprintf(rd_buf_ptr, str_len, "Preferred:  %d  0x%x  %d\n",
 229			link->preferred_link_setting.lane_count,
 230			link->preferred_link_setting.link_rate,
 231			link->preferred_link_setting.link_spread);
 232
 233	while (size) {
 234		if (*pos >= rd_buf_size)
 235			break;
 236
 237		r = put_user(*(rd_buf + result), buf);
 238		if (r) {
 239			kfree(rd_buf);
 240			return r; /* r = -EFAULT */
 241		}
 242
 243		buf += 1;
 244		size -= 1;
 245		*pos += 1;
 246		result += 1;
 247	}
 248
 249	kfree(rd_buf);
 250	return result;
 251}
 252
 253static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
 254				 size_t size, loff_t *pos)
 255{
 256	struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 257	struct dc_link *link = connector->dc_link;
 258	struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
 259	struct dc *dc = (struct dc *)link->dc;
 260	struct dc_link_settings prefer_link_settings;
 261	char *wr_buf = NULL;
 262	const uint32_t wr_buf_size = 40;
 263	/* 0: lane_count; 1: link_rate */
 264	int max_param_num = 2;
 265	uint8_t param_nums = 0;
 266	long param[2];
 267	bool valid_input = true;
 268
 269	if (size == 0)
 270		return -EINVAL;
 271
 272	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 273	if (!wr_buf)
 274		return -ENOSPC;
 275
 276	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 277					   (long *)param, buf,
 278					   max_param_num,
 279					   &param_nums)) {
 280		kfree(wr_buf);
 281		return -EINVAL;
 282	}
 283
 284	if (param_nums <= 0) {
 285		kfree(wr_buf);
 286		DRM_DEBUG_DRIVER("user data not be read\n");
 287		return -EINVAL;
 288	}
 289
 290	switch (param[0]) {
 291	case LANE_COUNT_ONE:
 292	case LANE_COUNT_TWO:
 293	case LANE_COUNT_FOUR:
 294		break;
 295	default:
 296		valid_input = false;
 297		break;
 298	}
 299
 300	switch (param[1]) {
 301	case LINK_RATE_LOW:
 302	case LINK_RATE_HIGH:
 303	case LINK_RATE_RBR2:
 304	case LINK_RATE_HIGH2:
 305	case LINK_RATE_HIGH3:
 306	case LINK_RATE_UHBR10:
 307	case LINK_RATE_UHBR13_5:
 308	case LINK_RATE_UHBR20:
 309		break;
 310	default:
 311		valid_input = false;
 312		break;
 313	}
 314
 315	if (!valid_input) {
 316		kfree(wr_buf);
 317		DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
 318		mutex_lock(&adev->dm.dc_lock);
 319		dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
 320		mutex_unlock(&adev->dm.dc_lock);
 321		return size;
 322	}
 323
 324	/* save user force lane_count, link_rate to preferred settings
 325	 * spread spectrum will not be changed
 326	 */
 327	prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
 328	prefer_link_settings.use_link_rate_set = false;
 329	prefer_link_settings.lane_count = param[0];
 330	prefer_link_settings.link_rate = param[1];
 331
 332	mutex_lock(&adev->dm.dc_lock);
 333	dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false);
 334	mutex_unlock(&adev->dm.dc_lock);
 335
 336	kfree(wr_buf);
 337	return size;
 338}
 339
 340static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector)
 341{
 342	bool is_end_device = false;
 343	struct drm_dp_mst_topology_mgr *mgr = NULL;
 344	struct drm_dp_mst_port *port = NULL;
 345
 346	if (aconnector->mst_root && aconnector->mst_root->mst_mgr.mst_state) {
 347		mgr = &aconnector->mst_root->mst_mgr;
 348		port = aconnector->mst_output_port;
 349
 350		drm_modeset_lock(&mgr->base.lock, NULL);
 351		if (port->pdt == DP_PEER_DEVICE_SST_SINK ||
 352			port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV)
 353			is_end_device = true;
 354		drm_modeset_unlock(&mgr->base.lock);
 355	}
 356
 357	return is_end_device;
 358}
 359
 360/* Change MST link setting
 361 *
 362 * valid lane count value: 1, 2, 4
 363 * valid link rate value:
 364 * 06h = 1.62Gbps per lane
 365 * 0Ah = 2.7Gbps per lane
 366 * 0Ch = 3.24Gbps per lane
 367 * 14h = 5.4Gbps per lane
 368 * 1Eh = 8.1Gbps per lane
 369 * 3E8h = 10.0Gbps per lane
 370 * 546h = 13.5Gbps per lane
 371 * 7D0h = 20.0Gbps per lane
 372 *
 373 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/mst_link_settings
 374 *
 375 * for example, to force to  2 lane, 10.0GHz,
 376 * echo 2 0x3e8 > /sys/kernel/debug/dri/0/DP-x/mst_link_settings
 377 *
 378 * Valid input will trigger hotplug event to get new link setting applied
 379 * Invalid input will trigger training setting reset
 380 *
 381 * The usage can be referred to link_settings entry
 382 *
 383 */
 384static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf,
 385				 size_t size, loff_t *pos)
 386{
 387	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
 388	struct dc_link *link = aconnector->dc_link;
 389	struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
 390	struct dc *dc = (struct dc *)link->dc;
 391	struct dc_link_settings prefer_link_settings;
 392	char *wr_buf = NULL;
 393	const uint32_t wr_buf_size = 40;
 394	/* 0: lane_count; 1: link_rate */
 395	int max_param_num = 2;
 396	uint8_t param_nums = 0;
 397	long param[2];
 398	bool valid_input = true;
 399
 400	if (!dp_mst_is_end_device(aconnector))
 401		return -EINVAL;
 402
 403	if (size == 0)
 404		return -EINVAL;
 405
 406	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 407	if (!wr_buf)
 408		return -ENOSPC;
 409
 410	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 411					   (long *)param, buf,
 412					   max_param_num,
 413					   &param_nums)) {
 414		kfree(wr_buf);
 415		return -EINVAL;
 416	}
 417
 418	if (param_nums <= 0) {
 419		kfree(wr_buf);
 420		DRM_DEBUG_DRIVER("user data not be read\n");
 421		return -EINVAL;
 422	}
 423
 424	switch (param[0]) {
 425	case LANE_COUNT_ONE:
 426	case LANE_COUNT_TWO:
 427	case LANE_COUNT_FOUR:
 428		break;
 429	default:
 430		valid_input = false;
 431		break;
 432	}
 433
 434	switch (param[1]) {
 435	case LINK_RATE_LOW:
 436	case LINK_RATE_HIGH:
 437	case LINK_RATE_RBR2:
 438	case LINK_RATE_HIGH2:
 439	case LINK_RATE_HIGH3:
 440	case LINK_RATE_UHBR10:
 441	case LINK_RATE_UHBR13_5:
 442	case LINK_RATE_UHBR20:
 443		break;
 444	default:
 445		valid_input = false;
 446		break;
 447	}
 448
 449	if (!valid_input) {
 450		kfree(wr_buf);
 451		DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
 452		mutex_lock(&adev->dm.dc_lock);
 453		dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
 454		mutex_unlock(&adev->dm.dc_lock);
 455		return -EINVAL;
 456	}
 457
 458	/* save user force lane_count, link_rate to preferred settings
 459	 * spread spectrum will not be changed
 460	 */
 461	prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
 462	prefer_link_settings.use_link_rate_set = false;
 463	prefer_link_settings.lane_count = param[0];
 464	prefer_link_settings.link_rate = param[1];
 465
 466	/* skip immediate retrain, and train to new link setting after hotplug event triggered */
 467	mutex_lock(&adev->dm.dc_lock);
 468	dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, true);
 469	mutex_unlock(&adev->dm.dc_lock);
 470
 471	mutex_lock(&aconnector->base.dev->mode_config.mutex);
 472	aconnector->base.force = DRM_FORCE_OFF;
 473	mutex_unlock(&aconnector->base.dev->mode_config.mutex);
 474	drm_kms_helper_hotplug_event(aconnector->base.dev);
 475
 476	msleep(100);
 477
 478	mutex_lock(&aconnector->base.dev->mode_config.mutex);
 479	aconnector->base.force = DRM_FORCE_UNSPECIFIED;
 480	mutex_unlock(&aconnector->base.dev->mode_config.mutex);
 481	drm_kms_helper_hotplug_event(aconnector->base.dev);
 482
 483	kfree(wr_buf);
 484	return size;
 485}
 486
 487/* function: get current DP PHY settings: voltage swing, pre-emphasis,
 488 * post-cursor2 (defined by VESA DP specification)
 489 *
 490 * valid values
 491 * voltage swing: 0,1,2,3
 492 * pre-emphasis : 0,1,2,3
 493 * post cursor2 : 0,1,2,3
 494 *
 495 *
 496 * how to use this debugfs
 497 *
 498 * debugfs is located at /sys/kernel/debug/dri/0/DP-x
 499 *
 500 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display
 501 *
 502 * To figure out which DP-x is the display for DP to be check,
 503 * cd DP-x
 504 * ls -ll
 505 * There should be debugfs file, like link_settings, phy_settings.
 506 * cat link_settings
 507 * from lane_count, link_rate to figure which DP-x is for display to be worked
 508 * on
 509 *
 510 * To get current DP PHY settings,
 511 * cat phy_settings
 512 *
 513 * To change DP PHY settings,
 514 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings
 515 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to
 516 * 0,
 517 * echo 2 3 0 > phy_settings
 518 *
 519 * To check if change be applied, get current phy settings by
 520 * cat phy_settings
 521 *
 522 * In case invalid values are set by user, like
 523 * echo 1 4 0 > phy_settings
 524 *
 525 * HW will NOT be programmed by these settings.
 526 * cat phy_settings will show the previous valid settings.
 527 */
 528static ssize_t dp_phy_settings_read(struct file *f, char __user *buf,
 529				 size_t size, loff_t *pos)
 530{
 531	struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 532	struct dc_link *link = connector->dc_link;
 533	char *rd_buf = NULL;
 534	const uint32_t rd_buf_size = 20;
 535	uint32_t result = 0;
 536	int r;
 537
 538	if (*pos & 3 || size & 3)
 539		return -EINVAL;
 540
 541	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 542	if (!rd_buf)
 543		return -EINVAL;
 544
 545	snprintf(rd_buf, rd_buf_size, "  %d  %d  %d\n",
 546			link->cur_lane_setting[0].VOLTAGE_SWING,
 547			link->cur_lane_setting[0].PRE_EMPHASIS,
 548			link->cur_lane_setting[0].POST_CURSOR2);
 549
 550	while (size) {
 551		if (*pos >= rd_buf_size)
 552			break;
 553
 554		r = put_user((*(rd_buf + result)), buf);
 555		if (r) {
 556			kfree(rd_buf);
 557			return r; /* r = -EFAULT */
 558		}
 559
 560		buf += 1;
 561		size -= 1;
 562		*pos += 1;
 563		result += 1;
 564	}
 565
 566	kfree(rd_buf);
 567	return result;
 568}
 569
 570static int dp_lttpr_status_show(struct seq_file *m, void *unused)
 571{
 572	struct drm_connector *connector = m->private;
 573	struct amdgpu_dm_connector *aconnector =
 574		to_amdgpu_dm_connector(connector);
 575	struct dc_lttpr_caps caps = aconnector->dc_link->dpcd_caps.lttpr_caps;
 576
 577	if (connector->status != connector_status_connected)
 578		return -ENODEV;
 579
 580	seq_printf(m, "phy repeater count: %u (raw: 0x%x)\n",
 581		   dp_parse_lttpr_repeater_count(caps.phy_repeater_cnt),
 582		   caps.phy_repeater_cnt);
 583
 584	seq_puts(m, "phy repeater mode: ");
 585
 586	switch (caps.mode) {
 587	case DP_PHY_REPEATER_MODE_TRANSPARENT:
 588		seq_puts(m, "transparent");
 589		break;
 590	case DP_PHY_REPEATER_MODE_NON_TRANSPARENT:
 591		seq_puts(m, "non-transparent");
 592		break;
 593	case 0x00:
 594		seq_puts(m, "non lttpr");
 595		break;
 596	default:
 597		seq_printf(m, "read error (raw: 0x%x)", caps.mode);
 598		break;
 599	}
 600
 601	seq_puts(m, "\n");
 602	return 0;
 603}
 604
 605static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
 606				 size_t size, loff_t *pos)
 607{
 608	struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 609	struct dc_link *link = connector->dc_link;
 610	struct dc *dc = (struct dc *)link->dc;
 611	char *wr_buf = NULL;
 612	uint32_t wr_buf_size = 40;
 613	long param[3];
 614	bool use_prefer_link_setting;
 615	struct link_training_settings link_lane_settings;
 616	int max_param_num = 3;
 617	uint8_t param_nums = 0;
 618	int r = 0;
 619
 620
 621	if (size == 0)
 622		return -EINVAL;
 623
 624	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 625	if (!wr_buf)
 626		return -ENOSPC;
 627
 628	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 629					   (long *)param, buf,
 630					   max_param_num,
 631					   &param_nums)) {
 632		kfree(wr_buf);
 633		return -EINVAL;
 634	}
 635
 636	if (param_nums <= 0) {
 637		kfree(wr_buf);
 638		DRM_DEBUG_DRIVER("user data not be read\n");
 639		return -EINVAL;
 640	}
 641
 642	if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) ||
 643			(param[1] > PRE_EMPHASIS_MAX_LEVEL) ||
 644			(param[2] > POST_CURSOR2_MAX_LEVEL)) {
 645		kfree(wr_buf);
 646		DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n");
 647		return size;
 648	}
 649
 650	/* get link settings: lane count, link rate */
 651	use_prefer_link_setting =
 652		((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) &&
 653		(link->test_pattern_enabled));
 654
 655	memset(&link_lane_settings, 0, sizeof(link_lane_settings));
 656
 657	if (use_prefer_link_setting) {
 658		link_lane_settings.link_settings.lane_count =
 659				link->preferred_link_setting.lane_count;
 660		link_lane_settings.link_settings.link_rate =
 661				link->preferred_link_setting.link_rate;
 662		link_lane_settings.link_settings.link_spread =
 663				link->preferred_link_setting.link_spread;
 664	} else {
 665		link_lane_settings.link_settings.lane_count =
 666				link->cur_link_settings.lane_count;
 667		link_lane_settings.link_settings.link_rate =
 668				link->cur_link_settings.link_rate;
 669		link_lane_settings.link_settings.link_spread =
 670				link->cur_link_settings.link_spread;
 671	}
 672
 673	/* apply phy settings from user */
 674	for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
 675		link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING =
 676				(enum dc_voltage_swing) (param[0]);
 677		link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS =
 678				(enum dc_pre_emphasis) (param[1]);
 679		link_lane_settings.hw_lane_settings[r].POST_CURSOR2 =
 680				(enum dc_post_cursor2) (param[2]);
 681	}
 682
 683	/* program ASIC registers and DPCD registers */
 684	dc_link_set_drive_settings(dc, &link_lane_settings, link);
 685
 686	kfree(wr_buf);
 687	return size;
 688}
 689
 690/* function description
 691 *
 692 * set PHY layer or Link layer test pattern
 693 * PHY test pattern is used for PHY SI check.
 694 * Link layer test will not affect PHY SI.
 695 *
 696 * Reset Test Pattern:
 697 * 0 = DP_TEST_PATTERN_VIDEO_MODE
 698 *
 699 * PHY test pattern supported:
 700 * 1 = DP_TEST_PATTERN_D102
 701 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR
 702 * 3 = DP_TEST_PATTERN_PRBS7
 703 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM
 704 * 5 = DP_TEST_PATTERN_CP2520_1
 705 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
 706 * 7 = DP_TEST_PATTERN_CP2520_3
 707 *
 708 * DP PHY Link Training Patterns
 709 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1
 710 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2
 711 * a = DP_TEST_PATTERN_TRAINING_PATTERN3
 712 * b = DP_TEST_PATTERN_TRAINING_PATTERN4
 713 *
 714 * DP Link Layer Test pattern
 715 * c = DP_TEST_PATTERN_COLOR_SQUARES
 716 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA
 717 * e = DP_TEST_PATTERN_VERTICAL_BARS
 718 * f = DP_TEST_PATTERN_HORIZONTAL_BARS
 719 * 10= DP_TEST_PATTERN_COLOR_RAMP
 720 *
 721 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x
 722 *
 723 * --- set test pattern
 724 * echo <test pattern #> > test_pattern
 725 *
 726 * If test pattern # is not supported, NO HW programming will be done.
 727 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data
 728 * for the user pattern. input 10 bytes data are separated by space
 729 *
 730 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern
 731 *
 732 * --- reset test pattern
 733 * echo 0 > test_pattern
 734 *
 735 * --- HPD detection is disabled when set PHY test pattern
 736 *
 737 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC
 738 * is disable. User could unplug DP display from DP connected and plug scope to
 739 * check test pattern PHY SI.
 740 * If there is need unplug scope and plug DP display back, do steps below:
 741 * echo 0 > phy_test_pattern
 742 * unplug scope
 743 * plug DP display.
 744 *
 745 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw
 746 * driver could detect "unplug scope" and "plug DP display"
 747 */
 748static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf,
 749				 size_t size, loff_t *pos)
 750{
 751	struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 752	struct dc_link *link = connector->dc_link;
 753	char *wr_buf = NULL;
 754	uint32_t wr_buf_size = 100;
 755	long param[11] = {0x0};
 756	int max_param_num = 11;
 757	enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 758	bool disable_hpd = false;
 759	bool valid_test_pattern = false;
 760	uint8_t param_nums = 0;
 761	/* init with default 80bit custom pattern */
 762	uint8_t custom_pattern[10] = {
 763			0x1f, 0x7c, 0xf0, 0xc1, 0x07,
 764			0x1f, 0x7c, 0xf0, 0xc1, 0x07
 765			};
 766	struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN,
 767			LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 768	struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN,
 769			LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 770	struct link_training_settings link_training_settings;
 771	int i;
 772
 773	if (size == 0)
 774		return -EINVAL;
 775
 776	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 777	if (!wr_buf)
 778		return -ENOSPC;
 779
 780	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 781					   (long *)param, buf,
 782					   max_param_num,
 783					   &param_nums)) {
 784		kfree(wr_buf);
 785		return -EINVAL;
 786	}
 787
 788	if (param_nums <= 0) {
 789		kfree(wr_buf);
 790		DRM_DEBUG_DRIVER("user data not be read\n");
 791		return -EINVAL;
 792	}
 793
 794
 795	test_pattern = param[0];
 796
 797	switch (test_pattern) {
 798	case DP_TEST_PATTERN_VIDEO_MODE:
 799	case DP_TEST_PATTERN_COLOR_SQUARES:
 800	case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
 801	case DP_TEST_PATTERN_VERTICAL_BARS:
 802	case DP_TEST_PATTERN_HORIZONTAL_BARS:
 803	case DP_TEST_PATTERN_COLOR_RAMP:
 804		valid_test_pattern = true;
 805		break;
 806
 807	case DP_TEST_PATTERN_D102:
 808	case DP_TEST_PATTERN_SYMBOL_ERROR:
 809	case DP_TEST_PATTERN_PRBS7:
 810	case DP_TEST_PATTERN_80BIT_CUSTOM:
 811	case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
 812	case DP_TEST_PATTERN_TRAINING_PATTERN4:
 813		disable_hpd = true;
 814		valid_test_pattern = true;
 815		break;
 816
 817	default:
 818		valid_test_pattern = false;
 819		test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 820		break;
 821	}
 822
 823	if (!valid_test_pattern) {
 824		kfree(wr_buf);
 825		DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n");
 826		return size;
 827	}
 828
 829	if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
 830		for (i = 0; i < 10; i++) {
 831			if ((uint8_t) param[i + 1] != 0x0)
 832				break;
 833		}
 834
 835		if (i < 10) {
 836			/* not use default value */
 837			for (i = 0; i < 10; i++)
 838				custom_pattern[i] = (uint8_t) param[i + 1];
 839		}
 840	}
 841
 842	/* Usage: set DP physical test pattern using debugfs with normal DP
 843	 * panel. Then plug out DP panel and connect a scope to measure
 844	 * For normal video mode and test pattern generated from CRCT,
 845	 * they are visibile to user. So do not disable HPD.
 846	 * Video Mode is also set to clear the test pattern, so enable HPD
 847	 * because it might have been disabled after a test pattern was set.
 848	 * AUX depends on HPD * sequence dependent, do not move!
 849	 */
 850	if (!disable_hpd)
 851		dc_link_enable_hpd(link);
 852
 853	prefer_link_settings.lane_count = link->verified_link_cap.lane_count;
 854	prefer_link_settings.link_rate = link->verified_link_cap.link_rate;
 855	prefer_link_settings.link_spread = link->verified_link_cap.link_spread;
 856
 857	cur_link_settings.lane_count = link->cur_link_settings.lane_count;
 858	cur_link_settings.link_rate = link->cur_link_settings.link_rate;
 859	cur_link_settings.link_spread = link->cur_link_settings.link_spread;
 860
 861	link_training_settings.link_settings = cur_link_settings;
 862
 863
 864	if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
 865		if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN &&
 866			prefer_link_settings.link_rate !=  LINK_RATE_UNKNOWN &&
 867			(prefer_link_settings.lane_count != cur_link_settings.lane_count ||
 868			prefer_link_settings.link_rate != cur_link_settings.link_rate))
 869			link_training_settings.link_settings = prefer_link_settings;
 870	}
 871
 872	for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
 873		link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i];
 874
 875	dc_link_dp_set_test_pattern(
 876		link,
 877		test_pattern,
 878		DP_TEST_PATTERN_COLOR_SPACE_RGB,
 879		&link_training_settings,
 880		custom_pattern,
 881		10);
 882
 883	/* Usage: Set DP physical test pattern using AMDDP with normal DP panel
 884	 * Then plug out DP panel and connect a scope to measure DP PHY signal.
 885	 * Need disable interrupt to avoid SW driver disable DP output. This is
 886	 * done after the test pattern is set.
 887	 */
 888	if (valid_test_pattern && disable_hpd)
 889		dc_link_disable_hpd(link);
 890
 891	kfree(wr_buf);
 892
 893	return size;
 894}
 895
 896/*
 897 * Returns the DMCUB tracebuffer contents.
 898 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
 899 */
 900static int dmub_tracebuffer_show(struct seq_file *m, void *data)
 901{
 902	struct amdgpu_device *adev = m->private;
 903	struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 904	struct dmub_debugfs_trace_entry *entries;
 905	uint8_t *tbuf_base;
 906	uint32_t tbuf_size, max_entries, num_entries, i;
 907
 908	if (!fb_info)
 909		return 0;
 910
 911	tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr;
 912	if (!tbuf_base)
 913		return 0;
 914
 915	tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size;
 916	max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) /
 917		      sizeof(struct dmub_debugfs_trace_entry);
 918
 919	num_entries =
 920		((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count;
 921
 922	num_entries = min(num_entries, max_entries);
 923
 924	entries = (struct dmub_debugfs_trace_entry
 925			   *)(tbuf_base +
 926			      sizeof(struct dmub_debugfs_trace_header));
 927
 928	for (i = 0; i < num_entries; ++i) {
 929		struct dmub_debugfs_trace_entry *entry = &entries[i];
 930
 931		seq_printf(m,
 932			   "trace_code=%u tick_count=%u param0=%u param1=%u\n",
 933			   entry->trace_code, entry->tick_count, entry->param0,
 934			   entry->param1);
 935	}
 936
 937	return 0;
 938}
 939
 940/*
 941 * Returns the DMCUB firmware state contents.
 942 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state
 943 */
 944static int dmub_fw_state_show(struct seq_file *m, void *data)
 945{
 946	struct amdgpu_device *adev = m->private;
 947	struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 948	uint8_t *state_base;
 949	uint32_t state_size;
 950
 951	if (!fb_info)
 952		return 0;
 953
 954	state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr;
 955	if (!state_base)
 956		return 0;
 957
 958	state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size;
 959
 960	return seq_write(m, state_base, state_size);
 961}
 962
 963/* psr_capability_show() - show eDP panel PSR capability
 964 *
 965 * The read function: sink_psr_capability_show
 966 * Shows if sink has PSR capability or not.
 967 * If yes - the PSR version is appended
 968 *
 969 *	cat /sys/kernel/debug/dri/0/eDP-X/psr_capability
 970 *
 971 * Expected output:
 972 * "Sink support: no\n" - if panel doesn't support PSR
 973 * "Sink support: yes [0x01]\n" - if panel supports PSR1
 974 * "Driver support: no\n" - if driver doesn't support PSR
 975 * "Driver support: yes [0x01]\n" - if driver supports PSR1
 976 */
 977static int psr_capability_show(struct seq_file *m, void *data)
 978{
 979	struct drm_connector *connector = m->private;
 980	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 981	struct dc_link *link = aconnector->dc_link;
 982
 983	if (!link)
 984		return -ENODEV;
 985
 986	if (link->type == dc_connection_none)
 987		return -ENODEV;
 988
 989	if (!(link->connector_signal & SIGNAL_TYPE_EDP))
 990		return -ENODEV;
 991
 992	seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0));
 993	if (link->dpcd_caps.psr_info.psr_version)
 994		seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version);
 995	seq_puts(m, "\n");
 996
 997	seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled));
 998	if (link->psr_settings.psr_version)
 999		seq_printf(m, " [0x%02x]", link->psr_settings.psr_version);
1000	seq_puts(m, "\n");
1001
1002	return 0;
1003}
1004
1005/*
1006 * Returns the current bpc for the crtc.
1007 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc
1008 */
1009static int amdgpu_current_bpc_show(struct seq_file *m, void *data)
1010{
1011	struct drm_crtc *crtc = m->private;
1012	struct drm_device *dev = crtc->dev;
1013	struct dm_crtc_state *dm_crtc_state = NULL;
1014	int res = -ENODEV;
1015	unsigned int bpc;
1016
1017	mutex_lock(&dev->mode_config.mutex);
1018	drm_modeset_lock(&crtc->mutex, NULL);
1019	if (crtc->state == NULL)
1020		goto unlock;
1021
1022	dm_crtc_state = to_dm_crtc_state(crtc->state);
1023	if (dm_crtc_state->stream == NULL)
1024		goto unlock;
1025
1026	switch (dm_crtc_state->stream->timing.display_color_depth) {
1027	case COLOR_DEPTH_666:
1028		bpc = 6;
1029		break;
1030	case COLOR_DEPTH_888:
1031		bpc = 8;
1032		break;
1033	case COLOR_DEPTH_101010:
1034		bpc = 10;
1035		break;
1036	case COLOR_DEPTH_121212:
1037		bpc = 12;
1038		break;
1039	case COLOR_DEPTH_161616:
1040		bpc = 16;
1041		break;
1042	default:
1043		goto unlock;
1044	}
1045
1046	seq_printf(m, "Current: %u\n", bpc);
1047	res = 0;
1048
1049unlock:
1050	drm_modeset_unlock(&crtc->mutex);
1051	mutex_unlock(&dev->mode_config.mutex);
1052
1053	return res;
1054}
1055DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc);
1056
1057/*
1058 * Returns the current colorspace for the crtc.
1059 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_colorspace
1060 */
1061static int amdgpu_current_colorspace_show(struct seq_file *m, void *data)
1062{
1063	struct drm_crtc *crtc = m->private;
1064	struct drm_device *dev = crtc->dev;
1065	struct dm_crtc_state *dm_crtc_state = NULL;
1066	int res = -ENODEV;
1067
1068	mutex_lock(&dev->mode_config.mutex);
1069	drm_modeset_lock(&crtc->mutex, NULL);
1070	if (crtc->state == NULL)
1071		goto unlock;
1072
1073	dm_crtc_state = to_dm_crtc_state(crtc->state);
1074	if (dm_crtc_state->stream == NULL)
1075		goto unlock;
1076
1077	switch (dm_crtc_state->stream->output_color_space) {
1078	case COLOR_SPACE_SRGB:
1079		seq_puts(m, "sRGB");
1080		break;
1081	case COLOR_SPACE_YCBCR601:
1082	case COLOR_SPACE_YCBCR601_LIMITED:
1083		seq_puts(m, "BT601_YCC");
1084		break;
1085	case COLOR_SPACE_YCBCR709:
1086	case COLOR_SPACE_YCBCR709_LIMITED:
1087		seq_puts(m, "BT709_YCC");
1088		break;
1089	case COLOR_SPACE_ADOBERGB:
1090		seq_puts(m, "opRGB");
1091		break;
1092	case COLOR_SPACE_2020_RGB_FULLRANGE:
1093		seq_puts(m, "BT2020_RGB");
1094		break;
1095	case COLOR_SPACE_2020_YCBCR:
1096		seq_puts(m, "BT2020_YCC");
1097		break;
1098	default:
1099		goto unlock;
1100	}
1101	res = 0;
1102
1103unlock:
1104	drm_modeset_unlock(&crtc->mutex);
1105	mutex_unlock(&dev->mode_config.mutex);
1106
1107	return res;
1108}
1109DEFINE_SHOW_ATTRIBUTE(amdgpu_current_colorspace);
1110
1111
1112/*
1113 * Example usage:
1114 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX
1115 *   echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
1116 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
1117 *   echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
1118 */
1119static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf,
1120				 size_t size, loff_t *pos)
1121{
1122	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1123	char *wr_buf = NULL;
1124	uint32_t wr_buf_size = 42;
1125	int max_param_num = 1;
1126	long param;
1127	uint8_t param_nums = 0;
1128
1129	if (size == 0)
1130		return -EINVAL;
1131
1132	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1133
1134	if (!wr_buf) {
1135		DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1136		return -ENOSPC;
1137	}
1138
1139	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1140					   &param, buf,
1141					   max_param_num,
1142					   &param_nums)) {
1143		kfree(wr_buf);
1144		return -EINVAL;
1145	}
1146
1147	aconnector->dsc_settings.dsc_force_disable_passthrough = param;
1148
1149	kfree(wr_buf);
1150	return 0;
1151}
1152
1153/*
1154 * Returns the HDCP capability of the Display (1.4 for now).
1155 *
1156 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable.
1157 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable.
1158 *
1159 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability
1160 *		or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability
1161 */
1162static int hdcp_sink_capability_show(struct seq_file *m, void *data)
1163{
1164	struct drm_connector *connector = m->private;
1165	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1166	bool hdcp_cap, hdcp2_cap;
1167
1168	if (connector->status != connector_status_connected)
1169		return -ENODEV;
1170
1171	seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id);
1172
1173	hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal);
1174	hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal);
1175
1176
1177	if (hdcp_cap)
1178		seq_printf(m, "%s ", "HDCP1.4");
1179	if (hdcp2_cap)
1180		seq_printf(m, "%s ", "HDCP2.2");
1181
1182	if (!hdcp_cap && !hdcp2_cap)
1183		seq_printf(m, "%s ", "None");
1184
1185	seq_puts(m, "\n");
1186
1187	return 0;
1188}
1189
1190/*
1191 * Returns whether the connected display is internal and not hotpluggable.
1192 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display
1193 */
1194static int internal_display_show(struct seq_file *m, void *data)
1195{
1196	struct drm_connector *connector = m->private;
1197	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1198	struct dc_link *link = aconnector->dc_link;
1199
1200	seq_printf(m, "Internal: %u\n", link->is_internal_display);
1201
1202	return 0;
1203}
1204
1205/*
1206 * Returns the number of segments used if ODM Combine mode is enabled.
1207 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/odm_combine_segments
1208 */
1209static int odm_combine_segments_show(struct seq_file *m, void *unused)
1210{
1211	struct drm_connector *connector = m->private;
1212	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1213	struct dc_link *link = aconnector->dc_link;
1214	struct pipe_ctx *pipe_ctx = NULL;
1215	int i, segments = -EOPNOTSUPP;
1216
1217	for (i = 0; i < MAX_PIPES; i++) {
1218		pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
1219		if (pipe_ctx->stream &&
1220		    pipe_ctx->stream->link == link)
1221			break;
1222	}
1223
1224	if (connector->status != connector_status_connected)
1225		return -ENODEV;
1226
1227	if (pipe_ctx != NULL && pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments)
1228		pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments);
1229
1230	seq_printf(m, "%d\n", segments);
1231	return 0;
1232}
1233
1234/* function description
1235 *
1236 * generic SDP message access for testing
1237 *
1238 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x
1239 *
1240 * SDP header
1241 * Hb0 : Secondary-Data Packet ID
1242 * Hb1 : Secondary-Data Packet type
1243 * Hb2 : Secondary-Data-packet-specific header, Byte 0
1244 * Hb3 : Secondary-Data-packet-specific header, Byte 1
1245 *
1246 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data
1247 */
1248static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf,
1249				 size_t size, loff_t *pos)
1250{
1251	int r;
1252	uint8_t data[36];
1253	struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1254	struct dm_crtc_state *acrtc_state;
1255	uint32_t write_size = 36;
1256
1257	if (connector->base.status != connector_status_connected)
1258		return -ENODEV;
1259
1260	if (size == 0)
1261		return 0;
1262
1263	acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state);
1264
1265	r = copy_from_user(data, buf, write_size);
1266
1267	write_size -= r;
1268
1269	dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size);
1270
1271	return write_size;
1272}
1273
1274/* function: Read link's DSC & FEC capabilities
1275 *
1276 *
1277 * Access it with the following command (you need to specify
1278 * connector like DP-1):
1279 *
1280 *	cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support
1281 *
1282 */
1283static int dp_dsc_fec_support_show(struct seq_file *m, void *data)
1284{
1285	struct drm_connector *connector = m->private;
1286	struct drm_modeset_acquire_ctx ctx;
1287	struct drm_device *dev = connector->dev;
1288	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1289	int ret = 0;
1290	bool try_again = false;
1291	bool is_fec_supported = false;
1292	bool is_dsc_supported = false;
1293	struct dpcd_caps dpcd_caps;
1294
1295	drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1296	do {
1297		try_again = false;
1298		ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
1299		if (ret) {
1300			if (ret == -EDEADLK) {
1301				ret = drm_modeset_backoff(&ctx);
1302				if (!ret) {
1303					try_again = true;
1304					continue;
1305				}
1306			}
1307			break;
1308		}
1309		if (connector->status != connector_status_connected) {
1310			ret = -ENODEV;
1311			break;
1312		}
1313		dpcd_caps = aconnector->dc_link->dpcd_caps;
1314		if (aconnector->mst_output_port) {
1315			/* aconnector sets dsc_aux during get_modes call
1316			 * if MST connector has it means it can either
1317			 * enable DSC on the sink device or on MST branch
1318			 * its connected to.
1319			 */
1320			if (aconnector->dsc_aux) {
1321				is_fec_supported = true;
1322				is_dsc_supported = true;
1323			}
1324		} else {
1325			is_fec_supported = dpcd_caps.fec_cap.raw & 0x1;
1326			is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1;
1327		}
1328	} while (try_again);
1329
1330	drm_modeset_drop_locks(&ctx);
1331	drm_modeset_acquire_fini(&ctx);
1332
1333	seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported));
1334	seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported));
1335
1336	return ret;
1337}
1338
1339/* function: Trigger virtual HPD redetection on connector
1340 *
1341 * This function will perform link rediscovery, link disable
1342 * and enable, and dm connector state update.
1343 *
1344 * Retrigger HPD on an existing connector by echoing 1 into
1345 * its respectful "trigger_hotplug" debugfs entry:
1346 *
1347 *	echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1348 *
1349 * This function can perform HPD unplug:
1350 *
1351 *	echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1352 *
1353 */
1354static ssize_t trigger_hotplug(struct file *f, const char __user *buf,
1355							size_t size, loff_t *pos)
1356{
1357	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1358	struct drm_connector *connector = &aconnector->base;
1359	struct dc_link *link = NULL;
1360	struct drm_device *dev = connector->dev;
1361	struct amdgpu_device *adev = drm_to_adev(dev);
1362	enum dc_connection_type new_connection_type = dc_connection_none;
1363	char *wr_buf = NULL;
1364	uint32_t wr_buf_size = 42;
1365	int max_param_num = 1;
1366	long param[1] = {0};
1367	uint8_t param_nums = 0;
1368	bool ret = false;
1369
1370	if (!aconnector || !aconnector->dc_link)
1371		return -EINVAL;
1372
1373	if (size == 0)
1374		return -EINVAL;
1375
1376	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1377
1378	if (!wr_buf) {
1379		DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1380		return -ENOSPC;
1381	}
1382
1383	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1384						(long *)param, buf,
1385						max_param_num,
1386						&param_nums)) {
1387		kfree(wr_buf);
1388		return -EINVAL;
1389	}
1390
1391	kfree(wr_buf);
1392
1393	if (param_nums <= 0) {
1394		DRM_DEBUG_DRIVER("user data not be read\n");
1395		return -EINVAL;
1396	}
1397
1398	mutex_lock(&aconnector->hpd_lock);
1399
1400	/* Don't support for mst end device*/
1401	if (aconnector->mst_root) {
1402		mutex_unlock(&aconnector->hpd_lock);
1403		return -EINVAL;
1404	}
1405
1406	if (param[0] == 1) {
1407
1408		if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type) &&
1409			new_connection_type != dc_connection_none)
1410			goto unlock;
1411
1412		mutex_lock(&adev->dm.dc_lock);
1413		ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
1414		mutex_unlock(&adev->dm.dc_lock);
1415
1416		if (!ret)
1417			goto unlock;
1418
1419		amdgpu_dm_update_connector_after_detect(aconnector);
1420
1421		drm_modeset_lock_all(dev);
1422		dm_restore_drm_connector_state(dev, connector);
1423		drm_modeset_unlock_all(dev);
1424
1425		drm_kms_helper_connector_hotplug_event(connector);
1426	} else if (param[0] == 0) {
1427		if (!aconnector->dc_link)
1428			goto unlock;
1429
1430		link = aconnector->dc_link;
1431
1432		if (link->local_sink) {
1433			dc_sink_release(link->local_sink);
1434			link->local_sink = NULL;
1435		}
1436
1437		link->dpcd_sink_count = 0;
1438		link->type = dc_connection_none;
1439		link->dongle_max_pix_clk = 0;
1440
1441		amdgpu_dm_update_connector_after_detect(aconnector);
1442
1443		/* If the aconnector is the root node in mst topology */
1444		if (aconnector->mst_mgr.mst_state == true)
1445			dc_link_reset_cur_dp_mst_topology(link);
1446
1447		drm_modeset_lock_all(dev);
1448		dm_restore_drm_connector_state(dev, connector);
1449		drm_modeset_unlock_all(dev);
1450
1451		drm_kms_helper_connector_hotplug_event(connector);
1452	}
1453
1454unlock:
1455	mutex_unlock(&aconnector->hpd_lock);
1456
1457	return size;
1458}
1459
1460/* function: read DSC status on the connector
1461 *
1462 * The read function: dp_dsc_clock_en_read
1463 * returns current status of DSC clock on the connector.
1464 * The return is a boolean flag: 1 or 0.
1465 *
1466 * Access it with the following command (you need to specify
1467 * connector like DP-1):
1468 *
1469 *	cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1470 *
1471 * Expected output:
1472 * 1 - means that DSC is currently enabled
1473 * 0 - means that DSC is disabled
1474 */
1475static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
1476				    size_t size, loff_t *pos)
1477{
1478	char *rd_buf = NULL;
1479	char *rd_buf_ptr = NULL;
1480	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1481	struct display_stream_compressor *dsc;
1482	struct dcn_dsc_state dsc_state = {0};
1483	const uint32_t rd_buf_size = 10;
1484	struct pipe_ctx *pipe_ctx;
1485	ssize_t result = 0;
1486	int i, r, str_len = 10;
1487
1488	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1489
1490	if (!rd_buf)
1491		return -ENOMEM;
1492
1493	rd_buf_ptr = rd_buf;
1494
1495	for (i = 0; i < MAX_PIPES; i++) {
1496		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1497		if (pipe_ctx->stream &&
1498		    pipe_ctx->stream->link == aconnector->dc_link &&
1499		    pipe_ctx->stream->sink &&
1500		    pipe_ctx->stream->sink == aconnector->dc_sink)
1501			break;
1502	}
1503
1504	dsc = pipe_ctx->stream_res.dsc;
1505	if (dsc)
1506		dsc->funcs->dsc_read_state(dsc, &dsc_state);
1507
1508	snprintf(rd_buf_ptr, str_len,
1509		"%d\n",
1510		dsc_state.dsc_clock_en);
1511	rd_buf_ptr += str_len;
1512
1513	while (size) {
1514		if (*pos >= rd_buf_size)
1515			break;
1516
1517		r = put_user(*(rd_buf + result), buf);
1518		if (r) {
1519			kfree(rd_buf);
1520			return r; /* r = -EFAULT */
1521		}
1522
1523		buf += 1;
1524		size -= 1;
1525		*pos += 1;
1526		result += 1;
1527	}
1528
1529	kfree(rd_buf);
1530	return result;
1531}
1532
1533/* function: write force DSC on the connector
1534 *
1535 * The write function: dp_dsc_clock_en_write
1536 * enables to force DSC on the connector.
1537 * User can write to either force enable or force disable DSC
1538 * on the next modeset or set it to driver default
1539 *
1540 * Accepted inputs:
1541 * 0 - default DSC enablement policy
1542 * 1 - force enable DSC on the connector
1543 * 2 - force disable DSC on the connector (might cause fail in atomic_check)
1544 *
1545 * Writing DSC settings is done with the following command:
1546 * - To force enable DSC (you need to specify
1547 * connector like DP-1):
1548 *
1549 *	echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1550 *
1551 * - To return to default state set the flag to zero and
1552 * let driver deal with DSC automatically
1553 * (you need to specify connector like DP-1):
1554 *
1555 *	echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1556 *
1557 */
1558static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
1559				     size_t size, loff_t *pos)
1560{
1561	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1562	struct drm_connector *connector = &aconnector->base;
1563	struct drm_device *dev = connector->dev;
1564	struct drm_crtc *crtc = NULL;
1565	struct dm_crtc_state *dm_crtc_state = NULL;
1566	struct pipe_ctx *pipe_ctx;
1567	int i;
1568	char *wr_buf = NULL;
1569	uint32_t wr_buf_size = 42;
1570	int max_param_num = 1;
1571	long param[1] = {0};
1572	uint8_t param_nums = 0;
1573
1574	if (size == 0)
1575		return -EINVAL;
1576
1577	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1578
1579	if (!wr_buf) {
1580		DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1581		return -ENOSPC;
1582	}
1583
1584	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1585					    (long *)param, buf,
1586					    max_param_num,
1587					    &param_nums)) {
1588		kfree(wr_buf);
1589		return -EINVAL;
1590	}
1591
1592	if (param_nums <= 0) {
1593		DRM_DEBUG_DRIVER("user data not be read\n");
1594		kfree(wr_buf);
1595		return -EINVAL;
1596	}
1597
1598	for (i = 0; i < MAX_PIPES; i++) {
1599		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1600		if (pipe_ctx->stream &&
1601		    pipe_ctx->stream->link == aconnector->dc_link &&
1602		    pipe_ctx->stream->sink &&
1603		    pipe_ctx->stream->sink == aconnector->dc_sink)
1604			break;
1605	}
1606
1607	if (!pipe_ctx->stream)
1608		goto done;
1609
1610	// Get CRTC state
1611	mutex_lock(&dev->mode_config.mutex);
1612	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1613
1614	if (connector->state == NULL)
1615		goto unlock;
1616
1617	crtc = connector->state->crtc;
1618	if (crtc == NULL)
1619		goto unlock;
1620
1621	drm_modeset_lock(&crtc->mutex, NULL);
1622	if (crtc->state == NULL)
1623		goto unlock;
1624
1625	dm_crtc_state = to_dm_crtc_state(crtc->state);
1626	if (dm_crtc_state->stream == NULL)
1627		goto unlock;
1628
1629	if (param[0] == 1)
1630		aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE;
1631	else if (param[0] == 2)
1632		aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE;
1633	else
1634		aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT;
1635
1636	dm_crtc_state->dsc_force_changed = true;
1637
1638unlock:
1639	if (crtc)
1640		drm_modeset_unlock(&crtc->mutex);
1641	drm_modeset_unlock(&dev->mode_config.connection_mutex);
1642	mutex_unlock(&dev->mode_config.mutex);
1643
1644done:
1645	kfree(wr_buf);
1646	return size;
1647}
1648
1649/* function: read DSC slice width parameter on the connector
1650 *
1651 * The read function: dp_dsc_slice_width_read
1652 * returns dsc slice width used in the current configuration
1653 * The return is an integer: 0 or other positive number
1654 *
1655 * Access the status with the following command:
1656 *
1657 *	cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1658 *
1659 * 0 - means that DSC is disabled
1660 *
1661 * Any other number more than zero represents the
1662 * slice width currently used by DSC in pixels
1663 *
1664 */
1665static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
1666				    size_t size, loff_t *pos)
1667{
1668	char *rd_buf = NULL;
1669	char *rd_buf_ptr = NULL;
1670	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1671	struct display_stream_compressor *dsc;
1672	struct dcn_dsc_state dsc_state = {0};
1673	const uint32_t rd_buf_size = 100;
1674	struct pipe_ctx *pipe_ctx;
1675	ssize_t result = 0;
1676	int i, r, str_len = 30;
1677
1678	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1679
1680	if (!rd_buf)
1681		return -ENOMEM;
1682
1683	rd_buf_ptr = rd_buf;
1684
1685	for (i = 0; i < MAX_PIPES; i++) {
1686		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1687		if (pipe_ctx->stream &&
1688		    pipe_ctx->stream->link == aconnector->dc_link &&
1689		    pipe_ctx->stream->sink &&
1690		    pipe_ctx->stream->sink == aconnector->dc_sink)
1691			break;
1692	}
1693
1694	dsc = pipe_ctx->stream_res.dsc;
1695	if (dsc)
1696		dsc->funcs->dsc_read_state(dsc, &dsc_state);
1697
1698	snprintf(rd_buf_ptr, str_len,
1699		"%d\n",
1700		dsc_state.dsc_slice_width);
1701	rd_buf_ptr += str_len;
1702
1703	while (size) {
1704		if (*pos >= rd_buf_size)
1705			break;
1706
1707		r = put_user(*(rd_buf + result), buf);
1708		if (r) {
1709			kfree(rd_buf);
1710			return r; /* r = -EFAULT */
1711		}
1712
1713		buf += 1;
1714		size -= 1;
1715		*pos += 1;
1716		result += 1;
1717	}
1718
1719	kfree(rd_buf);
1720	return result;
1721}
1722
1723/* function: write DSC slice width parameter
1724 *
1725 * The write function: dp_dsc_slice_width_write
1726 * overwrites automatically generated DSC configuration
1727 * of slice width.
1728 *
1729 * The user has to write the slice width divisible by the
1730 * picture width.
1731 *
1732 * Also the user has to write width in hexidecimal
1733 * rather than in decimal.
1734 *
1735 * Writing DSC settings is done with the following command:
1736 * - To force overwrite slice width: (example sets to 1920 pixels)
1737 *
1738 *	echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1739 *
1740 *  - To stop overwriting and let driver find the optimal size,
1741 * set the width to zero:
1742 *
1743 *	echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1744 *
1745 */
1746static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
1747				     size_t size, loff_t *pos)
1748{
1749	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1750	struct pipe_ctx *pipe_ctx;
1751	struct drm_connector *connector = &aconnector->base;
1752	struct drm_device *dev = connector->dev;
1753	struct drm_crtc *crtc = NULL;
1754	struct dm_crtc_state *dm_crtc_state = NULL;
1755	int i;
1756	char *wr_buf = NULL;
1757	uint32_t wr_buf_size = 42;
1758	int max_param_num = 1;
1759	long param[1] = {0};
1760	uint8_t param_nums = 0;
1761
1762	if (size == 0)
1763		return -EINVAL;
1764
1765	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1766
1767	if (!wr_buf) {
1768		DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1769		return -ENOSPC;
1770	}
1771
1772	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1773					    (long *)param, buf,
1774					    max_param_num,
1775					    &param_nums)) {
1776		kfree(wr_buf);
1777		return -EINVAL;
1778	}
1779
1780	if (param_nums <= 0) {
1781		DRM_DEBUG_DRIVER("user data not be read\n");
1782		kfree(wr_buf);
1783		return -EINVAL;
1784	}
1785
1786	for (i = 0; i < MAX_PIPES; i++) {
1787		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1788		if (pipe_ctx->stream &&
1789		    pipe_ctx->stream->link == aconnector->dc_link &&
1790		    pipe_ctx->stream->sink &&
1791		    pipe_ctx->stream->sink == aconnector->dc_sink)
1792			break;
1793	}
1794
1795	if (!pipe_ctx->stream)
1796		goto done;
1797
1798	// Safely get CRTC state
1799	mutex_lock(&dev->mode_config.mutex);
1800	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1801
1802	if (connector->state == NULL)
1803		goto unlock;
1804
1805	crtc = connector->state->crtc;
1806	if (crtc == NULL)
1807		goto unlock;
1808
1809	drm_modeset_lock(&crtc->mutex, NULL);
1810	if (crtc->state == NULL)
1811		goto unlock;
1812
1813	dm_crtc_state = to_dm_crtc_state(crtc->state);
1814	if (dm_crtc_state->stream == NULL)
1815		goto unlock;
1816
1817	if (param[0] > 0)
1818		aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP(
1819					pipe_ctx->stream->timing.h_addressable,
1820					param[0]);
1821	else
1822		aconnector->dsc_settings.dsc_num_slices_h = 0;
1823
1824	dm_crtc_state->dsc_force_changed = true;
1825
1826unlock:
1827	if (crtc)
1828		drm_modeset_unlock(&crtc->mutex);
1829	drm_modeset_unlock(&dev->mode_config.connection_mutex);
1830	mutex_unlock(&dev->mode_config.mutex);
1831
1832done:
1833	kfree(wr_buf);
1834	return size;
1835}
1836
1837/* function: read DSC slice height parameter on the connector
1838 *
1839 * The read function: dp_dsc_slice_height_read
1840 * returns dsc slice height used in the current configuration
1841 * The return is an integer: 0 or other positive number
1842 *
1843 * Access the status with the following command:
1844 *
1845 *	cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1846 *
1847 * 0 - means that DSC is disabled
1848 *
1849 * Any other number more than zero represents the
1850 * slice height currently used by DSC in pixels
1851 *
1852 */
1853static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
1854				    size_t size, loff_t *pos)
1855{
1856	char *rd_buf = NULL;
1857	char *rd_buf_ptr = NULL;
1858	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1859	struct display_stream_compressor *dsc;
1860	struct dcn_dsc_state dsc_state = {0};
1861	const uint32_t rd_buf_size = 100;
1862	struct pipe_ctx *pipe_ctx;
1863	ssize_t result = 0;
1864	int i, r, str_len = 30;
1865
1866	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1867
1868	if (!rd_buf)
1869		return -ENOMEM;
1870
1871	rd_buf_ptr = rd_buf;
1872
1873	for (i = 0; i < MAX_PIPES; i++) {
1874		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1875		if (pipe_ctx->stream &&
1876		    pipe_ctx->stream->link == aconnector->dc_link &&
1877		    pipe_ctx->stream->sink &&
1878		    pipe_ctx->stream->sink == aconnector->dc_sink)
1879			break;
1880	}
1881
1882	dsc = pipe_ctx->stream_res.dsc;
1883	if (dsc)
1884		dsc->funcs->dsc_read_state(dsc, &dsc_state);
1885
1886	snprintf(rd_buf_ptr, str_len,
1887		"%d\n",
1888		dsc_state.dsc_slice_height);
1889	rd_buf_ptr += str_len;
1890
1891	while (size) {
1892		if (*pos >= rd_buf_size)
1893			break;
1894
1895		r = put_user(*(rd_buf + result), buf);
1896		if (r) {
1897			kfree(rd_buf);
1898			return r; /* r = -EFAULT */
1899		}
1900
1901		buf += 1;
1902		size -= 1;
1903		*pos += 1;
1904		result += 1;
1905	}
1906
1907	kfree(rd_buf);
1908	return result;
1909}
1910
1911/* function: write DSC slice height parameter
1912 *
1913 * The write function: dp_dsc_slice_height_write
1914 * overwrites automatically generated DSC configuration
1915 * of slice height.
1916 *
1917 * The user has to write the slice height divisible by the
1918 * picture height.
1919 *
1920 * Also the user has to write height in hexidecimal
1921 * rather than in decimal.
1922 *
1923 * Writing DSC settings is done with the following command:
1924 * - To force overwrite slice height (example sets to 128 pixels):
1925 *
1926 *	echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1927 *
1928 *  - To stop overwriting and let driver find the optimal size,
1929 * set the height to zero:
1930 *
1931 *	echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1932 *
1933 */
1934static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
1935				     size_t size, loff_t *pos)
1936{
1937	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1938	struct drm_connector *connector = &aconnector->base;
1939	struct drm_device *dev = connector->dev;
1940	struct drm_crtc *crtc = NULL;
1941	struct dm_crtc_state *dm_crtc_state = NULL;
1942	struct pipe_ctx *pipe_ctx;
1943	int i;
1944	char *wr_buf = NULL;
1945	uint32_t wr_buf_size = 42;
1946	int max_param_num = 1;
1947	uint8_t param_nums = 0;
1948	long param[1] = {0};
1949
1950	if (size == 0)
1951		return -EINVAL;
1952
1953	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1954
1955	if (!wr_buf) {
1956		DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1957		return -ENOSPC;
1958	}
1959
1960	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1961					    (long *)param, buf,
1962					    max_param_num,
1963					    &param_nums)) {
1964		kfree(wr_buf);
1965		return -EINVAL;
1966	}
1967
1968	if (param_nums <= 0) {
1969		DRM_DEBUG_DRIVER("user data not be read\n");
1970		kfree(wr_buf);
1971		return -EINVAL;
1972	}
1973
1974	for (i = 0; i < MAX_PIPES; i++) {
1975		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1976		if (pipe_ctx->stream &&
1977		    pipe_ctx->stream->link == aconnector->dc_link &&
1978		    pipe_ctx->stream->sink &&
1979		    pipe_ctx->stream->sink == aconnector->dc_sink)
1980			break;
1981	}
1982
1983	if (!pipe_ctx->stream)
1984		goto done;
1985
1986	// Get CRTC state
1987	mutex_lock(&dev->mode_config.mutex);
1988	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1989
1990	if (connector->state == NULL)
1991		goto unlock;
1992
1993	crtc = connector->state->crtc;
1994	if (crtc == NULL)
1995		goto unlock;
1996
1997	drm_modeset_lock(&crtc->mutex, NULL);
1998	if (crtc->state == NULL)
1999		goto unlock;
2000
2001	dm_crtc_state = to_dm_crtc_state(crtc->state);
2002	if (dm_crtc_state->stream == NULL)
2003		goto unlock;
2004
2005	if (param[0] > 0)
2006		aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP(
2007					pipe_ctx->stream->timing.v_addressable,
2008					param[0]);
2009	else
2010		aconnector->dsc_settings.dsc_num_slices_v = 0;
2011
2012	dm_crtc_state->dsc_force_changed = true;
2013
2014unlock:
2015	if (crtc)
2016		drm_modeset_unlock(&crtc->mutex);
2017	drm_modeset_unlock(&dev->mode_config.connection_mutex);
2018	mutex_unlock(&dev->mode_config.mutex);
2019
2020done:
2021	kfree(wr_buf);
2022	return size;
2023}
2024
2025/* function: read DSC target rate on the connector in bits per pixel
2026 *
2027 * The read function: dp_dsc_bits_per_pixel_read
2028 * returns target rate of compression in bits per pixel
2029 * The return is an integer: 0 or other positive integer
2030 *
2031 * Access it with the following command:
2032 *
2033 *	cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2034 *
2035 *  0 - means that DSC is disabled
2036 */
2037static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
2038				    size_t size, loff_t *pos)
2039{
2040	char *rd_buf = NULL;
2041	char *rd_buf_ptr = NULL;
2042	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2043	struct display_stream_compressor *dsc;
2044	struct dcn_dsc_state dsc_state = {0};
2045	const uint32_t rd_buf_size = 100;
2046	struct pipe_ctx *pipe_ctx;
2047	ssize_t result = 0;
2048	int i, r, str_len = 30;
2049
2050	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2051
2052	if (!rd_buf)
2053		return -ENOMEM;
2054
2055	rd_buf_ptr = rd_buf;
2056
2057	for (i = 0; i < MAX_PIPES; i++) {
2058		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2059		if (pipe_ctx->stream &&
2060		    pipe_ctx->stream->link == aconnector->dc_link &&
2061		    pipe_ctx->stream->sink &&
2062		    pipe_ctx->stream->sink == aconnector->dc_sink)
2063			break;
2064	}
2065
2066	dsc = pipe_ctx->stream_res.dsc;
2067	if (dsc)
2068		dsc->funcs->dsc_read_state(dsc, &dsc_state);
2069
2070	snprintf(rd_buf_ptr, str_len,
2071		"%d\n",
2072		dsc_state.dsc_bits_per_pixel);
2073	rd_buf_ptr += str_len;
2074
2075	while (size) {
2076		if (*pos >= rd_buf_size)
2077			break;
2078
2079		r = put_user(*(rd_buf + result), buf);
2080		if (r) {
2081			kfree(rd_buf);
2082			return r; /* r = -EFAULT */
2083		}
2084
2085		buf += 1;
2086		size -= 1;
2087		*pos += 1;
2088		result += 1;
2089	}
2090
2091	kfree(rd_buf);
2092	return result;
2093}
2094
2095/* function: write DSC target rate in bits per pixel
2096 *
2097 * The write function: dp_dsc_bits_per_pixel_write
2098 * overwrites automatically generated DSC configuration
2099 * of DSC target bit rate.
2100 *
2101 * Also the user has to write bpp in hexidecimal
2102 * rather than in decimal.
2103 *
2104 * Writing DSC settings is done with the following command:
2105 * - To force overwrite rate (example sets to 256 bpp x 1/16):
2106 *
2107 *	echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2108 *
2109 *  - To stop overwriting and let driver find the optimal rate,
2110 * set the rate to zero:
2111 *
2112 *	echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2113 *
2114 */
2115static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf,
2116				     size_t size, loff_t *pos)
2117{
2118	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2119	struct drm_connector *connector = &aconnector->base;
2120	struct drm_device *dev = connector->dev;
2121	struct drm_crtc *crtc = NULL;
2122	struct dm_crtc_state *dm_crtc_state = NULL;
2123	struct pipe_ctx *pipe_ctx;
2124	int i;
2125	char *wr_buf = NULL;
2126	uint32_t wr_buf_size = 42;
2127	int max_param_num = 1;
2128	uint8_t param_nums = 0;
2129	long param[1] = {0};
2130
2131	if (size == 0)
2132		return -EINVAL;
2133
2134	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2135
2136	if (!wr_buf) {
2137		DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2138		return -ENOSPC;
2139	}
2140
2141	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2142					    (long *)param, buf,
2143					    max_param_num,
2144					    &param_nums)) {
2145		kfree(wr_buf);
2146		return -EINVAL;
2147	}
2148
2149	if (param_nums <= 0) {
2150		DRM_DEBUG_DRIVER("user data not be read\n");
2151		kfree(wr_buf);
2152		return -EINVAL;
2153	}
2154
2155	for (i = 0; i < MAX_PIPES; i++) {
2156		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2157		if (pipe_ctx->stream &&
2158		    pipe_ctx->stream->link == aconnector->dc_link &&
2159		    pipe_ctx->stream->sink &&
2160		    pipe_ctx->stream->sink == aconnector->dc_sink)
2161			break;
2162	}
2163
2164	if (!pipe_ctx->stream)
2165		goto done;
2166
2167	// Get CRTC state
2168	mutex_lock(&dev->mode_config.mutex);
2169	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2170
2171	if (connector->state == NULL)
2172		goto unlock;
2173
2174	crtc = connector->state->crtc;
2175	if (crtc == NULL)
2176		goto unlock;
2177
2178	drm_modeset_lock(&crtc->mutex, NULL);
2179	if (crtc->state == NULL)
2180		goto unlock;
2181
2182	dm_crtc_state = to_dm_crtc_state(crtc->state);
2183	if (dm_crtc_state->stream == NULL)
2184		goto unlock;
2185
2186	aconnector->dsc_settings.dsc_bits_per_pixel = param[0];
2187
2188	dm_crtc_state->dsc_force_changed = true;
2189
2190unlock:
2191	if (crtc)
2192		drm_modeset_unlock(&crtc->mutex);
2193	drm_modeset_unlock(&dev->mode_config.connection_mutex);
2194	mutex_unlock(&dev->mode_config.mutex);
2195
2196done:
2197	kfree(wr_buf);
2198	return size;
2199}
2200
2201/* function: read DSC picture width parameter on the connector
2202 *
2203 * The read function: dp_dsc_pic_width_read
2204 * returns dsc picture width used in the current configuration
2205 * It is the same as h_addressable of the current
2206 * display's timing
2207 * The return is an integer: 0 or other positive integer
2208 * If 0 then DSC is disabled.
2209 *
2210 * Access it with the following command:
2211 *
2212 *	cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width
2213 *
2214 * 0 - means that DSC is disabled
2215 */
2216static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
2217				    size_t size, loff_t *pos)
2218{
2219	char *rd_buf = NULL;
2220	char *rd_buf_ptr = NULL;
2221	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2222	struct display_stream_compressor *dsc;
2223	struct dcn_dsc_state dsc_state = {0};
2224	const uint32_t rd_buf_size = 100;
2225	struct pipe_ctx *pipe_ctx;
2226	ssize_t result = 0;
2227	int i, r, str_len = 30;
2228
2229	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2230
2231	if (!rd_buf)
2232		return -ENOMEM;
2233
2234	rd_buf_ptr = rd_buf;
2235
2236	for (i = 0; i < MAX_PIPES; i++) {
2237		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2238		if (pipe_ctx->stream &&
2239		    pipe_ctx->stream->link == aconnector->dc_link &&
2240		    pipe_ctx->stream->sink &&
2241		    pipe_ctx->stream->sink == aconnector->dc_sink)
2242			break;
2243	}
2244
2245	dsc = pipe_ctx->stream_res.dsc;
2246	if (dsc)
2247		dsc->funcs->dsc_read_state(dsc, &dsc_state);
2248
2249	snprintf(rd_buf_ptr, str_len,
2250		"%d\n",
2251		dsc_state.dsc_pic_width);
2252	rd_buf_ptr += str_len;
2253
2254	while (size) {
2255		if (*pos >= rd_buf_size)
2256			break;
2257
2258		r = put_user(*(rd_buf + result), buf);
2259		if (r) {
2260			kfree(rd_buf);
2261			return r; /* r = -EFAULT */
2262		}
2263
2264		buf += 1;
2265		size -= 1;
2266		*pos += 1;
2267		result += 1;
2268	}
2269
2270	kfree(rd_buf);
2271	return result;
2272}
2273
2274static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
2275				    size_t size, loff_t *pos)
2276{
2277	char *rd_buf = NULL;
2278	char *rd_buf_ptr = NULL;
2279	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2280	struct display_stream_compressor *dsc;
2281	struct dcn_dsc_state dsc_state = {0};
2282	const uint32_t rd_buf_size = 100;
2283	struct pipe_ctx *pipe_ctx;
2284	ssize_t result = 0;
2285	int i, r, str_len = 30;
2286
2287	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2288
2289	if (!rd_buf)
2290		return -ENOMEM;
2291
2292	rd_buf_ptr = rd_buf;
2293
2294	for (i = 0; i < MAX_PIPES; i++) {
2295		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2296		if (pipe_ctx->stream &&
2297		    pipe_ctx->stream->link == aconnector->dc_link &&
2298		    pipe_ctx->stream->sink &&
2299		    pipe_ctx->stream->sink == aconnector->dc_sink)
2300			break;
2301	}
2302
2303	dsc = pipe_ctx->stream_res.dsc;
2304	if (dsc)
2305		dsc->funcs->dsc_read_state(dsc, &dsc_state);
2306
2307	snprintf(rd_buf_ptr, str_len,
2308		"%d\n",
2309		dsc_state.dsc_pic_height);
2310	rd_buf_ptr += str_len;
2311
2312	while (size) {
2313		if (*pos >= rd_buf_size)
2314			break;
2315
2316		r = put_user(*(rd_buf + result), buf);
2317		if (r) {
2318			kfree(rd_buf);
2319			return r; /* r = -EFAULT */
2320		}
2321
2322		buf += 1;
2323		size -= 1;
2324		*pos += 1;
2325		result += 1;
2326	}
2327
2328	kfree(rd_buf);
2329	return result;
2330}
2331
2332/* function: read DSC chunk size parameter on the connector
2333 *
2334 * The read function: dp_dsc_chunk_size_read
2335 * returns dsc chunk size set in the current configuration
2336 * The value is calculated automatically by DSC code
2337 * and depends on slice parameters and bpp target rate
2338 * The return is an integer: 0 or other positive integer
2339 * If 0 then DSC is disabled.
2340 *
2341 * Access it with the following command:
2342 *
2343 *	cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size
2344 *
2345 * 0 - means that DSC is disabled
2346 */
2347static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
2348				    size_t size, loff_t *pos)
2349{
2350	char *rd_buf = NULL;
2351	char *rd_buf_ptr = NULL;
2352	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2353	struct display_stream_compressor *dsc;
2354	struct dcn_dsc_state dsc_state = {0};
2355	const uint32_t rd_buf_size = 100;
2356	struct pipe_ctx *pipe_ctx;
2357	ssize_t result = 0;
2358	int i, r, str_len = 30;
2359
2360	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2361
2362	if (!rd_buf)
2363		return -ENOMEM;
2364
2365	rd_buf_ptr = rd_buf;
2366
2367	for (i = 0; i < MAX_PIPES; i++) {
2368		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2369		if (pipe_ctx->stream &&
2370		    pipe_ctx->stream->link == aconnector->dc_link &&
2371		    pipe_ctx->stream->sink &&
2372		    pipe_ctx->stream->sink == aconnector->dc_sink)
2373			break;
2374	}
2375
2376	dsc = pipe_ctx->stream_res.dsc;
2377	if (dsc)
2378		dsc->funcs->dsc_read_state(dsc, &dsc_state);
2379
2380	snprintf(rd_buf_ptr, str_len,
2381		"%d\n",
2382		dsc_state.dsc_chunk_size);
2383	rd_buf_ptr += str_len;
2384
2385	while (size) {
2386		if (*pos >= rd_buf_size)
2387			break;
2388
2389		r = put_user(*(rd_buf + result), buf);
2390		if (r) {
2391			kfree(rd_buf);
2392			return r; /* r = -EFAULT */
2393		}
2394
2395		buf += 1;
2396		size -= 1;
2397		*pos += 1;
2398		result += 1;
2399	}
2400
2401	kfree(rd_buf);
2402	return result;
2403}
2404
2405/* function: read DSC slice bpg offset on the connector
2406 *
2407 * The read function: dp_dsc_slice_bpg_offset_read
2408 * returns dsc bpg slice offset set in the current configuration
2409 * The value is calculated automatically by DSC code
2410 * and depends on slice parameters and bpp target rate
2411 * The return is an integer: 0 or other positive integer
2412 * If 0 then DSC is disabled.
2413 *
2414 * Access it with the following command:
2415 *
2416 *	cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset
2417 *
2418 * 0 - means that DSC is disabled
2419 */
2420static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
2421				    size_t size, loff_t *pos)
2422{
2423	char *rd_buf = NULL;
2424	char *rd_buf_ptr = NULL;
2425	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2426	struct display_stream_compressor *dsc;
2427	struct dcn_dsc_state dsc_state = {0};
2428	const uint32_t rd_buf_size = 100;
2429	struct pipe_ctx *pipe_ctx;
2430	ssize_t result = 0;
2431	int i, r, str_len = 30;
2432
2433	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2434
2435	if (!rd_buf)
2436		return -ENOMEM;
2437
2438	rd_buf_ptr = rd_buf;
2439
2440	for (i = 0; i < MAX_PIPES; i++) {
2441		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2442		if (pipe_ctx->stream &&
2443		    pipe_ctx->stream->link == aconnector->dc_link &&
2444		    pipe_ctx->stream->sink &&
2445		    pipe_ctx->stream->sink == aconnector->dc_sink)
2446			break;
2447	}
2448
2449	dsc = pipe_ctx->stream_res.dsc;
2450	if (dsc)
2451		dsc->funcs->dsc_read_state(dsc, &dsc_state);
2452
2453	snprintf(rd_buf_ptr, str_len,
2454		"%d\n",
2455		dsc_state.dsc_slice_bpg_offset);
2456	rd_buf_ptr += str_len;
2457
2458	while (size) {
2459		if (*pos >= rd_buf_size)
2460			break;
2461
2462		r = put_user(*(rd_buf + result), buf);
2463		if (r) {
2464			kfree(rd_buf);
2465			return r; /* r = -EFAULT */
2466		}
2467
2468		buf += 1;
2469		size -= 1;
2470		*pos += 1;
2471		result += 1;
2472	}
2473
2474	kfree(rd_buf);
2475	return result;
2476}
2477
2478
2479/*
2480 * function description: Read max_requested_bpc property from the connector
2481 *
2482 * Access it with the following command:
2483 *
2484 *	cat /sys/kernel/debug/dri/0/DP-X/max_bpc
2485 *
2486 */
2487static ssize_t dp_max_bpc_read(struct file *f, char __user *buf,
2488		size_t size, loff_t *pos)
2489{
2490	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2491	struct drm_connector *connector = &aconnector->base;
2492	struct drm_device *dev = connector->dev;
2493	struct dm_connector_state *state;
2494	ssize_t result = 0;
2495	char *rd_buf = NULL;
2496	char *rd_buf_ptr = NULL;
2497	const uint32_t rd_buf_size = 10;
2498	int r;
2499
2500	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2501
2502	if (!rd_buf)
2503		return -ENOMEM;
2504
2505	mutex_lock(&dev->mode_config.mutex);
2506	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2507
2508	if (connector->state == NULL)
2509		goto unlock;
2510
2511	state = to_dm_connector_state(connector->state);
2512
2513	rd_buf_ptr = rd_buf;
2514	snprintf(rd_buf_ptr, rd_buf_size,
2515		"%u\n",
2516		state->base.max_requested_bpc);
2517
2518	while (size) {
2519		if (*pos >= rd_buf_size)
2520			break;
2521
2522		r = put_user(*(rd_buf + result), buf);
2523		if (r) {
2524			result = r; /* r = -EFAULT */
2525			goto unlock;
2526		}
2527		buf += 1;
2528		size -= 1;
2529		*pos += 1;
2530		result += 1;
2531	}
2532unlock:
2533	drm_modeset_unlock(&dev->mode_config.connection_mutex);
2534	mutex_unlock(&dev->mode_config.mutex);
2535	kfree(rd_buf);
2536	return result;
2537}
2538
2539
2540/*
2541 * function description: Set max_requested_bpc property on the connector
2542 *
2543 * This function will not force the input BPC on connector, it will only
2544 * change the max value. This is equivalent to setting max_bpc through
2545 * xrandr.
2546 *
2547 * The BPC value written must be >= 6 and <= 16. Values outside of this
2548 * range will result in errors.
2549 *
2550 * BPC values:
2551 *	0x6 - 6 BPC
2552 *	0x8 - 8 BPC
2553 *	0xa - 10 BPC
2554 *	0xc - 12 BPC
2555 *	0x10 - 16 BPC
2556 *
2557 * Write the max_bpc in the following way:
2558 *
2559 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc
2560 *
2561 */
2562static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf,
2563				     size_t size, loff_t *pos)
2564{
2565	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2566	struct drm_connector *connector = &aconnector->base;
2567	struct dm_connector_state *state;
2568	struct drm_device *dev = connector->dev;
2569	char *wr_buf = NULL;
2570	uint32_t wr_buf_size = 42;
2571	int max_param_num = 1;
2572	long param[1] = {0};
2573	uint8_t param_nums = 0;
2574
2575	if (size == 0)
2576		return -EINVAL;
2577
2578	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2579
2580	if (!wr_buf) {
2581		DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2582		return -ENOSPC;
2583	}
2584
2585	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2586					   (long *)param, buf,
2587					   max_param_num,
2588					   &param_nums)) {
2589		kfree(wr_buf);
2590		return -EINVAL;
2591	}
2592
2593	if (param_nums <= 0) {
2594		DRM_DEBUG_DRIVER("user data not be read\n");
2595		kfree(wr_buf);
2596		return -EINVAL;
2597	}
2598
2599	if (param[0] < 6 || param[0] > 16) {
2600		DRM_DEBUG_DRIVER("bad max_bpc value\n");
2601		kfree(wr_buf);
2602		return -EINVAL;
2603	}
2604
2605	mutex_lock(&dev->mode_config.mutex);
2606	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2607
2608	if (connector->state == NULL)
2609		goto unlock;
2610
2611	state = to_dm_connector_state(connector->state);
2612	state->base.max_requested_bpc = param[0];
2613unlock:
2614	drm_modeset_unlock(&dev->mode_config.connection_mutex);
2615	mutex_unlock(&dev->mode_config.mutex);
2616
2617	kfree(wr_buf);
2618	return size;
2619}
2620
2621/*
2622 * Backlight at this moment.  Read only.
2623 * As written to display, taking ABM and backlight lut into account.
2624 * Ranges from 0x0 to 0x10000 (= 100% PWM)
2625 *
2626 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight
2627 */
2628static int current_backlight_show(struct seq_file *m, void *unused)
2629{
2630	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2631	struct dc_link *link = aconnector->dc_link;
2632	unsigned int backlight;
2633
2634	backlight = dc_link_get_backlight_level(link);
2635	seq_printf(m, "0x%x\n", backlight);
2636
2637	return 0;
2638}
2639
2640/*
2641 * Backlight value that is being approached.  Read only.
2642 * As written to display, taking ABM and backlight lut into account.
2643 * Ranges from 0x0 to 0x10000 (= 100% PWM)
2644 *
2645 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight
2646 */
2647static int target_backlight_show(struct seq_file *m, void *unused)
2648{
2649	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2650	struct dc_link *link = aconnector->dc_link;
2651	unsigned int backlight;
2652
2653	backlight = dc_link_get_target_backlight_pwm(link);
2654	seq_printf(m, "0x%x\n", backlight);
2655
2656	return 0;
2657}
2658
2659/*
2660 * function description: Determine if the connector is mst connector
2661 *
2662 * This function helps to determine whether a connector is a mst connector.
2663 * - "root" stands for the root connector of the topology
2664 * - "branch" stands for branch device of the topology
2665 * - "end" stands for leaf node connector of the topology
2666 * - "no" stands for the connector is not a device of a mst topology
2667 * Access it with the following command:
2668 *
2669 *	cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector
2670 *
2671 */
2672static int dp_is_mst_connector_show(struct seq_file *m, void *unused)
2673{
2674	struct drm_connector *connector = m->private;
2675	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2676	struct drm_dp_mst_topology_mgr *mgr = NULL;
2677	struct drm_dp_mst_port *port = NULL;
2678	char *role = NULL;
2679
2680	mutex_lock(&aconnector->hpd_lock);
2681
2682	if (aconnector->mst_mgr.mst_state) {
2683		role = "root";
2684	} else if (aconnector->mst_root &&
2685		aconnector->mst_root->mst_mgr.mst_state) {
2686
2687		role = "end";
2688
2689		mgr = &aconnector->mst_root->mst_mgr;
2690		port = aconnector->mst_output_port;
2691
2692		drm_modeset_lock(&mgr->base.lock, NULL);
2693		if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING &&
2694			port->mcs)
2695			role = "branch";
2696		drm_modeset_unlock(&mgr->base.lock);
2697
2698	} else {
2699		role = "no";
2700	}
2701
2702	seq_printf(m, "%s\n", role);
2703
2704	mutex_unlock(&aconnector->hpd_lock);
2705
2706	return 0;
2707}
2708
2709/*
2710 * function description: Read out the mst progress status
2711 *
2712 * This function helps to determine the mst progress status of
2713 * a mst connector.
2714 *
2715 * Access it with the following command:
2716 *
2717 *	cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status
2718 *
2719 */
2720static int dp_mst_progress_status_show(struct seq_file *m, void *unused)
2721{
2722	struct drm_connector *connector = m->private;
2723	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2724	struct amdgpu_device *adev = drm_to_adev(connector->dev);
2725	int i;
2726
2727	mutex_lock(&aconnector->hpd_lock);
2728	mutex_lock(&adev->dm.dc_lock);
2729
2730	if (aconnector->mst_status == MST_STATUS_DEFAULT) {
2731		seq_puts(m, "disabled\n");
2732	} else {
2733		for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++)
2734			seq_printf(m, "%s:%s\n",
2735				mst_progress_status[i],
2736				aconnector->mst_status & BIT(i) ? "done" : "not_done");
2737	}
2738
2739	mutex_unlock(&adev->dm.dc_lock);
2740	mutex_unlock(&aconnector->hpd_lock);
2741
2742	return 0;
2743}
2744
2745/*
2746 * Reports whether the connected display is a USB4 DPIA tunneled display
2747 * Example usage: cat /sys/kernel/debug/dri/0/DP-8/is_dpia_link
2748 */
2749static int is_dpia_link_show(struct seq_file *m, void *data)
2750{
2751	struct drm_connector *connector = m->private;
2752	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2753	struct dc_link *link = aconnector->dc_link;
2754
2755	if (connector->status != connector_status_connected)
2756		return -ENODEV;
2757
2758	seq_printf(m, "%s\n", (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? "yes" :
2759				(link->ep_type == DISPLAY_ENDPOINT_PHY) ? "no" : "unknown");
2760
2761	return 0;
2762}
2763
2764DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);
2765DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
2766DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
2767DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
2768DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
2769DEFINE_SHOW_ATTRIBUTE(internal_display);
2770DEFINE_SHOW_ATTRIBUTE(odm_combine_segments);
2771DEFINE_SHOW_ATTRIBUTE(psr_capability);
2772DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector);
2773DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status);
2774DEFINE_SHOW_ATTRIBUTE(is_dpia_link);
2775
2776static const struct file_operations dp_dsc_clock_en_debugfs_fops = {
2777	.owner = THIS_MODULE,
2778	.read = dp_dsc_clock_en_read,
2779	.write = dp_dsc_clock_en_write,
2780	.llseek = default_llseek
2781};
2782
2783static const struct file_operations dp_dsc_slice_width_debugfs_fops = {
2784	.owner = THIS_MODULE,
2785	.read = dp_dsc_slice_width_read,
2786	.write = dp_dsc_slice_width_write,
2787	.llseek = default_llseek
2788};
2789
2790static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
2791	.owner = THIS_MODULE,
2792	.read = dp_dsc_slice_height_read,
2793	.write = dp_dsc_slice_height_write,
2794	.llseek = default_llseek
2795};
2796
2797static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = {
2798	.owner = THIS_MODULE,
2799	.read = dp_dsc_bits_per_pixel_read,
2800	.write = dp_dsc_bits_per_pixel_write,
2801	.llseek = default_llseek
2802};
2803
2804static const struct file_operations dp_dsc_pic_width_debugfs_fops = {
2805	.owner = THIS_MODULE,
2806	.read = dp_dsc_pic_width_read,
2807	.llseek = default_llseek
2808};
2809
2810static const struct file_operations dp_dsc_pic_height_debugfs_fops = {
2811	.owner = THIS_MODULE,
2812	.read = dp_dsc_pic_height_read,
2813	.llseek = default_llseek
2814};
2815
2816static const struct file_operations dp_dsc_chunk_size_debugfs_fops = {
2817	.owner = THIS_MODULE,
2818	.read = dp_dsc_chunk_size_read,
2819	.llseek = default_llseek
2820};
2821
2822static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = {
2823	.owner = THIS_MODULE,
2824	.read = dp_dsc_slice_bpg_offset_read,
2825	.llseek = default_llseek
2826};
2827
2828static const struct file_operations trigger_hotplug_debugfs_fops = {
2829	.owner = THIS_MODULE,
2830	.write = trigger_hotplug,
2831	.llseek = default_llseek
2832};
2833
2834static const struct file_operations dp_link_settings_debugfs_fops = {
2835	.owner = THIS_MODULE,
2836	.read = dp_link_settings_read,
2837	.write = dp_link_settings_write,
2838	.llseek = default_llseek
2839};
2840
2841static const struct file_operations dp_phy_settings_debugfs_fop = {
2842	.owner = THIS_MODULE,
2843	.read = dp_phy_settings_read,
2844	.write = dp_phy_settings_write,
2845	.llseek = default_llseek
2846};
2847
2848static const struct file_operations dp_phy_test_pattern_fops = {
2849	.owner = THIS_MODULE,
2850	.write = dp_phy_test_pattern_debugfs_write,
2851	.llseek = default_llseek
2852};
2853
2854static const struct file_operations sdp_message_fops = {
2855	.owner = THIS_MODULE,
2856	.write = dp_sdp_message_debugfs_write,
2857	.llseek = default_llseek
2858};
2859
2860static const struct file_operations dp_max_bpc_debugfs_fops = {
2861	.owner = THIS_MODULE,
2862	.read = dp_max_bpc_read,
2863	.write = dp_max_bpc_write,
2864	.llseek = default_llseek
2865};
2866
2867static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = {
2868	.owner = THIS_MODULE,
2869	.write = dp_dsc_passthrough_set,
2870	.llseek = default_llseek
2871};
2872
2873static const struct file_operations dp_mst_link_settings_debugfs_fops = {
2874	.owner = THIS_MODULE,
2875	.write = dp_mst_link_setting,
2876	.llseek = default_llseek
2877};
2878
2879static const struct {
2880	char *name;
2881	const struct file_operations *fops;
2882} dp_debugfs_entries[] = {
2883		{"link_settings", &dp_link_settings_debugfs_fops},
2884		{"phy_settings", &dp_phy_settings_debugfs_fop},
2885		{"lttpr_status", &dp_lttpr_status_fops},
2886		{"test_pattern", &dp_phy_test_pattern_fops},
2887		{"hdcp_sink_capability", &hdcp_sink_capability_fops},
2888		{"sdp_message", &sdp_message_fops},
2889		{"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops},
2890		{"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops},
2891		{"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops},
2892		{"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops},
2893		{"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops},
2894		{"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops},
2895		{"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
2896		{"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops},
2897		{"dp_dsc_fec_support", &dp_dsc_fec_support_fops},
2898		{"max_bpc", &dp_max_bpc_debugfs_fops},
2899		{"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops},
2900		{"is_mst_connector", &dp_is_mst_connector_fops},
2901		{"mst_progress_status", &dp_mst_progress_status_fops},
2902		{"is_dpia_link", &is_dpia_link_fops},
2903		{"mst_link_settings", &dp_mst_link_settings_debugfs_fops}
2904};
2905
2906static const struct {
2907	char *name;
2908	const struct file_operations *fops;
2909} hdmi_debugfs_entries[] = {
2910		{"hdcp_sink_capability", &hdcp_sink_capability_fops}
2911};
2912
2913/*
2914 * Force YUV420 output if available from the given mode
2915 */
2916static int force_yuv420_output_set(void *data, u64 val)
2917{
2918	struct amdgpu_dm_connector *connector = data;
2919
2920	connector->force_yuv420_output = (bool)val;
2921
2922	return 0;
2923}
2924
2925/*
2926 * Check if YUV420 is forced when available from the given mode
2927 */
2928static int force_yuv420_output_get(void *data, u64 *val)
2929{
2930	struct amdgpu_dm_connector *connector = data;
2931
2932	*val = connector->force_yuv420_output;
2933
2934	return 0;
2935}
2936
2937DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
2938			 force_yuv420_output_set, "%llu\n");
2939
2940/*
2941 *  Read PSR state
2942 */
2943static int psr_get(void *data, u64 *val)
2944{
2945	struct amdgpu_dm_connector *connector = data;
2946	struct dc_link *link = connector->dc_link;
2947	enum dc_psr_state state = PSR_STATE0;
2948
2949	dc_link_get_psr_state(link, &state);
2950
2951	*val = state;
2952
2953	return 0;
2954}
2955
2956/*
2957 *  Read PSR state residency
2958 */
2959static int psr_read_residency(void *data, u64 *val)
2960{
2961	struct amdgpu_dm_connector *connector = data;
2962	struct dc_link *link = connector->dc_link;
2963	u32 residency;
2964
2965	link->dc->link_srv->edp_get_psr_residency(link, &residency);
2966
2967	*val = (u64)residency;
2968
2969	return 0;
2970}
2971
2972/* read allow_edp_hotplug_detection */
2973static int allow_edp_hotplug_detection_get(void *data, u64 *val)
2974{
2975	struct amdgpu_dm_connector *aconnector = data;
2976	struct drm_connector *connector = &aconnector->base;
2977	struct drm_device *dev = connector->dev;
2978	struct amdgpu_device *adev = drm_to_adev(dev);
2979
2980	*val = adev->dm.dc->config.allow_edp_hotplug_detection;
2981
2982	return 0;
2983}
2984
2985/* set allow_edp_hotplug_detection */
2986static int allow_edp_hotplug_detection_set(void *data, u64 val)
2987{
2988	struct amdgpu_dm_connector *aconnector = data;
2989	struct drm_connector *connector = &aconnector->base;
2990	struct drm_device *dev = connector->dev;
2991	struct amdgpu_device *adev = drm_to_adev(dev);
2992
2993	adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val;
2994
2995	return 0;
2996}
2997
2998/* check if kernel disallow eDP enter psr state
2999 * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3000 * 0: allow edp enter psr; 1: disallow
3001 */
3002static int disallow_edp_enter_psr_get(void *data, u64 *val)
3003{
3004	struct amdgpu_dm_connector *aconnector = data;
3005
3006	*val = (u64) aconnector->disallow_edp_enter_psr;
3007	return 0;
3008}
3009
3010/* set kernel disallow eDP enter psr state
3011 * echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3012 * 0: allow edp enter psr; 1: disallow
3013 *
3014 * usage: test app read crc from PSR eDP rx.
3015 *
3016 * during kernel boot up, kernel write dpcd 0x170 = 5.
3017 * this notify eDP rx psr enable and let rx check crc.
3018 * rx fw will start checking crc for rx internal logic.
3019 * crc read count within dpcd 0x246 is not updated and
3020 * value is 0. when eDP tx driver wants to read rx crc
3021 * from dpcd 0x246, 0x270, read count 0 lead tx driver
3022 * timeout.
3023 *
3024 * to avoid this, we add this debugfs to let test app to disbable
3025 * rx crc checking for rx internal logic. then test app can read
3026 * non-zero crc read count.
3027 *
3028 * expected app sequence is as below:
3029 * 1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2.
3030 * 2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3031 * 3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but
3032 *    without dpcd 0x170 = 5.
3033 * 4. read crc from rx dpcd 0x270, 0x246, etc.
3034 * 5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr.
3035 *    this will let eDP back to normal with psr setup dpcd 0x170 = 5.
3036 */
3037static int disallow_edp_enter_psr_set(void *data, u64 val)
3038{
3039	struct amdgpu_dm_connector *aconnector = data;
3040
3041	aconnector->disallow_edp_enter_psr = val ? true : false;
3042	return 0;
3043}
3044
3045static int dmub_trace_mask_set(void *data, u64 val)
3046{
3047	struct amdgpu_device *adev = data;
3048	struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;
3049	enum dmub_gpint_command cmd;
3050	u64 mask = 0xffff;
3051	u8 shift = 0;
3052	u32 res;
3053	int i;
3054
3055	if (!srv->fw_version)
3056		return -EINVAL;
3057
3058	for (i = 0;  i < 4; i++) {
3059		res = (val & mask) >> shift;
3060
3061		switch (i) {
3062		case 0:
3063			cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0;
3064			break;
3065		case 1:
3066			cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1;
3067			break;
3068		case 2:
3069			cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2;
3070			break;
3071		case 3:
3072			cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3;
3073			break;
3074		}
3075
3076		if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, res, NULL, DM_DMUB_WAIT_TYPE_WAIT))
3077			return -EIO;
3078
3079		usleep_range(100, 1000);
3080
3081		mask <<= 16;
3082		shift += 16;
3083	}
3084
3085	return 0;
3086}
3087
3088static int dmub_trace_mask_show(void *data, u64 *val)
3089{
3090	enum dmub_gpint_command cmd = DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0;
3091	struct amdgpu_device *adev = data;
3092	struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;
3093	u8 shift = 0;
3094	u64 raw = 0;
3095	u64 res = 0;
3096	int i = 0;
3097
3098	if (!srv->fw_version)
3099		return -EINVAL;
3100
3101	while (i < 4) {
3102		uint32_t response;
3103
3104		if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, 0, &response, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
3105			return -EIO;
3106
3107		raw = response;
3108		usleep_range(100, 1000);
3109
3110		cmd++;
3111		res |= (raw << shift);
3112		shift += 16;
3113		i++;
3114	}
3115
3116	*val = res;
3117
3118	return 0;
3119}
3120
3121DEFINE_DEBUGFS_ATTRIBUTE(dmub_trace_mask_fops, dmub_trace_mask_show,
3122			 dmub_trace_mask_set, "0x%llx\n");
3123
3124/*
3125 * Set dmcub trace event IRQ enable or disable.
3126 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3127 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3128 */
3129static int dmcub_trace_event_state_set(void *data, u64 val)
3130{
3131	struct amdgpu_device *adev = data;
3132
3133	if (val == 1 || val == 0) {
3134		dc_dmub_trace_event_control(adev->dm.dc, val);
3135		adev->dm.dmcub_trace_event_en = (bool)val;
3136	} else
3137		return 0;
3138
3139	return 0;
3140}
3141
3142/*
3143 * The interface doesn't need get function, so it will return the
3144 * value of zero
3145 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3146 */
3147static int dmcub_trace_event_state_get(void *data, u64 *val)
3148{
3149	struct amdgpu_device *adev = data;
3150
3151	*val = adev->dm.dmcub_trace_event_en;
3152	return 0;
3153}
3154
3155DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get,
3156			 dmcub_trace_event_state_set, "%llu\n");
3157
3158DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
3159DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL,
3160			 "%llu\n");
3161
3162DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops,
3163			allow_edp_hotplug_detection_get,
3164			allow_edp_hotplug_detection_set, "%llu\n");
3165
3166DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops,
3167			disallow_edp_enter_psr_get,
3168			disallow_edp_enter_psr_set, "%llu\n");
3169
3170DEFINE_SHOW_ATTRIBUTE(current_backlight);
3171DEFINE_SHOW_ATTRIBUTE(target_backlight);
3172
3173static const struct {
3174	char *name;
3175	const struct file_operations *fops;
3176} connector_debugfs_entries[] = {
3177		{"force_yuv420_output", &force_yuv420_output_fops},
3178		{"trigger_hotplug", &trigger_hotplug_debugfs_fops},
3179		{"internal_display", &internal_display_fops},
3180		{"odm_combine_segments", &odm_combine_segments_fops}
3181};
3182
3183/*
3184 * Returns supported customized link rates by this eDP panel.
3185 * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting
3186 */
3187static int edp_ilr_show(struct seq_file *m, void *unused)
3188{
3189	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
3190	struct dc_link *link = aconnector->dc_link;
3191	uint8_t supported_link_rates[16];
3192	uint32_t link_rate_in_khz;
3193	uint32_t entry = 0;
3194	uint8_t dpcd_rev;
3195
3196	memset(supported_link_rates, 0, sizeof(supported_link_rates));
3197	dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES,
3198		supported_link_rates, sizeof(supported_link_rates));
3199
3200	dpcd_rev = link->dpcd_caps.dpcd_rev.raw;
3201
3202	if (dpcd_rev >= DP_DPCD_REV_13 &&
3203		(supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) {
3204
3205		for (entry = 0; entry < 16; entry += 2) {
3206			link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
3207										supported_link_rates[entry]) * 200;
3208			seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz);
3209		}
3210	} else {
3211		seq_puts(m, "ILR is not supported by this eDP panel.\n");
3212	}
3213
3214	return 0;
3215}
3216
3217/*
3218 * Set supported customized link rate to eDP panel.
3219 *
3220 * echo <lane_count>  <link_rate option> > ilr_setting
3221 *
3222 * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ...
3223 * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting
3224 * to set 4 lanes and 2.16 GHz
3225 */
3226static ssize_t edp_ilr_write(struct file *f, const char __user *buf,
3227				 size_t size, loff_t *pos)
3228{
3229	struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
3230	struct dc_link *link = connector->dc_link;
3231	struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
3232	struct dc *dc = (struct dc *)link->dc;
3233	struct dc_link_settings prefer_link_settings;
3234	char *wr_buf = NULL;
3235	const uint32_t wr_buf_size = 40;
3236	/* 0: lane_count; 1: link_rate */
3237	int max_param_num = 2;
3238	uint8_t param_nums = 0;
3239	long param[2];
3240	bool valid_input = true;
3241
3242	if (size == 0)
3243		return -EINVAL;
3244
3245	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
3246	if (!wr_buf)
3247		return -ENOMEM;
3248
3249	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
3250					   (long *)param, buf,
3251					   max_param_num,
3252					   &param_nums)) {
3253		kfree(wr_buf);
3254		return -EINVAL;
3255	}
3256
3257	if (param_nums <= 0) {
3258		kfree(wr_buf);
3259		return -EINVAL;
3260	}
3261
3262	switch (param[0]) {
3263	case LANE_COUNT_ONE:
3264	case LANE_COUNT_TWO:
3265	case LANE_COUNT_FOUR:
3266		break;
3267	default:
3268		valid_input = false;
3269		break;
3270	}
3271
3272	if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count)
3273		valid_input = false;
3274
3275	if (!valid_input) {
3276		kfree(wr_buf);
3277		DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n");
3278		prefer_link_settings.use_link_rate_set = false;
3279		mutex_lock(&adev->dm.dc_lock);
3280		dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
3281		mutex_unlock(&adev->dm.dc_lock);
3282		return size;
3283	}
3284
3285	/* save user force lane_count, link_rate to preferred settings
3286	 * spread spectrum will not be changed
3287	 */
3288	prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
3289	prefer_link_settings.lane_count = param[0];
3290	prefer_link_settings.use_link_rate_set = true;
3291	prefer_link_settings.link_rate_set = param[1];
3292	prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]];
3293
3294	mutex_lock(&adev->dm.dc_lock);
3295	dc_link_set_preferred_training_settings(dc, &prefer_link_settings,
3296						NULL, link, false);
3297	mutex_unlock(&adev->dm.dc_lock);
3298
3299	kfree(wr_buf);
3300	return size;
3301}
3302
3303static int edp_ilr_open(struct inode *inode, struct file *file)
3304{
3305	return single_open(file, edp_ilr_show, inode->i_private);
3306}
3307
3308static const struct file_operations edp_ilr_debugfs_fops = {
3309	.owner = THIS_MODULE,
3310	.open = edp_ilr_open,
3311	.read = seq_read,
3312	.llseek = seq_lseek,
3313	.release = single_release,
3314	.write = edp_ilr_write
3315};
3316
3317void connector_debugfs_init(struct amdgpu_dm_connector *connector)
3318{
3319	int i;
3320	struct dentry *dir = connector->base.debugfs_entry;
3321
3322	if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3323	    connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3324		for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
3325			debugfs_create_file(dp_debugfs_entries[i].name,
3326					    0644, dir, connector,
3327					    dp_debugfs_entries[i].fops);
3328		}
3329	}
3330	if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3331		debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops);
3332		debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops);
3333		debugfs_create_file_unsafe("psr_residency", 0444, dir,
3334					   connector, &psr_residency_fops);
3335		debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector,
3336				    &current_backlight_fops);
3337		debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector,
3338				    &target_backlight_fops);
3339		debugfs_create_file("ilr_setting", 0644, dir, connector,
3340					&edp_ilr_debugfs_fops);
3341		debugfs_create_file("allow_edp_hotplug_detection", 0644, dir, connector,
3342					&allow_edp_hotplug_detection_fops);
3343		debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector,
3344					&disallow_edp_enter_psr_fops);
3345	}
3346
3347	for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
3348		debugfs_create_file(connector_debugfs_entries[i].name,
3349				    0644, dir, connector,
3350				    connector_debugfs_entries[i].fops);
3351	}
3352
3353	if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
3354		for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) {
3355			debugfs_create_file(hdmi_debugfs_entries[i].name,
3356					    0644, dir, connector,
3357					    hdmi_debugfs_entries[i].fops);
3358		}
3359	}
3360}
3361
3362#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3363/*
3364 * Set crc window coordinate x start
3365 */
3366static int crc_win_x_start_set(void *data, u64 val)
3367{
3368	struct drm_crtc *crtc = data;
3369	struct drm_device *drm_dev = crtc->dev;
3370	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3371
3372	spin_lock_irq(&drm_dev->event_lock);
3373	acrtc->dm_irq_params.window_param.x_start = (uint16_t) val;
3374	acrtc->dm_irq_params.window_param.update_win = false;
3375	spin_unlock_irq(&drm_dev->event_lock);
3376
3377	return 0;
3378}
3379
3380/*
3381 * Get crc window coordinate x start
3382 */
3383static int crc_win_x_start_get(void *data, u64 *val)
3384{
3385	struct drm_crtc *crtc = data;
3386	struct drm_device *drm_dev = crtc->dev;
3387	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3388
3389	spin_lock_irq(&drm_dev->event_lock);
3390	*val = acrtc->dm_irq_params.window_param.x_start;
3391	spin_unlock_irq(&drm_dev->event_lock);
3392
3393	return 0;
3394}
3395
3396DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get,
3397			 crc_win_x_start_set, "%llu\n");
3398
3399
3400/*
3401 * Set crc window coordinate y start
3402 */
3403static int crc_win_y_start_set(void *data, u64 val)
3404{
3405	struct drm_crtc *crtc = data;
3406	struct drm_device *drm_dev = crtc->dev;
3407	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3408
3409	spin_lock_irq(&drm_dev->event_lock);
3410	acrtc->dm_irq_params.window_param.y_start = (uint16_t) val;
3411	acrtc->dm_irq_params.window_param.update_win = false;
3412	spin_unlock_irq(&drm_dev->event_lock);
3413
3414	return 0;
3415}
3416
3417/*
3418 * Get crc window coordinate y start
3419 */
3420static int crc_win_y_start_get(void *data, u64 *val)
3421{
3422	struct drm_crtc *crtc = data;
3423	struct drm_device *drm_dev = crtc->dev;
3424	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3425
3426	spin_lock_irq(&drm_dev->event_lock);
3427	*val = acrtc->dm_irq_params.window_param.y_start;
3428	spin_unlock_irq(&drm_dev->event_lock);
3429
3430	return 0;
3431}
3432
3433DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get,
3434			 crc_win_y_start_set, "%llu\n");
3435
3436/*
3437 * Set crc window coordinate x end
3438 */
3439static int crc_win_x_end_set(void *data, u64 val)
3440{
3441	struct drm_crtc *crtc = data;
3442	struct drm_device *drm_dev = crtc->dev;
3443	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3444
3445	spin_lock_irq(&drm_dev->event_lock);
3446	acrtc->dm_irq_params.window_param.x_end = (uint16_t) val;
3447	acrtc->dm_irq_params.window_param.update_win = false;
3448	spin_unlock_irq(&drm_dev->event_lock);
3449
3450	return 0;
3451}
3452
3453/*
3454 * Get crc window coordinate x end
3455 */
3456static int crc_win_x_end_get(void *data, u64 *val)
3457{
3458	struct drm_crtc *crtc = data;
3459	struct drm_device *drm_dev = crtc->dev;
3460	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3461
3462	spin_lock_irq(&drm_dev->event_lock);
3463	*val = acrtc->dm_irq_params.window_param.x_end;
3464	spin_unlock_irq(&drm_dev->event_lock);
3465
3466	return 0;
3467}
3468
3469DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get,
3470			 crc_win_x_end_set, "%llu\n");
3471
3472/*
3473 * Set crc window coordinate y end
3474 */
3475static int crc_win_y_end_set(void *data, u64 val)
3476{
3477	struct drm_crtc *crtc = data;
3478	struct drm_device *drm_dev = crtc->dev;
3479	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3480
3481	spin_lock_irq(&drm_dev->event_lock);
3482	acrtc->dm_irq_params.window_param.y_end = (uint16_t) val;
3483	acrtc->dm_irq_params.window_param.update_win = false;
3484	spin_unlock_irq(&drm_dev->event_lock);
3485
3486	return 0;
3487}
3488
3489/*
3490 * Get crc window coordinate y end
3491 */
3492static int crc_win_y_end_get(void *data, u64 *val)
3493{
3494	struct drm_crtc *crtc = data;
3495	struct drm_device *drm_dev = crtc->dev;
3496	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3497
3498	spin_lock_irq(&drm_dev->event_lock);
3499	*val = acrtc->dm_irq_params.window_param.y_end;
3500	spin_unlock_irq(&drm_dev->event_lock);
3501
3502	return 0;
3503}
3504
3505DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get,
3506			 crc_win_y_end_set, "%llu\n");
3507/*
3508 * Trigger to commit crc window
3509 */
3510static int crc_win_update_set(void *data, u64 val)
3511{
3512	struct drm_crtc *crtc = data;
3513	struct amdgpu_crtc *acrtc;
3514	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
3515
3516	if (val) {
3517		acrtc = to_amdgpu_crtc(crtc);
3518		mutex_lock(&adev->dm.dc_lock);
3519		/* PSR may write to OTG CRC window control register,
3520		 * so close it before starting secure_display.
3521		 */
3522		amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream);
3523
3524		spin_lock_irq(&adev_to_drm(adev)->event_lock);
3525
3526		acrtc->dm_irq_params.window_param.activated = true;
3527		acrtc->dm_irq_params.window_param.update_win = true;
3528		acrtc->dm_irq_params.window_param.skip_frame_cnt = 0;
3529
3530		spin_unlock_irq(&adev_to_drm(adev)->event_lock);
3531		mutex_unlock(&adev->dm.dc_lock);
3532	}
3533
3534	return 0;
3535}
3536
3537/*
3538 * Get crc window update flag
3539 */
3540static int crc_win_update_get(void *data, u64 *val)
3541{
3542	*val = 0;
3543	return 0;
3544}
3545
3546DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get,
3547			 crc_win_update_set, "%llu\n");
3548#endif
3549void crtc_debugfs_init(struct drm_crtc *crtc)
3550{
3551#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3552	struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry);
3553
3554	if (!dir)
3555		return;
3556
3557	debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc,
3558				   &crc_win_x_start_fops);
3559	debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc,
3560				   &crc_win_y_start_fops);
3561	debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc,
3562				   &crc_win_x_end_fops);
3563	debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc,
3564				   &crc_win_y_end_fops);
3565	debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc,
3566				   &crc_win_update_fops);
3567	dput(dir);
3568#endif
3569	debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry,
3570			    crtc, &amdgpu_current_bpc_fops);
3571	debugfs_create_file("amdgpu_current_colorspace", 0644, crtc->debugfs_entry,
3572			    crtc, &amdgpu_current_colorspace_fops);
3573}
3574
3575/*
3576 * Writes DTN log state to the user supplied buffer.
3577 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3578 */
3579static ssize_t dtn_log_read(
3580	struct file *f,
3581	char __user *buf,
3582	size_t size,
3583	loff_t *pos)
3584{
3585	struct amdgpu_device *adev = file_inode(f)->i_private;
3586	struct dc *dc = adev->dm.dc;
3587	struct dc_log_buffer_ctx log_ctx = { 0 };
3588	ssize_t result = 0;
3589
3590	if (!buf || !size)
3591		return -EINVAL;
3592
3593	if (!dc->hwss.log_hw_state)
3594		return 0;
3595
3596	dc->hwss.log_hw_state(dc, &log_ctx);
3597
3598	if (*pos < log_ctx.pos) {
3599		size_t to_copy = log_ctx.pos - *pos;
3600
3601		to_copy = min(to_copy, size);
3602
3603		if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) {
3604			*pos += to_copy;
3605			result = to_copy;
3606		}
3607	}
3608
3609	kfree(log_ctx.buf);
3610
3611	return result;
3612}
3613
3614/*
3615 * Writes DTN log state to dmesg when triggered via a write.
3616 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3617 */
3618static ssize_t dtn_log_write(
3619	struct file *f,
3620	const char __user *buf,
3621	size_t size,
3622	loff_t *pos)
3623{
3624	struct amdgpu_device *adev = file_inode(f)->i_private;
3625	struct dc *dc = adev->dm.dc;
3626
3627	/* Write triggers log output via dmesg. */
3628	if (size == 0)
3629		return 0;
3630
3631	if (dc->hwss.log_hw_state)
3632		dc->hwss.log_hw_state(dc, NULL);
3633
3634	return size;
3635}
3636
3637static int mst_topo_show(struct seq_file *m, void *unused)
3638{
3639	struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3640	struct drm_device *dev = adev_to_drm(adev);
3641	struct drm_connector *connector;
3642	struct drm_connector_list_iter conn_iter;
3643	struct amdgpu_dm_connector *aconnector;
3644
3645	drm_connector_list_iter_begin(dev, &conn_iter);
3646	drm_for_each_connector_iter(connector, &conn_iter) {
3647		if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3648			continue;
3649
3650		aconnector = to_amdgpu_dm_connector(connector);
3651
3652		/* Ensure we're only dumping the topology of a root mst node */
3653		if (!aconnector->mst_mgr.mst_state)
3654			continue;
3655
3656		seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
3657		drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
3658	}
3659	drm_connector_list_iter_end(&conn_iter);
3660
3661	return 0;
3662}
3663
3664/*
3665 * Sets trigger hpd for MST topologies.
3666 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent.
3667 * All topologies will be disconnected if val of 0 is set .
3668 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3669 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3670 */
3671static int trigger_hpd_mst_set(void *data, u64 val)
3672{
3673	struct amdgpu_device *adev = data;
3674	struct drm_device *dev = adev_to_drm(adev);
3675	struct drm_connector_list_iter iter;
3676	struct amdgpu_dm_connector *aconnector;
3677	struct drm_connector *connector;
3678	struct dc_link *link = NULL;
3679
3680	if (val == 1) {
3681		drm_connector_list_iter_begin(dev, &iter);
3682		drm_for_each_connector_iter(connector, &iter) {
3683			aconnector = to_amdgpu_dm_connector(connector);
3684			if (aconnector->dc_link->type == dc_connection_mst_branch &&
3685			    aconnector->mst_mgr.aux) {
3686				mutex_lock(&adev->dm.dc_lock);
3687				dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3688				mutex_unlock(&adev->dm.dc_lock);
3689
3690				drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
3691			}
3692		}
3693	} else if (val == 0) {
3694		drm_connector_list_iter_begin(dev, &iter);
3695		drm_for_each_connector_iter(connector, &iter) {
3696			aconnector = to_amdgpu_dm_connector(connector);
3697			if (!aconnector->dc_link)
3698				continue;
3699
3700			if (!aconnector->mst_root)
3701				continue;
3702
3703			link = aconnector->dc_link;
3704			dc_link_dp_receiver_power_ctrl(link, false);
3705			drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_root->mst_mgr, false);
3706			link->mst_stream_alloc_table.stream_count = 0;
3707			memset(link->mst_stream_alloc_table.stream_allocations, 0,
3708					sizeof(link->mst_stream_alloc_table.stream_allocations));
3709		}
3710	} else {
3711		return 0;
3712	}
3713	drm_kms_helper_hotplug_event(dev);
3714
3715	return 0;
3716}
3717
3718/*
3719 * The interface doesn't need get function, so it will return the
3720 * value of zero
3721 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3722 */
3723static int trigger_hpd_mst_get(void *data, u64 *val)
3724{
3725	*val = 0;
3726	return 0;
3727}
3728
3729DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get,
3730			 trigger_hpd_mst_set, "%llu\n");
3731
3732
3733/*
3734 * Sets the force_timing_sync debug option from the given string.
3735 * All connected displays will be force synchronized immediately.
3736 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3737 */
3738static int force_timing_sync_set(void *data, u64 val)
3739{
3740	struct amdgpu_device *adev = data;
3741
3742	adev->dm.force_timing_sync = (bool)val;
3743
3744	amdgpu_dm_trigger_timing_sync(adev_to_drm(adev));
3745
3746	return 0;
3747}
3748
3749/*
3750 * Gets the force_timing_sync debug option value into the given buffer.
3751 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3752 */
3753static int force_timing_sync_get(void *data, u64 *val)
3754{
3755	struct amdgpu_device *adev = data;
3756
3757	*val = adev->dm.force_timing_sync;
3758
3759	return 0;
3760}
3761
3762DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get,
3763			 force_timing_sync_set, "%llu\n");
3764
3765
3766/*
3767 * Disables all HPD and HPD RX interrupt handling in the
3768 * driver when set to 1. Default is 0.
3769 */
3770static int disable_hpd_set(void *data, u64 val)
3771{
3772	struct amdgpu_device *adev = data;
3773
3774	adev->dm.disable_hpd_irq = (bool)val;
3775
3776	return 0;
3777}
3778
3779
3780/*
3781 * Returns 1 if HPD and HPRX interrupt handling is disabled,
3782 * 0 otherwise.
3783 */
3784static int disable_hpd_get(void *data, u64 *val)
3785{
3786	struct amdgpu_device *adev = data;
3787
3788	*val = adev->dm.disable_hpd_irq;
3789
3790	return 0;
3791}
3792
3793DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get,
3794			 disable_hpd_set, "%llu\n");
3795
3796/*
3797 * Prints hardware capabilities. These are used for IGT testing.
3798 */
3799static int capabilities_show(struct seq_file *m, void *unused)
3800{
3801	struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3802	struct dc *dc = adev->dm.dc;
3803	bool mall_supported = dc->caps.mall_size_total;
3804	bool subvp_supported = dc->caps.subvp_fw_processing_delay_us;
3805	unsigned int mall_in_use = false;
3806	unsigned int subvp_in_use = false;
3807
3808	struct hubbub *hubbub = dc->res_pool->hubbub;
3809
3810	if (hubbub->funcs->get_mall_en)
3811		hubbub->funcs->get_mall_en(hubbub, &mall_in_use);
3812
3813	if (dc->cap_funcs.get_subvp_en)
3814		subvp_in_use = dc->cap_funcs.get_subvp_en(dc, dc->current_state);
3815
3816	seq_printf(m, "mall supported: %s, enabled: %s\n",
3817			   mall_supported ? "yes" : "no", mall_in_use ? "yes" : "no");
3818	seq_printf(m, "sub-viewport supported: %s, enabled: %s\n",
3819			   subvp_supported ? "yes" : "no", subvp_in_use ? "yes" : "no");
3820
3821	return 0;
3822}
3823
3824DEFINE_SHOW_ATTRIBUTE(capabilities);
3825
3826/*
3827 * Temporary w/a to force sst sequence in M42D DP2 mst receiver
3828 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst
3829 */
3830static int dp_force_sst_set(void *data, u64 val)
3831{
3832	struct amdgpu_device *adev = data;
3833
3834	adev->dm.dc->debug.set_mst_en_for_sst = val;
3835
3836	return 0;
3837}
3838
3839static int dp_force_sst_get(void *data, u64 *val)
3840{
3841	struct amdgpu_device *adev = data;
3842
3843	*val = adev->dm.dc->debug.set_mst_en_for_sst;
3844
3845	return 0;
3846}
3847DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get,
3848			 dp_force_sst_set, "%llu\n");
3849
3850/*
3851 * Force DP2 sequence without VESA certified cable.
3852 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id
3853 */
3854static int dp_ignore_cable_id_set(void *data, u64 val)
3855{
3856	struct amdgpu_device *adev = data;
3857
3858	adev->dm.dc->debug.ignore_cable_id = val;
3859
3860	return 0;
3861}
3862
3863static int dp_ignore_cable_id_get(void *data, u64 *val)
3864{
3865	struct amdgpu_device *adev = data;
3866
3867	*val = adev->dm.dc->debug.ignore_cable_id;
3868
3869	return 0;
3870}
3871DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get,
3872			 dp_ignore_cable_id_set, "%llu\n");
3873
3874/*
3875 * Sets the DC visual confirm debug option from the given string.
3876 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm
3877 */
3878static int visual_confirm_set(void *data, u64 val)
3879{
3880	struct amdgpu_device *adev = data;
3881
3882	adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
3883
3884	return 0;
3885}
3886
3887/*
3888 * Reads the DC visual confirm debug option value into the given buffer.
3889 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
3890 */
3891static int visual_confirm_get(void *data, u64 *val)
3892{
3893	struct amdgpu_device *adev = data;
3894
3895	*val = adev->dm.dc->debug.visual_confirm;
3896
3897	return 0;
3898}
3899
3900DEFINE_SHOW_ATTRIBUTE(mst_topo);
3901DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
3902			 visual_confirm_set, "%llu\n");
3903
3904
3905/*
3906 * Sets the DC skip_detection_link_training debug option from the given string.
3907 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training
3908 */
3909static int skip_detection_link_training_set(void *data, u64 val)
3910{
3911	struct amdgpu_device *adev = data;
3912
3913	if (val == 0)
3914		adev->dm.dc->debug.skip_detection_link_training = false;
3915	else
3916		adev->dm.dc->debug.skip_detection_link_training = true;
3917
3918	return 0;
3919}
3920
3921/*
3922 * Reads the DC skip_detection_link_training debug option value into the given buffer.
3923 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training
3924 */
3925static int skip_detection_link_training_get(void *data, u64 *val)
3926{
3927	struct amdgpu_device *adev = data;
3928
3929	*val = adev->dm.dc->debug.skip_detection_link_training;
3930
3931	return 0;
3932}
3933
3934DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops,
3935			 skip_detection_link_training_get,
3936			 skip_detection_link_training_set, "%llu\n");
3937
3938/*
3939 * Dumps the DCC_EN bit for each pipe.
3940 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en
3941 */
3942static ssize_t dcc_en_bits_read(
3943	struct file *f,
3944	char __user *buf,
3945	size_t size,
3946	loff_t *pos)
3947{
3948	struct amdgpu_device *adev = file_inode(f)->i_private;
3949	struct dc *dc = adev->dm.dc;
3950	char *rd_buf = NULL;
3951	const uint32_t rd_buf_size = 32;
3952	uint32_t result = 0;
3953	int offset = 0;
3954	int num_pipes = dc->res_pool->pipe_count;
3955	int *dcc_en_bits;
3956	int i, r;
3957
3958	dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL);
3959	if (!dcc_en_bits)
3960		return -ENOMEM;
3961
3962	if (!dc->hwss.get_dcc_en_bits) {
3963		kfree(dcc_en_bits);
3964		return 0;
3965	}
3966
3967	dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
3968
3969	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
3970	if (!rd_buf) {
3971		kfree(dcc_en_bits);
3972		return -ENOMEM;
3973	}
3974
3975	for (i = 0; i < num_pipes; i++)
3976		offset += snprintf(rd_buf + offset, rd_buf_size - offset,
3977				   "%d  ", dcc_en_bits[i]);
3978	rd_buf[strlen(rd_buf)] = '\n';
3979
3980	kfree(dcc_en_bits);
3981
3982	while (size) {
3983		if (*pos >= rd_buf_size)
3984			break;
3985		r = put_user(*(rd_buf + result), buf);
3986		if (r) {
3987			kfree(rd_buf);
3988			return r; /* r = -EFAULT */
3989		}
3990		buf += 1;
3991		size -= 1;
3992		*pos += 1;
3993		result += 1;
3994	}
3995
3996	kfree(rd_buf);
3997	return result;
3998}
3999
4000void dtn_debugfs_init(struct amdgpu_device *adev)
4001{
4002	static const struct file_operations dtn_log_fops = {
4003		.owner = THIS_MODULE,
4004		.read = dtn_log_read,
4005		.write = dtn_log_write,
4006		.llseek = default_llseek
4007	};
4008	static const struct file_operations dcc_en_bits_fops = {
4009		.owner = THIS_MODULE,
4010		.read = dcc_en_bits_read,
4011		.llseek = default_llseek
4012	};
4013
4014	struct drm_minor *minor = adev_to_drm(adev)->primary;
4015	struct dentry *root = minor->debugfs_root;
4016
4017	debugfs_create_file("amdgpu_mst_topology", 0444, root,
4018			    adev, &mst_topo_fops);
4019	debugfs_create_file("amdgpu_dm_capabilities", 0444, root,
4020			    adev, &capabilities_fops);
4021	debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
4022			    &dtn_log_fops);
4023	debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev,
4024				&dp_set_mst_en_for_sst_ops);
4025	debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev,
4026				&dp_ignore_cable_id_ops);
4027
4028	debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev,
4029				   &visual_confirm_fops);
4030
4031	debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev,
4032				   &skip_detection_link_training_fops);
4033
4034	debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root,
4035				   adev, &dmub_tracebuffer_fops);
4036
4037	debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root,
4038				   adev, &dmub_fw_state_fops);
4039
4040	debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root,
4041				   adev, &force_timing_sync_ops);
4042
4043	debugfs_create_file_unsafe("amdgpu_dm_dmub_trace_mask", 0644, root,
4044				   adev, &dmub_trace_mask_fops);
4045
4046	debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,
4047				   adev, &dmcub_trace_event_state_fops);
4048
4049	debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root,
4050				   adev, &trigger_hpd_mst_ops);
4051
4052	debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev,
4053				   &dcc_en_bits_fops);
4054
4055	debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,
4056				   &disable_hpd_ops);
4057
4058}