1/*
  2 *  linux/arch/arm/common/vic.c
  3 *
  4 *  Copyright (C) 1999 - 2003 ARM Limited
  5 *  Copyright (C) 2000 Deep Blue Solutions Ltd
  6 *
  7 * This program is free software; you can redistribute it and/or modify
  8 * it under the terms of the GNU General Public License as published by
  9 * the Free Software Foundation; either version 2 of the License, or
 10 * (at your option) any later version.
 11 *
 12 * This program is distributed in the hope that it will be useful,
 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 15 * GNU General Public License for more details.
 16 *
 17 * You should have received a copy of the GNU General Public License
 18 * along with this program; if not, write to the Free Software
 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 20 */
 21
 22#include <linux/export.h>
 23#include <linux/init.h>
 24#include <linux/list.h>
 25#include <linux/io.h>
 26#include <linux/irqdomain.h>
 27#include <linux/of.h>
 28#include <linux/of_address.h>
 29#include <linux/of_irq.h>
 30#include <linux/syscore_ops.h>
 31#include <linux/device.h>
 32#include <linux/amba/bus.h>
 33
 34#include <asm/exception.h>
 35#include <asm/mach/irq.h>
 36#include <asm/hardware/vic.h>
 37
 38/**
 39 * struct vic_device - VIC PM device
 40 * @irq: The IRQ number for the base of the VIC.
 41 * @base: The register base for the VIC.
 42 * @valid_sources: A bitmask of valid interrupts
 43 * @resume_sources: A bitmask of interrupts for resume.
 44 * @resume_irqs: The IRQs enabled for resume.
 45 * @int_select: Save for VIC_INT_SELECT.
 46 * @int_enable: Save for VIC_INT_ENABLE.
 47 * @soft_int: Save for VIC_INT_SOFT.
 48 * @protect: Save for VIC_PROTECT.
 49 * @domain: The IRQ domain for the VIC.
 50 */
 51struct vic_device {
 52	void __iomem	*base;
 53	int		irq;
 54	u32		valid_sources;
 55	u32		resume_sources;
 56	u32		resume_irqs;
 57	u32		int_select;
 58	u32		int_enable;
 59	u32		soft_int;
 60	u32		protect;
 61	struct irq_domain *domain;
 62};
 63
 64/* we cannot allocate memory when VICs are initially registered */
 65static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
 66
 67static int vic_id;
 68
 69/**
 70 * vic_init2 - common initialisation code
 71 * @base: Base of the VIC.
 72 *
 73 * Common initialisation code for registration
 74 * and resume.
 75*/
 76static void vic_init2(void __iomem *base)
 77{
 78	int i;
 79
 80	for (i = 0; i < 16; i++) {
 81		void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
 82		writel(VIC_VECT_CNTL_ENABLE | i, reg);
 83	}
 84
 85	writel(32, base + VIC_PL190_DEF_VECT_ADDR);
 86}
 87
 88#ifdef CONFIG_PM
 89static void resume_one_vic(struct vic_device *vic)
 90{
 91	void __iomem *base = vic->base;
 92
 93	printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
 94
 95	/* re-initialise static settings */
 96	vic_init2(base);
 97
 98	writel(vic->int_select, base + VIC_INT_SELECT);
 99	writel(vic->protect, base + VIC_PROTECT);
100
101	/* set the enabled ints and then clear the non-enabled */
102	writel(vic->int_enable, base + VIC_INT_ENABLE);
103	writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
104
105	/* and the same for the soft-int register */
106
107	writel(vic->soft_int, base + VIC_INT_SOFT);
108	writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
109}
110
111static void vic_resume(void)
112{
113	int id;
114
115	for (id = vic_id - 1; id >= 0; id--)
116		resume_one_vic(vic_devices + id);
117}
118
119static void suspend_one_vic(struct vic_device *vic)
120{
121	void __iomem *base = vic->base;
122
123	printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
124
125	vic->int_select = readl(base + VIC_INT_SELECT);
126	vic->int_enable = readl(base + VIC_INT_ENABLE);
127	vic->soft_int = readl(base + VIC_INT_SOFT);
128	vic->protect = readl(base + VIC_PROTECT);
129
130	/* set the interrupts (if any) that are used for
131	 * resuming the system */
132
133	writel(vic->resume_irqs, base + VIC_INT_ENABLE);
134	writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
135}
136
137static int vic_suspend(void)
138{
139	int id;
140
141	for (id = 0; id < vic_id; id++)
142		suspend_one_vic(vic_devices + id);
143
144	return 0;
145}
146
147struct syscore_ops vic_syscore_ops = {
148	.suspend	= vic_suspend,
149	.resume		= vic_resume,
150};
151
152/**
153 * vic_pm_init - initicall to register VIC pm
154 *
155 * This is called via late_initcall() to register
156 * the resources for the VICs due to the early
157 * nature of the VIC's registration.
158*/
159static int __init vic_pm_init(void)
160{
161	if (vic_id > 0)
162		register_syscore_ops(&vic_syscore_ops);
163
164	return 0;
165}
166late_initcall(vic_pm_init);
167#endif /* CONFIG_PM */
168
169static struct irq_chip vic_chip;
170
171static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
172			     irq_hw_number_t hwirq)
173{
174	struct vic_device *v = d->host_data;
175
176	/* Skip invalid IRQs, only register handlers for the real ones */
177	if (!(v->valid_sources & (1 << hwirq)))
178		return -ENOTSUPP;
179	irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
180	irq_set_chip_data(irq, v->base);
181	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
182	return 0;
183}
184
185static struct irq_domain_ops vic_irqdomain_ops = {
186	.map = vic_irqdomain_map,
187	.xlate = irq_domain_xlate_onetwocell,
188};
189
190/**
191 * vic_register() - Register a VIC.
192 * @base: The base address of the VIC.
193 * @irq: The base IRQ for the VIC.
194 * @valid_sources: bitmask of valid interrupts
195 * @resume_sources: bitmask of interrupts allowed for resume sources.
196 * @node: The device tree node associated with the VIC.
197 *
198 * Register the VIC with the system device tree so that it can be notified
199 * of suspend and resume requests and ensure that the correct actions are
200 * taken to re-instate the settings on resume.
201 *
202 * This also configures the IRQ domain for the VIC.
203 */
204static void __init vic_register(void __iomem *base, unsigned int irq,
205				u32 valid_sources, u32 resume_sources,
206				struct device_node *node)
207{
208	struct vic_device *v;
209
210	if (vic_id >= ARRAY_SIZE(vic_devices)) {
211		printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
212		return;
213	}
214
215	v = &vic_devices[vic_id];
216	v->base = base;
217	v->valid_sources = valid_sources;
218	v->resume_sources = resume_sources;
219	v->irq = irq;
220	vic_id++;
221	v->domain = irq_domain_add_legacy(node, fls(valid_sources), irq, 0,
222					  &vic_irqdomain_ops, v);
223}
224
225static void vic_ack_irq(struct irq_data *d)
226{
227	void __iomem *base = irq_data_get_irq_chip_data(d);
228	unsigned int irq = d->hwirq;
229	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
230	/* moreover, clear the soft-triggered, in case it was the reason */
231	writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
232}
233
234static void vic_mask_irq(struct irq_data *d)
235{
236	void __iomem *base = irq_data_get_irq_chip_data(d);
237	unsigned int irq = d->hwirq;
238	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
239}
240
241static void vic_unmask_irq(struct irq_data *d)
242{
243	void __iomem *base = irq_data_get_irq_chip_data(d);
244	unsigned int irq = d->hwirq;
245	writel(1 << irq, base + VIC_INT_ENABLE);
246}
247
248#if defined(CONFIG_PM)
249static struct vic_device *vic_from_irq(unsigned int irq)
250{
251        struct vic_device *v = vic_devices;
252	unsigned int base_irq = irq & ~31;
253	int id;
254
255	for (id = 0; id < vic_id; id++, v++) {
256		if (v->irq == base_irq)
257			return v;
258	}
259
260	return NULL;
261}
262
263static int vic_set_wake(struct irq_data *d, unsigned int on)
264{
265	struct vic_device *v = vic_from_irq(d->irq);
266	unsigned int off = d->hwirq;
267	u32 bit = 1 << off;
268
269	if (!v)
270		return -EINVAL;
271
272	if (!(bit & v->resume_sources))
273		return -EINVAL;
274
275	if (on)
276		v->resume_irqs |= bit;
277	else
278		v->resume_irqs &= ~bit;
279
280	return 0;
281}
282#else
283#define vic_set_wake NULL
284#endif /* CONFIG_PM */
285
286static struct irq_chip vic_chip = {
287	.name		= "VIC",
288	.irq_ack	= vic_ack_irq,
289	.irq_mask	= vic_mask_irq,
290	.irq_unmask	= vic_unmask_irq,
291	.irq_set_wake	= vic_set_wake,
292};
293
294static void __init vic_disable(void __iomem *base)
295{
296	writel(0, base + VIC_INT_SELECT);
297	writel(0, base + VIC_INT_ENABLE);
298	writel(~0, base + VIC_INT_ENABLE_CLEAR);
299	writel(0, base + VIC_ITCR);
300	writel(~0, base + VIC_INT_SOFT_CLEAR);
301}
302
303static void __init vic_clear_interrupts(void __iomem *base)
304{
305	unsigned int i;
306
307	writel(0, base + VIC_PL190_VECT_ADDR);
308	for (i = 0; i < 19; i++) {
309		unsigned int value;
310
311		value = readl(base + VIC_PL190_VECT_ADDR);
312		writel(value, base + VIC_PL190_VECT_ADDR);
313	}
314}
315
316/*
317 * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
318 * The original cell has 32 interrupts, while the modified one has 64,
319 * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
320 * the probe function is called twice, with base set to offset 000
321 *  and 020 within the page. We call this "second block".
322 */
323static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
324			       u32 vic_sources, struct device_node *node)
325{
326	unsigned int i;
327	int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
328
329	/* Disable all interrupts initially. */
330	vic_disable(base);
331
332	/*
333	 * Make sure we clear all existing interrupts. The vector registers
334	 * in this cell are after the second block of general registers,
335	 * so we can address them using standard offsets, but only from
336	 * the second base address, which is 0x20 in the page
337	 */
338	if (vic_2nd_block) {
339		vic_clear_interrupts(base);
340
341		/* ST has 16 vectors as well, but we don't enable them by now */
342		for (i = 0; i < 16; i++) {
343			void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
344			writel(0, reg);
345		}
346
347		writel(32, base + VIC_PL190_DEF_VECT_ADDR);
348	}
349
350	vic_register(base, irq_start, vic_sources, 0, node);
351}
352
353void __init __vic_init(void __iomem *base, unsigned int irq_start,
354			      u32 vic_sources, u32 resume_sources,
355			      struct device_node *node)
356{
357	unsigned int i;
358	u32 cellid = 0;
359	enum amba_vendor vendor;
360
361	/* Identify which VIC cell this one is, by reading the ID */
362	for (i = 0; i < 4; i++) {
363		void __iomem *addr;
364		addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
365		cellid |= (readl(addr) & 0xff) << (8 * i);
366	}
367	vendor = (cellid >> 12) & 0xff;
368	printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
369	       base, cellid, vendor);
370
371	switch(vendor) {
372	case AMBA_VENDOR_ST:
373		vic_init_st(base, irq_start, vic_sources, node);
374		return;
375	default:
376		printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
377		/* fall through */
378	case AMBA_VENDOR_ARM:
379		break;
380	}
381
382	/* Disable all interrupts initially. */
383	vic_disable(base);
384
385	/* Make sure we clear all existing interrupts */
386	vic_clear_interrupts(base);
387
388	vic_init2(base);
389
390	vic_register(base, irq_start, vic_sources, resume_sources, node);
391}
392
393/**
394 * vic_init() - initialise a vectored interrupt controller
395 * @base: iomem base address
396 * @irq_start: starting interrupt number, must be muliple of 32
397 * @vic_sources: bitmask of interrupt sources to allow
398 * @resume_sources: bitmask of interrupt sources to allow for resume
399 */
400void __init vic_init(void __iomem *base, unsigned int irq_start,
401		     u32 vic_sources, u32 resume_sources)
402{
403	__vic_init(base, irq_start, vic_sources, resume_sources, NULL);
404}
405
406#ifdef CONFIG_OF
407int __init vic_of_init(struct device_node *node, struct device_node *parent)
408{
409	void __iomem *regs;
410	int irq_base;
411
412	if (WARN(parent, "non-root VICs are not supported"))
413		return -EINVAL;
414
415	regs = of_iomap(node, 0);
416	if (WARN_ON(!regs))
417		return -EIO;
418
419	irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
420	if (WARN_ON(irq_base < 0))
421		goto out_unmap;
422
423	__vic_init(regs, irq_base, ~0, ~0, node);
424
425	return 0;
426
427 out_unmap:
428	iounmap(regs);
429
430	return -EIO;
431}
432#endif /* CONFIG OF */
433
434/*
435 * Handle each interrupt in a single VIC.  Returns non-zero if we've
436 * handled at least one interrupt.  This reads the status register
437 * before handling each interrupt, which is necessary given that
438 * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
439 */
440static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
441{
442	u32 stat, irq;
443	int handled = 0;
444
445	while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
446		irq = ffs(stat) - 1;
447		handle_IRQ(irq_find_mapping(vic->domain, irq), regs);
448		handled = 1;
449	}
450
451	return handled;
452}
453
454/*
455 * Keep iterating over all registered VIC's until there are no pending
456 * interrupts.
457 */
458asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
459{
460	int i, handled;
461
462	do {
463		for (i = 0, handled = 0; i < vic_id; ++i)
464			handled |= handle_one_vic(&vic_devices[i], regs);
465	} while (handled);
466}