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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2014, Sony Mobile Communications AB.
5 *
6 */
7
8#include <linux/acpi.h>
9#include <linux/atomic.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/dmaengine.h>
13#include <linux/dmapool.h>
14#include <linux/dma-mapping.h>
15#include <linux/err.h>
16#include <linux/i2c.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23#include <linux/scatterlist.h>
24
25/* QUP Registers */
26#define QUP_CONFIG 0x000
27#define QUP_STATE 0x004
28#define QUP_IO_MODE 0x008
29#define QUP_SW_RESET 0x00c
30#define QUP_OPERATIONAL 0x018
31#define QUP_ERROR_FLAGS 0x01c
32#define QUP_ERROR_FLAGS_EN 0x020
33#define QUP_OPERATIONAL_MASK 0x028
34#define QUP_HW_VERSION 0x030
35#define QUP_MX_OUTPUT_CNT 0x100
36#define QUP_OUT_FIFO_BASE 0x110
37#define QUP_MX_WRITE_CNT 0x150
38#define QUP_MX_INPUT_CNT 0x200
39#define QUP_MX_READ_CNT 0x208
40#define QUP_IN_FIFO_BASE 0x218
41#define QUP_I2C_CLK_CTL 0x400
42#define QUP_I2C_STATUS 0x404
43#define QUP_I2C_MASTER_GEN 0x408
44
45/* QUP States and reset values */
46#define QUP_RESET_STATE 0
47#define QUP_RUN_STATE 1
48#define QUP_PAUSE_STATE 3
49#define QUP_STATE_MASK 3
50
51#define QUP_STATE_VALID BIT(2)
52#define QUP_I2C_MAST_GEN BIT(4)
53#define QUP_I2C_FLUSH BIT(6)
54
55#define QUP_OPERATIONAL_RESET 0x000ff0
56#define QUP_I2C_STATUS_RESET 0xfffffc
57
58/* QUP OPERATIONAL FLAGS */
59#define QUP_I2C_NACK_FLAG BIT(3)
60#define QUP_OUT_NOT_EMPTY BIT(4)
61#define QUP_IN_NOT_EMPTY BIT(5)
62#define QUP_OUT_FULL BIT(6)
63#define QUP_OUT_SVC_FLAG BIT(8)
64#define QUP_IN_SVC_FLAG BIT(9)
65#define QUP_MX_OUTPUT_DONE BIT(10)
66#define QUP_MX_INPUT_DONE BIT(11)
67#define OUT_BLOCK_WRITE_REQ BIT(12)
68#define IN_BLOCK_READ_REQ BIT(13)
69
70/* I2C mini core related values */
71#define QUP_NO_INPUT BIT(7)
72#define QUP_CLOCK_AUTO_GATE BIT(13)
73#define I2C_MINI_CORE (2 << 8)
74#define I2C_N_VAL 15
75#define I2C_N_VAL_V2 7
76
77/* Most significant word offset in FIFO port */
78#define QUP_MSW_SHIFT (I2C_N_VAL + 1)
79
80/* Packing/Unpacking words in FIFOs, and IO modes */
81#define QUP_OUTPUT_BLK_MODE (1 << 10)
82#define QUP_OUTPUT_BAM_MODE (3 << 10)
83#define QUP_INPUT_BLK_MODE (1 << 12)
84#define QUP_INPUT_BAM_MODE (3 << 12)
85#define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE)
86#define QUP_UNPACK_EN BIT(14)
87#define QUP_PACK_EN BIT(15)
88
89#define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN)
90#define QUP_V2_TAGS_EN 1
91
92#define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
93#define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
94#define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03)
95#define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07)
96
97/* QUP tags */
98#define QUP_TAG_START (1 << 8)
99#define QUP_TAG_DATA (2 << 8)
100#define QUP_TAG_STOP (3 << 8)
101#define QUP_TAG_REC (4 << 8)
102#define QUP_BAM_INPUT_EOT 0x93
103#define QUP_BAM_FLUSH_STOP 0x96
104
105/* QUP v2 tags */
106#define QUP_TAG_V2_START 0x81
107#define QUP_TAG_V2_DATAWR 0x82
108#define QUP_TAG_V2_DATAWR_STOP 0x83
109#define QUP_TAG_V2_DATARD 0x85
110#define QUP_TAG_V2_DATARD_NACK 0x86
111#define QUP_TAG_V2_DATARD_STOP 0x87
112
113/* Status, Error flags */
114#define I2C_STATUS_WR_BUFFER_FULL BIT(0)
115#define I2C_STATUS_BUS_ACTIVE BIT(8)
116#define I2C_STATUS_ERROR_MASK 0x38000fc
117#define QUP_STATUS_ERROR_FLAGS 0x7c
118
119#define QUP_READ_LIMIT 256
120#define SET_BIT 0x1
121#define RESET_BIT 0x0
122#define ONE_BYTE 0x1
123#define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31)
124
125/* Maximum transfer length for single DMA descriptor */
126#define MX_TX_RX_LEN SZ_64K
127#define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT)
128/* Maximum transfer length for all DMA descriptors */
129#define MX_DMA_TX_RX_LEN (2 * MX_TX_RX_LEN)
130#define MX_DMA_BLOCKS (MX_DMA_TX_RX_LEN / QUP_READ_LIMIT)
131
132/*
133 * Minimum transfer timeout for i2c transfers in seconds. It will be added on
134 * the top of maximum transfer time calculated from i2c bus speed to compensate
135 * the overheads.
136 */
137#define TOUT_MIN 2
138
139/* Default values. Use these if FW query fails */
140#define DEFAULT_CLK_FREQ I2C_MAX_STANDARD_MODE_FREQ
141#define DEFAULT_SRC_CLK 20000000
142
143/*
144 * Max tags length (start, stop and maximum 2 bytes address) for each QUP
145 * data transfer
146 */
147#define QUP_MAX_TAGS_LEN 4
148/* Max data length for each DATARD tags */
149#define RECV_MAX_DATA_LEN 254
150/* TAG length for DATA READ in RX FIFO */
151#define READ_RX_TAGS_LEN 2
152
153static unsigned int scl_freq;
154module_param_named(scl_freq, scl_freq, uint, 0444);
155MODULE_PARM_DESC(scl_freq, "SCL frequency override");
156
157/*
158 * count: no of blocks
159 * pos: current block number
160 * tx_tag_len: tx tag length for current block
161 * rx_tag_len: rx tag length for current block
162 * data_len: remaining data length for current message
163 * cur_blk_len: data length for current block
164 * total_tx_len: total tx length including tag bytes for current QUP transfer
165 * total_rx_len: total rx length including tag bytes for current QUP transfer
166 * tx_fifo_data_pos: current byte number in TX FIFO word
167 * tx_fifo_free: number of free bytes in current QUP block write.
168 * rx_fifo_data_pos: current byte number in RX FIFO word
169 * fifo_available: number of available bytes in RX FIFO for current
170 * QUP block read
171 * tx_fifo_data: QUP TX FIFO write works on word basis (4 bytes). New byte write
172 * to TX FIFO will be appended in this data and will be written to
173 * TX FIFO when all the 4 bytes are available.
174 * rx_fifo_data: QUP RX FIFO read works on word basis (4 bytes). This will
175 * contains the 4 bytes of RX data.
176 * cur_data: pointer to tell cur data position for current message
177 * cur_tx_tags: pointer to tell cur position in tags
178 * tx_tags_sent: all tx tag bytes have been written in FIFO word
179 * send_last_word: for tx FIFO, last word send is pending in current block
180 * rx_bytes_read: if all the bytes have been read from rx FIFO.
181 * rx_tags_fetched: all the rx tag bytes have been fetched from rx fifo word
182 * is_tx_blk_mode: whether tx uses block or FIFO mode in case of non BAM xfer.
183 * is_rx_blk_mode: whether rx uses block or FIFO mode in case of non BAM xfer.
184 * tags: contains tx tag bytes for current QUP transfer
185 */
186struct qup_i2c_block {
187 int count;
188 int pos;
189 int tx_tag_len;
190 int rx_tag_len;
191 int data_len;
192 int cur_blk_len;
193 int total_tx_len;
194 int total_rx_len;
195 int tx_fifo_data_pos;
196 int tx_fifo_free;
197 int rx_fifo_data_pos;
198 int fifo_available;
199 u32 tx_fifo_data;
200 u32 rx_fifo_data;
201 u8 *cur_data;
202 u8 *cur_tx_tags;
203 bool tx_tags_sent;
204 bool send_last_word;
205 bool rx_tags_fetched;
206 bool rx_bytes_read;
207 bool is_tx_blk_mode;
208 bool is_rx_blk_mode;
209 u8 tags[6];
210};
211
212struct qup_i2c_tag {
213 u8 *start;
214 dma_addr_t addr;
215};
216
217struct qup_i2c_bam {
218 struct qup_i2c_tag tag;
219 struct dma_chan *dma;
220 struct scatterlist *sg;
221 unsigned int sg_cnt;
222};
223
224struct qup_i2c_dev {
225 struct device *dev;
226 void __iomem *base;
227 int irq;
228 struct clk *clk;
229 struct clk *pclk;
230 struct i2c_adapter adap;
231
232 int clk_ctl;
233 int out_fifo_sz;
234 int in_fifo_sz;
235 int out_blk_sz;
236 int in_blk_sz;
237
238 int blk_xfer_limit;
239 unsigned long one_byte_t;
240 unsigned long xfer_timeout;
241 struct qup_i2c_block blk;
242
243 struct i2c_msg *msg;
244 /* Current posion in user message buffer */
245 int pos;
246 /* I2C protocol errors */
247 u32 bus_err;
248 /* QUP core errors */
249 u32 qup_err;
250
251 /* To check if this is the last msg */
252 bool is_last;
253 bool is_smbus_read;
254
255 /* To configure when bus is in run state */
256 u32 config_run;
257
258 /* dma parameters */
259 bool is_dma;
260 /* To check if the current transfer is using DMA */
261 bool use_dma;
262 unsigned int max_xfer_sg_len;
263 unsigned int tag_buf_pos;
264 /* The threshold length above which block mode will be used */
265 unsigned int blk_mode_threshold;
266 struct dma_pool *dpool;
267 struct qup_i2c_tag start_tag;
268 struct qup_i2c_bam brx;
269 struct qup_i2c_bam btx;
270
271 struct completion xfer;
272 /* function to write data in tx fifo */
273 void (*write_tx_fifo)(struct qup_i2c_dev *qup);
274 /* function to read data from rx fifo */
275 void (*read_rx_fifo)(struct qup_i2c_dev *qup);
276 /* function to write tags in tx fifo for i2c read transfer */
277 void (*write_rx_tags)(struct qup_i2c_dev *qup);
278};
279
280static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
281{
282 struct qup_i2c_dev *qup = dev;
283 struct qup_i2c_block *blk = &qup->blk;
284 u32 bus_err;
285 u32 qup_err;
286 u32 opflags;
287
288 bus_err = readl(qup->base + QUP_I2C_STATUS);
289 qup_err = readl(qup->base + QUP_ERROR_FLAGS);
290 opflags = readl(qup->base + QUP_OPERATIONAL);
291
292 if (!qup->msg) {
293 /* Clear Error interrupt */
294 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
295 return IRQ_HANDLED;
296 }
297
298 bus_err &= I2C_STATUS_ERROR_MASK;
299 qup_err &= QUP_STATUS_ERROR_FLAGS;
300
301 /* Clear the error bits in QUP_ERROR_FLAGS */
302 if (qup_err)
303 writel(qup_err, qup->base + QUP_ERROR_FLAGS);
304
305 /* Clear the error bits in QUP_I2C_STATUS */
306 if (bus_err)
307 writel(bus_err, qup->base + QUP_I2C_STATUS);
308
309 /*
310 * Check for BAM mode and returns if already error has come for current
311 * transfer. In Error case, sometimes, QUP generates more than one
312 * interrupt.
313 */
314 if (qup->use_dma && (qup->qup_err || qup->bus_err))
315 return IRQ_HANDLED;
316
317 /* Reset the QUP State in case of error */
318 if (qup_err || bus_err) {
319 /*
320 * Don’t reset the QUP state in case of BAM mode. The BAM
321 * flush operation needs to be scheduled in transfer function
322 * which will clear the remaining schedule descriptors in BAM
323 * HW FIFO and generates the BAM interrupt.
324 */
325 if (!qup->use_dma)
326 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
327 goto done;
328 }
329
330 if (opflags & QUP_OUT_SVC_FLAG) {
331 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
332
333 if (opflags & OUT_BLOCK_WRITE_REQ) {
334 blk->tx_fifo_free += qup->out_blk_sz;
335 if (qup->msg->flags & I2C_M_RD)
336 qup->write_rx_tags(qup);
337 else
338 qup->write_tx_fifo(qup);
339 }
340 }
341
342 if (opflags & QUP_IN_SVC_FLAG) {
343 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
344
345 if (!blk->is_rx_blk_mode) {
346 blk->fifo_available += qup->in_fifo_sz;
347 qup->read_rx_fifo(qup);
348 } else if (opflags & IN_BLOCK_READ_REQ) {
349 blk->fifo_available += qup->in_blk_sz;
350 qup->read_rx_fifo(qup);
351 }
352 }
353
354 if (qup->msg->flags & I2C_M_RD) {
355 if (!blk->rx_bytes_read)
356 return IRQ_HANDLED;
357 } else {
358 /*
359 * Ideally, QUP_MAX_OUTPUT_DONE_FLAG should be checked
360 * for FIFO mode also. But, QUP_MAX_OUTPUT_DONE_FLAG lags
361 * behind QUP_OUTPUT_SERVICE_FLAG sometimes. The only reason
362 * of interrupt for write message in FIFO mode is
363 * QUP_MAX_OUTPUT_DONE_FLAG condition.
364 */
365 if (blk->is_tx_blk_mode && !(opflags & QUP_MX_OUTPUT_DONE))
366 return IRQ_HANDLED;
367 }
368
369done:
370 qup->qup_err = qup_err;
371 qup->bus_err = bus_err;
372 complete(&qup->xfer);
373 return IRQ_HANDLED;
374}
375
376static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,
377 u32 req_state, u32 req_mask)
378{
379 int retries = 1;
380 u32 state;
381
382 /*
383 * State transition takes 3 AHB clocks cycles + 3 I2C master clock
384 * cycles. So retry once after a 1uS delay.
385 */
386 do {
387 state = readl(qup->base + QUP_STATE);
388
389 if (state & QUP_STATE_VALID &&
390 (state & req_mask) == req_state)
391 return 0;
392
393 udelay(1);
394 } while (retries--);
395
396 return -ETIMEDOUT;
397}
398
399static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
400{
401 return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
402}
403
404static void qup_i2c_flush(struct qup_i2c_dev *qup)
405{
406 u32 val = readl(qup->base + QUP_STATE);
407
408 val |= QUP_I2C_FLUSH;
409 writel(val, qup->base + QUP_STATE);
410}
411
412static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
413{
414 return qup_i2c_poll_state_mask(qup, 0, 0);
415}
416
417static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)
418{
419 return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
420}
421
422static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
423{
424 if (qup_i2c_poll_state_valid(qup) != 0)
425 return -EIO;
426
427 writel(state, qup->base + QUP_STATE);
428
429 if (qup_i2c_poll_state(qup, state) != 0)
430 return -EIO;
431 return 0;
432}
433
434/* Check if I2C bus returns to IDLE state */
435static int qup_i2c_bus_active(struct qup_i2c_dev *qup, int len)
436{
437 unsigned long timeout;
438 u32 status;
439 int ret = 0;
440
441 timeout = jiffies + len * 4;
442 for (;;) {
443 status = readl(qup->base + QUP_I2C_STATUS);
444 if (!(status & I2C_STATUS_BUS_ACTIVE))
445 break;
446
447 if (time_after(jiffies, timeout))
448 ret = -ETIMEDOUT;
449
450 usleep_range(len, len * 2);
451 }
452
453 return ret;
454}
455
456static void qup_i2c_write_tx_fifo_v1(struct qup_i2c_dev *qup)
457{
458 struct qup_i2c_block *blk = &qup->blk;
459 struct i2c_msg *msg = qup->msg;
460 u32 addr = i2c_8bit_addr_from_msg(msg);
461 u32 qup_tag;
462 int idx;
463 u32 val;
464
465 if (qup->pos == 0) {
466 val = QUP_TAG_START | addr;
467 idx = 1;
468 blk->tx_fifo_free--;
469 } else {
470 val = 0;
471 idx = 0;
472 }
473
474 while (blk->tx_fifo_free && qup->pos < msg->len) {
475 if (qup->pos == msg->len - 1)
476 qup_tag = QUP_TAG_STOP;
477 else
478 qup_tag = QUP_TAG_DATA;
479
480 if (idx & 1)
481 val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT;
482 else
483 val = qup_tag | msg->buf[qup->pos];
484
485 /* Write out the pair and the last odd value */
486 if (idx & 1 || qup->pos == msg->len - 1)
487 writel(val, qup->base + QUP_OUT_FIFO_BASE);
488
489 qup->pos++;
490 idx++;
491 blk->tx_fifo_free--;
492 }
493}
494
495static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup,
496 struct i2c_msg *msg)
497{
498 qup->blk.pos = 0;
499 qup->blk.data_len = msg->len;
500 qup->blk.count = DIV_ROUND_UP(msg->len, qup->blk_xfer_limit);
501}
502
503static int qup_i2c_get_data_len(struct qup_i2c_dev *qup)
504{
505 int data_len;
506
507 if (qup->blk.data_len > qup->blk_xfer_limit)
508 data_len = qup->blk_xfer_limit;
509 else
510 data_len = qup->blk.data_len;
511
512 return data_len;
513}
514
515static bool qup_i2c_check_msg_len(struct i2c_msg *msg)
516{
517 return ((msg->flags & I2C_M_RD) && (msg->flags & I2C_M_RECV_LEN));
518}
519
520static int qup_i2c_set_tags_smb(u16 addr, u8 *tags, struct qup_i2c_dev *qup,
521 struct i2c_msg *msg)
522{
523 int len = 0;
524
525 if (qup->is_smbus_read) {
526 tags[len++] = QUP_TAG_V2_DATARD_STOP;
527 tags[len++] = qup_i2c_get_data_len(qup);
528 } else {
529 tags[len++] = QUP_TAG_V2_START;
530 tags[len++] = addr & 0xff;
531
532 if (msg->flags & I2C_M_TEN)
533 tags[len++] = addr >> 8;
534
535 tags[len++] = QUP_TAG_V2_DATARD;
536 /* Read 1 byte indicating the length of the SMBus message */
537 tags[len++] = 1;
538 }
539 return len;
540}
541
542static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
543 struct i2c_msg *msg)
544{
545 u16 addr = i2c_8bit_addr_from_msg(msg);
546 int len = 0;
547 int data_len;
548
549 int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last);
550
551 /* Handle tags for SMBus block read */
552 if (qup_i2c_check_msg_len(msg))
553 return qup_i2c_set_tags_smb(addr, tags, qup, msg);
554
555 if (qup->blk.pos == 0) {
556 tags[len++] = QUP_TAG_V2_START;
557 tags[len++] = addr & 0xff;
558
559 if (msg->flags & I2C_M_TEN)
560 tags[len++] = addr >> 8;
561 }
562
563 /* Send _STOP commands for the last block */
564 if (last) {
565 if (msg->flags & I2C_M_RD)
566 tags[len++] = QUP_TAG_V2_DATARD_STOP;
567 else
568 tags[len++] = QUP_TAG_V2_DATAWR_STOP;
569 } else {
570 if (msg->flags & I2C_M_RD)
571 tags[len++] = qup->blk.pos == (qup->blk.count - 1) ?
572 QUP_TAG_V2_DATARD_NACK :
573 QUP_TAG_V2_DATARD;
574 else
575 tags[len++] = QUP_TAG_V2_DATAWR;
576 }
577
578 data_len = qup_i2c_get_data_len(qup);
579
580 /* 0 implies 256 bytes */
581 if (data_len == QUP_READ_LIMIT)
582 tags[len++] = 0;
583 else
584 tags[len++] = data_len;
585
586 return len;
587}
588
589
590static void qup_i2c_bam_cb(void *data)
591{
592 struct qup_i2c_dev *qup = data;
593
594 complete(&qup->xfer);
595}
596
597static int qup_sg_set_buf(struct scatterlist *sg, void *buf,
598 unsigned int buflen, struct qup_i2c_dev *qup,
599 int dir)
600{
601 int ret;
602
603 sg_set_buf(sg, buf, buflen);
604 ret = dma_map_sg(qup->dev, sg, 1, dir);
605 if (!ret)
606 return -EINVAL;
607
608 return 0;
609}
610
611static void qup_i2c_rel_dma(struct qup_i2c_dev *qup)
612{
613 if (qup->btx.dma)
614 dma_release_channel(qup->btx.dma);
615 if (qup->brx.dma)
616 dma_release_channel(qup->brx.dma);
617 qup->btx.dma = NULL;
618 qup->brx.dma = NULL;
619}
620
621static int qup_i2c_req_dma(struct qup_i2c_dev *qup)
622{
623 int err;
624
625 if (!qup->btx.dma) {
626 qup->btx.dma = dma_request_chan(qup->dev, "tx");
627 if (IS_ERR(qup->btx.dma)) {
628 err = PTR_ERR(qup->btx.dma);
629 qup->btx.dma = NULL;
630 dev_err(qup->dev, "\n tx channel not available");
631 return err;
632 }
633 }
634
635 if (!qup->brx.dma) {
636 qup->brx.dma = dma_request_chan(qup->dev, "rx");
637 if (IS_ERR(qup->brx.dma)) {
638 dev_err(qup->dev, "\n rx channel not available");
639 err = PTR_ERR(qup->brx.dma);
640 qup->brx.dma = NULL;
641 qup_i2c_rel_dma(qup);
642 return err;
643 }
644 }
645 return 0;
646}
647
648static int qup_i2c_bam_make_desc(struct qup_i2c_dev *qup, struct i2c_msg *msg)
649{
650 int ret = 0, limit = QUP_READ_LIMIT;
651 u32 len = 0, blocks, rem;
652 u32 i = 0, tlen, tx_len = 0;
653 u8 *tags;
654
655 qup->blk_xfer_limit = QUP_READ_LIMIT;
656 qup_i2c_set_blk_data(qup, msg);
657
658 blocks = qup->blk.count;
659 rem = msg->len - (blocks - 1) * limit;
660
661 if (msg->flags & I2C_M_RD) {
662 while (qup->blk.pos < blocks) {
663 tlen = (i == (blocks - 1)) ? rem : limit;
664 tags = &qup->start_tag.start[qup->tag_buf_pos + len];
665 len += qup_i2c_set_tags(tags, qup, msg);
666 qup->blk.data_len -= tlen;
667
668 /* scratch buf to read the start and len tags */
669 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++],
670 &qup->brx.tag.start[0],
671 2, qup, DMA_FROM_DEVICE);
672
673 if (ret)
674 return ret;
675
676 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++],
677 &msg->buf[limit * i],
678 tlen, qup,
679 DMA_FROM_DEVICE);
680 if (ret)
681 return ret;
682
683 i++;
684 qup->blk.pos = i;
685 }
686 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
687 &qup->start_tag.start[qup->tag_buf_pos],
688 len, qup, DMA_TO_DEVICE);
689 if (ret)
690 return ret;
691
692 qup->tag_buf_pos += len;
693 } else {
694 while (qup->blk.pos < blocks) {
695 tlen = (i == (blocks - 1)) ? rem : limit;
696 tags = &qup->start_tag.start[qup->tag_buf_pos + tx_len];
697 len = qup_i2c_set_tags(tags, qup, msg);
698 qup->blk.data_len -= tlen;
699
700 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
701 tags, len,
702 qup, DMA_TO_DEVICE);
703 if (ret)
704 return ret;
705
706 tx_len += len;
707 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
708 &msg->buf[limit * i],
709 tlen, qup, DMA_TO_DEVICE);
710 if (ret)
711 return ret;
712 i++;
713 qup->blk.pos = i;
714 }
715
716 qup->tag_buf_pos += tx_len;
717 }
718
719 return 0;
720}
721
722static int qup_i2c_bam_schedule_desc(struct qup_i2c_dev *qup)
723{
724 struct dma_async_tx_descriptor *txd, *rxd = NULL;
725 int ret = 0;
726 dma_cookie_t cookie_rx, cookie_tx;
727 u32 len = 0;
728 u32 tx_cnt = qup->btx.sg_cnt, rx_cnt = qup->brx.sg_cnt;
729
730 /* schedule the EOT and FLUSH I2C tags */
731 len = 1;
732 if (rx_cnt) {
733 qup->btx.tag.start[0] = QUP_BAM_INPUT_EOT;
734 len++;
735
736 /* scratch buf to read the BAM EOT FLUSH tags */
737 ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++],
738 &qup->brx.tag.start[0],
739 1, qup, DMA_FROM_DEVICE);
740 if (ret)
741 return ret;
742 }
743
744 qup->btx.tag.start[len - 1] = QUP_BAM_FLUSH_STOP;
745 ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++], &qup->btx.tag.start[0],
746 len, qup, DMA_TO_DEVICE);
747 if (ret)
748 return ret;
749
750 txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_cnt,
751 DMA_MEM_TO_DEV,
752 DMA_PREP_INTERRUPT | DMA_PREP_FENCE);
753 if (!txd) {
754 dev_err(qup->dev, "failed to get tx desc\n");
755 ret = -EINVAL;
756 goto desc_err;
757 }
758
759 if (!rx_cnt) {
760 txd->callback = qup_i2c_bam_cb;
761 txd->callback_param = qup;
762 }
763
764 cookie_tx = dmaengine_submit(txd);
765 if (dma_submit_error(cookie_tx)) {
766 ret = -EINVAL;
767 goto desc_err;
768 }
769
770 dma_async_issue_pending(qup->btx.dma);
771
772 if (rx_cnt) {
773 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg,
774 rx_cnt, DMA_DEV_TO_MEM,
775 DMA_PREP_INTERRUPT);
776 if (!rxd) {
777 dev_err(qup->dev, "failed to get rx desc\n");
778 ret = -EINVAL;
779
780 /* abort TX descriptors */
781 dmaengine_terminate_sync(qup->btx.dma);
782 goto desc_err;
783 }
784
785 rxd->callback = qup_i2c_bam_cb;
786 rxd->callback_param = qup;
787 cookie_rx = dmaengine_submit(rxd);
788 if (dma_submit_error(cookie_rx)) {
789 ret = -EINVAL;
790 goto desc_err;
791 }
792
793 dma_async_issue_pending(qup->brx.dma);
794 }
795
796 if (!wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout)) {
797 dev_err(qup->dev, "normal trans timed out\n");
798 ret = -ETIMEDOUT;
799 }
800
801 if (ret || qup->bus_err || qup->qup_err) {
802 reinit_completion(&qup->xfer);
803
804 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
805 if (ret) {
806 dev_err(qup->dev, "change to run state timed out");
807 goto desc_err;
808 }
809
810 qup_i2c_flush(qup);
811
812 /* wait for remaining interrupts to occur */
813 if (!wait_for_completion_timeout(&qup->xfer, HZ))
814 dev_err(qup->dev, "flush timed out\n");
815
816 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
817 }
818
819desc_err:
820 dma_unmap_sg(qup->dev, qup->btx.sg, tx_cnt, DMA_TO_DEVICE);
821
822 if (rx_cnt)
823 dma_unmap_sg(qup->dev, qup->brx.sg, rx_cnt,
824 DMA_FROM_DEVICE);
825
826 return ret;
827}
828
829static void qup_i2c_bam_clear_tag_buffers(struct qup_i2c_dev *qup)
830{
831 qup->btx.sg_cnt = 0;
832 qup->brx.sg_cnt = 0;
833 qup->tag_buf_pos = 0;
834}
835
836static int qup_i2c_bam_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
837 int num)
838{
839 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
840 int ret = 0;
841 int idx = 0;
842
843 enable_irq(qup->irq);
844 ret = qup_i2c_req_dma(qup);
845
846 if (ret)
847 goto out;
848
849 writel(0, qup->base + QUP_MX_INPUT_CNT);
850 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
851
852 /* set BAM mode */
853 writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE);
854
855 /* mask fifo irqs */
856 writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK);
857
858 /* set RUN STATE */
859 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
860 if (ret)
861 goto out;
862
863 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
864 qup_i2c_bam_clear_tag_buffers(qup);
865
866 for (idx = 0; idx < num; idx++) {
867 qup->msg = msg + idx;
868 qup->is_last = idx == (num - 1);
869
870 ret = qup_i2c_bam_make_desc(qup, qup->msg);
871 if (ret)
872 break;
873
874 /*
875 * Make DMA descriptor and schedule the BAM transfer if its
876 * already crossed the maximum length. Since the memory for all
877 * tags buffers have been taken for 2 maximum possible
878 * transfers length so it will never cross the buffer actual
879 * length.
880 */
881 if (qup->btx.sg_cnt > qup->max_xfer_sg_len ||
882 qup->brx.sg_cnt > qup->max_xfer_sg_len ||
883 qup->is_last) {
884 ret = qup_i2c_bam_schedule_desc(qup);
885 if (ret)
886 break;
887
888 qup_i2c_bam_clear_tag_buffers(qup);
889 }
890 }
891
892out:
893 disable_irq(qup->irq);
894
895 qup->msg = NULL;
896 return ret;
897}
898
899static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup,
900 struct i2c_msg *msg)
901{
902 unsigned long left;
903 int ret = 0;
904
905 left = wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout);
906 if (!left) {
907 writel(1, qup->base + QUP_SW_RESET);
908 ret = -ETIMEDOUT;
909 }
910
911 if (qup->bus_err || qup->qup_err)
912 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
913
914 return ret;
915}
916
917static void qup_i2c_read_rx_fifo_v1(struct qup_i2c_dev *qup)
918{
919 struct qup_i2c_block *blk = &qup->blk;
920 struct i2c_msg *msg = qup->msg;
921 u32 val = 0;
922 int idx = 0;
923
924 while (blk->fifo_available && qup->pos < msg->len) {
925 if ((idx & 1) == 0) {
926 /* Reading 2 words at time */
927 val = readl(qup->base + QUP_IN_FIFO_BASE);
928 msg->buf[qup->pos++] = val & 0xFF;
929 } else {
930 msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
931 }
932 idx++;
933 blk->fifo_available--;
934 }
935
936 if (qup->pos == msg->len)
937 blk->rx_bytes_read = true;
938}
939
940static void qup_i2c_write_rx_tags_v1(struct qup_i2c_dev *qup)
941{
942 struct i2c_msg *msg = qup->msg;
943 u32 addr, len, val;
944
945 addr = i2c_8bit_addr_from_msg(msg);
946
947 /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
948 len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
949
950 val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
951 writel(val, qup->base + QUP_OUT_FIFO_BASE);
952}
953
954static void qup_i2c_conf_v1(struct qup_i2c_dev *qup)
955{
956 struct qup_i2c_block *blk = &qup->blk;
957 u32 qup_config = I2C_MINI_CORE | I2C_N_VAL;
958 u32 io_mode = QUP_REPACK_EN;
959
960 blk->is_tx_blk_mode = blk->total_tx_len > qup->out_fifo_sz;
961 blk->is_rx_blk_mode = blk->total_rx_len > qup->in_fifo_sz;
962
963 if (blk->is_tx_blk_mode) {
964 io_mode |= QUP_OUTPUT_BLK_MODE;
965 writel(0, qup->base + QUP_MX_WRITE_CNT);
966 writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT);
967 } else {
968 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
969 writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT);
970 }
971
972 if (blk->total_rx_len) {
973 if (blk->is_rx_blk_mode) {
974 io_mode |= QUP_INPUT_BLK_MODE;
975 writel(0, qup->base + QUP_MX_READ_CNT);
976 writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT);
977 } else {
978 writel(0, qup->base + QUP_MX_INPUT_CNT);
979 writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT);
980 }
981 } else {
982 qup_config |= QUP_NO_INPUT;
983 }
984
985 writel(qup_config, qup->base + QUP_CONFIG);
986 writel(io_mode, qup->base + QUP_IO_MODE);
987}
988
989static void qup_i2c_clear_blk_v1(struct qup_i2c_block *blk)
990{
991 blk->tx_fifo_free = 0;
992 blk->fifo_available = 0;
993 blk->rx_bytes_read = false;
994}
995
996static int qup_i2c_conf_xfer_v1(struct qup_i2c_dev *qup, bool is_rx)
997{
998 struct qup_i2c_block *blk = &qup->blk;
999 int ret;
1000
1001 qup_i2c_clear_blk_v1(blk);
1002 qup_i2c_conf_v1(qup);
1003 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1004 if (ret)
1005 return ret;
1006
1007 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1008
1009 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1010 if (ret)
1011 return ret;
1012
1013 reinit_completion(&qup->xfer);
1014 enable_irq(qup->irq);
1015 if (!blk->is_tx_blk_mode) {
1016 blk->tx_fifo_free = qup->out_fifo_sz;
1017
1018 if (is_rx)
1019 qup_i2c_write_rx_tags_v1(qup);
1020 else
1021 qup_i2c_write_tx_fifo_v1(qup);
1022 }
1023
1024 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1025 if (ret)
1026 goto err;
1027
1028 ret = qup_i2c_wait_for_complete(qup, qup->msg);
1029 if (ret)
1030 goto err;
1031
1032 ret = qup_i2c_bus_active(qup, ONE_BYTE);
1033
1034err:
1035 disable_irq(qup->irq);
1036 return ret;
1037}
1038
1039static int qup_i2c_write_one(struct qup_i2c_dev *qup)
1040{
1041 struct i2c_msg *msg = qup->msg;
1042 struct qup_i2c_block *blk = &qup->blk;
1043
1044 qup->pos = 0;
1045 blk->total_tx_len = msg->len + 1;
1046 blk->total_rx_len = 0;
1047
1048 return qup_i2c_conf_xfer_v1(qup, false);
1049}
1050
1051static int qup_i2c_read_one(struct qup_i2c_dev *qup)
1052{
1053 struct qup_i2c_block *blk = &qup->blk;
1054
1055 qup->pos = 0;
1056 blk->total_tx_len = 2;
1057 blk->total_rx_len = qup->msg->len;
1058
1059 return qup_i2c_conf_xfer_v1(qup, true);
1060}
1061
1062static int qup_i2c_xfer(struct i2c_adapter *adap,
1063 struct i2c_msg msgs[],
1064 int num)
1065{
1066 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1067 int ret, idx;
1068
1069 ret = pm_runtime_get_sync(qup->dev);
1070 if (ret < 0)
1071 goto out;
1072
1073 qup->bus_err = 0;
1074 qup->qup_err = 0;
1075
1076 writel(1, qup->base + QUP_SW_RESET);
1077 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1078 if (ret)
1079 goto out;
1080
1081 /* Configure QUP as I2C mini core */
1082 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);
1083
1084 for (idx = 0; idx < num; idx++) {
1085 if (qup_i2c_poll_state_i2c_master(qup)) {
1086 ret = -EIO;
1087 goto out;
1088 }
1089
1090 if (qup_i2c_check_msg_len(&msgs[idx])) {
1091 ret = -EINVAL;
1092 goto out;
1093 }
1094
1095 qup->msg = &msgs[idx];
1096 if (msgs[idx].flags & I2C_M_RD)
1097 ret = qup_i2c_read_one(qup);
1098 else
1099 ret = qup_i2c_write_one(qup);
1100
1101 if (ret)
1102 break;
1103
1104 ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
1105 if (ret)
1106 break;
1107 }
1108
1109 if (ret == 0)
1110 ret = num;
1111out:
1112
1113 pm_runtime_mark_last_busy(qup->dev);
1114 pm_runtime_put_autosuspend(qup->dev);
1115
1116 return ret;
1117}
1118
1119/*
1120 * Configure registers related with reconfiguration during run and call it
1121 * before each i2c sub transfer.
1122 */
1123static void qup_i2c_conf_count_v2(struct qup_i2c_dev *qup)
1124{
1125 struct qup_i2c_block *blk = &qup->blk;
1126 u32 qup_config = I2C_MINI_CORE | I2C_N_VAL_V2;
1127
1128 if (blk->is_tx_blk_mode)
1129 writel(qup->config_run | blk->total_tx_len,
1130 qup->base + QUP_MX_OUTPUT_CNT);
1131 else
1132 writel(qup->config_run | blk->total_tx_len,
1133 qup->base + QUP_MX_WRITE_CNT);
1134
1135 if (blk->total_rx_len) {
1136 if (blk->is_rx_blk_mode)
1137 writel(qup->config_run | blk->total_rx_len,
1138 qup->base + QUP_MX_INPUT_CNT);
1139 else
1140 writel(qup->config_run | blk->total_rx_len,
1141 qup->base + QUP_MX_READ_CNT);
1142 } else {
1143 qup_config |= QUP_NO_INPUT;
1144 }
1145
1146 writel(qup_config, qup->base + QUP_CONFIG);
1147}
1148
1149/*
1150 * Configure registers related with transfer mode (FIFO/Block)
1151 * before starting of i2c transfer. It will be called only once in
1152 * QUP RESET state.
1153 */
1154static void qup_i2c_conf_mode_v2(struct qup_i2c_dev *qup)
1155{
1156 struct qup_i2c_block *blk = &qup->blk;
1157 u32 io_mode = QUP_REPACK_EN;
1158
1159 if (blk->is_tx_blk_mode) {
1160 io_mode |= QUP_OUTPUT_BLK_MODE;
1161 writel(0, qup->base + QUP_MX_WRITE_CNT);
1162 } else {
1163 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
1164 }
1165
1166 if (blk->is_rx_blk_mode) {
1167 io_mode |= QUP_INPUT_BLK_MODE;
1168 writel(0, qup->base + QUP_MX_READ_CNT);
1169 } else {
1170 writel(0, qup->base + QUP_MX_INPUT_CNT);
1171 }
1172
1173 writel(io_mode, qup->base + QUP_IO_MODE);
1174}
1175
1176/* Clear required variables before starting of any QUP v2 sub transfer. */
1177static void qup_i2c_clear_blk_v2(struct qup_i2c_block *blk)
1178{
1179 blk->send_last_word = false;
1180 blk->tx_tags_sent = false;
1181 blk->tx_fifo_data = 0;
1182 blk->tx_fifo_data_pos = 0;
1183 blk->tx_fifo_free = 0;
1184
1185 blk->rx_tags_fetched = false;
1186 blk->rx_bytes_read = false;
1187 blk->rx_fifo_data = 0;
1188 blk->rx_fifo_data_pos = 0;
1189 blk->fifo_available = 0;
1190}
1191
1192/* Receive data from RX FIFO for read message in QUP v2 i2c transfer. */
1193static void qup_i2c_recv_data(struct qup_i2c_dev *qup)
1194{
1195 struct qup_i2c_block *blk = &qup->blk;
1196 int j;
1197
1198 for (j = blk->rx_fifo_data_pos;
1199 blk->cur_blk_len && blk->fifo_available;
1200 blk->cur_blk_len--, blk->fifo_available--) {
1201 if (j == 0)
1202 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE);
1203
1204 *(blk->cur_data++) = blk->rx_fifo_data;
1205 blk->rx_fifo_data >>= 8;
1206
1207 if (j == 3)
1208 j = 0;
1209 else
1210 j++;
1211 }
1212
1213 blk->rx_fifo_data_pos = j;
1214}
1215
1216/* Receive tags for read message in QUP v2 i2c transfer. */
1217static void qup_i2c_recv_tags(struct qup_i2c_dev *qup)
1218{
1219 struct qup_i2c_block *blk = &qup->blk;
1220
1221 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE);
1222 blk->rx_fifo_data >>= blk->rx_tag_len * 8;
1223 blk->rx_fifo_data_pos = blk->rx_tag_len;
1224 blk->fifo_available -= blk->rx_tag_len;
1225}
1226
1227/*
1228 * Read the data and tags from RX FIFO. Since in read case, the tags will be
1229 * preceded by received data bytes so
1230 * 1. Check if rx_tags_fetched is false i.e. the start of QUP block so receive
1231 * all tag bytes and discard that.
1232 * 2. Read the data from RX FIFO. When all the data bytes have been read then
1233 * set rx_bytes_read to true.
1234 */
1235static void qup_i2c_read_rx_fifo_v2(struct qup_i2c_dev *qup)
1236{
1237 struct qup_i2c_block *blk = &qup->blk;
1238
1239 if (!blk->rx_tags_fetched) {
1240 qup_i2c_recv_tags(qup);
1241 blk->rx_tags_fetched = true;
1242 }
1243
1244 qup_i2c_recv_data(qup);
1245 if (!blk->cur_blk_len)
1246 blk->rx_bytes_read = true;
1247}
1248
1249/*
1250 * Write bytes in TX FIFO for write message in QUP v2 i2c transfer. QUP TX FIFO
1251 * write works on word basis (4 bytes). Append new data byte write for TX FIFO
1252 * in tx_fifo_data and write to TX FIFO when all the 4 bytes are present.
1253 */
1254static void
1255qup_i2c_write_blk_data(struct qup_i2c_dev *qup, u8 **data, unsigned int *len)
1256{
1257 struct qup_i2c_block *blk = &qup->blk;
1258 unsigned int j;
1259
1260 for (j = blk->tx_fifo_data_pos; *len && blk->tx_fifo_free;
1261 (*len)--, blk->tx_fifo_free--) {
1262 blk->tx_fifo_data |= *(*data)++ << (j * 8);
1263 if (j == 3) {
1264 writel(blk->tx_fifo_data,
1265 qup->base + QUP_OUT_FIFO_BASE);
1266 blk->tx_fifo_data = 0x0;
1267 j = 0;
1268 } else {
1269 j++;
1270 }
1271 }
1272
1273 blk->tx_fifo_data_pos = j;
1274}
1275
1276/* Transfer tags for read message in QUP v2 i2c transfer. */
1277static void qup_i2c_write_rx_tags_v2(struct qup_i2c_dev *qup)
1278{
1279 struct qup_i2c_block *blk = &qup->blk;
1280
1281 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, &blk->tx_tag_len);
1282 if (blk->tx_fifo_data_pos)
1283 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE);
1284}
1285
1286/*
1287 * Write the data and tags in TX FIFO. Since in write case, both tags and data
1288 * need to be written and QUP write tags can have maximum 256 data length, so
1289 *
1290 * 1. Check if tx_tags_sent is false i.e. the start of QUP block so write the
1291 * tags to TX FIFO and set tx_tags_sent to true.
1292 * 2. Check if send_last_word is true. It will be set when last few data bytes
1293 * (less than 4 bytes) are remaining to be written in FIFO because of no FIFO
1294 * space. All this data bytes are available in tx_fifo_data so write this
1295 * in FIFO.
1296 * 3. Write the data to TX FIFO and check for cur_blk_len. If it is non zero
1297 * then more data is pending otherwise following 3 cases can be possible
1298 * a. if tx_fifo_data_pos is zero i.e. all the data bytes in this block
1299 * have been written in TX FIFO so nothing else is required.
1300 * b. tx_fifo_free is non zero i.e tx FIFO is free so copy the remaining data
1301 * from tx_fifo_data to tx FIFO. Since, qup_i2c_write_blk_data do write
1302 * in 4 bytes and FIFO space is in multiple of 4 bytes so tx_fifo_free
1303 * will be always greater than or equal to 4 bytes.
1304 * c. tx_fifo_free is zero. In this case, last few bytes (less than 4
1305 * bytes) are copied to tx_fifo_data but couldn't be sent because of
1306 * FIFO full so make send_last_word true.
1307 */
1308static void qup_i2c_write_tx_fifo_v2(struct qup_i2c_dev *qup)
1309{
1310 struct qup_i2c_block *blk = &qup->blk;
1311
1312 if (!blk->tx_tags_sent) {
1313 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags,
1314 &blk->tx_tag_len);
1315 blk->tx_tags_sent = true;
1316 }
1317
1318 if (blk->send_last_word)
1319 goto send_last_word;
1320
1321 qup_i2c_write_blk_data(qup, &blk->cur_data, &blk->cur_blk_len);
1322 if (!blk->cur_blk_len) {
1323 if (!blk->tx_fifo_data_pos)
1324 return;
1325
1326 if (blk->tx_fifo_free)
1327 goto send_last_word;
1328
1329 blk->send_last_word = true;
1330 }
1331
1332 return;
1333
1334send_last_word:
1335 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE);
1336}
1337
1338/*
1339 * Main transfer function which read or write i2c data.
1340 * The QUP v2 supports reconfiguration during run in which multiple i2c sub
1341 * transfers can be scheduled.
1342 */
1343static int
1344qup_i2c_conf_xfer_v2(struct qup_i2c_dev *qup, bool is_rx, bool is_first,
1345 bool change_pause_state)
1346{
1347 struct qup_i2c_block *blk = &qup->blk;
1348 struct i2c_msg *msg = qup->msg;
1349 int ret;
1350
1351 /*
1352 * Check if its SMBus Block read for which the top level read will be
1353 * done into 2 QUP reads. One with message length 1 while other one is
1354 * with actual length.
1355 */
1356 if (qup_i2c_check_msg_len(msg)) {
1357 if (qup->is_smbus_read) {
1358 /*
1359 * If the message length is already read in
1360 * the first byte of the buffer, account for
1361 * that by setting the offset
1362 */
1363 blk->cur_data += 1;
1364 is_first = false;
1365 } else {
1366 change_pause_state = false;
1367 }
1368 }
1369
1370 qup->config_run = is_first ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN;
1371
1372 qup_i2c_clear_blk_v2(blk);
1373 qup_i2c_conf_count_v2(qup);
1374
1375 /* If it is first sub transfer, then configure i2c bus clocks */
1376 if (is_first) {
1377 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1378 if (ret)
1379 return ret;
1380
1381 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1382
1383 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1384 if (ret)
1385 return ret;
1386 }
1387
1388 reinit_completion(&qup->xfer);
1389 enable_irq(qup->irq);
1390 /*
1391 * In FIFO mode, tx FIFO can be written directly while in block mode the
1392 * it will be written after getting OUT_BLOCK_WRITE_REQ interrupt
1393 */
1394 if (!blk->is_tx_blk_mode) {
1395 blk->tx_fifo_free = qup->out_fifo_sz;
1396
1397 if (is_rx)
1398 qup_i2c_write_rx_tags_v2(qup);
1399 else
1400 qup_i2c_write_tx_fifo_v2(qup);
1401 }
1402
1403 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1404 if (ret)
1405 goto err;
1406
1407 ret = qup_i2c_wait_for_complete(qup, msg);
1408 if (ret)
1409 goto err;
1410
1411 /* Move to pause state for all the transfers, except last one */
1412 if (change_pause_state) {
1413 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1414 if (ret)
1415 goto err;
1416 }
1417
1418err:
1419 disable_irq(qup->irq);
1420 return ret;
1421}
1422
1423/*
1424 * Transfer one read/write message in i2c transfer. It splits the message into
1425 * multiple of blk_xfer_limit data length blocks and schedule each
1426 * QUP block individually.
1427 */
1428static int qup_i2c_xfer_v2_msg(struct qup_i2c_dev *qup, int msg_id, bool is_rx)
1429{
1430 int ret = 0;
1431 unsigned int data_len, i;
1432 struct i2c_msg *msg = qup->msg;
1433 struct qup_i2c_block *blk = &qup->blk;
1434 u8 *msg_buf = msg->buf;
1435
1436 qup->blk_xfer_limit = is_rx ? RECV_MAX_DATA_LEN : QUP_READ_LIMIT;
1437 qup_i2c_set_blk_data(qup, msg);
1438
1439 for (i = 0; i < blk->count; i++) {
1440 data_len = qup_i2c_get_data_len(qup);
1441 blk->pos = i;
1442 blk->cur_tx_tags = blk->tags;
1443 blk->cur_blk_len = data_len;
1444 blk->tx_tag_len =
1445 qup_i2c_set_tags(blk->cur_tx_tags, qup, qup->msg);
1446
1447 blk->cur_data = msg_buf;
1448
1449 if (is_rx) {
1450 blk->total_tx_len = blk->tx_tag_len;
1451 blk->rx_tag_len = 2;
1452 blk->total_rx_len = blk->rx_tag_len + data_len;
1453 } else {
1454 blk->total_tx_len = blk->tx_tag_len + data_len;
1455 blk->total_rx_len = 0;
1456 }
1457
1458 ret = qup_i2c_conf_xfer_v2(qup, is_rx, !msg_id && !i,
1459 !qup->is_last || i < blk->count - 1);
1460 if (ret)
1461 return ret;
1462
1463 /* Handle SMBus block read length */
1464 if (qup_i2c_check_msg_len(msg) && msg->len == 1 &&
1465 !qup->is_smbus_read) {
1466 if (msg->buf[0] > I2C_SMBUS_BLOCK_MAX)
1467 return -EPROTO;
1468
1469 msg->len = msg->buf[0];
1470 qup->is_smbus_read = true;
1471 ret = qup_i2c_xfer_v2_msg(qup, msg_id, true);
1472 qup->is_smbus_read = false;
1473 if (ret)
1474 return ret;
1475
1476 msg->len += 1;
1477 }
1478
1479 msg_buf += data_len;
1480 blk->data_len -= qup->blk_xfer_limit;
1481 }
1482
1483 return ret;
1484}
1485
1486/*
1487 * QUP v2 supports 3 modes
1488 * Programmed IO using FIFO mode : Less than FIFO size
1489 * Programmed IO using Block mode : Greater than FIFO size
1490 * DMA using BAM : Appropriate for any transaction size but the address should
1491 * be DMA applicable
1492 *
1493 * This function determines the mode which will be used for this transfer. An
1494 * i2c transfer contains multiple message. Following are the rules to determine
1495 * the mode used.
1496 * 1. Determine complete length, maximum tx and rx length for complete transfer.
1497 * 2. If complete transfer length is greater than fifo size then use the DMA
1498 * mode.
1499 * 3. In FIFO or block mode, tx and rx can operate in different mode so check
1500 * for maximum tx and rx length to determine mode.
1501 */
1502static int
1503qup_i2c_determine_mode_v2(struct qup_i2c_dev *qup,
1504 struct i2c_msg msgs[], int num)
1505{
1506 int idx;
1507 bool no_dma = false;
1508 unsigned int max_tx_len = 0, max_rx_len = 0, total_len = 0;
1509
1510 /* All i2c_msgs should be transferred using either dma or cpu */
1511 for (idx = 0; idx < num; idx++) {
1512 if (msgs[idx].flags & I2C_M_RD)
1513 max_rx_len = max_t(unsigned int, max_rx_len,
1514 msgs[idx].len);
1515 else
1516 max_tx_len = max_t(unsigned int, max_tx_len,
1517 msgs[idx].len);
1518
1519 if (is_vmalloc_addr(msgs[idx].buf))
1520 no_dma = true;
1521
1522 total_len += msgs[idx].len;
1523 }
1524
1525 if (!no_dma && qup->is_dma &&
1526 (total_len > qup->out_fifo_sz || total_len > qup->in_fifo_sz)) {
1527 qup->use_dma = true;
1528 } else {
1529 qup->blk.is_tx_blk_mode = max_tx_len > qup->out_fifo_sz -
1530 QUP_MAX_TAGS_LEN;
1531 qup->blk.is_rx_blk_mode = max_rx_len > qup->in_fifo_sz -
1532 READ_RX_TAGS_LEN;
1533 }
1534
1535 return 0;
1536}
1537
1538static int qup_i2c_xfer_v2(struct i2c_adapter *adap,
1539 struct i2c_msg msgs[],
1540 int num)
1541{
1542 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1543 int ret, idx = 0;
1544
1545 qup->bus_err = 0;
1546 qup->qup_err = 0;
1547
1548 ret = pm_runtime_get_sync(qup->dev);
1549 if (ret < 0)
1550 goto out;
1551
1552 ret = qup_i2c_determine_mode_v2(qup, msgs, num);
1553 if (ret)
1554 goto out;
1555
1556 writel(1, qup->base + QUP_SW_RESET);
1557 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1558 if (ret)
1559 goto out;
1560
1561 /* Configure QUP as I2C mini core */
1562 writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG);
1563 writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN);
1564
1565 if (qup_i2c_poll_state_i2c_master(qup)) {
1566 ret = -EIO;
1567 goto out;
1568 }
1569
1570 if (qup->use_dma) {
1571 reinit_completion(&qup->xfer);
1572 ret = qup_i2c_bam_xfer(adap, &msgs[0], num);
1573 qup->use_dma = false;
1574 } else {
1575 qup_i2c_conf_mode_v2(qup);
1576
1577 for (idx = 0; idx < num; idx++) {
1578 qup->msg = &msgs[idx];
1579 qup->is_last = idx == (num - 1);
1580
1581 ret = qup_i2c_xfer_v2_msg(qup, idx,
1582 !!(msgs[idx].flags & I2C_M_RD));
1583 if (ret)
1584 break;
1585 }
1586 qup->msg = NULL;
1587 }
1588
1589 if (!ret)
1590 ret = qup_i2c_bus_active(qup, ONE_BYTE);
1591
1592 if (!ret)
1593 qup_i2c_change_state(qup, QUP_RESET_STATE);
1594
1595 if (ret == 0)
1596 ret = num;
1597out:
1598 pm_runtime_mark_last_busy(qup->dev);
1599 pm_runtime_put_autosuspend(qup->dev);
1600
1601 return ret;
1602}
1603
1604static u32 qup_i2c_func(struct i2c_adapter *adap)
1605{
1606 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL_ALL & ~I2C_FUNC_SMBUS_QUICK);
1607}
1608
1609static const struct i2c_algorithm qup_i2c_algo = {
1610 .master_xfer = qup_i2c_xfer,
1611 .functionality = qup_i2c_func,
1612};
1613
1614static const struct i2c_algorithm qup_i2c_algo_v2 = {
1615 .master_xfer = qup_i2c_xfer_v2,
1616 .functionality = qup_i2c_func,
1617};
1618
1619/*
1620 * The QUP block will issue a NACK and STOP on the bus when reaching
1621 * the end of the read, the length of the read is specified as one byte
1622 * which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
1623 */
1624static const struct i2c_adapter_quirks qup_i2c_quirks = {
1625 .flags = I2C_AQ_NO_ZERO_LEN,
1626 .max_read_len = QUP_READ_LIMIT,
1627};
1628
1629static const struct i2c_adapter_quirks qup_i2c_quirks_v2 = {
1630 .flags = I2C_AQ_NO_ZERO_LEN,
1631};
1632
1633static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
1634{
1635 clk_prepare_enable(qup->clk);
1636 clk_prepare_enable(qup->pclk);
1637}
1638
1639static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)
1640{
1641 u32 config;
1642
1643 qup_i2c_change_state(qup, QUP_RESET_STATE);
1644 clk_disable_unprepare(qup->clk);
1645 config = readl(qup->base + QUP_CONFIG);
1646 config |= QUP_CLOCK_AUTO_GATE;
1647 writel(config, qup->base + QUP_CONFIG);
1648 clk_disable_unprepare(qup->pclk);
1649}
1650
1651static const struct acpi_device_id qup_i2c_acpi_match[] = {
1652 { "QCOM8010"},
1653 { },
1654};
1655MODULE_DEVICE_TABLE(acpi, qup_i2c_acpi_match);
1656
1657static int qup_i2c_probe(struct platform_device *pdev)
1658{
1659 static const int blk_sizes[] = {4, 16, 32};
1660 struct qup_i2c_dev *qup;
1661 unsigned long one_bit_t;
1662 u32 io_mode, hw_ver, size;
1663 int ret, fs_div, hs_div;
1664 u32 src_clk_freq = DEFAULT_SRC_CLK;
1665 u32 clk_freq = DEFAULT_CLK_FREQ;
1666 int blocks;
1667 bool is_qup_v1;
1668
1669 qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
1670 if (!qup)
1671 return -ENOMEM;
1672
1673 qup->dev = &pdev->dev;
1674 init_completion(&qup->xfer);
1675 platform_set_drvdata(pdev, qup);
1676
1677 if (scl_freq) {
1678 dev_notice(qup->dev, "Using override frequency of %u\n", scl_freq);
1679 clk_freq = scl_freq;
1680 } else {
1681 ret = device_property_read_u32(qup->dev, "clock-frequency", &clk_freq);
1682 if (ret) {
1683 dev_notice(qup->dev, "using default clock-frequency %d",
1684 DEFAULT_CLK_FREQ);
1685 }
1686 }
1687
1688 if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) {
1689 qup->adap.algo = &qup_i2c_algo;
1690 qup->adap.quirks = &qup_i2c_quirks;
1691 is_qup_v1 = true;
1692 } else {
1693 qup->adap.algo = &qup_i2c_algo_v2;
1694 qup->adap.quirks = &qup_i2c_quirks_v2;
1695 is_qup_v1 = false;
1696 if (acpi_match_device(qup_i2c_acpi_match, qup->dev))
1697 goto nodma;
1698 else
1699 ret = qup_i2c_req_dma(qup);
1700
1701 if (ret == -EPROBE_DEFER)
1702 goto fail_dma;
1703 else if (ret != 0)
1704 goto nodma;
1705
1706 qup->max_xfer_sg_len = (MX_BLOCKS << 1);
1707 blocks = (MX_DMA_BLOCKS << 1) + 1;
1708 qup->btx.sg = devm_kcalloc(&pdev->dev,
1709 blocks, sizeof(*qup->btx.sg),
1710 GFP_KERNEL);
1711 if (!qup->btx.sg) {
1712 ret = -ENOMEM;
1713 goto fail_dma;
1714 }
1715 sg_init_table(qup->btx.sg, blocks);
1716
1717 qup->brx.sg = devm_kcalloc(&pdev->dev,
1718 blocks, sizeof(*qup->brx.sg),
1719 GFP_KERNEL);
1720 if (!qup->brx.sg) {
1721 ret = -ENOMEM;
1722 goto fail_dma;
1723 }
1724 sg_init_table(qup->brx.sg, blocks);
1725
1726 /* 2 tag bytes for each block + 5 for start, stop tags */
1727 size = blocks * 2 + 5;
1728
1729 qup->start_tag.start = devm_kzalloc(&pdev->dev,
1730 size, GFP_KERNEL);
1731 if (!qup->start_tag.start) {
1732 ret = -ENOMEM;
1733 goto fail_dma;
1734 }
1735
1736 qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
1737 if (!qup->brx.tag.start) {
1738 ret = -ENOMEM;
1739 goto fail_dma;
1740 }
1741
1742 qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
1743 if (!qup->btx.tag.start) {
1744 ret = -ENOMEM;
1745 goto fail_dma;
1746 }
1747 qup->is_dma = true;
1748 }
1749
1750nodma:
1751 /* We support frequencies up to FAST Mode Plus (1MHz) */
1752 if (!clk_freq || clk_freq > I2C_MAX_FAST_MODE_PLUS_FREQ) {
1753 dev_err(qup->dev, "clock frequency not supported %d\n",
1754 clk_freq);
1755 ret = -EINVAL;
1756 goto fail_dma;
1757 }
1758
1759 qup->base = devm_platform_ioremap_resource(pdev, 0);
1760 if (IS_ERR(qup->base)) {
1761 ret = PTR_ERR(qup->base);
1762 goto fail_dma;
1763 }
1764
1765 qup->irq = platform_get_irq(pdev, 0);
1766 if (qup->irq < 0) {
1767 ret = qup->irq;
1768 goto fail_dma;
1769 }
1770
1771 if (has_acpi_companion(qup->dev)) {
1772 ret = device_property_read_u32(qup->dev,
1773 "src-clock-hz", &src_clk_freq);
1774 if (ret) {
1775 dev_notice(qup->dev, "using default src-clock-hz %d",
1776 DEFAULT_SRC_CLK);
1777 }
1778 ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev));
1779 } else {
1780 qup->clk = devm_clk_get(qup->dev, "core");
1781 if (IS_ERR(qup->clk)) {
1782 dev_err(qup->dev, "Could not get core clock\n");
1783 ret = PTR_ERR(qup->clk);
1784 goto fail_dma;
1785 }
1786
1787 qup->pclk = devm_clk_get(qup->dev, "iface");
1788 if (IS_ERR(qup->pclk)) {
1789 dev_err(qup->dev, "Could not get iface clock\n");
1790 ret = PTR_ERR(qup->pclk);
1791 goto fail_dma;
1792 }
1793 qup_i2c_enable_clocks(qup);
1794 src_clk_freq = clk_get_rate(qup->clk);
1795 }
1796
1797 /*
1798 * Bootloaders might leave a pending interrupt on certain QUP's,
1799 * so we reset the core before registering for interrupts.
1800 */
1801 writel(1, qup->base + QUP_SW_RESET);
1802 ret = qup_i2c_poll_state_valid(qup);
1803 if (ret)
1804 goto fail;
1805
1806 ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
1807 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN,
1808 "i2c_qup", qup);
1809 if (ret) {
1810 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
1811 goto fail;
1812 }
1813
1814 hw_ver = readl(qup->base + QUP_HW_VERSION);
1815 dev_dbg(qup->dev, "Revision %x\n", hw_ver);
1816
1817 io_mode = readl(qup->base + QUP_IO_MODE);
1818
1819 /*
1820 * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
1821 * associated with each byte written/received
1822 */
1823 size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
1824 if (size >= ARRAY_SIZE(blk_sizes)) {
1825 ret = -EIO;
1826 goto fail;
1827 }
1828 qup->out_blk_sz = blk_sizes[size];
1829
1830 size = QUP_INPUT_BLOCK_SIZE(io_mode);
1831 if (size >= ARRAY_SIZE(blk_sizes)) {
1832 ret = -EIO;
1833 goto fail;
1834 }
1835 qup->in_blk_sz = blk_sizes[size];
1836
1837 if (is_qup_v1) {
1838 /*
1839 * in QUP v1, QUP_CONFIG uses N as 15 i.e 16 bits constitutes a
1840 * single transfer but the block size is in bytes so divide the
1841 * in_blk_sz and out_blk_sz by 2
1842 */
1843 qup->in_blk_sz /= 2;
1844 qup->out_blk_sz /= 2;
1845 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1;
1846 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1;
1847 qup->write_rx_tags = qup_i2c_write_rx_tags_v1;
1848 } else {
1849 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v2;
1850 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v2;
1851 qup->write_rx_tags = qup_i2c_write_rx_tags_v2;
1852 }
1853
1854 size = QUP_OUTPUT_FIFO_SIZE(io_mode);
1855 qup->out_fifo_sz = qup->out_blk_sz * (2 << size);
1856
1857 size = QUP_INPUT_FIFO_SIZE(io_mode);
1858 qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
1859
1860 hs_div = 3;
1861 if (clk_freq <= I2C_MAX_STANDARD_MODE_FREQ) {
1862 fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
1863 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
1864 } else {
1865 /* 33%/66% duty cycle */
1866 fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3;
1867 qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff);
1868 }
1869
1870 /*
1871 * Time it takes for a byte to be clocked out on the bus.
1872 * Each byte takes 9 clock cycles (8 bits + 1 ack).
1873 */
1874 one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
1875 qup->one_byte_t = one_bit_t * 9;
1876 qup->xfer_timeout = TOUT_MIN * HZ +
1877 usecs_to_jiffies(MX_DMA_TX_RX_LEN * qup->one_byte_t);
1878
1879 dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
1880 qup->in_blk_sz, qup->in_fifo_sz,
1881 qup->out_blk_sz, qup->out_fifo_sz);
1882
1883 i2c_set_adapdata(&qup->adap, qup);
1884 qup->adap.dev.parent = qup->dev;
1885 qup->adap.dev.of_node = pdev->dev.of_node;
1886 qup->is_last = true;
1887
1888 strscpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
1889
1890 pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
1891 pm_runtime_use_autosuspend(qup->dev);
1892 pm_runtime_set_active(qup->dev);
1893 pm_runtime_enable(qup->dev);
1894
1895 ret = i2c_add_adapter(&qup->adap);
1896 if (ret)
1897 goto fail_runtime;
1898
1899 return 0;
1900
1901fail_runtime:
1902 pm_runtime_disable(qup->dev);
1903 pm_runtime_set_suspended(qup->dev);
1904fail:
1905 qup_i2c_disable_clocks(qup);
1906fail_dma:
1907 if (qup->btx.dma)
1908 dma_release_channel(qup->btx.dma);
1909 if (qup->brx.dma)
1910 dma_release_channel(qup->brx.dma);
1911 return ret;
1912}
1913
1914static void qup_i2c_remove(struct platform_device *pdev)
1915{
1916 struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
1917
1918 if (qup->is_dma) {
1919 dma_release_channel(qup->btx.dma);
1920 dma_release_channel(qup->brx.dma);
1921 }
1922
1923 disable_irq(qup->irq);
1924 qup_i2c_disable_clocks(qup);
1925 i2c_del_adapter(&qup->adap);
1926 pm_runtime_disable(qup->dev);
1927 pm_runtime_set_suspended(qup->dev);
1928}
1929
1930static int qup_i2c_pm_suspend_runtime(struct device *device)
1931{
1932 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1933
1934 dev_dbg(device, "pm_runtime: suspending...\n");
1935 qup_i2c_disable_clocks(qup);
1936 return 0;
1937}
1938
1939static int qup_i2c_pm_resume_runtime(struct device *device)
1940{
1941 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1942
1943 dev_dbg(device, "pm_runtime: resuming...\n");
1944 qup_i2c_enable_clocks(qup);
1945 return 0;
1946}
1947
1948static int qup_i2c_suspend(struct device *device)
1949{
1950 if (!pm_runtime_suspended(device))
1951 return qup_i2c_pm_suspend_runtime(device);
1952 return 0;
1953}
1954
1955static int qup_i2c_resume(struct device *device)
1956{
1957 qup_i2c_pm_resume_runtime(device);
1958 pm_runtime_mark_last_busy(device);
1959 pm_request_autosuspend(device);
1960 return 0;
1961}
1962
1963static const struct dev_pm_ops qup_i2c_qup_pm_ops = {
1964 SYSTEM_SLEEP_PM_OPS(qup_i2c_suspend, qup_i2c_resume)
1965 RUNTIME_PM_OPS(qup_i2c_pm_suspend_runtime,
1966 qup_i2c_pm_resume_runtime, NULL)
1967};
1968
1969static const struct of_device_id qup_i2c_dt_match[] = {
1970 { .compatible = "qcom,i2c-qup-v1.1.1" },
1971 { .compatible = "qcom,i2c-qup-v2.1.1" },
1972 { .compatible = "qcom,i2c-qup-v2.2.1" },
1973 {}
1974};
1975MODULE_DEVICE_TABLE(of, qup_i2c_dt_match);
1976
1977static struct platform_driver qup_i2c_driver = {
1978 .probe = qup_i2c_probe,
1979 .remove_new = qup_i2c_remove,
1980 .driver = {
1981 .name = "i2c_qup",
1982 .pm = pm_ptr(&qup_i2c_qup_pm_ops),
1983 .of_match_table = qup_i2c_dt_match,
1984 .acpi_match_table = ACPI_PTR(qup_i2c_acpi_match),
1985 },
1986};
1987
1988module_platform_driver(qup_i2c_driver);
1989
1990MODULE_LICENSE("GPL v2");
1991MODULE_ALIAS("platform:i2c_qup");