Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 1999 Eddie C. Dost (ecd@atecom.com)
4 */
5
6#include <linux/types.h>
7#include <linux/sched.h>
8
9#include <linux/uaccess.h>
10#include <asm/reg.h>
11#include <asm/switch_to.h>
12
13#include <asm/sfp-machine.h>
14#include <math-emu/double.h>
15
16#define FLOATFUNC(x) extern int x(void *, void *, void *, void *)
17
18/* The instructions list which may be not implemented by a hardware FPU */
19FLOATFUNC(fre);
20FLOATFUNC(frsqrtes);
21FLOATFUNC(fsqrt);
22FLOATFUNC(fsqrts);
23FLOATFUNC(mtfsf);
24FLOATFUNC(mtfsfi);
25
26#ifdef CONFIG_MATH_EMULATION_HW_UNIMPLEMENTED
27#undef FLOATFUNC
28#define FLOATFUNC(x) static inline int x(void *op1, void *op2, void *op3, \
29 void *op4) { return 0; }
30#endif
31
32FLOATFUNC(fadd);
33FLOATFUNC(fadds);
34FLOATFUNC(fdiv);
35FLOATFUNC(fdivs);
36FLOATFUNC(fmul);
37FLOATFUNC(fmuls);
38FLOATFUNC(fsub);
39FLOATFUNC(fsubs);
40
41FLOATFUNC(fmadd);
42FLOATFUNC(fmadds);
43FLOATFUNC(fmsub);
44FLOATFUNC(fmsubs);
45FLOATFUNC(fnmadd);
46FLOATFUNC(fnmadds);
47FLOATFUNC(fnmsub);
48FLOATFUNC(fnmsubs);
49
50FLOATFUNC(fctiw);
51FLOATFUNC(fctiwz);
52FLOATFUNC(frsp);
53
54FLOATFUNC(fcmpo);
55FLOATFUNC(fcmpu);
56
57FLOATFUNC(mcrfs);
58FLOATFUNC(mffs);
59FLOATFUNC(mtfsb0);
60FLOATFUNC(mtfsb1);
61
62FLOATFUNC(lfd);
63FLOATFUNC(lfs);
64
65FLOATFUNC(stfd);
66FLOATFUNC(stfs);
67FLOATFUNC(stfiwx);
68
69FLOATFUNC(fabs);
70FLOATFUNC(fmr);
71FLOATFUNC(fnabs);
72FLOATFUNC(fneg);
73
74/* Optional */
75FLOATFUNC(fres);
76FLOATFUNC(frsqrte);
77FLOATFUNC(fsel);
78
79
80#define OP31 0x1f /* 31 */
81#define LFS 0x30 /* 48 */
82#define LFSU 0x31 /* 49 */
83#define LFD 0x32 /* 50 */
84#define LFDU 0x33 /* 51 */
85#define STFS 0x34 /* 52 */
86#define STFSU 0x35 /* 53 */
87#define STFD 0x36 /* 54 */
88#define STFDU 0x37 /* 55 */
89#define OP59 0x3b /* 59 */
90#define OP63 0x3f /* 63 */
91
92/* Opcode 31: */
93/* X-Form: */
94#define LFSX 0x217 /* 535 */
95#define LFSUX 0x237 /* 567 */
96#define LFDX 0x257 /* 599 */
97#define LFDUX 0x277 /* 631 */
98#define STFSX 0x297 /* 663 */
99#define STFSUX 0x2b7 /* 695 */
100#define STFDX 0x2d7 /* 727 */
101#define STFDUX 0x2f7 /* 759 */
102#define STFIWX 0x3d7 /* 983 */
103
104/* Opcode 59: */
105/* A-Form: */
106#define FDIVS 0x012 /* 18 */
107#define FSUBS 0x014 /* 20 */
108#define FADDS 0x015 /* 21 */
109#define FSQRTS 0x016 /* 22 */
110#define FRES 0x018 /* 24 */
111#define FMULS 0x019 /* 25 */
112#define FRSQRTES 0x01a /* 26 */
113#define FMSUBS 0x01c /* 28 */
114#define FMADDS 0x01d /* 29 */
115#define FNMSUBS 0x01e /* 30 */
116#define FNMADDS 0x01f /* 31 */
117
118/* Opcode 63: */
119/* A-Form: */
120#define FDIV 0x012 /* 18 */
121#define FSUB 0x014 /* 20 */
122#define FADD 0x015 /* 21 */
123#define FSQRT 0x016 /* 22 */
124#define FSEL 0x017 /* 23 */
125#define FRE 0x018 /* 24 */
126#define FMUL 0x019 /* 25 */
127#define FRSQRTE 0x01a /* 26 */
128#define FMSUB 0x01c /* 28 */
129#define FMADD 0x01d /* 29 */
130#define FNMSUB 0x01e /* 30 */
131#define FNMADD 0x01f /* 31 */
132
133/* X-Form: */
134#define FCMPU 0x000 /* 0 */
135#define FRSP 0x00c /* 12 */
136#define FCTIW 0x00e /* 14 */
137#define FCTIWZ 0x00f /* 15 */
138#define FCMPO 0x020 /* 32 */
139#define MTFSB1 0x026 /* 38 */
140#define FNEG 0x028 /* 40 */
141#define MCRFS 0x040 /* 64 */
142#define MTFSB0 0x046 /* 70 */
143#define FMR 0x048 /* 72 */
144#define MTFSFI 0x086 /* 134 */
145#define FNABS 0x088 /* 136 */
146#define FABS 0x108 /* 264 */
147#define MFFS 0x247 /* 583 */
148#define MTFSF 0x2c7 /* 711 */
149
150
151#define AB 2
152#define AC 3
153#define ABC 4
154#define D 5
155#define DU 6
156#define X 7
157#define XA 8
158#define XB 9
159#define XCR 11
160#define XCRB 12
161#define XCRI 13
162#define XCRL 16
163#define XE 14
164#define XEU 15
165#define XFLB 10
166
167static int
168record_exception(struct pt_regs *regs, int eflag)
169{
170 u32 fpscr;
171
172 fpscr = __FPU_FPSCR;
173
174 if (eflag) {
175 fpscr |= FPSCR_FX;
176 if (eflag & EFLAG_OVERFLOW)
177 fpscr |= FPSCR_OX;
178 if (eflag & EFLAG_UNDERFLOW)
179 fpscr |= FPSCR_UX;
180 if (eflag & EFLAG_DIVZERO)
181 fpscr |= FPSCR_ZX;
182 if (eflag & EFLAG_INEXACT)
183 fpscr |= FPSCR_XX;
184 if (eflag & EFLAG_INVALID)
185 fpscr |= FPSCR_VX;
186 if (eflag & EFLAG_VXSNAN)
187 fpscr |= FPSCR_VXSNAN;
188 if (eflag & EFLAG_VXISI)
189 fpscr |= FPSCR_VXISI;
190 if (eflag & EFLAG_VXIDI)
191 fpscr |= FPSCR_VXIDI;
192 if (eflag & EFLAG_VXZDZ)
193 fpscr |= FPSCR_VXZDZ;
194 if (eflag & EFLAG_VXIMZ)
195 fpscr |= FPSCR_VXIMZ;
196 if (eflag & EFLAG_VXVC)
197 fpscr |= FPSCR_VXVC;
198 if (eflag & EFLAG_VXSOFT)
199 fpscr |= FPSCR_VXSOFT;
200 if (eflag & EFLAG_VXSQRT)
201 fpscr |= FPSCR_VXSQRT;
202 if (eflag & EFLAG_VXCVI)
203 fpscr |= FPSCR_VXCVI;
204 }
205
206// fpscr &= ~(FPSCR_VX);
207 if (fpscr & (FPSCR_VXSNAN | FPSCR_VXISI | FPSCR_VXIDI |
208 FPSCR_VXZDZ | FPSCR_VXIMZ | FPSCR_VXVC |
209 FPSCR_VXSOFT | FPSCR_VXSQRT | FPSCR_VXCVI))
210 fpscr |= FPSCR_VX;
211
212 fpscr &= ~(FPSCR_FEX);
213 if (((fpscr & FPSCR_VX) && (fpscr & FPSCR_VE)) ||
214 ((fpscr & FPSCR_OX) && (fpscr & FPSCR_OE)) ||
215 ((fpscr & FPSCR_UX) && (fpscr & FPSCR_UE)) ||
216 ((fpscr & FPSCR_ZX) && (fpscr & FPSCR_ZE)) ||
217 ((fpscr & FPSCR_XX) && (fpscr & FPSCR_XE)))
218 fpscr |= FPSCR_FEX;
219
220 __FPU_FPSCR = fpscr;
221
222 return (fpscr & FPSCR_FEX) ? 1 : 0;
223}
224
225int
226do_mathemu(struct pt_regs *regs)
227{
228 void *op0 = NULL, *op1 = NULL, *op2 = NULL, *op3 = NULL;
229 unsigned long pc = regs->nip;
230 signed short sdisp;
231 u32 insn = 0;
232 int idx = 0;
233 int (*func)(void *, void *, void *, void *);
234 int type = 0;
235 int eflag, trap;
236
237 if (get_user(insn, (u32 __user *)pc))
238 return -EFAULT;
239
240 switch (insn >> 26) {
241 case LFS: func = lfs; type = D; break;
242 case LFSU: func = lfs; type = DU; break;
243 case LFD: func = lfd; type = D; break;
244 case LFDU: func = lfd; type = DU; break;
245 case STFS: func = stfs; type = D; break;
246 case STFSU: func = stfs; type = DU; break;
247 case STFD: func = stfd; type = D; break;
248 case STFDU: func = stfd; type = DU; break;
249
250 case OP31:
251 switch ((insn >> 1) & 0x3ff) {
252 case LFSX: func = lfs; type = XE; break;
253 case LFSUX: func = lfs; type = XEU; break;
254 case LFDX: func = lfd; type = XE; break;
255 case LFDUX: func = lfd; type = XEU; break;
256 case STFSX: func = stfs; type = XE; break;
257 case STFSUX: func = stfs; type = XEU; break;
258 case STFDX: func = stfd; type = XE; break;
259 case STFDUX: func = stfd; type = XEU; break;
260 case STFIWX: func = stfiwx; type = XE; break;
261 default:
262 goto illegal;
263 }
264 break;
265
266 case OP59:
267 switch ((insn >> 1) & 0x1f) {
268 case FDIVS: func = fdivs; type = AB; break;
269 case FSUBS: func = fsubs; type = AB; break;
270 case FADDS: func = fadds; type = AB; break;
271 case FSQRTS: func = fsqrts; type = XB; break;
272 case FRES: func = fres; type = XB; break;
273 case FMULS: func = fmuls; type = AC; break;
274 case FRSQRTES: func = frsqrtes;type = XB; break;
275 case FMSUBS: func = fmsubs; type = ABC; break;
276 case FMADDS: func = fmadds; type = ABC; break;
277 case FNMSUBS: func = fnmsubs; type = ABC; break;
278 case FNMADDS: func = fnmadds; type = ABC; break;
279 default:
280 goto illegal;
281 }
282 break;
283
284 case OP63:
285 if (insn & 0x20) {
286 switch ((insn >> 1) & 0x1f) {
287 case FDIV: func = fdiv; type = AB; break;
288 case FSUB: func = fsub; type = AB; break;
289 case FADD: func = fadd; type = AB; break;
290 case FSQRT: func = fsqrt; type = XB; break;
291 case FRE: func = fre; type = XB; break;
292 case FSEL: func = fsel; type = ABC; break;
293 case FMUL: func = fmul; type = AC; break;
294 case FRSQRTE: func = frsqrte; type = XB; break;
295 case FMSUB: func = fmsub; type = ABC; break;
296 case FMADD: func = fmadd; type = ABC; break;
297 case FNMSUB: func = fnmsub; type = ABC; break;
298 case FNMADD: func = fnmadd; type = ABC; break;
299 default:
300 goto illegal;
301 }
302 break;
303 }
304
305 switch ((insn >> 1) & 0x3ff) {
306 case FCMPU: func = fcmpu; type = XCR; break;
307 case FRSP: func = frsp; type = XB; break;
308 case FCTIW: func = fctiw; type = XB; break;
309 case FCTIWZ: func = fctiwz; type = XB; break;
310 case FCMPO: func = fcmpo; type = XCR; break;
311 case MTFSB1: func = mtfsb1; type = XCRB; break;
312 case FNEG: func = fneg; type = XB; break;
313 case MCRFS: func = mcrfs; type = XCRL; break;
314 case MTFSB0: func = mtfsb0; type = XCRB; break;
315 case FMR: func = fmr; type = XB; break;
316 case MTFSFI: func = mtfsfi; type = XCRI; break;
317 case FNABS: func = fnabs; type = XB; break;
318 case FABS: func = fabs; type = XB; break;
319 case MFFS: func = mffs; type = X; break;
320 case MTFSF: func = mtfsf; type = XFLB; break;
321 default:
322 goto illegal;
323 }
324 break;
325
326 default:
327 goto illegal;
328 }
329
330 switch (type) {
331 case AB:
332 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
333 op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
334 op2 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
335 break;
336
337 case AC:
338 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
339 op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
340 op2 = (void *)¤t->thread.TS_FPR((insn >> 6) & 0x1f);
341 break;
342
343 case ABC:
344 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
345 op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
346 op2 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
347 op3 = (void *)¤t->thread.TS_FPR((insn >> 6) & 0x1f);
348 break;
349
350 case D:
351 idx = (insn >> 16) & 0x1f;
352 sdisp = (insn & 0xffff);
353 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
354 op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp);
355 break;
356
357 case DU:
358 idx = (insn >> 16) & 0x1f;
359 if (!idx)
360 goto illegal;
361
362 sdisp = (insn & 0xffff);
363 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
364 op1 = (void *)(regs->gpr[idx] + sdisp);
365 break;
366
367 case X:
368 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
369 break;
370
371 case XA:
372 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
373 op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
374 break;
375
376 case XB:
377 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
378 op1 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
379 break;
380
381 case XE:
382 idx = (insn >> 16) & 0x1f;
383 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
384 op1 = (void *)((idx ? regs->gpr[idx] : 0)
385 + regs->gpr[(insn >> 11) & 0x1f]);
386 break;
387
388 case XEU:
389 idx = (insn >> 16) & 0x1f;
390 if (!idx)
391 goto illegal;
392 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
393 op1 = (void *)(regs->gpr[idx]
394 + regs->gpr[(insn >> 11) & 0x1f]);
395 break;
396
397 case XCR:
398 op0 = (void *)®s->ccr;
399 op1 = (void *)(long)((insn >> 23) & 0x7);
400 op2 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
401 op3 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
402 break;
403
404 case XCRL:
405 op0 = (void *)®s->ccr;
406 op1 = (void *)(long)((insn >> 23) & 0x7);
407 op2 = (void *)(long)((insn >> 18) & 0x7);
408 break;
409
410 case XCRB:
411 op0 = (void *)(long)((insn >> 21) & 0x1f);
412 break;
413
414 case XCRI:
415 op0 = (void *)(long)((insn >> 23) & 0x7);
416 op1 = (void *)(long)((insn >> 12) & 0xf);
417 break;
418
419 case XFLB:
420 op0 = (void *)(long)((insn >> 17) & 0xff);
421 op1 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
422 break;
423
424 default:
425 goto illegal;
426 }
427
428 /*
429 * If we support a HW FPU, we need to ensure the FP state
430 * is flushed into the thread_struct before attempting
431 * emulation
432 */
433 flush_fp_to_thread(current);
434
435 eflag = func(op0, op1, op2, op3);
436
437 if (insn & 1) {
438 regs->ccr &= ~(0x0f000000);
439 regs->ccr |= (__FPU_FPSCR >> 4) & 0x0f000000;
440 }
441
442 trap = record_exception(regs, eflag);
443 if (trap)
444 return 1;
445
446 switch (type) {
447 case DU:
448 case XEU:
449 regs->gpr[idx] = (unsigned long)op1;
450 break;
451
452 default:
453 break;
454 }
455
456 regs_add_return_ip(regs, 4);
457 return 0;
458
459illegal:
460 return -ENOSYS;
461}
1/*
2 * Copyright (C) 1999 Eddie C. Dost (ecd@atecom.com)
3 */
4
5#include <linux/types.h>
6#include <linux/sched.h>
7
8#include <asm/uaccess.h>
9#include <asm/reg.h>
10
11#include <asm/sfp-machine.h>
12#include <math-emu/double.h>
13
14#define FLOATFUNC(x) extern int x(void *, void *, void *, void *)
15
16FLOATFUNC(fadd);
17FLOATFUNC(fadds);
18FLOATFUNC(fdiv);
19FLOATFUNC(fdivs);
20FLOATFUNC(fmul);
21FLOATFUNC(fmuls);
22FLOATFUNC(fsub);
23FLOATFUNC(fsubs);
24
25FLOATFUNC(fmadd);
26FLOATFUNC(fmadds);
27FLOATFUNC(fmsub);
28FLOATFUNC(fmsubs);
29FLOATFUNC(fnmadd);
30FLOATFUNC(fnmadds);
31FLOATFUNC(fnmsub);
32FLOATFUNC(fnmsubs);
33
34FLOATFUNC(fctiw);
35FLOATFUNC(fctiwz);
36FLOATFUNC(frsp);
37
38FLOATFUNC(fcmpo);
39FLOATFUNC(fcmpu);
40
41FLOATFUNC(mcrfs);
42FLOATFUNC(mffs);
43FLOATFUNC(mtfsb0);
44FLOATFUNC(mtfsb1);
45FLOATFUNC(mtfsf);
46FLOATFUNC(mtfsfi);
47
48FLOATFUNC(lfd);
49FLOATFUNC(lfs);
50
51FLOATFUNC(stfd);
52FLOATFUNC(stfs);
53FLOATFUNC(stfiwx);
54
55FLOATFUNC(fabs);
56FLOATFUNC(fmr);
57FLOATFUNC(fnabs);
58FLOATFUNC(fneg);
59
60/* Optional */
61FLOATFUNC(fres);
62FLOATFUNC(frsqrte);
63FLOATFUNC(fsel);
64FLOATFUNC(fsqrt);
65FLOATFUNC(fsqrts);
66
67
68#define OP31 0x1f /* 31 */
69#define LFS 0x30 /* 48 */
70#define LFSU 0x31 /* 49 */
71#define LFD 0x32 /* 50 */
72#define LFDU 0x33 /* 51 */
73#define STFS 0x34 /* 52 */
74#define STFSU 0x35 /* 53 */
75#define STFD 0x36 /* 54 */
76#define STFDU 0x37 /* 55 */
77#define OP59 0x3b /* 59 */
78#define OP63 0x3f /* 63 */
79
80/* Opcode 31: */
81/* X-Form: */
82#define LFSX 0x217 /* 535 */
83#define LFSUX 0x237 /* 567 */
84#define LFDX 0x257 /* 599 */
85#define LFDUX 0x277 /* 631 */
86#define STFSX 0x297 /* 663 */
87#define STFSUX 0x2b7 /* 695 */
88#define STFDX 0x2d7 /* 727 */
89#define STFDUX 0x2f7 /* 759 */
90#define STFIWX 0x3d7 /* 983 */
91
92/* Opcode 59: */
93/* A-Form: */
94#define FDIVS 0x012 /* 18 */
95#define FSUBS 0x014 /* 20 */
96#define FADDS 0x015 /* 21 */
97#define FSQRTS 0x016 /* 22 */
98#define FRES 0x018 /* 24 */
99#define FMULS 0x019 /* 25 */
100#define FMSUBS 0x01c /* 28 */
101#define FMADDS 0x01d /* 29 */
102#define FNMSUBS 0x01e /* 30 */
103#define FNMADDS 0x01f /* 31 */
104
105/* Opcode 63: */
106/* A-Form: */
107#define FDIV 0x012 /* 18 */
108#define FSUB 0x014 /* 20 */
109#define FADD 0x015 /* 21 */
110#define FSQRT 0x016 /* 22 */
111#define FSEL 0x017 /* 23 */
112#define FMUL 0x019 /* 25 */
113#define FRSQRTE 0x01a /* 26 */
114#define FMSUB 0x01c /* 28 */
115#define FMADD 0x01d /* 29 */
116#define FNMSUB 0x01e /* 30 */
117#define FNMADD 0x01f /* 31 */
118
119/* X-Form: */
120#define FCMPU 0x000 /* 0 */
121#define FRSP 0x00c /* 12 */
122#define FCTIW 0x00e /* 14 */
123#define FCTIWZ 0x00f /* 15 */
124#define FCMPO 0x020 /* 32 */
125#define MTFSB1 0x026 /* 38 */
126#define FNEG 0x028 /* 40 */
127#define MCRFS 0x040 /* 64 */
128#define MTFSB0 0x046 /* 70 */
129#define FMR 0x048 /* 72 */
130#define MTFSFI 0x086 /* 134 */
131#define FNABS 0x088 /* 136 */
132#define FABS 0x108 /* 264 */
133#define MFFS 0x247 /* 583 */
134#define MTFSF 0x2c7 /* 711 */
135
136
137#define AB 2
138#define AC 3
139#define ABC 4
140#define D 5
141#define DU 6
142#define X 7
143#define XA 8
144#define XB 9
145#define XCR 11
146#define XCRB 12
147#define XCRI 13
148#define XCRL 16
149#define XE 14
150#define XEU 15
151#define XFLB 10
152
153#ifdef CONFIG_MATH_EMULATION
154static int
155record_exception(struct pt_regs *regs, int eflag)
156{
157 u32 fpscr;
158
159 fpscr = __FPU_FPSCR;
160
161 if (eflag) {
162 fpscr |= FPSCR_FX;
163 if (eflag & EFLAG_OVERFLOW)
164 fpscr |= FPSCR_OX;
165 if (eflag & EFLAG_UNDERFLOW)
166 fpscr |= FPSCR_UX;
167 if (eflag & EFLAG_DIVZERO)
168 fpscr |= FPSCR_ZX;
169 if (eflag & EFLAG_INEXACT)
170 fpscr |= FPSCR_XX;
171 if (eflag & EFLAG_INVALID)
172 fpscr |= FPSCR_VX;
173 if (eflag & EFLAG_VXSNAN)
174 fpscr |= FPSCR_VXSNAN;
175 if (eflag & EFLAG_VXISI)
176 fpscr |= FPSCR_VXISI;
177 if (eflag & EFLAG_VXIDI)
178 fpscr |= FPSCR_VXIDI;
179 if (eflag & EFLAG_VXZDZ)
180 fpscr |= FPSCR_VXZDZ;
181 if (eflag & EFLAG_VXIMZ)
182 fpscr |= FPSCR_VXIMZ;
183 if (eflag & EFLAG_VXVC)
184 fpscr |= FPSCR_VXVC;
185 if (eflag & EFLAG_VXSOFT)
186 fpscr |= FPSCR_VXSOFT;
187 if (eflag & EFLAG_VXSQRT)
188 fpscr |= FPSCR_VXSQRT;
189 if (eflag & EFLAG_VXCVI)
190 fpscr |= FPSCR_VXCVI;
191 }
192
193// fpscr &= ~(FPSCR_VX);
194 if (fpscr & (FPSCR_VXSNAN | FPSCR_VXISI | FPSCR_VXIDI |
195 FPSCR_VXZDZ | FPSCR_VXIMZ | FPSCR_VXVC |
196 FPSCR_VXSOFT | FPSCR_VXSQRT | FPSCR_VXCVI))
197 fpscr |= FPSCR_VX;
198
199 fpscr &= ~(FPSCR_FEX);
200 if (((fpscr & FPSCR_VX) && (fpscr & FPSCR_VE)) ||
201 ((fpscr & FPSCR_OX) && (fpscr & FPSCR_OE)) ||
202 ((fpscr & FPSCR_UX) && (fpscr & FPSCR_UE)) ||
203 ((fpscr & FPSCR_ZX) && (fpscr & FPSCR_ZE)) ||
204 ((fpscr & FPSCR_XX) && (fpscr & FPSCR_XE)))
205 fpscr |= FPSCR_FEX;
206
207 __FPU_FPSCR = fpscr;
208
209 return (fpscr & FPSCR_FEX) ? 1 : 0;
210}
211#endif /* CONFIG_MATH_EMULATION */
212
213int
214do_mathemu(struct pt_regs *regs)
215{
216 void *op0 = 0, *op1 = 0, *op2 = 0, *op3 = 0;
217 unsigned long pc = regs->nip;
218 signed short sdisp;
219 u32 insn = 0;
220 int idx = 0;
221#ifdef CONFIG_MATH_EMULATION
222 int (*func)(void *, void *, void *, void *);
223 int type = 0;
224 int eflag, trap;
225#endif
226
227 if (get_user(insn, (u32 *)pc))
228 return -EFAULT;
229
230#ifndef CONFIG_MATH_EMULATION
231 switch (insn >> 26) {
232 case LFD:
233 idx = (insn >> 16) & 0x1f;
234 sdisp = (insn & 0xffff);
235 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
236 op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp);
237 lfd(op0, op1, op2, op3);
238 break;
239 case LFDU:
240 idx = (insn >> 16) & 0x1f;
241 sdisp = (insn & 0xffff);
242 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
243 op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp);
244 lfd(op0, op1, op2, op3);
245 regs->gpr[idx] = (unsigned long)op1;
246 break;
247 case STFD:
248 idx = (insn >> 16) & 0x1f;
249 sdisp = (insn & 0xffff);
250 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
251 op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp);
252 stfd(op0, op1, op2, op3);
253 break;
254 case STFDU:
255 idx = (insn >> 16) & 0x1f;
256 sdisp = (insn & 0xffff);
257 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
258 op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp);
259 stfd(op0, op1, op2, op3);
260 regs->gpr[idx] = (unsigned long)op1;
261 break;
262 case OP63:
263 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
264 op1 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
265 fmr(op0, op1, op2, op3);
266 break;
267 default:
268 goto illegal;
269 }
270#else /* CONFIG_MATH_EMULATION */
271 switch (insn >> 26) {
272 case LFS: func = lfs; type = D; break;
273 case LFSU: func = lfs; type = DU; break;
274 case LFD: func = lfd; type = D; break;
275 case LFDU: func = lfd; type = DU; break;
276 case STFS: func = stfs; type = D; break;
277 case STFSU: func = stfs; type = DU; break;
278 case STFD: func = stfd; type = D; break;
279 case STFDU: func = stfd; type = DU; break;
280
281 case OP31:
282 switch ((insn >> 1) & 0x3ff) {
283 case LFSX: func = lfs; type = XE; break;
284 case LFSUX: func = lfs; type = XEU; break;
285 case LFDX: func = lfd; type = XE; break;
286 case LFDUX: func = lfd; type = XEU; break;
287 case STFSX: func = stfs; type = XE; break;
288 case STFSUX: func = stfs; type = XEU; break;
289 case STFDX: func = stfd; type = XE; break;
290 case STFDUX: func = stfd; type = XEU; break;
291 case STFIWX: func = stfiwx; type = XE; break;
292 default:
293 goto illegal;
294 }
295 break;
296
297 case OP59:
298 switch ((insn >> 1) & 0x1f) {
299 case FDIVS: func = fdivs; type = AB; break;
300 case FSUBS: func = fsubs; type = AB; break;
301 case FADDS: func = fadds; type = AB; break;
302 case FSQRTS: func = fsqrts; type = AB; break;
303 case FRES: func = fres; type = AB; break;
304 case FMULS: func = fmuls; type = AC; break;
305 case FMSUBS: func = fmsubs; type = ABC; break;
306 case FMADDS: func = fmadds; type = ABC; break;
307 case FNMSUBS: func = fnmsubs; type = ABC; break;
308 case FNMADDS: func = fnmadds; type = ABC; break;
309 default:
310 goto illegal;
311 }
312 break;
313
314 case OP63:
315 if (insn & 0x20) {
316 switch ((insn >> 1) & 0x1f) {
317 case FDIV: func = fdiv; type = AB; break;
318 case FSUB: func = fsub; type = AB; break;
319 case FADD: func = fadd; type = AB; break;
320 case FSQRT: func = fsqrt; type = AB; break;
321 case FSEL: func = fsel; type = ABC; break;
322 case FMUL: func = fmul; type = AC; break;
323 case FRSQRTE: func = frsqrte; type = AB; break;
324 case FMSUB: func = fmsub; type = ABC; break;
325 case FMADD: func = fmadd; type = ABC; break;
326 case FNMSUB: func = fnmsub; type = ABC; break;
327 case FNMADD: func = fnmadd; type = ABC; break;
328 default:
329 goto illegal;
330 }
331 break;
332 }
333
334 switch ((insn >> 1) & 0x3ff) {
335 case FCMPU: func = fcmpu; type = XCR; break;
336 case FRSP: func = frsp; type = XB; break;
337 case FCTIW: func = fctiw; type = XB; break;
338 case FCTIWZ: func = fctiwz; type = XB; break;
339 case FCMPO: func = fcmpo; type = XCR; break;
340 case MTFSB1: func = mtfsb1; type = XCRB; break;
341 case FNEG: func = fneg; type = XB; break;
342 case MCRFS: func = mcrfs; type = XCRL; break;
343 case MTFSB0: func = mtfsb0; type = XCRB; break;
344 case FMR: func = fmr; type = XB; break;
345 case MTFSFI: func = mtfsfi; type = XCRI; break;
346 case FNABS: func = fnabs; type = XB; break;
347 case FABS: func = fabs; type = XB; break;
348 case MFFS: func = mffs; type = X; break;
349 case MTFSF: func = mtfsf; type = XFLB; break;
350 default:
351 goto illegal;
352 }
353 break;
354
355 default:
356 goto illegal;
357 }
358
359 switch (type) {
360 case AB:
361 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
362 op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
363 op2 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
364 break;
365
366 case AC:
367 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
368 op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
369 op2 = (void *)¤t->thread.TS_FPR((insn >> 6) & 0x1f);
370 break;
371
372 case ABC:
373 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
374 op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
375 op2 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
376 op3 = (void *)¤t->thread.TS_FPR((insn >> 6) & 0x1f);
377 break;
378
379 case D:
380 idx = (insn >> 16) & 0x1f;
381 sdisp = (insn & 0xffff);
382 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
383 op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp);
384 break;
385
386 case DU:
387 idx = (insn >> 16) & 0x1f;
388 if (!idx)
389 goto illegal;
390
391 sdisp = (insn & 0xffff);
392 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
393 op1 = (void *)(regs->gpr[idx] + sdisp);
394 break;
395
396 case X:
397 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
398 break;
399
400 case XA:
401 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
402 op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
403 break;
404
405 case XB:
406 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
407 op1 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
408 break;
409
410 case XE:
411 idx = (insn >> 16) & 0x1f;
412 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
413 if (!idx) {
414 if (((insn >> 1) & 0x3ff) == STFIWX)
415 op1 = (void *)(regs->gpr[(insn >> 11) & 0x1f]);
416 else
417 goto illegal;
418 } else {
419 op1 = (void *)(regs->gpr[idx] + regs->gpr[(insn >> 11) & 0x1f]);
420 }
421
422 break;
423
424 case XEU:
425 idx = (insn >> 16) & 0x1f;
426 op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
427 op1 = (void *)((idx ? regs->gpr[idx] : 0)
428 + regs->gpr[(insn >> 11) & 0x1f]);
429 break;
430
431 case XCR:
432 op0 = (void *)®s->ccr;
433 op1 = (void *)((insn >> 23) & 0x7);
434 op2 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
435 op3 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
436 break;
437
438 case XCRL:
439 op0 = (void *)®s->ccr;
440 op1 = (void *)((insn >> 23) & 0x7);
441 op2 = (void *)((insn >> 18) & 0x7);
442 break;
443
444 case XCRB:
445 op0 = (void *)((insn >> 21) & 0x1f);
446 break;
447
448 case XCRI:
449 op0 = (void *)((insn >> 23) & 0x7);
450 op1 = (void *)((insn >> 12) & 0xf);
451 break;
452
453 case XFLB:
454 op0 = (void *)((insn >> 17) & 0xff);
455 op1 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
456 break;
457
458 default:
459 goto illegal;
460 }
461
462 eflag = func(op0, op1, op2, op3);
463
464 if (insn & 1) {
465 regs->ccr &= ~(0x0f000000);
466 regs->ccr |= (__FPU_FPSCR >> 4) & 0x0f000000;
467 }
468
469 trap = record_exception(regs, eflag);
470 if (trap)
471 return 1;
472
473 switch (type) {
474 case DU:
475 case XEU:
476 regs->gpr[idx] = (unsigned long)op1;
477 break;
478
479 default:
480 break;
481 }
482#endif /* CONFIG_MATH_EMULATION */
483
484 regs->nip += 4;
485 return 0;
486
487illegal:
488 return -ENOSYS;
489}