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1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
4// http://www.samsung.com
5//
6// Exynos - Power Management support
7//
8// Based on arch/arm/mach-s3c2410/pm.c
9// Copyright (c) 2006 Simtec Electronics
10// Ben Dooks <ben@simtec.co.uk>
11
12#include <linux/init.h>
13#include <linux/suspend.h>
14#include <linux/cpu_pm.h>
15#include <linux/io.h>
16#include <linux/of.h>
17#include <linux/soc/samsung/exynos-regs-pmu.h>
18#include <linux/soc/samsung/exynos-pmu.h>
19
20#include <asm/firmware.h>
21#include <asm/smp_scu.h>
22#include <asm/suspend.h>
23#include <asm/cacheflush.h>
24
25#include "common.h"
26
27static inline void __iomem *exynos_boot_vector_addr(void)
28{
29 if (exynos_rev() == EXYNOS4210_REV_1_1)
30 return pmu_base_addr + S5P_INFORM7;
31 else if (exynos_rev() == EXYNOS4210_REV_1_0)
32 return sysram_base_addr + 0x24;
33 return pmu_base_addr + S5P_INFORM0;
34}
35
36static inline void __iomem *exynos_boot_vector_flag(void)
37{
38 if (exynos_rev() == EXYNOS4210_REV_1_1)
39 return pmu_base_addr + S5P_INFORM6;
40 else if (exynos_rev() == EXYNOS4210_REV_1_0)
41 return sysram_base_addr + 0x20;
42 return pmu_base_addr + S5P_INFORM1;
43}
44
45#define S5P_CHECK_AFTR 0xFCBA0D10
46
47/* For Cortex-A9 Diagnostic and Power control register */
48static unsigned int save_arm_register[2];
49
50void exynos_cpu_save_register(void)
51{
52 unsigned long tmp;
53
54 /* Save Power control register */
55 asm ("mrc p15, 0, %0, c15, c0, 0"
56 : "=r" (tmp) : : "cc");
57
58 save_arm_register[0] = tmp;
59
60 /* Save Diagnostic register */
61 asm ("mrc p15, 0, %0, c15, c0, 1"
62 : "=r" (tmp) : : "cc");
63
64 save_arm_register[1] = tmp;
65}
66
67void exynos_cpu_restore_register(void)
68{
69 unsigned long tmp;
70
71 /* Restore Power control register */
72 tmp = save_arm_register[0];
73
74 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
75 : : "r" (tmp)
76 : "cc");
77
78 /* Restore Diagnostic register */
79 tmp = save_arm_register[1];
80
81 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
82 : : "r" (tmp)
83 : "cc");
84}
85
86void exynos_pm_central_suspend(void)
87{
88 unsigned long tmp;
89
90 /* Setting Central Sequence Register for power down mode */
91 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
92 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
93 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
94}
95
96int exynos_pm_central_resume(void)
97{
98 unsigned long tmp;
99
100 /*
101 * If PMU failed while entering sleep mode, WFI will be
102 * ignored by PMU and then exiting cpu_do_idle().
103 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
104 * in this situation.
105 */
106 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
107 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
108 tmp |= S5P_CENTRAL_LOWPWR_CFG;
109 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
110 /* clear the wakeup state register */
111 pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
112 /* No need to perform below restore code */
113 return -1;
114 }
115
116 return 0;
117}
118
119/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
120static void exynos_set_wakeupmask(long mask)
121{
122 pmu_raw_writel(mask, S5P_WAKEUP_MASK);
123 if (soc_is_exynos3250())
124 pmu_raw_writel(0x0, S5P_WAKEUP_MASK2);
125}
126
127static void exynos_cpu_set_boot_vector(long flags)
128{
129 writel_relaxed(__pa_symbol(exynos_cpu_resume),
130 exynos_boot_vector_addr());
131 writel_relaxed(flags, exynos_boot_vector_flag());
132}
133
134static int exynos_aftr_finisher(unsigned long flags)
135{
136 int ret;
137
138 exynos_set_wakeupmask(soc_is_exynos3250() ? 0x40003ffe : 0x0000ff3e);
139 /* Set value of power down register for aftr mode */
140 exynos_sys_powerdown_conf(SYS_AFTR);
141
142 ret = call_firmware_op(do_idle, FW_DO_IDLE_AFTR);
143 if (ret == -ENOSYS) {
144 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
145 exynos_cpu_save_register();
146 exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
147 cpu_do_idle();
148 }
149
150 return 1;
151}
152
153void exynos_enter_aftr(void)
154{
155 unsigned int cpuid = smp_processor_id();
156
157 cpu_pm_enter();
158
159 if (soc_is_exynos3250())
160 exynos_set_boot_flag(cpuid, C2_STATE);
161
162 exynos_pm_central_suspend();
163
164 if (soc_is_exynos4212() || soc_is_exynos4412()) {
165 /* Setting SEQ_OPTION register */
166 pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
167 S5P_CENTRAL_SEQ_OPTION);
168 }
169
170 cpu_suspend(0, exynos_aftr_finisher);
171
172 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
173 exynos_scu_enable();
174 if (call_firmware_op(resume) == -ENOSYS)
175 exynos_cpu_restore_register();
176 }
177
178 exynos_pm_central_resume();
179
180 if (soc_is_exynos3250())
181 exynos_clear_boot_flag(cpuid, C2_STATE);
182
183 cpu_pm_exit();
184}
185
186#if defined(CONFIG_SMP) && defined(CONFIG_ARM_EXYNOS_CPUIDLE)
187static atomic_t cpu1_wakeup = ATOMIC_INIT(0);
188
189static int exynos_cpu0_enter_aftr(void)
190{
191 int ret = -1;
192
193 /*
194 * If the other cpu is powered on, we have to power it off, because
195 * the AFTR state won't work otherwise
196 */
197 if (cpu_online(1)) {
198 /*
199 * We reach a sync point with the coupled idle state, we know
200 * the other cpu will power down itself or will abort the
201 * sequence, let's wait for one of these to happen
202 */
203 while (exynos_cpu_power_state(1)) {
204 unsigned long boot_addr;
205
206 /*
207 * The other cpu may skip idle and boot back
208 * up again
209 */
210 if (atomic_read(&cpu1_wakeup))
211 goto abort;
212
213 /*
214 * The other cpu may bounce through idle and
215 * boot back up again, getting stuck in the
216 * boot rom code
217 */
218 ret = exynos_get_boot_addr(1, &boot_addr);
219 if (ret)
220 goto fail;
221 ret = -1;
222 if (boot_addr == 0)
223 goto abort;
224
225 cpu_relax();
226 }
227 }
228
229 exynos_enter_aftr();
230 ret = 0;
231
232abort:
233 if (cpu_online(1)) {
234 unsigned long boot_addr = __pa_symbol(exynos_cpu_resume);
235
236 /*
237 * Set the boot vector to something non-zero
238 */
239 ret = exynos_set_boot_addr(1, boot_addr);
240 if (ret)
241 goto fail;
242 dsb();
243
244 /*
245 * Turn on cpu1 and wait for it to be on
246 */
247 exynos_cpu_power_up(1);
248 while (exynos_cpu_power_state(1) != S5P_CORE_LOCAL_PWR_EN)
249 cpu_relax();
250
251 if (soc_is_exynos3250()) {
252 while (!pmu_raw_readl(S5P_PMU_SPARE2) &&
253 !atomic_read(&cpu1_wakeup))
254 cpu_relax();
255
256 if (!atomic_read(&cpu1_wakeup))
257 exynos_core_restart(1);
258 }
259
260 while (!atomic_read(&cpu1_wakeup)) {
261 smp_rmb();
262
263 /*
264 * Poke cpu1 out of the boot rom
265 */
266
267 ret = exynos_set_boot_addr(1, boot_addr);
268 if (ret)
269 goto fail;
270
271 call_firmware_op(cpu_boot, 1);
272 dsb_sev();
273 }
274 }
275fail:
276 return ret;
277}
278
279static int exynos_wfi_finisher(unsigned long flags)
280{
281 if (soc_is_exynos3250())
282 flush_cache_all();
283 cpu_do_idle();
284
285 return -1;
286}
287
288static int exynos_cpu1_powerdown(void)
289{
290 int ret = -1;
291
292 /*
293 * Idle sequence for cpu1
294 */
295 if (cpu_pm_enter())
296 goto cpu1_aborted;
297
298 /*
299 * Turn off cpu 1
300 */
301 exynos_cpu_power_down(1);
302
303 if (soc_is_exynos3250())
304 pmu_raw_writel(0, S5P_PMU_SPARE2);
305
306 ret = cpu_suspend(0, exynos_wfi_finisher);
307
308 cpu_pm_exit();
309
310cpu1_aborted:
311 dsb();
312 /*
313 * Notify cpu 0 that cpu 1 is awake
314 */
315 atomic_set(&cpu1_wakeup, 1);
316
317 return ret;
318}
319
320static void exynos_pre_enter_aftr(void)
321{
322 unsigned long boot_addr = __pa_symbol(exynos_cpu_resume);
323
324 (void)exynos_set_boot_addr(1, boot_addr);
325}
326
327static void exynos_post_enter_aftr(void)
328{
329 atomic_set(&cpu1_wakeup, 0);
330}
331
332struct cpuidle_exynos_data cpuidle_coupled_exynos_data = {
333 .cpu0_enter_aftr = exynos_cpu0_enter_aftr,
334 .cpu1_powerdown = exynos_cpu1_powerdown,
335 .pre_enter_aftr = exynos_pre_enter_aftr,
336 .post_enter_aftr = exynos_post_enter_aftr,
337};
338#endif /* CONFIG_SMP && CONFIG_ARM_EXYNOS_CPUIDLE */
1/*
2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS - Power Management support
6 *
7 * Based on arch/arm/mach-s3c2410/pm.c
8 * Copyright (c) 2006 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#include <linux/init.h>
17#include <linux/suspend.h>
18#include <linux/syscore_ops.h>
19#include <linux/io.h>
20#include <linux/err.h>
21#include <linux/clk.h>
22
23#include <asm/cacheflush.h>
24#include <asm/hardware/cache-l2x0.h>
25#include <asm/smp_scu.h>
26
27#include <plat/cpu.h>
28#include <plat/pm.h>
29#include <plat/pll.h>
30#include <plat/regs-srom.h>
31
32#include <mach/regs-irq.h>
33#include <mach/regs-gpio.h>
34#include <mach/regs-clock.h>
35#include <mach/regs-pmu.h>
36#include <mach/pm-core.h>
37#include <mach/pmu.h>
38
39static struct sleep_save exynos4_set_clksrc[] = {
40 { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },
41 { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, },
42 { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, },
43 { .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
44 { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
45 { .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, },
46 { .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
47 { .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
48 { .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, },
49};
50
51static struct sleep_save exynos4210_set_clksrc[] = {
52 { .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
53};
54
55static struct sleep_save exynos4_epll_save[] = {
56 SAVE_ITEM(EXYNOS4_EPLL_CON0),
57 SAVE_ITEM(EXYNOS4_EPLL_CON1),
58};
59
60static struct sleep_save exynos4_vpll_save[] = {
61 SAVE_ITEM(EXYNOS4_VPLL_CON0),
62 SAVE_ITEM(EXYNOS4_VPLL_CON1),
63};
64
65static struct sleep_save exynos_core_save[] = {
66 /* SROM side */
67 SAVE_ITEM(S5P_SROM_BW),
68 SAVE_ITEM(S5P_SROM_BC0),
69 SAVE_ITEM(S5P_SROM_BC1),
70 SAVE_ITEM(S5P_SROM_BC2),
71 SAVE_ITEM(S5P_SROM_BC3),
72};
73
74
75/* For Cortex-A9 Diagnostic and Power control register */
76static unsigned int save_arm_register[2];
77
78static int exynos_cpu_suspend(unsigned long arg)
79{
80#ifdef CONFIG_CACHE_L2X0
81 outer_flush_all();
82#endif
83
84 /* issue the standby signal into the pm unit. */
85 cpu_do_idle();
86
87 /* we should never get past here */
88 panic("sleep resumed to originator?");
89}
90
91static void exynos_pm_prepare(void)
92{
93 unsigned int tmp;
94
95 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
96
97 if (!soc_is_exynos5250()) {
98 s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
99 s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
100 } else {
101 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
102 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
103 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
104 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
105 }
106
107 /* Set value of power down register for sleep mode */
108
109 exynos_sys_powerdown_conf(SYS_SLEEP);
110 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
111
112 /* ensure at least INFORM0 has the resume address */
113
114 __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
115
116 /* Before enter central sequence mode, clock src register have to set */
117
118 if (!soc_is_exynos5250())
119 s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
120
121 if (soc_is_exynos4210())
122 s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
123
124}
125
126static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
127{
128 pm_cpu_prep = exynos_pm_prepare;
129 pm_cpu_sleep = exynos_cpu_suspend;
130
131 return 0;
132}
133
134static unsigned long pll_base_rate;
135
136static void exynos4_restore_pll(void)
137{
138 unsigned long pll_con, locktime, lockcnt;
139 unsigned long pll_in_rate;
140 unsigned int p_div, epll_wait = 0, vpll_wait = 0;
141
142 if (pll_base_rate == 0)
143 return;
144
145 pll_in_rate = pll_base_rate;
146
147 /* EPLL */
148 pll_con = exynos4_epll_save[0].val;
149
150 if (pll_con & (1 << 31)) {
151 pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
152 p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
153
154 pll_in_rate /= 1000000;
155
156 locktime = (3000 / pll_in_rate) * p_div;
157 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
158
159 __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
160
161 s3c_pm_do_restore_core(exynos4_epll_save,
162 ARRAY_SIZE(exynos4_epll_save));
163 epll_wait = 1;
164 }
165
166 pll_in_rate = pll_base_rate;
167
168 /* VPLL */
169 pll_con = exynos4_vpll_save[0].val;
170
171 if (pll_con & (1 << 31)) {
172 pll_in_rate /= 1000000;
173 /* 750us */
174 locktime = 750;
175 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
176
177 __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
178
179 s3c_pm_do_restore_core(exynos4_vpll_save,
180 ARRAY_SIZE(exynos4_vpll_save));
181 vpll_wait = 1;
182 }
183
184 /* Wait PLL locking */
185
186 do {
187 if (epll_wait) {
188 pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
189 if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
190 epll_wait = 0;
191 }
192
193 if (vpll_wait) {
194 pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
195 if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
196 vpll_wait = 0;
197 }
198 } while (epll_wait || vpll_wait);
199}
200
201static struct subsys_interface exynos_pm_interface = {
202 .name = "exynos_pm",
203 .subsys = &exynos_subsys,
204 .add_dev = exynos_pm_add,
205};
206
207static __init int exynos_pm_drvinit(void)
208{
209 struct clk *pll_base;
210 unsigned int tmp;
211
212 s3c_pm_init();
213
214 /* All wakeup disable */
215
216 tmp = __raw_readl(S5P_WAKEUP_MASK);
217 tmp |= ((0xFF << 8) | (0x1F << 1));
218 __raw_writel(tmp, S5P_WAKEUP_MASK);
219
220 if (!soc_is_exynos5250()) {
221 pll_base = clk_get(NULL, "xtal");
222
223 if (!IS_ERR(pll_base)) {
224 pll_base_rate = clk_get_rate(pll_base);
225 clk_put(pll_base);
226 }
227 }
228
229 return subsys_interface_register(&exynos_pm_interface);
230}
231arch_initcall(exynos_pm_drvinit);
232
233static int exynos_pm_suspend(void)
234{
235 unsigned long tmp;
236
237 /* Setting Central Sequence Register for power down mode */
238
239 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
240 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
241 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
242
243 /* Setting SEQ_OPTION register */
244
245 tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
246 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
247
248 if (!soc_is_exynos5250()) {
249 /* Save Power control register */
250 asm ("mrc p15, 0, %0, c15, c0, 0"
251 : "=r" (tmp) : : "cc");
252 save_arm_register[0] = tmp;
253
254 /* Save Diagnostic register */
255 asm ("mrc p15, 0, %0, c15, c0, 1"
256 : "=r" (tmp) : : "cc");
257 save_arm_register[1] = tmp;
258 }
259
260 return 0;
261}
262
263static void exynos_pm_resume(void)
264{
265 unsigned long tmp;
266
267 /*
268 * If PMU failed while entering sleep mode, WFI will be
269 * ignored by PMU and then exiting cpu_do_idle().
270 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
271 * in this situation.
272 */
273 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
274 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
275 tmp |= S5P_CENTRAL_LOWPWR_CFG;
276 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
277 /* No need to perform below restore code */
278 goto early_wakeup;
279 }
280 if (!soc_is_exynos5250()) {
281 /* Restore Power control register */
282 tmp = save_arm_register[0];
283 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
284 : : "r" (tmp)
285 : "cc");
286
287 /* Restore Diagnostic register */
288 tmp = save_arm_register[1];
289 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
290 : : "r" (tmp)
291 : "cc");
292 }
293
294 /* For release retention */
295
296 __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
297 __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
298 __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
299 __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
300 __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
301 __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
302 __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
303
304 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
305
306 if (!soc_is_exynos5250()) {
307 exynos4_restore_pll();
308
309#ifdef CONFIG_SMP
310 scu_enable(S5P_VA_SCU);
311#endif
312 }
313
314early_wakeup:
315 return;
316}
317
318static struct syscore_ops exynos_pm_syscore_ops = {
319 .suspend = exynos_pm_suspend,
320 .resume = exynos_pm_resume,
321};
322
323static __init int exynos_pm_syscore_init(void)
324{
325 register_syscore_ops(&exynos_pm_syscore_ops);
326 return 0;
327}
328arch_initcall(exynos_pm_syscore_init);