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1/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3/*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31#include <drm/drmP.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/drm_fb_helper.h>
34#include "intel_drv.h"
35#include <drm/i915_drm.h>
36#include "i915_drv.h"
37#include "i915_trace.h"
38#include <linux/pci.h>
39#include <linux/vgaarb.h>
40#include <linux/acpi.h>
41#include <linux/pnp.h>
42#include <linux/vga_switcheroo.h>
43#include <linux/slab.h>
44#include <acpi/video.h>
45#include <linux/pm.h>
46#include <linux/pm_runtime.h>
47
48#define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
49
50#define BEGIN_LP_RING(n) \
51 intel_ring_begin(LP_RING(dev_priv), (n))
52
53#define OUT_RING(x) \
54 intel_ring_emit(LP_RING(dev_priv), x)
55
56#define ADVANCE_LP_RING() \
57 __intel_ring_advance(LP_RING(dev_priv))
58
59/**
60 * Lock test for when it's just for synchronization of ring access.
61 *
62 * In that case, we don't need to do it when GEM is initialized as nobody else
63 * has access to the ring.
64 */
65#define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
66 if (LP_RING(dev->dev_private)->obj == NULL) \
67 LOCK_TEST_WITH_RETURN(dev, file); \
68} while (0)
69
70static inline u32
71intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
72{
73 if (I915_NEED_GFX_HWS(dev_priv->dev))
74 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
75 else
76 return intel_read_status_page(LP_RING(dev_priv), reg);
77}
78
79#define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
80#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
81#define I915_BREADCRUMB_INDEX 0x21
82
83void i915_update_dri1_breadcrumb(struct drm_device *dev)
84{
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 struct drm_i915_master_private *master_priv;
87
88 /*
89 * The dri breadcrumb update races against the drm master disappearing.
90 * Instead of trying to fix this (this is by far not the only ums issue)
91 * just don't do the update in kms mode.
92 */
93 if (drm_core_check_feature(dev, DRIVER_MODESET))
94 return;
95
96 if (dev->primary->master) {
97 master_priv = dev->primary->master->driver_priv;
98 if (master_priv->sarea_priv)
99 master_priv->sarea_priv->last_dispatch =
100 READ_BREADCRUMB(dev_priv);
101 }
102}
103
104static void i915_write_hws_pga(struct drm_device *dev)
105{
106 struct drm_i915_private *dev_priv = dev->dev_private;
107 u32 addr;
108
109 addr = dev_priv->status_page_dmah->busaddr;
110 if (INTEL_INFO(dev)->gen >= 4)
111 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
112 I915_WRITE(HWS_PGA, addr);
113}
114
115/**
116 * Frees the hardware status page, whether it's a physical address or a virtual
117 * address set up by the X Server.
118 */
119static void i915_free_hws(struct drm_device *dev)
120{
121 struct drm_i915_private *dev_priv = dev->dev_private;
122 struct intel_ring_buffer *ring = LP_RING(dev_priv);
123
124 if (dev_priv->status_page_dmah) {
125 drm_pci_free(dev, dev_priv->status_page_dmah);
126 dev_priv->status_page_dmah = NULL;
127 }
128
129 if (ring->status_page.gfx_addr) {
130 ring->status_page.gfx_addr = 0;
131 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
132 }
133
134 /* Need to rewrite hardware status page */
135 I915_WRITE(HWS_PGA, 0x1ffff000);
136}
137
138void i915_kernel_lost_context(struct drm_device * dev)
139{
140 struct drm_i915_private *dev_priv = dev->dev_private;
141 struct drm_i915_master_private *master_priv;
142 struct intel_ring_buffer *ring = LP_RING(dev_priv);
143
144 /*
145 * We should never lose context on the ring with modesetting
146 * as we don't expose it to userspace
147 */
148 if (drm_core_check_feature(dev, DRIVER_MODESET))
149 return;
150
151 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
152 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
153 ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
154 if (ring->space < 0)
155 ring->space += ring->size;
156
157 if (!dev->primary->master)
158 return;
159
160 master_priv = dev->primary->master->driver_priv;
161 if (ring->head == ring->tail && master_priv->sarea_priv)
162 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
163}
164
165static int i915_dma_cleanup(struct drm_device * dev)
166{
167 struct drm_i915_private *dev_priv = dev->dev_private;
168 int i;
169
170 /* Make sure interrupts are disabled here because the uninstall ioctl
171 * may not have been called from userspace and after dev_private
172 * is freed, it's too late.
173 */
174 if (dev->irq_enabled)
175 drm_irq_uninstall(dev);
176
177 mutex_lock(&dev->struct_mutex);
178 for (i = 0; i < I915_NUM_RINGS; i++)
179 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
180 mutex_unlock(&dev->struct_mutex);
181
182 /* Clear the HWS virtual address at teardown */
183 if (I915_NEED_GFX_HWS(dev))
184 i915_free_hws(dev);
185
186 return 0;
187}
188
189static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
190{
191 struct drm_i915_private *dev_priv = dev->dev_private;
192 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
193 int ret;
194
195 master_priv->sarea = drm_getsarea(dev);
196 if (master_priv->sarea) {
197 master_priv->sarea_priv = (drm_i915_sarea_t *)
198 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
199 } else {
200 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
201 }
202
203 if (init->ring_size != 0) {
204 if (LP_RING(dev_priv)->obj != NULL) {
205 i915_dma_cleanup(dev);
206 DRM_ERROR("Client tried to initialize ringbuffer in "
207 "GEM mode\n");
208 return -EINVAL;
209 }
210
211 ret = intel_render_ring_init_dri(dev,
212 init->ring_start,
213 init->ring_size);
214 if (ret) {
215 i915_dma_cleanup(dev);
216 return ret;
217 }
218 }
219
220 dev_priv->dri1.cpp = init->cpp;
221 dev_priv->dri1.back_offset = init->back_offset;
222 dev_priv->dri1.front_offset = init->front_offset;
223 dev_priv->dri1.current_page = 0;
224 if (master_priv->sarea_priv)
225 master_priv->sarea_priv->pf_current_page = 0;
226
227 /* Allow hardware batchbuffers unless told otherwise.
228 */
229 dev_priv->dri1.allow_batchbuffer = 1;
230
231 return 0;
232}
233
234static int i915_dma_resume(struct drm_device * dev)
235{
236 struct drm_i915_private *dev_priv = dev->dev_private;
237 struct intel_ring_buffer *ring = LP_RING(dev_priv);
238
239 DRM_DEBUG_DRIVER("%s\n", __func__);
240
241 if (ring->virtual_start == NULL) {
242 DRM_ERROR("can not ioremap virtual address for"
243 " ring buffer\n");
244 return -ENOMEM;
245 }
246
247 /* Program Hardware Status Page */
248 if (!ring->status_page.page_addr) {
249 DRM_ERROR("Can not find hardware status page\n");
250 return -EINVAL;
251 }
252 DRM_DEBUG_DRIVER("hw status page @ %p\n",
253 ring->status_page.page_addr);
254 if (ring->status_page.gfx_addr != 0)
255 intel_ring_setup_status_page(ring);
256 else
257 i915_write_hws_pga(dev);
258
259 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
260
261 return 0;
262}
263
264static int i915_dma_init(struct drm_device *dev, void *data,
265 struct drm_file *file_priv)
266{
267 drm_i915_init_t *init = data;
268 int retcode = 0;
269
270 if (drm_core_check_feature(dev, DRIVER_MODESET))
271 return -ENODEV;
272
273 switch (init->func) {
274 case I915_INIT_DMA:
275 retcode = i915_initialize(dev, init);
276 break;
277 case I915_CLEANUP_DMA:
278 retcode = i915_dma_cleanup(dev);
279 break;
280 case I915_RESUME_DMA:
281 retcode = i915_dma_resume(dev);
282 break;
283 default:
284 retcode = -EINVAL;
285 break;
286 }
287
288 return retcode;
289}
290
291/* Implement basically the same security restrictions as hardware does
292 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
293 *
294 * Most of the calculations below involve calculating the size of a
295 * particular instruction. It's important to get the size right as
296 * that tells us where the next instruction to check is. Any illegal
297 * instruction detected will be given a size of zero, which is a
298 * signal to abort the rest of the buffer.
299 */
300static int validate_cmd(int cmd)
301{
302 switch (((cmd >> 29) & 0x7)) {
303 case 0x0:
304 switch ((cmd >> 23) & 0x3f) {
305 case 0x0:
306 return 1; /* MI_NOOP */
307 case 0x4:
308 return 1; /* MI_FLUSH */
309 default:
310 return 0; /* disallow everything else */
311 }
312 break;
313 case 0x1:
314 return 0; /* reserved */
315 case 0x2:
316 return (cmd & 0xff) + 2; /* 2d commands */
317 case 0x3:
318 if (((cmd >> 24) & 0x1f) <= 0x18)
319 return 1;
320
321 switch ((cmd >> 24) & 0x1f) {
322 case 0x1c:
323 return 1;
324 case 0x1d:
325 switch ((cmd >> 16) & 0xff) {
326 case 0x3:
327 return (cmd & 0x1f) + 2;
328 case 0x4:
329 return (cmd & 0xf) + 2;
330 default:
331 return (cmd & 0xffff) + 2;
332 }
333 case 0x1e:
334 if (cmd & (1 << 23))
335 return (cmd & 0xffff) + 1;
336 else
337 return 1;
338 case 0x1f:
339 if ((cmd & (1 << 23)) == 0) /* inline vertices */
340 return (cmd & 0x1ffff) + 2;
341 else if (cmd & (1 << 17)) /* indirect random */
342 if ((cmd & 0xffff) == 0)
343 return 0; /* unknown length, too hard */
344 else
345 return (((cmd & 0xffff) + 1) / 2) + 1;
346 else
347 return 2; /* indirect sequential */
348 default:
349 return 0;
350 }
351 default:
352 return 0;
353 }
354
355 return 0;
356}
357
358static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
359{
360 struct drm_i915_private *dev_priv = dev->dev_private;
361 int i, ret;
362
363 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
364 return -EINVAL;
365
366 for (i = 0; i < dwords;) {
367 int sz = validate_cmd(buffer[i]);
368 if (sz == 0 || i + sz > dwords)
369 return -EINVAL;
370 i += sz;
371 }
372
373 ret = BEGIN_LP_RING((dwords+1)&~1);
374 if (ret)
375 return ret;
376
377 for (i = 0; i < dwords; i++)
378 OUT_RING(buffer[i]);
379 if (dwords & 1)
380 OUT_RING(0);
381
382 ADVANCE_LP_RING();
383
384 return 0;
385}
386
387int
388i915_emit_box(struct drm_device *dev,
389 struct drm_clip_rect *box,
390 int DR1, int DR4)
391{
392 struct drm_i915_private *dev_priv = dev->dev_private;
393 int ret;
394
395 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
396 box->y2 <= 0 || box->x2 <= 0) {
397 DRM_ERROR("Bad box %d,%d..%d,%d\n",
398 box->x1, box->y1, box->x2, box->y2);
399 return -EINVAL;
400 }
401
402 if (INTEL_INFO(dev)->gen >= 4) {
403 ret = BEGIN_LP_RING(4);
404 if (ret)
405 return ret;
406
407 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
408 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
409 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
410 OUT_RING(DR4);
411 } else {
412 ret = BEGIN_LP_RING(6);
413 if (ret)
414 return ret;
415
416 OUT_RING(GFX_OP_DRAWRECT_INFO);
417 OUT_RING(DR1);
418 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
419 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
420 OUT_RING(DR4);
421 OUT_RING(0);
422 }
423 ADVANCE_LP_RING();
424
425 return 0;
426}
427
428/* XXX: Emitting the counter should really be moved to part of the IRQ
429 * emit. For now, do it in both places:
430 */
431
432static void i915_emit_breadcrumb(struct drm_device *dev)
433{
434 struct drm_i915_private *dev_priv = dev->dev_private;
435 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
436
437 dev_priv->dri1.counter++;
438 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
439 dev_priv->dri1.counter = 0;
440 if (master_priv->sarea_priv)
441 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
442
443 if (BEGIN_LP_RING(4) == 0) {
444 OUT_RING(MI_STORE_DWORD_INDEX);
445 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
446 OUT_RING(dev_priv->dri1.counter);
447 OUT_RING(0);
448 ADVANCE_LP_RING();
449 }
450}
451
452static int i915_dispatch_cmdbuffer(struct drm_device * dev,
453 drm_i915_cmdbuffer_t *cmd,
454 struct drm_clip_rect *cliprects,
455 void *cmdbuf)
456{
457 int nbox = cmd->num_cliprects;
458 int i = 0, count, ret;
459
460 if (cmd->sz & 0x3) {
461 DRM_ERROR("alignment");
462 return -EINVAL;
463 }
464
465 i915_kernel_lost_context(dev);
466
467 count = nbox ? nbox : 1;
468
469 for (i = 0; i < count; i++) {
470 if (i < nbox) {
471 ret = i915_emit_box(dev, &cliprects[i],
472 cmd->DR1, cmd->DR4);
473 if (ret)
474 return ret;
475 }
476
477 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
478 if (ret)
479 return ret;
480 }
481
482 i915_emit_breadcrumb(dev);
483 return 0;
484}
485
486static int i915_dispatch_batchbuffer(struct drm_device * dev,
487 drm_i915_batchbuffer_t * batch,
488 struct drm_clip_rect *cliprects)
489{
490 struct drm_i915_private *dev_priv = dev->dev_private;
491 int nbox = batch->num_cliprects;
492 int i, count, ret;
493
494 if ((batch->start | batch->used) & 0x7) {
495 DRM_ERROR("alignment");
496 return -EINVAL;
497 }
498
499 i915_kernel_lost_context(dev);
500
501 count = nbox ? nbox : 1;
502 for (i = 0; i < count; i++) {
503 if (i < nbox) {
504 ret = i915_emit_box(dev, &cliprects[i],
505 batch->DR1, batch->DR4);
506 if (ret)
507 return ret;
508 }
509
510 if (!IS_I830(dev) && !IS_845G(dev)) {
511 ret = BEGIN_LP_RING(2);
512 if (ret)
513 return ret;
514
515 if (INTEL_INFO(dev)->gen >= 4) {
516 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
517 OUT_RING(batch->start);
518 } else {
519 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
520 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
521 }
522 } else {
523 ret = BEGIN_LP_RING(4);
524 if (ret)
525 return ret;
526
527 OUT_RING(MI_BATCH_BUFFER);
528 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
529 OUT_RING(batch->start + batch->used - 4);
530 OUT_RING(0);
531 }
532 ADVANCE_LP_RING();
533 }
534
535
536 if (IS_G4X(dev) || IS_GEN5(dev)) {
537 if (BEGIN_LP_RING(2) == 0) {
538 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
539 OUT_RING(MI_NOOP);
540 ADVANCE_LP_RING();
541 }
542 }
543
544 i915_emit_breadcrumb(dev);
545 return 0;
546}
547
548static int i915_dispatch_flip(struct drm_device * dev)
549{
550 struct drm_i915_private *dev_priv = dev->dev_private;
551 struct drm_i915_master_private *master_priv =
552 dev->primary->master->driver_priv;
553 int ret;
554
555 if (!master_priv->sarea_priv)
556 return -EINVAL;
557
558 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
559 __func__,
560 dev_priv->dri1.current_page,
561 master_priv->sarea_priv->pf_current_page);
562
563 i915_kernel_lost_context(dev);
564
565 ret = BEGIN_LP_RING(10);
566 if (ret)
567 return ret;
568
569 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
570 OUT_RING(0);
571
572 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
573 OUT_RING(0);
574 if (dev_priv->dri1.current_page == 0) {
575 OUT_RING(dev_priv->dri1.back_offset);
576 dev_priv->dri1.current_page = 1;
577 } else {
578 OUT_RING(dev_priv->dri1.front_offset);
579 dev_priv->dri1.current_page = 0;
580 }
581 OUT_RING(0);
582
583 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
584 OUT_RING(0);
585
586 ADVANCE_LP_RING();
587
588 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
589
590 if (BEGIN_LP_RING(4) == 0) {
591 OUT_RING(MI_STORE_DWORD_INDEX);
592 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
593 OUT_RING(dev_priv->dri1.counter);
594 OUT_RING(0);
595 ADVANCE_LP_RING();
596 }
597
598 master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
599 return 0;
600}
601
602static int i915_quiescent(struct drm_device *dev)
603{
604 i915_kernel_lost_context(dev);
605 return intel_ring_idle(LP_RING(dev->dev_private));
606}
607
608static int i915_flush_ioctl(struct drm_device *dev, void *data,
609 struct drm_file *file_priv)
610{
611 int ret;
612
613 if (drm_core_check_feature(dev, DRIVER_MODESET))
614 return -ENODEV;
615
616 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
617
618 mutex_lock(&dev->struct_mutex);
619 ret = i915_quiescent(dev);
620 mutex_unlock(&dev->struct_mutex);
621
622 return ret;
623}
624
625static int i915_batchbuffer(struct drm_device *dev, void *data,
626 struct drm_file *file_priv)
627{
628 struct drm_i915_private *dev_priv = dev->dev_private;
629 struct drm_i915_master_private *master_priv;
630 drm_i915_sarea_t *sarea_priv;
631 drm_i915_batchbuffer_t *batch = data;
632 int ret;
633 struct drm_clip_rect *cliprects = NULL;
634
635 if (drm_core_check_feature(dev, DRIVER_MODESET))
636 return -ENODEV;
637
638 master_priv = dev->primary->master->driver_priv;
639 sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv;
640
641 if (!dev_priv->dri1.allow_batchbuffer) {
642 DRM_ERROR("Batchbuffer ioctl disabled\n");
643 return -EINVAL;
644 }
645
646 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
647 batch->start, batch->used, batch->num_cliprects);
648
649 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
650
651 if (batch->num_cliprects < 0)
652 return -EINVAL;
653
654 if (batch->num_cliprects) {
655 cliprects = kcalloc(batch->num_cliprects,
656 sizeof(*cliprects),
657 GFP_KERNEL);
658 if (cliprects == NULL)
659 return -ENOMEM;
660
661 ret = copy_from_user(cliprects, batch->cliprects,
662 batch->num_cliprects *
663 sizeof(struct drm_clip_rect));
664 if (ret != 0) {
665 ret = -EFAULT;
666 goto fail_free;
667 }
668 }
669
670 mutex_lock(&dev->struct_mutex);
671 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
672 mutex_unlock(&dev->struct_mutex);
673
674 if (sarea_priv)
675 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
676
677fail_free:
678 kfree(cliprects);
679
680 return ret;
681}
682
683static int i915_cmdbuffer(struct drm_device *dev, void *data,
684 struct drm_file *file_priv)
685{
686 struct drm_i915_private *dev_priv = dev->dev_private;
687 struct drm_i915_master_private *master_priv;
688 drm_i915_sarea_t *sarea_priv;
689 drm_i915_cmdbuffer_t *cmdbuf = data;
690 struct drm_clip_rect *cliprects = NULL;
691 void *batch_data;
692 int ret;
693
694 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
695 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
696
697 if (drm_core_check_feature(dev, DRIVER_MODESET))
698 return -ENODEV;
699
700 master_priv = dev->primary->master->driver_priv;
701 sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv;
702
703 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
704
705 if (cmdbuf->num_cliprects < 0)
706 return -EINVAL;
707
708 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
709 if (batch_data == NULL)
710 return -ENOMEM;
711
712 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
713 if (ret != 0) {
714 ret = -EFAULT;
715 goto fail_batch_free;
716 }
717
718 if (cmdbuf->num_cliprects) {
719 cliprects = kcalloc(cmdbuf->num_cliprects,
720 sizeof(*cliprects), GFP_KERNEL);
721 if (cliprects == NULL) {
722 ret = -ENOMEM;
723 goto fail_batch_free;
724 }
725
726 ret = copy_from_user(cliprects, cmdbuf->cliprects,
727 cmdbuf->num_cliprects *
728 sizeof(struct drm_clip_rect));
729 if (ret != 0) {
730 ret = -EFAULT;
731 goto fail_clip_free;
732 }
733 }
734
735 mutex_lock(&dev->struct_mutex);
736 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
737 mutex_unlock(&dev->struct_mutex);
738 if (ret) {
739 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
740 goto fail_clip_free;
741 }
742
743 if (sarea_priv)
744 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
745
746fail_clip_free:
747 kfree(cliprects);
748fail_batch_free:
749 kfree(batch_data);
750
751 return ret;
752}
753
754static int i915_emit_irq(struct drm_device * dev)
755{
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
758
759 i915_kernel_lost_context(dev);
760
761 DRM_DEBUG_DRIVER("\n");
762
763 dev_priv->dri1.counter++;
764 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
765 dev_priv->dri1.counter = 1;
766 if (master_priv->sarea_priv)
767 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
768
769 if (BEGIN_LP_RING(4) == 0) {
770 OUT_RING(MI_STORE_DWORD_INDEX);
771 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
772 OUT_RING(dev_priv->dri1.counter);
773 OUT_RING(MI_USER_INTERRUPT);
774 ADVANCE_LP_RING();
775 }
776
777 return dev_priv->dri1.counter;
778}
779
780static int i915_wait_irq(struct drm_device * dev, int irq_nr)
781{
782 struct drm_i915_private *dev_priv = dev->dev_private;
783 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
784 int ret = 0;
785 struct intel_ring_buffer *ring = LP_RING(dev_priv);
786
787 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
788 READ_BREADCRUMB(dev_priv));
789
790 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
791 if (master_priv->sarea_priv)
792 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
793 return 0;
794 }
795
796 if (master_priv->sarea_priv)
797 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
798
799 if (ring->irq_get(ring)) {
800 DRM_WAIT_ON(ret, ring->irq_queue, 3 * HZ,
801 READ_BREADCRUMB(dev_priv) >= irq_nr);
802 ring->irq_put(ring);
803 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
804 ret = -EBUSY;
805
806 if (ret == -EBUSY) {
807 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
808 READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
809 }
810
811 return ret;
812}
813
814/* Needs the lock as it touches the ring.
815 */
816static int i915_irq_emit(struct drm_device *dev, void *data,
817 struct drm_file *file_priv)
818{
819 struct drm_i915_private *dev_priv = dev->dev_private;
820 drm_i915_irq_emit_t *emit = data;
821 int result;
822
823 if (drm_core_check_feature(dev, DRIVER_MODESET))
824 return -ENODEV;
825
826 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
827 DRM_ERROR("called with no initialization\n");
828 return -EINVAL;
829 }
830
831 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
832
833 mutex_lock(&dev->struct_mutex);
834 result = i915_emit_irq(dev);
835 mutex_unlock(&dev->struct_mutex);
836
837 if (copy_to_user(emit->irq_seq, &result, sizeof(int))) {
838 DRM_ERROR("copy_to_user\n");
839 return -EFAULT;
840 }
841
842 return 0;
843}
844
845/* Doesn't need the hardware lock.
846 */
847static int i915_irq_wait(struct drm_device *dev, void *data,
848 struct drm_file *file_priv)
849{
850 struct drm_i915_private *dev_priv = dev->dev_private;
851 drm_i915_irq_wait_t *irqwait = data;
852
853 if (drm_core_check_feature(dev, DRIVER_MODESET))
854 return -ENODEV;
855
856 if (!dev_priv) {
857 DRM_ERROR("called with no initialization\n");
858 return -EINVAL;
859 }
860
861 return i915_wait_irq(dev, irqwait->irq_seq);
862}
863
864static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
865 struct drm_file *file_priv)
866{
867 struct drm_i915_private *dev_priv = dev->dev_private;
868 drm_i915_vblank_pipe_t *pipe = data;
869
870 if (drm_core_check_feature(dev, DRIVER_MODESET))
871 return -ENODEV;
872
873 if (!dev_priv) {
874 DRM_ERROR("called with no initialization\n");
875 return -EINVAL;
876 }
877
878 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
879
880 return 0;
881}
882
883/**
884 * Schedule buffer swap at given vertical blank.
885 */
886static int i915_vblank_swap(struct drm_device *dev, void *data,
887 struct drm_file *file_priv)
888{
889 /* The delayed swap mechanism was fundamentally racy, and has been
890 * removed. The model was that the client requested a delayed flip/swap
891 * from the kernel, then waited for vblank before continuing to perform
892 * rendering. The problem was that the kernel might wake the client
893 * up before it dispatched the vblank swap (since the lock has to be
894 * held while touching the ringbuffer), in which case the client would
895 * clear and start the next frame before the swap occurred, and
896 * flicker would occur in addition to likely missing the vblank.
897 *
898 * In the absence of this ioctl, userland falls back to a correct path
899 * of waiting for a vblank, then dispatching the swap on its own.
900 * Context switching to userland and back is plenty fast enough for
901 * meeting the requirements of vblank swapping.
902 */
903 return -EINVAL;
904}
905
906static int i915_flip_bufs(struct drm_device *dev, void *data,
907 struct drm_file *file_priv)
908{
909 int ret;
910
911 if (drm_core_check_feature(dev, DRIVER_MODESET))
912 return -ENODEV;
913
914 DRM_DEBUG_DRIVER("%s\n", __func__);
915
916 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
917
918 mutex_lock(&dev->struct_mutex);
919 ret = i915_dispatch_flip(dev);
920 mutex_unlock(&dev->struct_mutex);
921
922 return ret;
923}
924
925static int i915_getparam(struct drm_device *dev, void *data,
926 struct drm_file *file_priv)
927{
928 struct drm_i915_private *dev_priv = dev->dev_private;
929 drm_i915_getparam_t *param = data;
930 int value;
931
932 if (!dev_priv) {
933 DRM_ERROR("called with no initialization\n");
934 return -EINVAL;
935 }
936
937 switch (param->param) {
938 case I915_PARAM_IRQ_ACTIVE:
939 value = dev->pdev->irq ? 1 : 0;
940 break;
941 case I915_PARAM_ALLOW_BATCHBUFFER:
942 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
943 break;
944 case I915_PARAM_LAST_DISPATCH:
945 value = READ_BREADCRUMB(dev_priv);
946 break;
947 case I915_PARAM_CHIPSET_ID:
948 value = dev->pdev->device;
949 break;
950 case I915_PARAM_HAS_GEM:
951 value = 1;
952 break;
953 case I915_PARAM_NUM_FENCES_AVAIL:
954 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
955 break;
956 case I915_PARAM_HAS_OVERLAY:
957 value = dev_priv->overlay ? 1 : 0;
958 break;
959 case I915_PARAM_HAS_PAGEFLIPPING:
960 value = 1;
961 break;
962 case I915_PARAM_HAS_EXECBUF2:
963 /* depends on GEM */
964 value = 1;
965 break;
966 case I915_PARAM_HAS_BSD:
967 value = intel_ring_initialized(&dev_priv->ring[VCS]);
968 break;
969 case I915_PARAM_HAS_BLT:
970 value = intel_ring_initialized(&dev_priv->ring[BCS]);
971 break;
972 case I915_PARAM_HAS_VEBOX:
973 value = intel_ring_initialized(&dev_priv->ring[VECS]);
974 break;
975 case I915_PARAM_HAS_RELAXED_FENCING:
976 value = 1;
977 break;
978 case I915_PARAM_HAS_COHERENT_RINGS:
979 value = 1;
980 break;
981 case I915_PARAM_HAS_EXEC_CONSTANTS:
982 value = INTEL_INFO(dev)->gen >= 4;
983 break;
984 case I915_PARAM_HAS_RELAXED_DELTA:
985 value = 1;
986 break;
987 case I915_PARAM_HAS_GEN7_SOL_RESET:
988 value = 1;
989 break;
990 case I915_PARAM_HAS_LLC:
991 value = HAS_LLC(dev);
992 break;
993 case I915_PARAM_HAS_WT:
994 value = HAS_WT(dev);
995 break;
996 case I915_PARAM_HAS_ALIASING_PPGTT:
997 value = dev_priv->mm.aliasing_ppgtt || USES_FULL_PPGTT(dev);
998 break;
999 case I915_PARAM_HAS_WAIT_TIMEOUT:
1000 value = 1;
1001 break;
1002 case I915_PARAM_HAS_SEMAPHORES:
1003 value = i915_semaphore_is_enabled(dev);
1004 break;
1005 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
1006 value = 1;
1007 break;
1008 case I915_PARAM_HAS_SECURE_BATCHES:
1009 value = capable(CAP_SYS_ADMIN);
1010 break;
1011 case I915_PARAM_HAS_PINNED_BATCHES:
1012 value = 1;
1013 break;
1014 case I915_PARAM_HAS_EXEC_NO_RELOC:
1015 value = 1;
1016 break;
1017 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
1018 value = 1;
1019 break;
1020 default:
1021 DRM_DEBUG("Unknown parameter %d\n", param->param);
1022 return -EINVAL;
1023 }
1024
1025 if (copy_to_user(param->value, &value, sizeof(int))) {
1026 DRM_ERROR("copy_to_user failed\n");
1027 return -EFAULT;
1028 }
1029
1030 return 0;
1031}
1032
1033static int i915_setparam(struct drm_device *dev, void *data,
1034 struct drm_file *file_priv)
1035{
1036 struct drm_i915_private *dev_priv = dev->dev_private;
1037 drm_i915_setparam_t *param = data;
1038
1039 if (!dev_priv) {
1040 DRM_ERROR("called with no initialization\n");
1041 return -EINVAL;
1042 }
1043
1044 switch (param->param) {
1045 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1046 break;
1047 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1048 break;
1049 case I915_SETPARAM_ALLOW_BATCHBUFFER:
1050 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1051 break;
1052 case I915_SETPARAM_NUM_USED_FENCES:
1053 if (param->value > dev_priv->num_fence_regs ||
1054 param->value < 0)
1055 return -EINVAL;
1056 /* Userspace can use first N regs */
1057 dev_priv->fence_reg_start = param->value;
1058 break;
1059 default:
1060 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1061 param->param);
1062 return -EINVAL;
1063 }
1064
1065 return 0;
1066}
1067
1068static int i915_set_status_page(struct drm_device *dev, void *data,
1069 struct drm_file *file_priv)
1070{
1071 struct drm_i915_private *dev_priv = dev->dev_private;
1072 drm_i915_hws_addr_t *hws = data;
1073 struct intel_ring_buffer *ring;
1074
1075 if (drm_core_check_feature(dev, DRIVER_MODESET))
1076 return -ENODEV;
1077
1078 if (!I915_NEED_GFX_HWS(dev))
1079 return -EINVAL;
1080
1081 if (!dev_priv) {
1082 DRM_ERROR("called with no initialization\n");
1083 return -EINVAL;
1084 }
1085
1086 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1087 WARN(1, "tried to set status page when mode setting active\n");
1088 return 0;
1089 }
1090
1091 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1092
1093 ring = LP_RING(dev_priv);
1094 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1095
1096 dev_priv->dri1.gfx_hws_cpu_addr =
1097 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1098 if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1099 i915_dma_cleanup(dev);
1100 ring->status_page.gfx_addr = 0;
1101 DRM_ERROR("can not ioremap virtual address for"
1102 " G33 hw status page\n");
1103 return -ENOMEM;
1104 }
1105
1106 memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1107 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1108
1109 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1110 ring->status_page.gfx_addr);
1111 DRM_DEBUG_DRIVER("load hws at %p\n",
1112 ring->status_page.page_addr);
1113 return 0;
1114}
1115
1116static int i915_get_bridge_dev(struct drm_device *dev)
1117{
1118 struct drm_i915_private *dev_priv = dev->dev_private;
1119
1120 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1121 if (!dev_priv->bridge_dev) {
1122 DRM_ERROR("bridge device not found\n");
1123 return -1;
1124 }
1125 return 0;
1126}
1127
1128#define MCHBAR_I915 0x44
1129#define MCHBAR_I965 0x48
1130#define MCHBAR_SIZE (4*4096)
1131
1132#define DEVEN_REG 0x54
1133#define DEVEN_MCHBAR_EN (1 << 28)
1134
1135/* Allocate space for the MCH regs if needed, return nonzero on error */
1136static int
1137intel_alloc_mchbar_resource(struct drm_device *dev)
1138{
1139 struct drm_i915_private *dev_priv = dev->dev_private;
1140 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1141 u32 temp_lo, temp_hi = 0;
1142 u64 mchbar_addr;
1143 int ret;
1144
1145 if (INTEL_INFO(dev)->gen >= 4)
1146 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1147 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1148 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1149
1150 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1151#ifdef CONFIG_PNP
1152 if (mchbar_addr &&
1153 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1154 return 0;
1155#endif
1156
1157 /* Get some space for it */
1158 dev_priv->mch_res.name = "i915 MCHBAR";
1159 dev_priv->mch_res.flags = IORESOURCE_MEM;
1160 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1161 &dev_priv->mch_res,
1162 MCHBAR_SIZE, MCHBAR_SIZE,
1163 PCIBIOS_MIN_MEM,
1164 0, pcibios_align_resource,
1165 dev_priv->bridge_dev);
1166 if (ret) {
1167 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1168 dev_priv->mch_res.start = 0;
1169 return ret;
1170 }
1171
1172 if (INTEL_INFO(dev)->gen >= 4)
1173 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1174 upper_32_bits(dev_priv->mch_res.start));
1175
1176 pci_write_config_dword(dev_priv->bridge_dev, reg,
1177 lower_32_bits(dev_priv->mch_res.start));
1178 return 0;
1179}
1180
1181/* Setup MCHBAR if possible, return true if we should disable it again */
1182static void
1183intel_setup_mchbar(struct drm_device *dev)
1184{
1185 struct drm_i915_private *dev_priv = dev->dev_private;
1186 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1187 u32 temp;
1188 bool enabled;
1189
1190 if (IS_VALLEYVIEW(dev))
1191 return;
1192
1193 dev_priv->mchbar_need_disable = false;
1194
1195 if (IS_I915G(dev) || IS_I915GM(dev)) {
1196 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1197 enabled = !!(temp & DEVEN_MCHBAR_EN);
1198 } else {
1199 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1200 enabled = temp & 1;
1201 }
1202
1203 /* If it's already enabled, don't have to do anything */
1204 if (enabled)
1205 return;
1206
1207 if (intel_alloc_mchbar_resource(dev))
1208 return;
1209
1210 dev_priv->mchbar_need_disable = true;
1211
1212 /* Space is allocated or reserved, so enable it. */
1213 if (IS_I915G(dev) || IS_I915GM(dev)) {
1214 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1215 temp | DEVEN_MCHBAR_EN);
1216 } else {
1217 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1218 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1219 }
1220}
1221
1222static void
1223intel_teardown_mchbar(struct drm_device *dev)
1224{
1225 struct drm_i915_private *dev_priv = dev->dev_private;
1226 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1227 u32 temp;
1228
1229 if (dev_priv->mchbar_need_disable) {
1230 if (IS_I915G(dev) || IS_I915GM(dev)) {
1231 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1232 temp &= ~DEVEN_MCHBAR_EN;
1233 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1234 } else {
1235 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1236 temp &= ~1;
1237 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1238 }
1239 }
1240
1241 if (dev_priv->mch_res.start)
1242 release_resource(&dev_priv->mch_res);
1243}
1244
1245/* true = enable decode, false = disable decoder */
1246static unsigned int i915_vga_set_decode(void *cookie, bool state)
1247{
1248 struct drm_device *dev = cookie;
1249
1250 intel_modeset_vga_set_state(dev, state);
1251 if (state)
1252 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1253 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1254 else
1255 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1256}
1257
1258static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1259{
1260 struct drm_device *dev = pci_get_drvdata(pdev);
1261 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1262 if (state == VGA_SWITCHEROO_ON) {
1263 pr_info("switched on\n");
1264 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1265 /* i915 resume handler doesn't set to D0 */
1266 pci_set_power_state(dev->pdev, PCI_D0);
1267 i915_resume(dev);
1268 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1269 } else {
1270 pr_err("switched off\n");
1271 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1272 i915_suspend(dev, pmm);
1273 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1274 }
1275}
1276
1277static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1278{
1279 struct drm_device *dev = pci_get_drvdata(pdev);
1280 bool can_switch;
1281
1282 spin_lock(&dev->count_lock);
1283 can_switch = (dev->open_count == 0);
1284 spin_unlock(&dev->count_lock);
1285 return can_switch;
1286}
1287
1288static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1289 .set_gpu_state = i915_switcheroo_set_state,
1290 .reprobe = NULL,
1291 .can_switch = i915_switcheroo_can_switch,
1292};
1293
1294static int i915_load_modeset_init(struct drm_device *dev)
1295{
1296 struct drm_i915_private *dev_priv = dev->dev_private;
1297 int ret;
1298
1299 ret = intel_parse_bios(dev);
1300 if (ret)
1301 DRM_INFO("failed to find VBIOS tables\n");
1302
1303 /* If we have > 1 VGA cards, then we need to arbitrate access
1304 * to the common VGA resources.
1305 *
1306 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1307 * then we do not take part in VGA arbitration and the
1308 * vga_client_register() fails with -ENODEV.
1309 */
1310 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1311 if (ret && ret != -ENODEV)
1312 goto out;
1313
1314 intel_register_dsm_handler();
1315
1316 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
1317 if (ret)
1318 goto cleanup_vga_client;
1319
1320 /* Initialise stolen first so that we may reserve preallocated
1321 * objects for the BIOS to KMS transition.
1322 */
1323 ret = i915_gem_init_stolen(dev);
1324 if (ret)
1325 goto cleanup_vga_switcheroo;
1326
1327 intel_power_domains_init_hw(dev_priv);
1328
1329 ret = drm_irq_install(dev);
1330 if (ret)
1331 goto cleanup_gem_stolen;
1332
1333 /* Important: The output setup functions called by modeset_init need
1334 * working irqs for e.g. gmbus and dp aux transfers. */
1335 intel_modeset_init(dev);
1336
1337 ret = i915_gem_init(dev);
1338 if (ret)
1339 goto cleanup_power;
1340
1341 INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1342
1343 intel_modeset_gem_init(dev);
1344
1345 /* Always safe in the mode setting case. */
1346 /* FIXME: do pre/post-mode set stuff in core KMS code */
1347 dev->vblank_disable_allowed = true;
1348 if (INTEL_INFO(dev)->num_pipes == 0) {
1349 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
1350 return 0;
1351 }
1352
1353 ret = intel_fbdev_init(dev);
1354 if (ret)
1355 goto cleanup_gem;
1356
1357 /* Only enable hotplug handling once the fbdev is fully set up. */
1358 intel_hpd_init(dev);
1359
1360 /*
1361 * Some ports require correctly set-up hpd registers for detection to
1362 * work properly (leading to ghost connected connector status), e.g. VGA
1363 * on gm45. Hence we can only set up the initial fbdev config after hpd
1364 * irqs are fully enabled. Now we should scan for the initial config
1365 * only once hotplug handling is enabled, but due to screwed-up locking
1366 * around kms/fbdev init we can't protect the fdbev initial config
1367 * scanning against hotplug events. Hence do this first and ignore the
1368 * tiny window where we will loose hotplug notifactions.
1369 */
1370 intel_fbdev_initial_config(dev);
1371
1372 /* Only enable hotplug handling once the fbdev is fully set up. */
1373 dev_priv->enable_hotplug_processing = true;
1374
1375 drm_kms_helper_poll_init(dev);
1376
1377 return 0;
1378
1379cleanup_gem:
1380 mutex_lock(&dev->struct_mutex);
1381 i915_gem_cleanup_ringbuffer(dev);
1382 i915_gem_context_fini(dev);
1383 mutex_unlock(&dev->struct_mutex);
1384 WARN_ON(dev_priv->mm.aliasing_ppgtt);
1385 drm_mm_takedown(&dev_priv->gtt.base.mm);
1386cleanup_power:
1387 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
1388 drm_irq_uninstall(dev);
1389cleanup_gem_stolen:
1390 i915_gem_cleanup_stolen(dev);
1391cleanup_vga_switcheroo:
1392 vga_switcheroo_unregister_client(dev->pdev);
1393cleanup_vga_client:
1394 vga_client_register(dev->pdev, NULL, NULL, NULL);
1395out:
1396 return ret;
1397}
1398
1399int i915_master_create(struct drm_device *dev, struct drm_master *master)
1400{
1401 struct drm_i915_master_private *master_priv;
1402
1403 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1404 if (!master_priv)
1405 return -ENOMEM;
1406
1407 master->driver_priv = master_priv;
1408 return 0;
1409}
1410
1411void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1412{
1413 struct drm_i915_master_private *master_priv = master->driver_priv;
1414
1415 if (!master_priv)
1416 return;
1417
1418 kfree(master_priv);
1419
1420 master->driver_priv = NULL;
1421}
1422
1423#if IS_ENABLED(CONFIG_FB)
1424static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1425{
1426 struct apertures_struct *ap;
1427 struct pci_dev *pdev = dev_priv->dev->pdev;
1428 bool primary;
1429
1430 ap = alloc_apertures(1);
1431 if (!ap)
1432 return;
1433
1434 ap->ranges[0].base = dev_priv->gtt.mappable_base;
1435 ap->ranges[0].size = dev_priv->gtt.mappable_end;
1436
1437 primary =
1438 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1439
1440 remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1441
1442 kfree(ap);
1443}
1444#else
1445static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1446{
1447}
1448#endif
1449
1450static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1451{
1452 const struct intel_device_info *info = &dev_priv->info;
1453
1454#define PRINT_S(name) "%s"
1455#define SEP_EMPTY
1456#define PRINT_FLAG(name) info->name ? #name "," : ""
1457#define SEP_COMMA ,
1458 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1459 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
1460 info->gen,
1461 dev_priv->dev->pdev->device,
1462 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
1463#undef PRINT_S
1464#undef SEP_EMPTY
1465#undef PRINT_FLAG
1466#undef SEP_COMMA
1467}
1468
1469/*
1470 * Determine various intel_device_info fields at runtime.
1471 *
1472 * Use it when either:
1473 * - it's judged too laborious to fill n static structures with the limit
1474 * when a simple if statement does the job,
1475 * - run-time checks (eg read fuse/strap registers) are needed.
1476 *
1477 * This function needs to be called:
1478 * - after the MMIO has been setup as we are reading registers,
1479 * - after the PCH has been detected,
1480 * - before the first usage of the fields it can tweak.
1481 */
1482static void intel_device_info_runtime_init(struct drm_device *dev)
1483{
1484 struct drm_i915_private *dev_priv = dev->dev_private;
1485 struct intel_device_info *info;
1486 enum pipe pipe;
1487
1488 info = (struct intel_device_info *)&dev_priv->info;
1489
1490 if (IS_VALLEYVIEW(dev))
1491 for_each_pipe(pipe)
1492 info->num_sprites[pipe] = 2;
1493 else
1494 for_each_pipe(pipe)
1495 info->num_sprites[pipe] = 1;
1496
1497 if (i915.disable_display) {
1498 DRM_INFO("Display disabled (module parameter)\n");
1499 info->num_pipes = 0;
1500 } else if (info->num_pipes > 0 &&
1501 (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
1502 !IS_VALLEYVIEW(dev)) {
1503 u32 fuse_strap = I915_READ(FUSE_STRAP);
1504 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
1505
1506 /*
1507 * SFUSE_STRAP is supposed to have a bit signalling the display
1508 * is fused off. Unfortunately it seems that, at least in
1509 * certain cases, fused off display means that PCH display
1510 * reads don't land anywhere. In that case, we read 0s.
1511 *
1512 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
1513 * should be set when taking over after the firmware.
1514 */
1515 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
1516 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
1517 (dev_priv->pch_type == PCH_CPT &&
1518 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
1519 DRM_INFO("Display fused off, disabling\n");
1520 info->num_pipes = 0;
1521 }
1522 }
1523}
1524
1525/**
1526 * i915_driver_load - setup chip and create an initial config
1527 * @dev: DRM device
1528 * @flags: startup flags
1529 *
1530 * The driver load routine has to do several things:
1531 * - drive output discovery via intel_modeset_init()
1532 * - initialize the memory manager
1533 * - allocate initial config memory
1534 * - setup the DRM framebuffer with the allocated memory
1535 */
1536int i915_driver_load(struct drm_device *dev, unsigned long flags)
1537{
1538 struct drm_i915_private *dev_priv;
1539 struct intel_device_info *info, *device_info;
1540 int ret = 0, mmio_bar, mmio_size;
1541 uint32_t aperture_size;
1542
1543 info = (struct intel_device_info *) flags;
1544
1545 /* Refuse to load on gen6+ without kms enabled. */
1546 if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
1547 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
1548 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
1549 return -ENODEV;
1550 }
1551
1552 /* UMS needs agp support. */
1553 if (!drm_core_check_feature(dev, DRIVER_MODESET) && !dev->agp)
1554 return -EINVAL;
1555
1556 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1557 if (dev_priv == NULL)
1558 return -ENOMEM;
1559
1560 dev->dev_private = (void *)dev_priv;
1561 dev_priv->dev = dev;
1562
1563 /* copy initial configuration to dev_priv->info */
1564 device_info = (struct intel_device_info *)&dev_priv->info;
1565 *device_info = *info;
1566
1567 spin_lock_init(&dev_priv->irq_lock);
1568 spin_lock_init(&dev_priv->gpu_error.lock);
1569 spin_lock_init(&dev_priv->backlight_lock);
1570 spin_lock_init(&dev_priv->uncore.lock);
1571 spin_lock_init(&dev_priv->mm.object_stat_lock);
1572 mutex_init(&dev_priv->dpio_lock);
1573 mutex_init(&dev_priv->modeset_restore_lock);
1574
1575 intel_pm_setup(dev);
1576
1577 intel_display_crc_init(dev);
1578
1579 i915_dump_device_info(dev_priv);
1580
1581 /* Not all pre-production machines fall into this category, only the
1582 * very first ones. Almost everything should work, except for maybe
1583 * suspend/resume. And we don't implement workarounds that affect only
1584 * pre-production machines. */
1585 if (IS_HSW_EARLY_SDV(dev))
1586 DRM_INFO("This is an early pre-production Haswell machine. "
1587 "It may not be fully functional.\n");
1588
1589 if (i915_get_bridge_dev(dev)) {
1590 ret = -EIO;
1591 goto free_priv;
1592 }
1593
1594 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1595 /* Before gen4, the registers and the GTT are behind different BARs.
1596 * However, from gen4 onwards, the registers and the GTT are shared
1597 * in the same BAR, so we want to restrict this ioremap from
1598 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1599 * the register BAR remains the same size for all the earlier
1600 * generations up to Ironlake.
1601 */
1602 if (info->gen < 5)
1603 mmio_size = 512*1024;
1604 else
1605 mmio_size = 2*1024*1024;
1606
1607 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1608 if (!dev_priv->regs) {
1609 DRM_ERROR("failed to map registers\n");
1610 ret = -EIO;
1611 goto put_bridge;
1612 }
1613
1614 /* This must be called before any calls to HAS_PCH_* */
1615 intel_detect_pch(dev);
1616
1617 intel_uncore_init(dev);
1618
1619 ret = i915_gem_gtt_init(dev);
1620 if (ret)
1621 goto out_regs;
1622
1623 if (drm_core_check_feature(dev, DRIVER_MODESET))
1624 i915_kick_out_firmware_fb(dev_priv);
1625
1626 pci_set_master(dev->pdev);
1627
1628 /* overlay on gen2 is broken and can't address above 1G */
1629 if (IS_GEN2(dev))
1630 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1631
1632 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1633 * using 32bit addressing, overwriting memory if HWS is located
1634 * above 4GB.
1635 *
1636 * The documentation also mentions an issue with undefined
1637 * behaviour if any general state is accessed within a page above 4GB,
1638 * which also needs to be handled carefully.
1639 */
1640 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1641 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1642
1643 aperture_size = dev_priv->gtt.mappable_end;
1644
1645 dev_priv->gtt.mappable =
1646 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1647 aperture_size);
1648 if (dev_priv->gtt.mappable == NULL) {
1649 ret = -EIO;
1650 goto out_gtt;
1651 }
1652
1653 dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
1654 aperture_size);
1655
1656 /* The i915 workqueue is primarily used for batched retirement of
1657 * requests (and thus managing bo) once the task has been completed
1658 * by the GPU. i915_gem_retire_requests() is called directly when we
1659 * need high-priority retirement, such as waiting for an explicit
1660 * bo.
1661 *
1662 * It is also used for periodic low-priority events, such as
1663 * idle-timers and recording error state.
1664 *
1665 * All tasks on the workqueue are expected to acquire the dev mutex
1666 * so there is no point in running more than one instance of the
1667 * workqueue at any time. Use an ordered one.
1668 */
1669 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1670 if (dev_priv->wq == NULL) {
1671 DRM_ERROR("Failed to create our workqueue.\n");
1672 ret = -ENOMEM;
1673 goto out_mtrrfree;
1674 }
1675
1676 intel_irq_init(dev);
1677 intel_uncore_sanitize(dev);
1678
1679 /* Try to make sure MCHBAR is enabled before poking at it */
1680 intel_setup_mchbar(dev);
1681 intel_setup_gmbus(dev);
1682 intel_opregion_setup(dev);
1683
1684 intel_setup_bios(dev);
1685
1686 i915_gem_load(dev);
1687
1688 /* On the 945G/GM, the chipset reports the MSI capability on the
1689 * integrated graphics even though the support isn't actually there
1690 * according to the published specs. It doesn't appear to function
1691 * correctly in testing on 945G.
1692 * This may be a side effect of MSI having been made available for PEG
1693 * and the registers being closely associated.
1694 *
1695 * According to chipset errata, on the 965GM, MSI interrupts may
1696 * be lost or delayed, but we use them anyways to avoid
1697 * stuck interrupts on some machines.
1698 */
1699 if (!IS_I945G(dev) && !IS_I945GM(dev))
1700 pci_enable_msi(dev->pdev);
1701
1702 intel_device_info_runtime_init(dev);
1703
1704 if (INTEL_INFO(dev)->num_pipes) {
1705 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1706 if (ret)
1707 goto out_gem_unload;
1708 }
1709
1710 intel_power_domains_init(dev_priv);
1711
1712 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1713 ret = i915_load_modeset_init(dev);
1714 if (ret < 0) {
1715 DRM_ERROR("failed to init modeset\n");
1716 goto out_power_well;
1717 }
1718 } else {
1719 /* Start out suspended in ums mode. */
1720 dev_priv->ums.mm_suspended = 1;
1721 }
1722
1723 i915_setup_sysfs(dev);
1724
1725 if (INTEL_INFO(dev)->num_pipes) {
1726 /* Must be done after probing outputs */
1727 intel_opregion_init(dev);
1728 acpi_video_register();
1729 }
1730
1731 if (IS_GEN5(dev))
1732 intel_gpu_ips_init(dev_priv);
1733
1734 intel_init_runtime_pm(dev_priv);
1735
1736 return 0;
1737
1738out_power_well:
1739 intel_power_domains_remove(dev_priv);
1740 drm_vblank_cleanup(dev);
1741out_gem_unload:
1742 if (dev_priv->mm.inactive_shrinker.scan_objects)
1743 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1744
1745 if (dev->pdev->msi_enabled)
1746 pci_disable_msi(dev->pdev);
1747
1748 intel_teardown_gmbus(dev);
1749 intel_teardown_mchbar(dev);
1750 pm_qos_remove_request(&dev_priv->pm_qos);
1751 destroy_workqueue(dev_priv->wq);
1752out_mtrrfree:
1753 arch_phys_wc_del(dev_priv->gtt.mtrr);
1754 io_mapping_free(dev_priv->gtt.mappable);
1755out_gtt:
1756 list_del(&dev_priv->gtt.base.global_link);
1757 drm_mm_takedown(&dev_priv->gtt.base.mm);
1758 dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1759out_regs:
1760 intel_uncore_fini(dev);
1761 pci_iounmap(dev->pdev, dev_priv->regs);
1762put_bridge:
1763 pci_dev_put(dev_priv->bridge_dev);
1764free_priv:
1765 if (dev_priv->slab)
1766 kmem_cache_destroy(dev_priv->slab);
1767 kfree(dev_priv);
1768 return ret;
1769}
1770
1771int i915_driver_unload(struct drm_device *dev)
1772{
1773 struct drm_i915_private *dev_priv = dev->dev_private;
1774 int ret;
1775
1776 ret = i915_gem_suspend(dev);
1777 if (ret) {
1778 DRM_ERROR("failed to idle hardware: %d\n", ret);
1779 return ret;
1780 }
1781
1782 intel_fini_runtime_pm(dev_priv);
1783
1784 intel_gpu_ips_teardown();
1785
1786 /* The i915.ko module is still not prepared to be loaded when
1787 * the power well is not enabled, so just enable it in case
1788 * we're going to unload/reload. */
1789 intel_display_set_init_power(dev_priv, true);
1790 intel_power_domains_remove(dev_priv);
1791
1792 i915_teardown_sysfs(dev);
1793
1794 if (dev_priv->mm.inactive_shrinker.scan_objects)
1795 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1796
1797 io_mapping_free(dev_priv->gtt.mappable);
1798 arch_phys_wc_del(dev_priv->gtt.mtrr);
1799
1800 acpi_video_unregister();
1801
1802 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1803 intel_fbdev_fini(dev);
1804 intel_modeset_cleanup(dev);
1805 cancel_work_sync(&dev_priv->console_resume_work);
1806
1807 /*
1808 * free the memory space allocated for the child device
1809 * config parsed from VBT
1810 */
1811 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1812 kfree(dev_priv->vbt.child_dev);
1813 dev_priv->vbt.child_dev = NULL;
1814 dev_priv->vbt.child_dev_num = 0;
1815 }
1816
1817 vga_switcheroo_unregister_client(dev->pdev);
1818 vga_client_register(dev->pdev, NULL, NULL, NULL);
1819 }
1820
1821 /* Free error state after interrupts are fully disabled. */
1822 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1823 cancel_work_sync(&dev_priv->gpu_error.work);
1824 i915_destroy_error_state(dev);
1825
1826 if (dev->pdev->msi_enabled)
1827 pci_disable_msi(dev->pdev);
1828
1829 intel_opregion_fini(dev);
1830
1831 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1832 /* Flush any outstanding unpin_work. */
1833 flush_workqueue(dev_priv->wq);
1834
1835 mutex_lock(&dev->struct_mutex);
1836 i915_gem_cleanup_ringbuffer(dev);
1837 i915_gem_context_fini(dev);
1838 WARN_ON(dev_priv->mm.aliasing_ppgtt);
1839 mutex_unlock(&dev->struct_mutex);
1840 i915_gem_cleanup_stolen(dev);
1841
1842 if (!I915_NEED_GFX_HWS(dev))
1843 i915_free_hws(dev);
1844 }
1845
1846 list_del(&dev_priv->gtt.base.global_link);
1847 WARN_ON(!list_empty(&dev_priv->vm_list));
1848
1849 drm_vblank_cleanup(dev);
1850
1851 intel_teardown_gmbus(dev);
1852 intel_teardown_mchbar(dev);
1853
1854 destroy_workqueue(dev_priv->wq);
1855 pm_qos_remove_request(&dev_priv->pm_qos);
1856
1857 dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1858
1859 intel_uncore_fini(dev);
1860 if (dev_priv->regs != NULL)
1861 pci_iounmap(dev->pdev, dev_priv->regs);
1862
1863 if (dev_priv->slab)
1864 kmem_cache_destroy(dev_priv->slab);
1865
1866 pci_dev_put(dev_priv->bridge_dev);
1867 kfree(dev->dev_private);
1868
1869 return 0;
1870}
1871
1872int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1873{
1874 int ret;
1875
1876 ret = i915_gem_open(dev, file);
1877 if (ret)
1878 return ret;
1879
1880 return 0;
1881}
1882
1883/**
1884 * i915_driver_lastclose - clean up after all DRM clients have exited
1885 * @dev: DRM device
1886 *
1887 * Take care of cleaning up after all DRM clients have exited. In the
1888 * mode setting case, we want to restore the kernel's initial mode (just
1889 * in case the last client left us in a bad state).
1890 *
1891 * Additionally, in the non-mode setting case, we'll tear down the GTT
1892 * and DMA structures, since the kernel won't be using them, and clea
1893 * up any GEM state.
1894 */
1895void i915_driver_lastclose(struct drm_device * dev)
1896{
1897 struct drm_i915_private *dev_priv = dev->dev_private;
1898
1899 /* On gen6+ we refuse to init without kms enabled, but then the drm core
1900 * goes right around and calls lastclose. Check for this and don't clean
1901 * up anything. */
1902 if (!dev_priv)
1903 return;
1904
1905 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1906 intel_fbdev_restore_mode(dev);
1907 vga_switcheroo_process_delayed_switch();
1908 return;
1909 }
1910
1911 i915_gem_lastclose(dev);
1912
1913 i915_dma_cleanup(dev);
1914}
1915
1916void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1917{
1918 mutex_lock(&dev->struct_mutex);
1919 i915_gem_context_close(dev, file_priv);
1920 i915_gem_release(dev, file_priv);
1921 mutex_unlock(&dev->struct_mutex);
1922}
1923
1924void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1925{
1926 struct drm_i915_file_private *file_priv = file->driver_priv;
1927
1928 kfree(file_priv);
1929}
1930
1931const struct drm_ioctl_desc i915_ioctls[] = {
1932 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1933 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1934 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1935 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1936 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1937 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1938 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1939 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1940 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1941 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1942 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1943 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1944 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1945 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1946 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
1947 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1948 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1949 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1950 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1951 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1952 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1953 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1954 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1955 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1956 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1957 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1958 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1959 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1960 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1961 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1962 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1963 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1964 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1965 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1966 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1967 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1968 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1969 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1970 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1971 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1972 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1973 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1974 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1975 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1976 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1977 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1978 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1979 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1980 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1981};
1982
1983int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1984
1985/*
1986 * This is really ugly: Because old userspace abused the linux agp interface to
1987 * manage the gtt, we need to claim that all intel devices are agp. For
1988 * otherwise the drm core refuses to initialize the agp support code.
1989 */
1990int i915_driver_device_is_agp(struct drm_device * dev)
1991{
1992 return 1;
1993}