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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#define SWSMU_CODE_LAYER_L2
25
26#include <linux/firmware.h>
27#include <linux/pci.h>
28#include <linux/i2c.h>
29#include "amdgpu.h"
30#include "amdgpu_dpm.h"
31#include "amdgpu_smu.h"
32#include "atomfirmware.h"
33#include "amdgpu_atomfirmware.h"
34#include "amdgpu_atombios.h"
35#include "soc15_common.h"
36#include "smu_v11_0.h"
37#include "smu11_driver_if_navi10.h"
38#include "atom.h"
39#include "navi10_ppt.h"
40#include "smu_v11_0_pptable.h"
41#include "smu_v11_0_ppsmc.h"
42#include "nbio/nbio_2_3_offset.h"
43#include "nbio/nbio_2_3_sh_mask.h"
44#include "thm/thm_11_0_2_offset.h"
45#include "thm/thm_11_0_2_sh_mask.h"
46
47#include "asic_reg/mp/mp_11_0_sh_mask.h"
48#include "smu_cmn.h"
49#include "smu_11_0_cdr_table.h"
50
51/*
52 * DO NOT use these for err/warn/info/debug messages.
53 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
54 * They are more MGPU friendly.
55 */
56#undef pr_err
57#undef pr_warn
58#undef pr_info
59#undef pr_debug
60
61#define FEATURE_MASK(feature) (1ULL << feature)
62#define SMC_DPM_FEATURE ( \
63 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
70 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
71
72#define SMU_11_0_GFX_BUSY_THRESHOLD 15
73
74static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
75 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
76 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
77 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
78 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
79 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
80 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
81 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
82 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 0),
83 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 0),
84 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0),
85 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0),
86 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
87 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
88 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 0),
89 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
90 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
91 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
92 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
93 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
94 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
95 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
96 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
97 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0),
98 MSG_MAP(RunBtc, PPSMC_MSG_RunBtc, 0),
99 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
100 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
101 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
102 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0),
103 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
104 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
105 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
106 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
107 MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig, 0),
108 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
109 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
110 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
111 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
112 MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk, 0),
113 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
114 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
115 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
116 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
117 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
118 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
119 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
120 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
121 MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt, 0),
122 MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays, 0),
123 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
124 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0),
125 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
126 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
127 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
128 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
129 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
130 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
131 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0),
132 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0),
133 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
134 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
135 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
136 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
137 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
138 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
139 MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALDisableDummyPstateChange, 0),
140 MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange, 0),
141 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0),
142 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
143 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
144 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, PPSMC_MSG_SetDriverDummyTableDramAddrHigh, 0),
145 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, PPSMC_MSG_SetDriverDummyTableDramAddrLow, 0),
146 MSG_MAP(GET_UMC_FW_WA, PPSMC_MSG_GetUMCFWWA, 0),
147};
148
149static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = {
150 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
151 CLK_MAP(SCLK, PPCLK_GFXCLK),
152 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
153 CLK_MAP(FCLK, PPCLK_SOCCLK),
154 CLK_MAP(UCLK, PPCLK_UCLK),
155 CLK_MAP(MCLK, PPCLK_UCLK),
156 CLK_MAP(DCLK, PPCLK_DCLK),
157 CLK_MAP(VCLK, PPCLK_VCLK),
158 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
159 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
160 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
161 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
162};
163
164static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
165 FEA_MAP(DPM_PREFETCHER),
166 FEA_MAP(DPM_GFXCLK),
167 FEA_MAP(DPM_GFX_PACE),
168 FEA_MAP(DPM_UCLK),
169 FEA_MAP(DPM_SOCCLK),
170 FEA_MAP(DPM_MP0CLK),
171 FEA_MAP(DPM_LINK),
172 FEA_MAP(DPM_DCEFCLK),
173 FEA_MAP(MEM_VDDCI_SCALING),
174 FEA_MAP(MEM_MVDD_SCALING),
175 FEA_MAP(DS_GFXCLK),
176 FEA_MAP(DS_SOCCLK),
177 FEA_MAP(DS_LCLK),
178 FEA_MAP(DS_DCEFCLK),
179 FEA_MAP(DS_UCLK),
180 FEA_MAP(GFX_ULV),
181 FEA_MAP(FW_DSTATE),
182 FEA_MAP(GFXOFF),
183 FEA_MAP(BACO),
184 FEA_MAP(VCN_PG),
185 FEA_MAP(JPEG_PG),
186 FEA_MAP(USB_PG),
187 FEA_MAP(RSMU_SMN_CG),
188 FEA_MAP(PPT),
189 FEA_MAP(TDC),
190 FEA_MAP(GFX_EDC),
191 FEA_MAP(APCC_PLUS),
192 FEA_MAP(GTHR),
193 FEA_MAP(ACDC),
194 FEA_MAP(VR0HOT),
195 FEA_MAP(VR1HOT),
196 FEA_MAP(FW_CTF),
197 FEA_MAP(FAN_CONTROL),
198 FEA_MAP(THERMAL),
199 FEA_MAP(GFX_DCS),
200 FEA_MAP(RM),
201 FEA_MAP(LED_DISPLAY),
202 FEA_MAP(GFX_SS),
203 FEA_MAP(OUT_OF_BAND_MONITOR),
204 FEA_MAP(TEMP_DEPENDENT_VMIN),
205 FEA_MAP(MMHUB_PG),
206 FEA_MAP(ATHUB_PG),
207 FEA_MAP(APCC_DFLL),
208};
209
210static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = {
211 TAB_MAP(PPTABLE),
212 TAB_MAP(WATERMARKS),
213 TAB_MAP(AVFS),
214 TAB_MAP(AVFS_PSM_DEBUG),
215 TAB_MAP(AVFS_FUSE_OVERRIDE),
216 TAB_MAP(PMSTATUSLOG),
217 TAB_MAP(SMU_METRICS),
218 TAB_MAP(DRIVER_SMU_CONFIG),
219 TAB_MAP(ACTIVITY_MONITOR_COEFF),
220 TAB_MAP(OVERDRIVE),
221 TAB_MAP(I2C_COMMANDS),
222 TAB_MAP(PACE),
223};
224
225static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
226 PWR_MAP(AC),
227 PWR_MAP(DC),
228};
229
230static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
231 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
232 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
238};
239
240static const uint8_t navi1x_throttler_map[] = {
241 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
242 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
243 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
244 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
245 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
246 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
247 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
248 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
249 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
250 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
251 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
252 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
253 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
254 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
255 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
256 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
257 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
258 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
259};
260
261
262static bool is_asic_secure(struct smu_context *smu)
263{
264 struct amdgpu_device *adev = smu->adev;
265 bool is_secure = true;
266 uint32_t mp0_fw_intf;
267
268 mp0_fw_intf = RREG32_PCIE(MP0_Public |
269 (smnMP0_FW_INTF & 0xffffffff));
270
271 if (!(mp0_fw_intf & (1 << 19)))
272 is_secure = false;
273
274 return is_secure;
275}
276
277static int
278navi10_get_allowed_feature_mask(struct smu_context *smu,
279 uint32_t *feature_mask, uint32_t num)
280{
281 struct amdgpu_device *adev = smu->adev;
282
283 if (num > 2)
284 return -EINVAL;
285
286 memset(feature_mask, 0, sizeof(uint32_t) * num);
287
288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
289 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
290 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
291 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
292 | FEATURE_MASK(FEATURE_PPT_BIT)
293 | FEATURE_MASK(FEATURE_TDC_BIT)
294 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
295 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
296 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
297 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
298 | FEATURE_MASK(FEATURE_THERMAL_BIT)
299 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
300 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
301 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
302 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
303 | FEATURE_MASK(FEATURE_BACO_BIT)
304 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
305 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
306 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
307 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT)
308 | FEATURE_MASK(FEATURE_TEMP_DEPENDENT_VMIN_BIT);
309
310 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
312
313 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
315
316 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
318
319 if (adev->pm.pp_feature & PP_ULV_MASK)
320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
321
322 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
323 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
324
325 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
327
328 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
330
331 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
333
334 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
335 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
336
337 if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
338 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
339
340 if (smu->dc_controlled_by_gpio)
341 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
342
343 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
344 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
345
346 /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
347 if (!(is_asic_secure(smu) &&
348 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
349 (adev->rev_id == 0)) &&
350 (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
351 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
352 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
353 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
354
355 /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
356 if (is_asic_secure(smu) &&
357 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
358 (adev->rev_id == 0))
359 *(uint64_t *)feature_mask &=
360 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
361
362 return 0;
363}
364
365static void navi10_check_bxco_support(struct smu_context *smu)
366{
367 struct smu_table_context *table_context = &smu->smu_table;
368 struct smu_11_0_powerplay_table *powerplay_table =
369 table_context->power_play_table;
370 struct smu_baco_context *smu_baco = &smu->smu_baco;
371 struct amdgpu_device *adev = smu->adev;
372 uint32_t val;
373
374 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
375 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
376 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
377 smu_baco->platform_support =
378 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
379 false;
380 }
381}
382
383static int navi10_check_powerplay_table(struct smu_context *smu)
384{
385 struct smu_table_context *table_context = &smu->smu_table;
386 struct smu_11_0_powerplay_table *powerplay_table =
387 table_context->power_play_table;
388
389 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC)
390 smu->dc_controlled_by_gpio = true;
391
392 navi10_check_bxco_support(smu);
393
394 table_context->thermal_controller_type =
395 powerplay_table->thermal_controller_type;
396
397 /*
398 * Instead of having its own buffer space and get overdrive_table copied,
399 * smu->od_settings just points to the actual overdrive_table
400 */
401 smu->od_settings = &powerplay_table->overdrive_table;
402
403 return 0;
404}
405
406static int navi10_append_powerplay_table(struct smu_context *smu)
407{
408 struct amdgpu_device *adev = smu->adev;
409 struct smu_table_context *table_context = &smu->smu_table;
410 PPTable_t *smc_pptable = table_context->driver_pptable;
411 struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
412 struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7;
413 int index, ret;
414
415 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
416 smc_dpm_info);
417
418 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
419 (uint8_t **)&smc_dpm_table);
420 if (ret)
421 return ret;
422
423 dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
424 smc_dpm_table->table_header.format_revision,
425 smc_dpm_table->table_header.content_revision);
426
427 if (smc_dpm_table->table_header.format_revision != 4) {
428 dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n");
429 return -EINVAL;
430 }
431
432 switch (smc_dpm_table->table_header.content_revision) {
433 case 5: /* nv10 and nv14 */
434 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved,
435 smc_dpm_table, I2cControllers);
436 break;
437 case 7: /* nv12 */
438 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
439 (uint8_t **)&smc_dpm_table_v4_7);
440 if (ret)
441 return ret;
442 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved,
443 smc_dpm_table_v4_7, I2cControllers);
444 break;
445 default:
446 dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n",
447 smc_dpm_table->table_header.content_revision);
448 return -EINVAL;
449 }
450
451 if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
452 /* TODO: remove it once SMU fw fix it */
453 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
454 }
455
456 return 0;
457}
458
459static int navi10_store_powerplay_table(struct smu_context *smu)
460{
461 struct smu_table_context *table_context = &smu->smu_table;
462 struct smu_11_0_powerplay_table *powerplay_table =
463 table_context->power_play_table;
464
465 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
466 sizeof(PPTable_t));
467
468 return 0;
469}
470
471static int navi10_setup_pptable(struct smu_context *smu)
472{
473 int ret = 0;
474
475 ret = smu_v11_0_setup_pptable(smu);
476 if (ret)
477 return ret;
478
479 ret = navi10_store_powerplay_table(smu);
480 if (ret)
481 return ret;
482
483 ret = navi10_append_powerplay_table(smu);
484 if (ret)
485 return ret;
486
487 ret = navi10_check_powerplay_table(smu);
488 if (ret)
489 return ret;
490
491 return ret;
492}
493
494static int navi10_tables_init(struct smu_context *smu)
495{
496 struct smu_table_context *smu_table = &smu->smu_table;
497 struct smu_table *tables = smu_table->tables;
498 struct smu_table *dummy_read_1_table =
499 &smu_table->dummy_read_1_table;
500
501 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
502 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
503 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
504 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
505 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV1X_t),
506 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
507 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
508 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
509 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
510 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
511 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
512 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
513 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
514 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
515 AMDGPU_GEM_DOMAIN_VRAM);
516 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfig_t),
517 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
518
519 dummy_read_1_table->size = 0x40000;
520 dummy_read_1_table->align = PAGE_SIZE;
521 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
522
523 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_NV1X_t),
524 GFP_KERNEL);
525 if (!smu_table->metrics_table)
526 goto err0_out;
527 smu_table->metrics_time = 0;
528
529 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
530 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
531 if (!smu_table->gpu_metrics_table)
532 goto err1_out;
533
534 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
535 if (!smu_table->watermarks_table)
536 goto err2_out;
537
538 smu_table->driver_smu_config_table =
539 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL);
540 if (!smu_table->driver_smu_config_table)
541 goto err3_out;
542
543 return 0;
544
545err3_out:
546 kfree(smu_table->watermarks_table);
547err2_out:
548 kfree(smu_table->gpu_metrics_table);
549err1_out:
550 kfree(smu_table->metrics_table);
551err0_out:
552 return -ENOMEM;
553}
554
555static int navi10_get_legacy_smu_metrics_data(struct smu_context *smu,
556 MetricsMember_t member,
557 uint32_t *value)
558{
559 struct smu_table_context *smu_table = &smu->smu_table;
560 SmuMetrics_legacy_t *metrics =
561 (SmuMetrics_legacy_t *)smu_table->metrics_table;
562 int ret = 0;
563
564 ret = smu_cmn_get_metrics_table(smu,
565 NULL,
566 false);
567 if (ret)
568 return ret;
569
570 switch (member) {
571 case METRICS_CURR_GFXCLK:
572 *value = metrics->CurrClock[PPCLK_GFXCLK];
573 break;
574 case METRICS_CURR_SOCCLK:
575 *value = metrics->CurrClock[PPCLK_SOCCLK];
576 break;
577 case METRICS_CURR_UCLK:
578 *value = metrics->CurrClock[PPCLK_UCLK];
579 break;
580 case METRICS_CURR_VCLK:
581 *value = metrics->CurrClock[PPCLK_VCLK];
582 break;
583 case METRICS_CURR_DCLK:
584 *value = metrics->CurrClock[PPCLK_DCLK];
585 break;
586 case METRICS_CURR_DCEFCLK:
587 *value = metrics->CurrClock[PPCLK_DCEFCLK];
588 break;
589 case METRICS_AVERAGE_GFXCLK:
590 *value = metrics->AverageGfxclkFrequency;
591 break;
592 case METRICS_AVERAGE_SOCCLK:
593 *value = metrics->AverageSocclkFrequency;
594 break;
595 case METRICS_AVERAGE_UCLK:
596 *value = metrics->AverageUclkFrequency;
597 break;
598 case METRICS_AVERAGE_GFXACTIVITY:
599 *value = metrics->AverageGfxActivity;
600 break;
601 case METRICS_AVERAGE_MEMACTIVITY:
602 *value = metrics->AverageUclkActivity;
603 break;
604 case METRICS_AVERAGE_SOCKETPOWER:
605 *value = metrics->AverageSocketPower << 8;
606 break;
607 case METRICS_TEMPERATURE_EDGE:
608 *value = metrics->TemperatureEdge *
609 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
610 break;
611 case METRICS_TEMPERATURE_HOTSPOT:
612 *value = metrics->TemperatureHotspot *
613 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
614 break;
615 case METRICS_TEMPERATURE_MEM:
616 *value = metrics->TemperatureMem *
617 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
618 break;
619 case METRICS_TEMPERATURE_VRGFX:
620 *value = metrics->TemperatureVrGfx *
621 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
622 break;
623 case METRICS_TEMPERATURE_VRSOC:
624 *value = metrics->TemperatureVrSoc *
625 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
626 break;
627 case METRICS_THROTTLER_STATUS:
628 *value = metrics->ThrottlerStatus;
629 break;
630 case METRICS_CURR_FANSPEED:
631 *value = metrics->CurrFanSpeed;
632 break;
633 default:
634 *value = UINT_MAX;
635 break;
636 }
637
638 return ret;
639}
640
641static int navi10_get_smu_metrics_data(struct smu_context *smu,
642 MetricsMember_t member,
643 uint32_t *value)
644{
645 struct smu_table_context *smu_table = &smu->smu_table;
646 SmuMetrics_t *metrics =
647 (SmuMetrics_t *)smu_table->metrics_table;
648 int ret = 0;
649
650 ret = smu_cmn_get_metrics_table(smu,
651 NULL,
652 false);
653 if (ret)
654 return ret;
655
656 switch (member) {
657 case METRICS_CURR_GFXCLK:
658 *value = metrics->CurrClock[PPCLK_GFXCLK];
659 break;
660 case METRICS_CURR_SOCCLK:
661 *value = metrics->CurrClock[PPCLK_SOCCLK];
662 break;
663 case METRICS_CURR_UCLK:
664 *value = metrics->CurrClock[PPCLK_UCLK];
665 break;
666 case METRICS_CURR_VCLK:
667 *value = metrics->CurrClock[PPCLK_VCLK];
668 break;
669 case METRICS_CURR_DCLK:
670 *value = metrics->CurrClock[PPCLK_DCLK];
671 break;
672 case METRICS_CURR_DCEFCLK:
673 *value = metrics->CurrClock[PPCLK_DCEFCLK];
674 break;
675 case METRICS_AVERAGE_GFXCLK:
676 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
677 *value = metrics->AverageGfxclkFrequencyPreDs;
678 else
679 *value = metrics->AverageGfxclkFrequencyPostDs;
680 break;
681 case METRICS_AVERAGE_SOCCLK:
682 *value = metrics->AverageSocclkFrequency;
683 break;
684 case METRICS_AVERAGE_UCLK:
685 *value = metrics->AverageUclkFrequencyPostDs;
686 break;
687 case METRICS_AVERAGE_GFXACTIVITY:
688 *value = metrics->AverageGfxActivity;
689 break;
690 case METRICS_AVERAGE_MEMACTIVITY:
691 *value = metrics->AverageUclkActivity;
692 break;
693 case METRICS_AVERAGE_SOCKETPOWER:
694 *value = metrics->AverageSocketPower << 8;
695 break;
696 case METRICS_TEMPERATURE_EDGE:
697 *value = metrics->TemperatureEdge *
698 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
699 break;
700 case METRICS_TEMPERATURE_HOTSPOT:
701 *value = metrics->TemperatureHotspot *
702 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
703 break;
704 case METRICS_TEMPERATURE_MEM:
705 *value = metrics->TemperatureMem *
706 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
707 break;
708 case METRICS_TEMPERATURE_VRGFX:
709 *value = metrics->TemperatureVrGfx *
710 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
711 break;
712 case METRICS_TEMPERATURE_VRSOC:
713 *value = metrics->TemperatureVrSoc *
714 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
715 break;
716 case METRICS_THROTTLER_STATUS:
717 *value = metrics->ThrottlerStatus;
718 break;
719 case METRICS_CURR_FANSPEED:
720 *value = metrics->CurrFanSpeed;
721 break;
722 default:
723 *value = UINT_MAX;
724 break;
725 }
726
727 return ret;
728}
729
730static int navi12_get_legacy_smu_metrics_data(struct smu_context *smu,
731 MetricsMember_t member,
732 uint32_t *value)
733{
734 struct smu_table_context *smu_table = &smu->smu_table;
735 SmuMetrics_NV12_legacy_t *metrics =
736 (SmuMetrics_NV12_legacy_t *)smu_table->metrics_table;
737 int ret = 0;
738
739 ret = smu_cmn_get_metrics_table(smu,
740 NULL,
741 false);
742 if (ret)
743 return ret;
744
745 switch (member) {
746 case METRICS_CURR_GFXCLK:
747 *value = metrics->CurrClock[PPCLK_GFXCLK];
748 break;
749 case METRICS_CURR_SOCCLK:
750 *value = metrics->CurrClock[PPCLK_SOCCLK];
751 break;
752 case METRICS_CURR_UCLK:
753 *value = metrics->CurrClock[PPCLK_UCLK];
754 break;
755 case METRICS_CURR_VCLK:
756 *value = metrics->CurrClock[PPCLK_VCLK];
757 break;
758 case METRICS_CURR_DCLK:
759 *value = metrics->CurrClock[PPCLK_DCLK];
760 break;
761 case METRICS_CURR_DCEFCLK:
762 *value = metrics->CurrClock[PPCLK_DCEFCLK];
763 break;
764 case METRICS_AVERAGE_GFXCLK:
765 *value = metrics->AverageGfxclkFrequency;
766 break;
767 case METRICS_AVERAGE_SOCCLK:
768 *value = metrics->AverageSocclkFrequency;
769 break;
770 case METRICS_AVERAGE_UCLK:
771 *value = metrics->AverageUclkFrequency;
772 break;
773 case METRICS_AVERAGE_GFXACTIVITY:
774 *value = metrics->AverageGfxActivity;
775 break;
776 case METRICS_AVERAGE_MEMACTIVITY:
777 *value = metrics->AverageUclkActivity;
778 break;
779 case METRICS_AVERAGE_SOCKETPOWER:
780 *value = metrics->AverageSocketPower << 8;
781 break;
782 case METRICS_TEMPERATURE_EDGE:
783 *value = metrics->TemperatureEdge *
784 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
785 break;
786 case METRICS_TEMPERATURE_HOTSPOT:
787 *value = metrics->TemperatureHotspot *
788 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
789 break;
790 case METRICS_TEMPERATURE_MEM:
791 *value = metrics->TemperatureMem *
792 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
793 break;
794 case METRICS_TEMPERATURE_VRGFX:
795 *value = metrics->TemperatureVrGfx *
796 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
797 break;
798 case METRICS_TEMPERATURE_VRSOC:
799 *value = metrics->TemperatureVrSoc *
800 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
801 break;
802 case METRICS_THROTTLER_STATUS:
803 *value = metrics->ThrottlerStatus;
804 break;
805 case METRICS_CURR_FANSPEED:
806 *value = metrics->CurrFanSpeed;
807 break;
808 default:
809 *value = UINT_MAX;
810 break;
811 }
812
813 return ret;
814}
815
816static int navi12_get_smu_metrics_data(struct smu_context *smu,
817 MetricsMember_t member,
818 uint32_t *value)
819{
820 struct smu_table_context *smu_table = &smu->smu_table;
821 SmuMetrics_NV12_t *metrics =
822 (SmuMetrics_NV12_t *)smu_table->metrics_table;
823 int ret = 0;
824
825 ret = smu_cmn_get_metrics_table(smu,
826 NULL,
827 false);
828 if (ret)
829 return ret;
830
831 switch (member) {
832 case METRICS_CURR_GFXCLK:
833 *value = metrics->CurrClock[PPCLK_GFXCLK];
834 break;
835 case METRICS_CURR_SOCCLK:
836 *value = metrics->CurrClock[PPCLK_SOCCLK];
837 break;
838 case METRICS_CURR_UCLK:
839 *value = metrics->CurrClock[PPCLK_UCLK];
840 break;
841 case METRICS_CURR_VCLK:
842 *value = metrics->CurrClock[PPCLK_VCLK];
843 break;
844 case METRICS_CURR_DCLK:
845 *value = metrics->CurrClock[PPCLK_DCLK];
846 break;
847 case METRICS_CURR_DCEFCLK:
848 *value = metrics->CurrClock[PPCLK_DCEFCLK];
849 break;
850 case METRICS_AVERAGE_GFXCLK:
851 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
852 *value = metrics->AverageGfxclkFrequencyPreDs;
853 else
854 *value = metrics->AverageGfxclkFrequencyPostDs;
855 break;
856 case METRICS_AVERAGE_SOCCLK:
857 *value = metrics->AverageSocclkFrequency;
858 break;
859 case METRICS_AVERAGE_UCLK:
860 *value = metrics->AverageUclkFrequencyPostDs;
861 break;
862 case METRICS_AVERAGE_GFXACTIVITY:
863 *value = metrics->AverageGfxActivity;
864 break;
865 case METRICS_AVERAGE_MEMACTIVITY:
866 *value = metrics->AverageUclkActivity;
867 break;
868 case METRICS_AVERAGE_SOCKETPOWER:
869 *value = metrics->AverageSocketPower << 8;
870 break;
871 case METRICS_TEMPERATURE_EDGE:
872 *value = metrics->TemperatureEdge *
873 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
874 break;
875 case METRICS_TEMPERATURE_HOTSPOT:
876 *value = metrics->TemperatureHotspot *
877 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
878 break;
879 case METRICS_TEMPERATURE_MEM:
880 *value = metrics->TemperatureMem *
881 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
882 break;
883 case METRICS_TEMPERATURE_VRGFX:
884 *value = metrics->TemperatureVrGfx *
885 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
886 break;
887 case METRICS_TEMPERATURE_VRSOC:
888 *value = metrics->TemperatureVrSoc *
889 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
890 break;
891 case METRICS_THROTTLER_STATUS:
892 *value = metrics->ThrottlerStatus;
893 break;
894 case METRICS_CURR_FANSPEED:
895 *value = metrics->CurrFanSpeed;
896 break;
897 default:
898 *value = UINT_MAX;
899 break;
900 }
901
902 return ret;
903}
904
905static int navi1x_get_smu_metrics_data(struct smu_context *smu,
906 MetricsMember_t member,
907 uint32_t *value)
908{
909 struct amdgpu_device *adev = smu->adev;
910 int ret = 0;
911
912 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
913 case IP_VERSION(11, 0, 9):
914 if (smu->smc_fw_version > 0x00341C00)
915 ret = navi12_get_smu_metrics_data(smu, member, value);
916 else
917 ret = navi12_get_legacy_smu_metrics_data(smu, member, value);
918 break;
919 case IP_VERSION(11, 0, 0):
920 case IP_VERSION(11, 0, 5):
921 default:
922 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
923 IP_VERSION(11, 0, 5)) &&
924 smu->smc_fw_version > 0x00351F00) ||
925 ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
926 IP_VERSION(11, 0, 0)) &&
927 smu->smc_fw_version > 0x002A3B00))
928 ret = navi10_get_smu_metrics_data(smu, member, value);
929 else
930 ret = navi10_get_legacy_smu_metrics_data(smu, member, value);
931 break;
932 }
933
934 return ret;
935}
936
937static int navi10_allocate_dpm_context(struct smu_context *smu)
938{
939 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
940
941 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
942 GFP_KERNEL);
943 if (!smu_dpm->dpm_context)
944 return -ENOMEM;
945
946 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
947
948 return 0;
949}
950
951static int navi10_init_smc_tables(struct smu_context *smu)
952{
953 int ret = 0;
954
955 ret = navi10_tables_init(smu);
956 if (ret)
957 return ret;
958
959 ret = navi10_allocate_dpm_context(smu);
960 if (ret)
961 return ret;
962
963 return smu_v11_0_init_smc_tables(smu);
964}
965
966static int navi10_set_default_dpm_table(struct smu_context *smu)
967{
968 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
969 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
970 struct smu_11_0_dpm_table *dpm_table;
971 int ret = 0;
972
973 /* socclk dpm table setup */
974 dpm_table = &dpm_context->dpm_tables.soc_table;
975 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
976 ret = smu_v11_0_set_single_dpm_table(smu,
977 SMU_SOCCLK,
978 dpm_table);
979 if (ret)
980 return ret;
981 dpm_table->is_fine_grained =
982 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
983 } else {
984 dpm_table->count = 1;
985 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
986 dpm_table->dpm_levels[0].enabled = true;
987 dpm_table->min = dpm_table->dpm_levels[0].value;
988 dpm_table->max = dpm_table->dpm_levels[0].value;
989 }
990
991 /* gfxclk dpm table setup */
992 dpm_table = &dpm_context->dpm_tables.gfx_table;
993 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
994 ret = smu_v11_0_set_single_dpm_table(smu,
995 SMU_GFXCLK,
996 dpm_table);
997 if (ret)
998 return ret;
999 dpm_table->is_fine_grained =
1000 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
1001 } else {
1002 dpm_table->count = 1;
1003 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
1004 dpm_table->dpm_levels[0].enabled = true;
1005 dpm_table->min = dpm_table->dpm_levels[0].value;
1006 dpm_table->max = dpm_table->dpm_levels[0].value;
1007 }
1008
1009 /* uclk dpm table setup */
1010 dpm_table = &dpm_context->dpm_tables.uclk_table;
1011 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1012 ret = smu_v11_0_set_single_dpm_table(smu,
1013 SMU_UCLK,
1014 dpm_table);
1015 if (ret)
1016 return ret;
1017 dpm_table->is_fine_grained =
1018 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
1019 } else {
1020 dpm_table->count = 1;
1021 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
1022 dpm_table->dpm_levels[0].enabled = true;
1023 dpm_table->min = dpm_table->dpm_levels[0].value;
1024 dpm_table->max = dpm_table->dpm_levels[0].value;
1025 }
1026
1027 /* vclk dpm table setup */
1028 dpm_table = &dpm_context->dpm_tables.vclk_table;
1029 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1030 ret = smu_v11_0_set_single_dpm_table(smu,
1031 SMU_VCLK,
1032 dpm_table);
1033 if (ret)
1034 return ret;
1035 dpm_table->is_fine_grained =
1036 !driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete;
1037 } else {
1038 dpm_table->count = 1;
1039 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1040 dpm_table->dpm_levels[0].enabled = true;
1041 dpm_table->min = dpm_table->dpm_levels[0].value;
1042 dpm_table->max = dpm_table->dpm_levels[0].value;
1043 }
1044
1045 /* dclk dpm table setup */
1046 dpm_table = &dpm_context->dpm_tables.dclk_table;
1047 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1048 ret = smu_v11_0_set_single_dpm_table(smu,
1049 SMU_DCLK,
1050 dpm_table);
1051 if (ret)
1052 return ret;
1053 dpm_table->is_fine_grained =
1054 !driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete;
1055 } else {
1056 dpm_table->count = 1;
1057 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1058 dpm_table->dpm_levels[0].enabled = true;
1059 dpm_table->min = dpm_table->dpm_levels[0].value;
1060 dpm_table->max = dpm_table->dpm_levels[0].value;
1061 }
1062
1063 /* dcefclk dpm table setup */
1064 dpm_table = &dpm_context->dpm_tables.dcef_table;
1065 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1066 ret = smu_v11_0_set_single_dpm_table(smu,
1067 SMU_DCEFCLK,
1068 dpm_table);
1069 if (ret)
1070 return ret;
1071 dpm_table->is_fine_grained =
1072 !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
1073 } else {
1074 dpm_table->count = 1;
1075 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1076 dpm_table->dpm_levels[0].enabled = true;
1077 dpm_table->min = dpm_table->dpm_levels[0].value;
1078 dpm_table->max = dpm_table->dpm_levels[0].value;
1079 }
1080
1081 /* pixelclk dpm table setup */
1082 dpm_table = &dpm_context->dpm_tables.pixel_table;
1083 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1084 ret = smu_v11_0_set_single_dpm_table(smu,
1085 SMU_PIXCLK,
1086 dpm_table);
1087 if (ret)
1088 return ret;
1089 dpm_table->is_fine_grained =
1090 !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
1091 } else {
1092 dpm_table->count = 1;
1093 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1094 dpm_table->dpm_levels[0].enabled = true;
1095 dpm_table->min = dpm_table->dpm_levels[0].value;
1096 dpm_table->max = dpm_table->dpm_levels[0].value;
1097 }
1098
1099 /* displayclk dpm table setup */
1100 dpm_table = &dpm_context->dpm_tables.display_table;
1101 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1102 ret = smu_v11_0_set_single_dpm_table(smu,
1103 SMU_DISPCLK,
1104 dpm_table);
1105 if (ret)
1106 return ret;
1107 dpm_table->is_fine_grained =
1108 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
1109 } else {
1110 dpm_table->count = 1;
1111 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1112 dpm_table->dpm_levels[0].enabled = true;
1113 dpm_table->min = dpm_table->dpm_levels[0].value;
1114 dpm_table->max = dpm_table->dpm_levels[0].value;
1115 }
1116
1117 /* phyclk dpm table setup */
1118 dpm_table = &dpm_context->dpm_tables.phy_table;
1119 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1120 ret = smu_v11_0_set_single_dpm_table(smu,
1121 SMU_PHYCLK,
1122 dpm_table);
1123 if (ret)
1124 return ret;
1125 dpm_table->is_fine_grained =
1126 !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
1127 } else {
1128 dpm_table->count = 1;
1129 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1130 dpm_table->dpm_levels[0].enabled = true;
1131 dpm_table->min = dpm_table->dpm_levels[0].value;
1132 dpm_table->max = dpm_table->dpm_levels[0].value;
1133 }
1134
1135 return 0;
1136}
1137
1138static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1139{
1140 int ret = 0;
1141
1142 if (enable) {
1143 /* vcn dpm on is a prerequisite for vcn power gate messages */
1144 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1145 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
1146 if (ret)
1147 return ret;
1148 }
1149 } else {
1150 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1151 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
1152 if (ret)
1153 return ret;
1154 }
1155 }
1156
1157 return ret;
1158}
1159
1160static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1161{
1162 int ret = 0;
1163
1164 if (enable) {
1165 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
1166 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL);
1167 if (ret)
1168 return ret;
1169 }
1170 } else {
1171 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
1172 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);
1173 if (ret)
1174 return ret;
1175 }
1176 }
1177
1178 return ret;
1179}
1180
1181static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
1182 enum smu_clk_type clk_type,
1183 uint32_t *value)
1184{
1185 MetricsMember_t member_type;
1186 int clk_id = 0;
1187
1188 clk_id = smu_cmn_to_asic_specific_index(smu,
1189 CMN2ASIC_MAPPING_CLK,
1190 clk_type);
1191 if (clk_id < 0)
1192 return clk_id;
1193
1194 switch (clk_id) {
1195 case PPCLK_GFXCLK:
1196 member_type = METRICS_CURR_GFXCLK;
1197 break;
1198 case PPCLK_UCLK:
1199 member_type = METRICS_CURR_UCLK;
1200 break;
1201 case PPCLK_SOCCLK:
1202 member_type = METRICS_CURR_SOCCLK;
1203 break;
1204 case PPCLK_VCLK:
1205 member_type = METRICS_CURR_VCLK;
1206 break;
1207 case PPCLK_DCLK:
1208 member_type = METRICS_CURR_DCLK;
1209 break;
1210 case PPCLK_DCEFCLK:
1211 member_type = METRICS_CURR_DCEFCLK;
1212 break;
1213 default:
1214 return -EINVAL;
1215 }
1216
1217 return navi1x_get_smu_metrics_data(smu,
1218 member_type,
1219 value);
1220}
1221
1222static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1223{
1224 PPTable_t *pptable = smu->smu_table.driver_pptable;
1225 DpmDescriptor_t *dpm_desc = NULL;
1226 uint32_t clk_index = 0;
1227
1228 clk_index = smu_cmn_to_asic_specific_index(smu,
1229 CMN2ASIC_MAPPING_CLK,
1230 clk_type);
1231 dpm_desc = &pptable->DpmDescriptor[clk_index];
1232
1233 /* 0 - Fine grained DPM, 1 - Discrete DPM */
1234 return dpm_desc->SnapToDiscrete == 0;
1235}
1236
1237static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap)
1238{
1239 return od_table->cap[cap];
1240}
1241
1242static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table,
1243 enum SMU_11_0_ODSETTING_ID setting,
1244 uint32_t *min, uint32_t *max)
1245{
1246 if (min)
1247 *min = od_table->min[setting];
1248 if (max)
1249 *max = od_table->max[setting];
1250}
1251
1252static int navi10_emit_clk_levels(struct smu_context *smu,
1253 enum smu_clk_type clk_type,
1254 char *buf,
1255 int *offset)
1256{
1257 uint16_t *curve_settings;
1258 int ret = 0;
1259 uint32_t cur_value = 0, value = 0;
1260 uint32_t freq_values[3] = {0};
1261 uint32_t i, levels, mark_index = 0, count = 0;
1262 struct smu_table_context *table_context = &smu->smu_table;
1263 uint32_t gen_speed, lane_width;
1264 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1265 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1266 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
1267 OverDriveTable_t *od_table =
1268 (OverDriveTable_t *)table_context->overdrive_table;
1269 struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
1270 uint32_t min_value, max_value;
1271
1272 switch (clk_type) {
1273 case SMU_GFXCLK:
1274 case SMU_SCLK:
1275 case SMU_SOCCLK:
1276 case SMU_MCLK:
1277 case SMU_UCLK:
1278 case SMU_FCLK:
1279 case SMU_VCLK:
1280 case SMU_DCLK:
1281 case SMU_DCEFCLK:
1282 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1283 if (ret)
1284 return ret;
1285
1286 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1287 if (ret)
1288 return ret;
1289
1290 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1291 for (i = 0; i < count; i++) {
1292 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1293 clk_type, i, &value);
1294 if (ret)
1295 return ret;
1296
1297 *offset += sysfs_emit_at(buf, *offset,
1298 "%d: %uMhz %s\n",
1299 i, value,
1300 cur_value == value ? "*" : "");
1301 }
1302 } else {
1303 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1304 clk_type, 0, &freq_values[0]);
1305 if (ret)
1306 return ret;
1307 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1308 clk_type,
1309 count - 1,
1310 &freq_values[2]);
1311 if (ret)
1312 return ret;
1313
1314 freq_values[1] = cur_value;
1315 mark_index = cur_value == freq_values[0] ? 0 :
1316 cur_value == freq_values[2] ? 2 : 1;
1317
1318 levels = 3;
1319 if (mark_index != 1) {
1320 levels = 2;
1321 freq_values[1] = freq_values[2];
1322 }
1323
1324 for (i = 0; i < levels; i++) {
1325 *offset += sysfs_emit_at(buf, *offset,
1326 "%d: %uMhz %s\n",
1327 i, freq_values[i],
1328 i == mark_index ? "*" : "");
1329 }
1330 }
1331 break;
1332 case SMU_PCIE:
1333 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1334 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1335 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1336 *offset += sysfs_emit_at(buf, *offset, "%d: %s %s %dMhz %s\n", i,
1337 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1338 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1339 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1340 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1341 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1342 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1343 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1344 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1345 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1346 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1347 pptable->LclkFreq[i],
1348 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1349 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1350 "*" : "");
1351 }
1352 break;
1353 case SMU_OD_SCLK:
1354 if (!smu->od_enabled || !od_table || !od_settings)
1355 return -EOPNOTSUPP;
1356 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
1357 break;
1358 *offset += sysfs_emit_at(buf, *offset, "OD_SCLK:\n0: %uMhz\n1: %uMhz\n",
1359 od_table->GfxclkFmin, od_table->GfxclkFmax);
1360 break;
1361 case SMU_OD_MCLK:
1362 if (!smu->od_enabled || !od_table || !od_settings)
1363 return -EOPNOTSUPP;
1364 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
1365 break;
1366 *offset += sysfs_emit_at(buf, *offset, "OD_MCLK:\n1: %uMHz\n", od_table->UclkFmax);
1367 break;
1368 case SMU_OD_VDDC_CURVE:
1369 if (!smu->od_enabled || !od_table || !od_settings)
1370 return -EOPNOTSUPP;
1371 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
1372 break;
1373 *offset += sysfs_emit_at(buf, *offset, "OD_VDDC_CURVE:\n");
1374 for (i = 0; i < 3; i++) {
1375 switch (i) {
1376 case 0:
1377 curve_settings = &od_table->GfxclkFreq1;
1378 break;
1379 case 1:
1380 curve_settings = &od_table->GfxclkFreq2;
1381 break;
1382 case 2:
1383 curve_settings = &od_table->GfxclkFreq3;
1384 break;
1385 default:
1386 break;
1387 }
1388 *offset += sysfs_emit_at(buf, *offset, "%d: %uMHz %umV\n",
1389 i, curve_settings[0],
1390 curve_settings[1] / NAVI10_VOLTAGE_SCALE);
1391 }
1392 break;
1393 case SMU_OD_RANGE:
1394 if (!smu->od_enabled || !od_table || !od_settings)
1395 return -EOPNOTSUPP;
1396 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_RANGE");
1397
1398 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
1399 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
1400 &min_value, NULL);
1401 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
1402 NULL, &max_value);
1403 *offset += sysfs_emit_at(buf, *offset, "SCLK: %7uMhz %10uMhz\n",
1404 min_value, max_value);
1405 }
1406
1407 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
1408 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
1409 &min_value, &max_value);
1410 *offset += sysfs_emit_at(buf, *offset, "MCLK: %7uMhz %10uMhz\n",
1411 min_value, max_value);
1412 }
1413
1414 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
1415 navi10_od_setting_get_range(od_settings,
1416 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
1417 &min_value, &max_value);
1418 *offset += sysfs_emit_at(buf, *offset,
1419 "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1420 min_value, max_value);
1421 navi10_od_setting_get_range(od_settings,
1422 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
1423 &min_value, &max_value);
1424 *offset += sysfs_emit_at(buf, *offset,
1425 "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1426 min_value, max_value);
1427 navi10_od_setting_get_range(od_settings,
1428 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
1429 &min_value, &max_value);
1430 *offset += sysfs_emit_at(buf, *offset,
1431 "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1432 min_value, max_value);
1433 navi10_od_setting_get_range(od_settings,
1434 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
1435 &min_value, &max_value);
1436 *offset += sysfs_emit_at(buf, *offset,
1437 "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1438 min_value, max_value);
1439 navi10_od_setting_get_range(od_settings,
1440 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
1441 &min_value, &max_value);
1442 *offset += sysfs_emit_at(buf, *offset,
1443 "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1444 min_value, max_value);
1445 navi10_od_setting_get_range(od_settings,
1446 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
1447 &min_value, &max_value);
1448 *offset += sysfs_emit_at(buf, *offset,
1449 "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1450 min_value, max_value);
1451 }
1452
1453 break;
1454 default:
1455 break;
1456 }
1457
1458 return 0;
1459}
1460
1461static int navi10_print_clk_levels(struct smu_context *smu,
1462 enum smu_clk_type clk_type, char *buf)
1463{
1464 uint16_t *curve_settings;
1465 int i, levels, size = 0, ret = 0;
1466 uint32_t cur_value = 0, value = 0, count = 0;
1467 uint32_t freq_values[3] = {0};
1468 uint32_t mark_index = 0;
1469 struct smu_table_context *table_context = &smu->smu_table;
1470 uint32_t gen_speed, lane_width;
1471 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1472 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1473 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
1474 OverDriveTable_t *od_table =
1475 (OverDriveTable_t *)table_context->overdrive_table;
1476 struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
1477 uint32_t min_value, max_value;
1478
1479 smu_cmn_get_sysfs_buf(&buf, &size);
1480
1481 switch (clk_type) {
1482 case SMU_GFXCLK:
1483 case SMU_SCLK:
1484 case SMU_SOCCLK:
1485 case SMU_MCLK:
1486 case SMU_UCLK:
1487 case SMU_FCLK:
1488 case SMU_VCLK:
1489 case SMU_DCLK:
1490 case SMU_DCEFCLK:
1491 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1492 if (ret)
1493 return size;
1494
1495 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1496 if (ret)
1497 return size;
1498
1499 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1500 for (i = 0; i < count; i++) {
1501 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1502 if (ret)
1503 return size;
1504
1505 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1506 cur_value == value ? "*" : "");
1507 }
1508 } else {
1509 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1510 if (ret)
1511 return size;
1512 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1513 if (ret)
1514 return size;
1515
1516 freq_values[1] = cur_value;
1517 mark_index = cur_value == freq_values[0] ? 0 :
1518 cur_value == freq_values[2] ? 2 : 1;
1519
1520 levels = 3;
1521 if (mark_index != 1) {
1522 levels = 2;
1523 freq_values[1] = freq_values[2];
1524 }
1525
1526 for (i = 0; i < levels; i++) {
1527 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1528 i == mark_index ? "*" : "");
1529 }
1530 }
1531 break;
1532 case SMU_PCIE:
1533 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1534 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1535 for (i = 0; i < NUM_LINK_LEVELS; i++)
1536 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1537 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1538 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1539 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1540 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1541 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1542 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1543 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1544 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1545 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1546 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1547 pptable->LclkFreq[i],
1548 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1549 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1550 "*" : "");
1551 break;
1552 case SMU_OD_SCLK:
1553 if (!smu->od_enabled || !od_table || !od_settings)
1554 break;
1555 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
1556 break;
1557 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1558 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1559 od_table->GfxclkFmin, od_table->GfxclkFmax);
1560 break;
1561 case SMU_OD_MCLK:
1562 if (!smu->od_enabled || !od_table || !od_settings)
1563 break;
1564 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
1565 break;
1566 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1567 size += sysfs_emit_at(buf, size, "1: %uMHz\n", od_table->UclkFmax);
1568 break;
1569 case SMU_OD_VDDC_CURVE:
1570 if (!smu->od_enabled || !od_table || !od_settings)
1571 break;
1572 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
1573 break;
1574 size += sysfs_emit_at(buf, size, "OD_VDDC_CURVE:\n");
1575 for (i = 0; i < 3; i++) {
1576 switch (i) {
1577 case 0:
1578 curve_settings = &od_table->GfxclkFreq1;
1579 break;
1580 case 1:
1581 curve_settings = &od_table->GfxclkFreq2;
1582 break;
1583 case 2:
1584 curve_settings = &od_table->GfxclkFreq3;
1585 break;
1586 default:
1587 break;
1588 }
1589 size += sysfs_emit_at(buf, size, "%d: %uMHz %umV\n",
1590 i, curve_settings[0],
1591 curve_settings[1] / NAVI10_VOLTAGE_SCALE);
1592 }
1593 break;
1594 case SMU_OD_RANGE:
1595 if (!smu->od_enabled || !od_table || !od_settings)
1596 break;
1597 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1598
1599 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
1600 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
1601 &min_value, NULL);
1602 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
1603 NULL, &max_value);
1604 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1605 min_value, max_value);
1606 }
1607
1608 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
1609 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
1610 &min_value, &max_value);
1611 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1612 min_value, max_value);
1613 }
1614
1615 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
1616 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
1617 &min_value, &max_value);
1618 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1619 min_value, max_value);
1620 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
1621 &min_value, &max_value);
1622 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1623 min_value, max_value);
1624 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
1625 &min_value, &max_value);
1626 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1627 min_value, max_value);
1628 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
1629 &min_value, &max_value);
1630 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1631 min_value, max_value);
1632 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
1633 &min_value, &max_value);
1634 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1635 min_value, max_value);
1636 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
1637 &min_value, &max_value);
1638 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1639 min_value, max_value);
1640 }
1641
1642 break;
1643 default:
1644 break;
1645 }
1646
1647 return size;
1648}
1649
1650static int navi10_force_clk_levels(struct smu_context *smu,
1651 enum smu_clk_type clk_type, uint32_t mask)
1652{
1653
1654 int ret = 0;
1655 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1656
1657 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1658 soft_max_level = mask ? (fls(mask) - 1) : 0;
1659
1660 switch (clk_type) {
1661 case SMU_GFXCLK:
1662 case SMU_SCLK:
1663 case SMU_SOCCLK:
1664 case SMU_MCLK:
1665 case SMU_UCLK:
1666 case SMU_FCLK:
1667 /* There is only 2 levels for fine grained DPM */
1668 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1669 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1670 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1671 }
1672
1673 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1674 if (ret)
1675 return 0;
1676
1677 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1678 if (ret)
1679 return 0;
1680
1681 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1682 if (ret)
1683 return 0;
1684 break;
1685 case SMU_DCEFCLK:
1686 dev_info(smu->adev->dev, "Setting DCEFCLK min/max dpm level is not supported!\n");
1687 break;
1688
1689 default:
1690 break;
1691 }
1692
1693 return 0;
1694}
1695
1696static int navi10_populate_umd_state_clk(struct smu_context *smu)
1697{
1698 struct smu_11_0_dpm_context *dpm_context =
1699 smu->smu_dpm.dpm_context;
1700 struct smu_11_0_dpm_table *gfx_table =
1701 &dpm_context->dpm_tables.gfx_table;
1702 struct smu_11_0_dpm_table *mem_table =
1703 &dpm_context->dpm_tables.uclk_table;
1704 struct smu_11_0_dpm_table *soc_table =
1705 &dpm_context->dpm_tables.soc_table;
1706 struct smu_umd_pstate_table *pstate_table =
1707 &smu->pstate_table;
1708 struct amdgpu_device *adev = smu->adev;
1709 uint32_t sclk_freq;
1710
1711 pstate_table->gfxclk_pstate.min = gfx_table->min;
1712 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1713 case IP_VERSION(11, 0, 0):
1714 switch (adev->pdev->revision) {
1715 case 0xf0: /* XTX */
1716 case 0xc0:
1717 sclk_freq = NAVI10_PEAK_SCLK_XTX;
1718 break;
1719 case 0xf1: /* XT */
1720 case 0xc1:
1721 sclk_freq = NAVI10_PEAK_SCLK_XT;
1722 break;
1723 default: /* XL */
1724 sclk_freq = NAVI10_PEAK_SCLK_XL;
1725 break;
1726 }
1727 break;
1728 case IP_VERSION(11, 0, 5):
1729 switch (adev->pdev->revision) {
1730 case 0xc7: /* XT */
1731 case 0xf4:
1732 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1733 break;
1734 case 0xc1: /* XTM */
1735 case 0xf2:
1736 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1737 break;
1738 case 0xc3: /* XLM */
1739 case 0xf3:
1740 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1741 break;
1742 case 0xc5: /* XTX */
1743 case 0xf6:
1744 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1745 break;
1746 default: /* XL */
1747 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1748 break;
1749 }
1750 break;
1751 case IP_VERSION(11, 0, 9):
1752 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
1753 break;
1754 default:
1755 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value;
1756 break;
1757 }
1758 pstate_table->gfxclk_pstate.peak = sclk_freq;
1759
1760 pstate_table->uclk_pstate.min = mem_table->min;
1761 pstate_table->uclk_pstate.peak = mem_table->max;
1762
1763 pstate_table->socclk_pstate.min = soc_table->min;
1764 pstate_table->socclk_pstate.peak = soc_table->max;
1765
1766 if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK &&
1767 mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK &&
1768 soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) {
1769 pstate_table->gfxclk_pstate.standard =
1770 NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
1771 pstate_table->uclk_pstate.standard =
1772 NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
1773 pstate_table->socclk_pstate.standard =
1774 NAVI10_UMD_PSTATE_PROFILING_SOCCLK;
1775 } else {
1776 pstate_table->gfxclk_pstate.standard =
1777 pstate_table->gfxclk_pstate.min;
1778 pstate_table->uclk_pstate.standard =
1779 pstate_table->uclk_pstate.min;
1780 pstate_table->socclk_pstate.standard =
1781 pstate_table->socclk_pstate.min;
1782 }
1783
1784 return 0;
1785}
1786
1787static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
1788 enum smu_clk_type clk_type,
1789 struct pp_clock_levels_with_latency *clocks)
1790{
1791 int ret = 0, i = 0;
1792 uint32_t level_count = 0, freq = 0;
1793
1794 switch (clk_type) {
1795 case SMU_GFXCLK:
1796 case SMU_DCEFCLK:
1797 case SMU_SOCCLK:
1798 case SMU_MCLK:
1799 case SMU_UCLK:
1800 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count);
1801 if (ret)
1802 return ret;
1803
1804 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
1805 clocks->num_levels = level_count;
1806
1807 for (i = 0; i < level_count; i++) {
1808 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq);
1809 if (ret)
1810 return ret;
1811
1812 clocks->data[i].clocks_in_khz = freq * 1000;
1813 clocks->data[i].latency_in_us = 0;
1814 }
1815 break;
1816 default:
1817 break;
1818 }
1819
1820 return ret;
1821}
1822
1823static int navi10_pre_display_config_changed(struct smu_context *smu)
1824{
1825 int ret = 0;
1826 uint32_t max_freq = 0;
1827
1828 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1829 if (ret)
1830 return ret;
1831
1832 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1833 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1834 if (ret)
1835 return ret;
1836 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1837 if (ret)
1838 return ret;
1839 }
1840
1841 return ret;
1842}
1843
1844static int navi10_display_config_changed(struct smu_context *smu)
1845{
1846 int ret = 0;
1847
1848 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1849 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1850 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1851 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1852 smu->display_config->num_display,
1853 NULL);
1854 if (ret)
1855 return ret;
1856 }
1857
1858 return ret;
1859}
1860
1861static bool navi10_is_dpm_running(struct smu_context *smu)
1862{
1863 int ret = 0;
1864 uint64_t feature_enabled;
1865
1866 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1867 if (ret)
1868 return false;
1869
1870 return !!(feature_enabled & SMC_DPM_FEATURE);
1871}
1872
1873static int navi10_get_fan_speed_rpm(struct smu_context *smu,
1874 uint32_t *speed)
1875{
1876 int ret = 0;
1877
1878 if (!speed)
1879 return -EINVAL;
1880
1881 switch (smu_v11_0_get_fan_control_mode(smu)) {
1882 case AMD_FAN_CTRL_AUTO:
1883 ret = navi10_get_smu_metrics_data(smu,
1884 METRICS_CURR_FANSPEED,
1885 speed);
1886 break;
1887 default:
1888 ret = smu_v11_0_get_fan_speed_rpm(smu,
1889 speed);
1890 break;
1891 }
1892
1893 return ret;
1894}
1895
1896static int navi10_get_fan_parameters(struct smu_context *smu)
1897{
1898 PPTable_t *pptable = smu->smu_table.driver_pptable;
1899
1900 smu->fan_max_rpm = pptable->FanMaximumRpm;
1901
1902 return 0;
1903}
1904
1905static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1906{
1907 DpmActivityMonitorCoeffInt_t activity_monitor;
1908 uint32_t i, size = 0;
1909 int16_t workload_type = 0;
1910 static const char *title[] = {
1911 "PROFILE_INDEX(NAME)",
1912 "CLOCK_TYPE(NAME)",
1913 "FPS",
1914 "MinFreqType",
1915 "MinActiveFreqType",
1916 "MinActiveFreq",
1917 "BoosterFreqType",
1918 "BoosterFreq",
1919 "PD_Data_limit_c",
1920 "PD_Data_error_coeff",
1921 "PD_Data_error_rate_coeff"};
1922 int result = 0;
1923
1924 if (!buf)
1925 return -EINVAL;
1926
1927 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1928 title[0], title[1], title[2], title[3], title[4], title[5],
1929 title[6], title[7], title[8], title[9], title[10]);
1930
1931 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1932 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1933 workload_type = smu_cmn_to_asic_specific_index(smu,
1934 CMN2ASIC_MAPPING_WORKLOAD,
1935 i);
1936 if (workload_type < 0)
1937 return -EINVAL;
1938
1939 result = smu_cmn_update_table(smu,
1940 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1941 (void *)(&activity_monitor), false);
1942 if (result) {
1943 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1944 return result;
1945 }
1946
1947 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1948 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1949
1950 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1951 " ",
1952 0,
1953 "GFXCLK",
1954 activity_monitor.Gfx_FPS,
1955 activity_monitor.Gfx_MinFreqStep,
1956 activity_monitor.Gfx_MinActiveFreqType,
1957 activity_monitor.Gfx_MinActiveFreq,
1958 activity_monitor.Gfx_BoosterFreqType,
1959 activity_monitor.Gfx_BoosterFreq,
1960 activity_monitor.Gfx_PD_Data_limit_c,
1961 activity_monitor.Gfx_PD_Data_error_coeff,
1962 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1963
1964 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1965 " ",
1966 1,
1967 "SOCCLK",
1968 activity_monitor.Soc_FPS,
1969 activity_monitor.Soc_MinFreqStep,
1970 activity_monitor.Soc_MinActiveFreqType,
1971 activity_monitor.Soc_MinActiveFreq,
1972 activity_monitor.Soc_BoosterFreqType,
1973 activity_monitor.Soc_BoosterFreq,
1974 activity_monitor.Soc_PD_Data_limit_c,
1975 activity_monitor.Soc_PD_Data_error_coeff,
1976 activity_monitor.Soc_PD_Data_error_rate_coeff);
1977
1978 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1979 " ",
1980 2,
1981 "MEMLK",
1982 activity_monitor.Mem_FPS,
1983 activity_monitor.Mem_MinFreqStep,
1984 activity_monitor.Mem_MinActiveFreqType,
1985 activity_monitor.Mem_MinActiveFreq,
1986 activity_monitor.Mem_BoosterFreqType,
1987 activity_monitor.Mem_BoosterFreq,
1988 activity_monitor.Mem_PD_Data_limit_c,
1989 activity_monitor.Mem_PD_Data_error_coeff,
1990 activity_monitor.Mem_PD_Data_error_rate_coeff);
1991 }
1992
1993 return size;
1994}
1995
1996static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1997{
1998 DpmActivityMonitorCoeffInt_t activity_monitor;
1999 int workload_type, ret = 0;
2000
2001 smu->power_profile_mode = input[size];
2002
2003 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
2004 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
2005 return -EINVAL;
2006 }
2007
2008 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
2009
2010 ret = smu_cmn_update_table(smu,
2011 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
2012 (void *)(&activity_monitor), false);
2013 if (ret) {
2014 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2015 return ret;
2016 }
2017
2018 switch (input[0]) {
2019 case 0: /* Gfxclk */
2020 activity_monitor.Gfx_FPS = input[1];
2021 activity_monitor.Gfx_MinFreqStep = input[2];
2022 activity_monitor.Gfx_MinActiveFreqType = input[3];
2023 activity_monitor.Gfx_MinActiveFreq = input[4];
2024 activity_monitor.Gfx_BoosterFreqType = input[5];
2025 activity_monitor.Gfx_BoosterFreq = input[6];
2026 activity_monitor.Gfx_PD_Data_limit_c = input[7];
2027 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
2028 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
2029 break;
2030 case 1: /* Socclk */
2031 activity_monitor.Soc_FPS = input[1];
2032 activity_monitor.Soc_MinFreqStep = input[2];
2033 activity_monitor.Soc_MinActiveFreqType = input[3];
2034 activity_monitor.Soc_MinActiveFreq = input[4];
2035 activity_monitor.Soc_BoosterFreqType = input[5];
2036 activity_monitor.Soc_BoosterFreq = input[6];
2037 activity_monitor.Soc_PD_Data_limit_c = input[7];
2038 activity_monitor.Soc_PD_Data_error_coeff = input[8];
2039 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
2040 break;
2041 case 2: /* Memlk */
2042 activity_monitor.Mem_FPS = input[1];
2043 activity_monitor.Mem_MinFreqStep = input[2];
2044 activity_monitor.Mem_MinActiveFreqType = input[3];
2045 activity_monitor.Mem_MinActiveFreq = input[4];
2046 activity_monitor.Mem_BoosterFreqType = input[5];
2047 activity_monitor.Mem_BoosterFreq = input[6];
2048 activity_monitor.Mem_PD_Data_limit_c = input[7];
2049 activity_monitor.Mem_PD_Data_error_coeff = input[8];
2050 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
2051 break;
2052 }
2053
2054 ret = smu_cmn_update_table(smu,
2055 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
2056 (void *)(&activity_monitor), true);
2057 if (ret) {
2058 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
2059 return ret;
2060 }
2061 }
2062
2063 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
2064 workload_type = smu_cmn_to_asic_specific_index(smu,
2065 CMN2ASIC_MAPPING_WORKLOAD,
2066 smu->power_profile_mode);
2067 if (workload_type < 0)
2068 return -EINVAL;
2069 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
2070 1 << workload_type, NULL);
2071
2072 return ret;
2073}
2074
2075static int navi10_notify_smc_display_config(struct smu_context *smu)
2076{
2077 struct smu_clocks min_clocks = {0};
2078 struct pp_display_clock_request clock_req;
2079 int ret = 0;
2080
2081 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
2082 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
2083 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
2084
2085 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
2086 clock_req.clock_type = amd_pp_dcef_clock;
2087 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
2088
2089 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
2090 if (!ret) {
2091 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
2092 ret = smu_cmn_send_smc_msg_with_param(smu,
2093 SMU_MSG_SetMinDeepSleepDcefclk,
2094 min_clocks.dcef_clock_in_sr/100,
2095 NULL);
2096 if (ret) {
2097 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
2098 return ret;
2099 }
2100 }
2101 } else {
2102 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
2103 }
2104 }
2105
2106 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2107 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
2108 if (ret) {
2109 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
2110 return ret;
2111 }
2112 }
2113
2114 return 0;
2115}
2116
2117static int navi10_set_watermarks_table(struct smu_context *smu,
2118 struct pp_smu_wm_range_sets *clock_ranges)
2119{
2120 Watermarks_t *table = smu->smu_table.watermarks_table;
2121 int ret = 0;
2122 int i;
2123
2124 if (clock_ranges) {
2125 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
2126 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
2127 return -EINVAL;
2128
2129 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
2130 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
2131 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
2132 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
2133 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
2134 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
2135 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
2136 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
2137 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
2138
2139 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
2140 clock_ranges->reader_wm_sets[i].wm_inst;
2141 }
2142
2143 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
2144 table->WatermarkRow[WM_SOCCLK][i].MinClock =
2145 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
2146 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
2147 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
2148 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
2149 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
2150 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
2151 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
2152
2153 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
2154 clock_ranges->writer_wm_sets[i].wm_inst;
2155 }
2156
2157 smu->watermarks_bitmap |= WATERMARKS_EXIST;
2158 }
2159
2160 /* pass data to smu controller */
2161 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2162 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
2163 ret = smu_cmn_write_watermarks_table(smu);
2164 if (ret) {
2165 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
2166 return ret;
2167 }
2168 smu->watermarks_bitmap |= WATERMARKS_LOADED;
2169 }
2170
2171 return 0;
2172}
2173
2174static int navi10_read_sensor(struct smu_context *smu,
2175 enum amd_pp_sensors sensor,
2176 void *data, uint32_t *size)
2177{
2178 int ret = 0;
2179 struct smu_table_context *table_context = &smu->smu_table;
2180 PPTable_t *pptable = table_context->driver_pptable;
2181
2182 if (!data || !size)
2183 return -EINVAL;
2184
2185 switch (sensor) {
2186 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
2187 *(uint32_t *)data = pptable->FanMaximumRpm;
2188 *size = 4;
2189 break;
2190 case AMDGPU_PP_SENSOR_MEM_LOAD:
2191 ret = navi1x_get_smu_metrics_data(smu,
2192 METRICS_AVERAGE_MEMACTIVITY,
2193 (uint32_t *)data);
2194 *size = 4;
2195 break;
2196 case AMDGPU_PP_SENSOR_GPU_LOAD:
2197 ret = navi1x_get_smu_metrics_data(smu,
2198 METRICS_AVERAGE_GFXACTIVITY,
2199 (uint32_t *)data);
2200 *size = 4;
2201 break;
2202 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
2203 ret = navi1x_get_smu_metrics_data(smu,
2204 METRICS_AVERAGE_SOCKETPOWER,
2205 (uint32_t *)data);
2206 *size = 4;
2207 break;
2208 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
2209 ret = navi1x_get_smu_metrics_data(smu,
2210 METRICS_TEMPERATURE_HOTSPOT,
2211 (uint32_t *)data);
2212 *size = 4;
2213 break;
2214 case AMDGPU_PP_SENSOR_EDGE_TEMP:
2215 ret = navi1x_get_smu_metrics_data(smu,
2216 METRICS_TEMPERATURE_EDGE,
2217 (uint32_t *)data);
2218 *size = 4;
2219 break;
2220 case AMDGPU_PP_SENSOR_MEM_TEMP:
2221 ret = navi1x_get_smu_metrics_data(smu,
2222 METRICS_TEMPERATURE_MEM,
2223 (uint32_t *)data);
2224 *size = 4;
2225 break;
2226 case AMDGPU_PP_SENSOR_GFX_MCLK:
2227 ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
2228 *(uint32_t *)data *= 100;
2229 *size = 4;
2230 break;
2231 case AMDGPU_PP_SENSOR_GFX_SCLK:
2232 ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data);
2233 *(uint32_t *)data *= 100;
2234 *size = 4;
2235 break;
2236 case AMDGPU_PP_SENSOR_VDDGFX:
2237 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
2238 *size = 4;
2239 break;
2240 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
2241 default:
2242 ret = -EOPNOTSUPP;
2243 break;
2244 }
2245
2246 return ret;
2247}
2248
2249static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
2250{
2251 uint32_t num_discrete_levels = 0;
2252 uint16_t *dpm_levels = NULL;
2253 uint16_t i = 0;
2254 struct smu_table_context *table_context = &smu->smu_table;
2255 PPTable_t *driver_ppt = NULL;
2256
2257 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
2258 return -EINVAL;
2259
2260 driver_ppt = table_context->driver_pptable;
2261 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
2262 dpm_levels = driver_ppt->FreqTableUclk;
2263
2264 if (num_discrete_levels == 0 || dpm_levels == NULL)
2265 return -EINVAL;
2266
2267 *num_states = num_discrete_levels;
2268 for (i = 0; i < num_discrete_levels; i++) {
2269 /* convert to khz */
2270 *clocks_in_khz = (*dpm_levels) * 1000;
2271 clocks_in_khz++;
2272 dpm_levels++;
2273 }
2274
2275 return 0;
2276}
2277
2278static int navi10_get_thermal_temperature_range(struct smu_context *smu,
2279 struct smu_temperature_range *range)
2280{
2281 struct smu_table_context *table_context = &smu->smu_table;
2282 struct smu_11_0_powerplay_table *powerplay_table =
2283 table_context->power_play_table;
2284 PPTable_t *pptable = smu->smu_table.driver_pptable;
2285
2286 if (!range)
2287 return -EINVAL;
2288
2289 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2290
2291 range->max = pptable->TedgeLimit *
2292 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2293 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
2294 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2295 range->hotspot_crit_max = pptable->ThotspotLimit *
2296 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2297 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
2298 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2299 range->mem_crit_max = pptable->TmemLimit *
2300 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2301 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
2302 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2303 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2304
2305 return 0;
2306}
2307
2308static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
2309 bool disable_memory_clock_switch)
2310{
2311 int ret = 0;
2312 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2313 (struct smu_11_0_max_sustainable_clocks *)
2314 smu->smu_table.max_sustainable_clocks;
2315 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2316 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2317
2318 if (smu->disable_uclk_switch == disable_memory_clock_switch)
2319 return 0;
2320
2321 if (disable_memory_clock_switch)
2322 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2323 else
2324 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2325
2326 if (!ret)
2327 smu->disable_uclk_switch = disable_memory_clock_switch;
2328
2329 return ret;
2330}
2331
2332static int navi10_get_power_limit(struct smu_context *smu,
2333 uint32_t *current_power_limit,
2334 uint32_t *default_power_limit,
2335 uint32_t *max_power_limit,
2336 uint32_t *min_power_limit)
2337{
2338 struct smu_11_0_powerplay_table *powerplay_table =
2339 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
2340 struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
2341 PPTable_t *pptable = smu->smu_table.driver_pptable;
2342 uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;
2343
2344 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
2345 /* the last hope to figure out the ppt limit */
2346 if (!pptable) {
2347 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
2348 return -EINVAL;
2349 }
2350 power_limit =
2351 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
2352 }
2353
2354 if (current_power_limit)
2355 *current_power_limit = power_limit;
2356 if (default_power_limit)
2357 *default_power_limit = power_limit;
2358
2359 if (powerplay_table) {
2360 if (smu->od_enabled &&
2361 navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {
2362 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
2363 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
2364 } else if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {
2365 od_percent_upper = 0;
2366 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
2367 }
2368 }
2369
2370 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
2371 od_percent_upper, od_percent_lower, power_limit);
2372
2373 if (max_power_limit) {
2374 *max_power_limit = power_limit * (100 + od_percent_upper);
2375 *max_power_limit /= 100;
2376 }
2377
2378 if (min_power_limit) {
2379 *min_power_limit = power_limit * (100 - od_percent_lower);
2380 *min_power_limit /= 100;
2381 }
2382
2383 return 0;
2384}
2385
2386static int navi10_update_pcie_parameters(struct smu_context *smu,
2387 uint8_t pcie_gen_cap,
2388 uint8_t pcie_width_cap)
2389{
2390 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2391 PPTable_t *pptable = smu->smu_table.driver_pptable;
2392 uint32_t smu_pcie_arg;
2393 int ret, i;
2394
2395 /* lclk dpm table setup */
2396 for (i = 0; i < MAX_PCIE_CONF; i++) {
2397 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
2398 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
2399 }
2400
2401 for (i = 0; i < NUM_LINK_LEVELS; i++) {
2402 smu_pcie_arg = (i << 16) |
2403 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
2404 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
2405 pptable->PcieLaneCount[i] : pcie_width_cap);
2406 ret = smu_cmn_send_smc_msg_with_param(smu,
2407 SMU_MSG_OverridePcieParameters,
2408 smu_pcie_arg,
2409 NULL);
2410
2411 if (ret)
2412 return ret;
2413
2414 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
2415 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
2416 if (pptable->PcieLaneCount[i] > pcie_width_cap)
2417 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
2418 }
2419
2420 return 0;
2421}
2422
2423static inline void navi10_dump_od_table(struct smu_context *smu,
2424 OverDriveTable_t *od_table)
2425{
2426 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
2427 dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
2428 dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
2429 dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
2430 dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax);
2431 dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct);
2432}
2433
2434static int navi10_od_setting_check_range(struct smu_context *smu,
2435 struct smu_11_0_overdrive_table *od_table,
2436 enum SMU_11_0_ODSETTING_ID setting,
2437 uint32_t value)
2438{
2439 if (value < od_table->min[setting]) {
2440 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
2441 return -EINVAL;
2442 }
2443 if (value > od_table->max[setting]) {
2444 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
2445 return -EINVAL;
2446 }
2447 return 0;
2448}
2449
2450static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
2451 uint16_t *voltage,
2452 uint32_t freq)
2453{
2454 uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16);
2455 uint32_t value = 0;
2456 int ret;
2457
2458 ret = smu_cmn_send_smc_msg_with_param(smu,
2459 SMU_MSG_GetVoltageByDpm,
2460 param,
2461 &value);
2462 if (ret) {
2463 dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
2464 return ret;
2465 }
2466
2467 *voltage = (uint16_t)value;
2468
2469 return 0;
2470}
2471
2472static int navi10_baco_enter(struct smu_context *smu)
2473{
2474 struct amdgpu_device *adev = smu->adev;
2475
2476 /*
2477 * This aims the case below:
2478 * amdgpu driver loaded -> runpm suspend kicked -> sound driver loaded
2479 *
2480 * For NAVI10 and later ASICs, we rely on PMFW to handle the runpm. To
2481 * make that possible, PMFW needs to acknowledge the dstate transition
2482 * process for both gfx(function 0) and audio(function 1) function of
2483 * the ASIC.
2484 *
2485 * The PCI device's initial runpm status is RUNPM_SUSPENDED. So as the
2486 * device representing the audio function of the ASIC. And that means
2487 * even if the sound driver(snd_hda_intel) was not loaded yet, it's still
2488 * possible runpm suspend kicked on the ASIC. However without the dstate
2489 * transition notification from audio function, pmfw cannot handle the
2490 * BACO in/exit correctly. And that will cause driver hang on runpm
2491 * resuming.
2492 *
2493 * To address this, we revert to legacy message way(driver masters the
2494 * timing for BACO in/exit) on sound driver missing.
2495 */
2496 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2497 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2498 else
2499 return smu_v11_0_baco_enter(smu);
2500}
2501
2502static int navi10_baco_exit(struct smu_context *smu)
2503{
2504 struct amdgpu_device *adev = smu->adev;
2505
2506 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2507 /* Wait for PMFW handling for the Dstate change */
2508 msleep(10);
2509 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2510 } else {
2511 return smu_v11_0_baco_exit(smu);
2512 }
2513}
2514
2515static int navi10_set_default_od_settings(struct smu_context *smu)
2516{
2517 OverDriveTable_t *od_table =
2518 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2519 OverDriveTable_t *boot_od_table =
2520 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2521 OverDriveTable_t *user_od_table =
2522 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2523 int ret = 0;
2524
2525 /*
2526 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as
2527 * - either they already have the default OD settings got during cold bootup
2528 * - or they have some user customized OD settings which cannot be overwritten
2529 */
2530 if (smu->adev->in_suspend)
2531 return 0;
2532
2533 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)boot_od_table, false);
2534 if (ret) {
2535 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2536 return ret;
2537 }
2538
2539 if (!boot_od_table->GfxclkVolt1) {
2540 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2541 &boot_od_table->GfxclkVolt1,
2542 boot_od_table->GfxclkFreq1);
2543 if (ret)
2544 return ret;
2545 }
2546
2547 if (!boot_od_table->GfxclkVolt2) {
2548 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2549 &boot_od_table->GfxclkVolt2,
2550 boot_od_table->GfxclkFreq2);
2551 if (ret)
2552 return ret;
2553 }
2554
2555 if (!boot_od_table->GfxclkVolt3) {
2556 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2557 &boot_od_table->GfxclkVolt3,
2558 boot_od_table->GfxclkFreq3);
2559 if (ret)
2560 return ret;
2561 }
2562
2563 navi10_dump_od_table(smu, boot_od_table);
2564
2565 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2566 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2567
2568 return 0;
2569}
2570
2571static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size)
2572{
2573 int i;
2574 int ret = 0;
2575 struct smu_table_context *table_context = &smu->smu_table;
2576 OverDriveTable_t *od_table;
2577 struct smu_11_0_overdrive_table *od_settings;
2578 enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
2579 uint16_t *freq_ptr, *voltage_ptr;
2580 od_table = (OverDriveTable_t *)table_context->overdrive_table;
2581
2582 if (!smu->od_enabled) {
2583 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2584 return -EINVAL;
2585 }
2586
2587 if (!smu->od_settings) {
2588 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2589 return -ENOENT;
2590 }
2591
2592 od_settings = smu->od_settings;
2593
2594 switch (type) {
2595 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2596 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
2597 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2598 return -ENOTSUPP;
2599 }
2600 if (!table_context->overdrive_table) {
2601 dev_err(smu->adev->dev, "Overdrive is not initialized\n");
2602 return -EINVAL;
2603 }
2604 for (i = 0; i < size; i += 2) {
2605 if (i + 2 > size) {
2606 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2607 return -EINVAL;
2608 }
2609 switch (input[i]) {
2610 case 0:
2611 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
2612 freq_ptr = &od_table->GfxclkFmin;
2613 if (input[i + 1] > od_table->GfxclkFmax) {
2614 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2615 input[i + 1],
2616 od_table->GfxclkFmin);
2617 return -EINVAL;
2618 }
2619 break;
2620 case 1:
2621 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
2622 freq_ptr = &od_table->GfxclkFmax;
2623 if (input[i + 1] < od_table->GfxclkFmin) {
2624 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2625 input[i + 1],
2626 od_table->GfxclkFmax);
2627 return -EINVAL;
2628 }
2629 break;
2630 default:
2631 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2632 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2633 return -EINVAL;
2634 }
2635 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]);
2636 if (ret)
2637 return ret;
2638 *freq_ptr = input[i + 1];
2639 }
2640 break;
2641 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2642 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
2643 dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n");
2644 return -ENOTSUPP;
2645 }
2646 if (size < 2) {
2647 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2648 return -EINVAL;
2649 }
2650 if (input[0] != 1) {
2651 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
2652 dev_info(smu->adev->dev, "Supported indices: [1:max]\n");
2653 return -EINVAL;
2654 }
2655 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
2656 if (ret)
2657 return ret;
2658 od_table->UclkFmax = input[1];
2659 break;
2660 case PP_OD_RESTORE_DEFAULT_TABLE:
2661 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2662 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2663 return -EINVAL;
2664 }
2665 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t));
2666 break;
2667 case PP_OD_COMMIT_DPM_TABLE:
2668 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2669 navi10_dump_od_table(smu, od_table);
2670 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2671 if (ret) {
2672 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2673 return ret;
2674 }
2675 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2676 smu->user_dpm_profile.user_od = true;
2677
2678 if (!memcmp(table_context->user_overdrive_table,
2679 table_context->boot_overdrive_table,
2680 sizeof(OverDriveTable_t)))
2681 smu->user_dpm_profile.user_od = false;
2682 }
2683 break;
2684 case PP_OD_EDIT_VDDC_CURVE:
2685 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
2686 dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n");
2687 return -ENOTSUPP;
2688 }
2689 if (size < 3) {
2690 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2691 return -EINVAL;
2692 }
2693 if (!od_table) {
2694 dev_info(smu->adev->dev, "Overdrive is not initialized\n");
2695 return -EINVAL;
2696 }
2697
2698 switch (input[0]) {
2699 case 0:
2700 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
2701 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
2702 freq_ptr = &od_table->GfxclkFreq1;
2703 voltage_ptr = &od_table->GfxclkVolt1;
2704 break;
2705 case 1:
2706 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
2707 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
2708 freq_ptr = &od_table->GfxclkFreq2;
2709 voltage_ptr = &od_table->GfxclkVolt2;
2710 break;
2711 case 2:
2712 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
2713 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
2714 freq_ptr = &od_table->GfxclkFreq3;
2715 voltage_ptr = &od_table->GfxclkVolt3;
2716 break;
2717 default:
2718 dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]);
2719 dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n");
2720 return -EINVAL;
2721 }
2722 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]);
2723 if (ret)
2724 return ret;
2725 // Allow setting zero to disable the OverDrive VDDC curve
2726 if (input[2] != 0) {
2727 ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]);
2728 if (ret)
2729 return ret;
2730 *freq_ptr = input[1];
2731 *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
2732 dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
2733 } else {
2734 // If setting 0, disable all voltage curve settings
2735 od_table->GfxclkVolt1 = 0;
2736 od_table->GfxclkVolt2 = 0;
2737 od_table->GfxclkVolt3 = 0;
2738 }
2739 navi10_dump_od_table(smu, od_table);
2740 break;
2741 default:
2742 return -ENOSYS;
2743 }
2744 return ret;
2745}
2746
2747static int navi10_run_btc(struct smu_context *smu)
2748{
2749 int ret = 0;
2750
2751 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL);
2752 if (ret)
2753 dev_err(smu->adev->dev, "RunBtc failed!\n");
2754
2755 return ret;
2756}
2757
2758static bool navi10_need_umc_cdr_workaround(struct smu_context *smu)
2759{
2760 struct amdgpu_device *adev = smu->adev;
2761
2762 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
2763 return false;
2764
2765 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0) ||
2766 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 5))
2767 return true;
2768
2769 return false;
2770}
2771
2772static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu)
2773{
2774 uint32_t uclk_count, uclk_min, uclk_max;
2775 int ret = 0;
2776
2777 /* This workaround can be applied only with uclk dpm enabled */
2778 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
2779 return 0;
2780
2781 ret = smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &uclk_count);
2782 if (ret)
2783 return ret;
2784
2785 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max);
2786 if (ret)
2787 return ret;
2788
2789 /*
2790 * The NAVI10_UMC_HYBRID_CDR_WORKAROUND_UCLK_THRESHOLD is 750Mhz.
2791 * This workaround is needed only when the max uclk frequency
2792 * not greater than that.
2793 */
2794 if (uclk_max > 0x2EE)
2795 return 0;
2796
2797 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min);
2798 if (ret)
2799 return ret;
2800
2801 /* Force UCLK out of the highest DPM */
2802 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min);
2803 if (ret)
2804 return ret;
2805
2806 /* Revert the UCLK Hardmax */
2807 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max);
2808 if (ret)
2809 return ret;
2810
2811 /*
2812 * In this case, SMU already disabled dummy pstate during enablement
2813 * of UCLK DPM, we have to re-enabled it.
2814 */
2815 return smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL);
2816}
2817
2818static int navi10_set_dummy_pstates_table_location(struct smu_context *smu)
2819{
2820 struct smu_table_context *smu_table = &smu->smu_table;
2821 struct smu_table *dummy_read_table =
2822 &smu_table->dummy_read_1_table;
2823 char *dummy_table = dummy_read_table->cpu_addr;
2824 int ret = 0;
2825 uint32_t i;
2826
2827 for (i = 0; i < 0x40000; i += 0x1000 * 2) {
2828 memcpy(dummy_table, &NoDbiPrbs7[0], 0x1000);
2829 dummy_table += 0x1000;
2830 memcpy(dummy_table, &DbiPrbs7[0], 0x1000);
2831 dummy_table += 0x1000;
2832 }
2833
2834 amdgpu_asic_flush_hdp(smu->adev, NULL);
2835
2836 ret = smu_cmn_send_smc_msg_with_param(smu,
2837 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH,
2838 upper_32_bits(dummy_read_table->mc_address),
2839 NULL);
2840 if (ret)
2841 return ret;
2842
2843 return smu_cmn_send_smc_msg_with_param(smu,
2844 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW,
2845 lower_32_bits(dummy_read_table->mc_address),
2846 NULL);
2847}
2848
2849static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
2850{
2851 struct amdgpu_device *adev = smu->adev;
2852 uint8_t umc_fw_greater_than_v136 = false;
2853 uint8_t umc_fw_disable_cdr = false;
2854 uint32_t param;
2855 int ret = 0;
2856
2857 if (!navi10_need_umc_cdr_workaround(smu))
2858 return 0;
2859
2860 /*
2861 * The messages below are only supported by Navi10 42.53.0 and later
2862 * PMFWs and Navi14 53.29.0 and later PMFWs.
2863 * - PPSMC_MSG_SetDriverDummyTableDramAddrHigh
2864 * - PPSMC_MSG_SetDriverDummyTableDramAddrLow
2865 * - PPSMC_MSG_GetUMCFWWA
2866 */
2867 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
2868 (smu->smc_fw_version >= 0x2a3500)) ||
2869 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 5)) &&
2870 (smu->smc_fw_version >= 0x351D00))) {
2871 ret = smu_cmn_send_smc_msg_with_param(smu,
2872 SMU_MSG_GET_UMC_FW_WA,
2873 0,
2874 ¶m);
2875 if (ret)
2876 return ret;
2877
2878 /* First bit indicates if the UMC f/w is above v137 */
2879 umc_fw_greater_than_v136 = param & 0x1;
2880
2881 /* Second bit indicates if hybrid-cdr is disabled */
2882 umc_fw_disable_cdr = param & 0x2;
2883
2884 /* w/a only allowed if UMC f/w is <= 136 */
2885 if (umc_fw_greater_than_v136)
2886 return 0;
2887
2888 if (umc_fw_disable_cdr) {
2889 if (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2890 IP_VERSION(11, 0, 0))
2891 return navi10_umc_hybrid_cdr_workaround(smu);
2892 } else {
2893 return navi10_set_dummy_pstates_table_location(smu);
2894 }
2895 } else {
2896 if (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2897 IP_VERSION(11, 0, 0))
2898 return navi10_umc_hybrid_cdr_workaround(smu);
2899 }
2900
2901 return 0;
2902}
2903
2904static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu,
2905 void **table)
2906{
2907 struct smu_table_context *smu_table = &smu->smu_table;
2908 struct gpu_metrics_v1_3 *gpu_metrics =
2909 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2910 SmuMetrics_legacy_t metrics;
2911 int ret = 0;
2912
2913 ret = smu_cmn_get_metrics_table(smu,
2914 NULL,
2915 true);
2916 if (ret)
2917 return ret;
2918
2919 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_legacy_t));
2920
2921 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2922
2923 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2924 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2925 gpu_metrics->temperature_mem = metrics.TemperatureMem;
2926 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2927 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2928 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2929
2930 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2931 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2932
2933 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2934
2935 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2936 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2937 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2938
2939 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2940 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2941 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2942 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2943 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2944
2945 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2946 gpu_metrics->indep_throttle_status =
2947 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2948 navi1x_throttler_map);
2949
2950 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2951
2952 gpu_metrics->pcie_link_width =
2953 smu_v11_0_get_current_pcie_link_width(smu);
2954 gpu_metrics->pcie_link_speed =
2955 smu_v11_0_get_current_pcie_link_speed(smu);
2956
2957 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2958
2959 if (metrics.CurrGfxVoltageOffset)
2960 gpu_metrics->voltage_gfx =
2961 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
2962 if (metrics.CurrMemVidOffset)
2963 gpu_metrics->voltage_mem =
2964 (155000 - 625 * metrics.CurrMemVidOffset) / 100;
2965 if (metrics.CurrSocVoltageOffset)
2966 gpu_metrics->voltage_soc =
2967 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
2968
2969 *table = (void *)gpu_metrics;
2970
2971 return sizeof(struct gpu_metrics_v1_3);
2972}
2973
2974static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap,
2975 struct i2c_msg *msg, int num_msgs)
2976{
2977 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
2978 struct amdgpu_device *adev = smu_i2c->adev;
2979 struct smu_context *smu = adev->powerplay.pp_handle;
2980 struct smu_table_context *smu_table = &smu->smu_table;
2981 struct smu_table *table = &smu_table->driver_table;
2982 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2983 int i, j, r, c;
2984 u16 dir;
2985
2986 if (!adev->pm.dpm_enabled)
2987 return -EBUSY;
2988
2989 req = kzalloc(sizeof(*req), GFP_KERNEL);
2990 if (!req)
2991 return -ENOMEM;
2992
2993 req->I2CcontrollerPort = smu_i2c->port;
2994 req->I2CSpeed = I2C_SPEED_FAST_400K;
2995 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2996 dir = msg[0].flags & I2C_M_RD;
2997
2998 for (c = i = 0; i < num_msgs; i++) {
2999 for (j = 0; j < msg[i].len; j++, c++) {
3000 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
3001
3002 if (!(msg[i].flags & I2C_M_RD)) {
3003 /* write */
3004 cmd->Cmd = I2C_CMD_WRITE;
3005 cmd->RegisterAddr = msg[i].buf[j];
3006 }
3007
3008 if ((dir ^ msg[i].flags) & I2C_M_RD) {
3009 /* The direction changes.
3010 */
3011 dir = msg[i].flags & I2C_M_RD;
3012 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
3013 }
3014
3015 req->NumCmds++;
3016
3017 /*
3018 * Insert STOP if we are at the last byte of either last
3019 * message for the transaction or the client explicitly
3020 * requires a STOP at this particular message.
3021 */
3022 if ((j == msg[i].len - 1) &&
3023 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3024 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
3025 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
3026 }
3027 }
3028 }
3029 mutex_lock(&adev->pm.mutex);
3030 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3031 if (r)
3032 goto fail;
3033
3034 for (c = i = 0; i < num_msgs; i++) {
3035 if (!(msg[i].flags & I2C_M_RD)) {
3036 c += msg[i].len;
3037 continue;
3038 }
3039 for (j = 0; j < msg[i].len; j++, c++) {
3040 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
3041
3042 msg[i].buf[j] = cmd->Data;
3043 }
3044 }
3045 r = num_msgs;
3046fail:
3047 mutex_unlock(&adev->pm.mutex);
3048 kfree(req);
3049 return r;
3050}
3051
3052static u32 navi10_i2c_func(struct i2c_adapter *adap)
3053{
3054 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3055}
3056
3057
3058static const struct i2c_algorithm navi10_i2c_algo = {
3059 .master_xfer = navi10_i2c_xfer,
3060 .functionality = navi10_i2c_func,
3061};
3062
3063static const struct i2c_adapter_quirks navi10_i2c_control_quirks = {
3064 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
3065 .max_read_len = MAX_SW_I2C_COMMANDS,
3066 .max_write_len = MAX_SW_I2C_COMMANDS,
3067 .max_comb_1st_msg_len = 2,
3068 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
3069};
3070
3071static int navi10_i2c_control_init(struct smu_context *smu)
3072{
3073 struct amdgpu_device *adev = smu->adev;
3074 int res, i;
3075
3076 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3077 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3078 struct i2c_adapter *control = &smu_i2c->adapter;
3079
3080 smu_i2c->adev = adev;
3081 smu_i2c->port = i;
3082 mutex_init(&smu_i2c->mutex);
3083 control->owner = THIS_MODULE;
3084 control->class = I2C_CLASS_HWMON;
3085 control->dev.parent = &adev->pdev->dev;
3086 control->algo = &navi10_i2c_algo;
3087 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
3088 control->quirks = &navi10_i2c_control_quirks;
3089 i2c_set_adapdata(control, smu_i2c);
3090
3091 res = i2c_add_adapter(control);
3092 if (res) {
3093 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3094 goto Out_err;
3095 }
3096 }
3097
3098 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
3099 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
3100
3101 return 0;
3102Out_err:
3103 for ( ; i >= 0; i--) {
3104 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3105 struct i2c_adapter *control = &smu_i2c->adapter;
3106
3107 i2c_del_adapter(control);
3108 }
3109 return res;
3110}
3111
3112static void navi10_i2c_control_fini(struct smu_context *smu)
3113{
3114 struct amdgpu_device *adev = smu->adev;
3115 int i;
3116
3117 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3118 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3119 struct i2c_adapter *control = &smu_i2c->adapter;
3120
3121 i2c_del_adapter(control);
3122 }
3123 adev->pm.ras_eeprom_i2c_bus = NULL;
3124 adev->pm.fru_eeprom_i2c_bus = NULL;
3125}
3126
3127static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
3128 void **table)
3129{
3130 struct smu_table_context *smu_table = &smu->smu_table;
3131 struct gpu_metrics_v1_3 *gpu_metrics =
3132 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3133 SmuMetrics_t metrics;
3134 int ret = 0;
3135
3136 ret = smu_cmn_get_metrics_table(smu,
3137 NULL,
3138 true);
3139 if (ret)
3140 return ret;
3141
3142 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_t));
3143
3144 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3145
3146 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
3147 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
3148 gpu_metrics->temperature_mem = metrics.TemperatureMem;
3149 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
3150 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
3151 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
3152
3153 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
3154 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
3155
3156 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
3157
3158 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
3159 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
3160 else
3161 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
3162
3163 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
3164 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
3165
3166 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
3167 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
3168 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
3169 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
3170 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
3171
3172 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
3173 gpu_metrics->indep_throttle_status =
3174 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
3175 navi1x_throttler_map);
3176
3177 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
3178
3179 gpu_metrics->pcie_link_width = metrics.PcieWidth;
3180 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
3181
3182 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3183
3184 if (metrics.CurrGfxVoltageOffset)
3185 gpu_metrics->voltage_gfx =
3186 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
3187 if (metrics.CurrMemVidOffset)
3188 gpu_metrics->voltage_mem =
3189 (155000 - 625 * metrics.CurrMemVidOffset) / 100;
3190 if (metrics.CurrSocVoltageOffset)
3191 gpu_metrics->voltage_soc =
3192 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
3193
3194 *table = (void *)gpu_metrics;
3195
3196 return sizeof(struct gpu_metrics_v1_3);
3197}
3198
3199static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu,
3200 void **table)
3201{
3202 struct smu_table_context *smu_table = &smu->smu_table;
3203 struct gpu_metrics_v1_3 *gpu_metrics =
3204 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3205 SmuMetrics_NV12_legacy_t metrics;
3206 int ret = 0;
3207
3208 ret = smu_cmn_get_metrics_table(smu,
3209 NULL,
3210 true);
3211 if (ret)
3212 return ret;
3213
3214 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_legacy_t));
3215
3216 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3217
3218 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
3219 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
3220 gpu_metrics->temperature_mem = metrics.TemperatureMem;
3221 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
3222 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
3223 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
3224
3225 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
3226 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
3227
3228 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
3229
3230 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
3231 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
3232 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
3233
3234 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
3235 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
3236 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
3237 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
3238
3239 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
3240 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
3241 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
3242 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
3243 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
3244
3245 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
3246 gpu_metrics->indep_throttle_status =
3247 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
3248 navi1x_throttler_map);
3249
3250 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
3251
3252 gpu_metrics->pcie_link_width =
3253 smu_v11_0_get_current_pcie_link_width(smu);
3254 gpu_metrics->pcie_link_speed =
3255 smu_v11_0_get_current_pcie_link_speed(smu);
3256
3257 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3258
3259 if (metrics.CurrGfxVoltageOffset)
3260 gpu_metrics->voltage_gfx =
3261 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
3262 if (metrics.CurrMemVidOffset)
3263 gpu_metrics->voltage_mem =
3264 (155000 - 625 * metrics.CurrMemVidOffset) / 100;
3265 if (metrics.CurrSocVoltageOffset)
3266 gpu_metrics->voltage_soc =
3267 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
3268
3269 *table = (void *)gpu_metrics;
3270
3271 return sizeof(struct gpu_metrics_v1_3);
3272}
3273
3274static ssize_t navi12_get_gpu_metrics(struct smu_context *smu,
3275 void **table)
3276{
3277 struct smu_table_context *smu_table = &smu->smu_table;
3278 struct gpu_metrics_v1_3 *gpu_metrics =
3279 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3280 SmuMetrics_NV12_t metrics;
3281 int ret = 0;
3282
3283 ret = smu_cmn_get_metrics_table(smu,
3284 NULL,
3285 true);
3286 if (ret)
3287 return ret;
3288
3289 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t));
3290
3291 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3292
3293 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
3294 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
3295 gpu_metrics->temperature_mem = metrics.TemperatureMem;
3296 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
3297 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
3298 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
3299
3300 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
3301 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
3302
3303 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
3304
3305 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
3306 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
3307 else
3308 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
3309
3310 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
3311 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
3312
3313 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
3314 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
3315 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
3316 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
3317
3318 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
3319 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
3320 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
3321 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
3322 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
3323
3324 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
3325 gpu_metrics->indep_throttle_status =
3326 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
3327 navi1x_throttler_map);
3328
3329 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
3330
3331 gpu_metrics->pcie_link_width = metrics.PcieWidth;
3332 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
3333
3334 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3335
3336 if (metrics.CurrGfxVoltageOffset)
3337 gpu_metrics->voltage_gfx =
3338 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
3339 if (metrics.CurrMemVidOffset)
3340 gpu_metrics->voltage_mem =
3341 (155000 - 625 * metrics.CurrMemVidOffset) / 100;
3342 if (metrics.CurrSocVoltageOffset)
3343 gpu_metrics->voltage_soc =
3344 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
3345
3346 *table = (void *)gpu_metrics;
3347
3348 return sizeof(struct gpu_metrics_v1_3);
3349}
3350
3351static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
3352 void **table)
3353{
3354 struct amdgpu_device *adev = smu->adev;
3355 int ret = 0;
3356
3357 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
3358 case IP_VERSION(11, 0, 9):
3359 if (smu->smc_fw_version > 0x00341C00)
3360 ret = navi12_get_gpu_metrics(smu, table);
3361 else
3362 ret = navi12_get_legacy_gpu_metrics(smu, table);
3363 break;
3364 case IP_VERSION(11, 0, 0):
3365 case IP_VERSION(11, 0, 5):
3366 default:
3367 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
3368 IP_VERSION(11, 0, 5)) &&
3369 smu->smc_fw_version > 0x00351F00) ||
3370 ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
3371 IP_VERSION(11, 0, 0)) &&
3372 smu->smc_fw_version > 0x002A3B00))
3373 ret = navi10_get_gpu_metrics(smu, table);
3374 else
3375 ret = navi10_get_legacy_gpu_metrics(smu, table);
3376 break;
3377 }
3378
3379 return ret;
3380}
3381
3382static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
3383{
3384 struct smu_table_context *table_context = &smu->smu_table;
3385 PPTable_t *smc_pptable = table_context->driver_pptable;
3386 struct amdgpu_device *adev = smu->adev;
3387 uint32_t param = 0;
3388
3389 /* Navi12 does not support this */
3390 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 9))
3391 return 0;
3392
3393 /*
3394 * Skip the MGpuFanBoost setting for those ASICs
3395 * which do not support it
3396 */
3397 if (!smc_pptable->MGpuFanBoostLimitRpm)
3398 return 0;
3399
3400 /* Workaround for WS SKU */
3401 if (adev->pdev->device == 0x7312 &&
3402 adev->pdev->revision == 0)
3403 param = 0xD188;
3404
3405 return smu_cmn_send_smc_msg_with_param(smu,
3406 SMU_MSG_SetMGpuFanBoostLimitRpm,
3407 param,
3408 NULL);
3409}
3410
3411static int navi10_post_smu_init(struct smu_context *smu)
3412{
3413 struct amdgpu_device *adev = smu->adev;
3414 int ret = 0;
3415
3416 if (amdgpu_sriov_vf(adev))
3417 return 0;
3418
3419 ret = navi10_run_umc_cdr_workaround(smu);
3420 if (ret)
3421 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n");
3422
3423 return ret;
3424}
3425
3426static int navi10_get_default_config_table_settings(struct smu_context *smu,
3427 struct config_table_setting *table)
3428{
3429 if (!table)
3430 return -EINVAL;
3431
3432 table->gfxclk_average_tau = 10;
3433 table->socclk_average_tau = 10;
3434 table->uclk_average_tau = 10;
3435 table->gfx_activity_average_tau = 10;
3436 table->mem_activity_average_tau = 10;
3437 table->socket_power_average_tau = 10;
3438
3439 return 0;
3440}
3441
3442static int navi10_set_config_table(struct smu_context *smu,
3443 struct config_table_setting *table)
3444{
3445 DriverSmuConfig_t driver_smu_config_table;
3446
3447 if (!table)
3448 return -EINVAL;
3449
3450 memset(&driver_smu_config_table,
3451 0,
3452 sizeof(driver_smu_config_table));
3453
3454 driver_smu_config_table.GfxclkAverageLpfTau =
3455 table->gfxclk_average_tau;
3456 driver_smu_config_table.SocclkAverageLpfTau =
3457 table->socclk_average_tau;
3458 driver_smu_config_table.UclkAverageLpfTau =
3459 table->uclk_average_tau;
3460 driver_smu_config_table.GfxActivityLpfTau =
3461 table->gfx_activity_average_tau;
3462 driver_smu_config_table.UclkActivityLpfTau =
3463 table->mem_activity_average_tau;
3464 driver_smu_config_table.SocketPowerLpfTau =
3465 table->socket_power_average_tau;
3466
3467 return smu_cmn_update_table(smu,
3468 SMU_TABLE_DRIVER_SMU_CONFIG,
3469 0,
3470 (void *)&driver_smu_config_table,
3471 true);
3472}
3473
3474static const struct pptable_funcs navi10_ppt_funcs = {
3475 .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
3476 .set_default_dpm_table = navi10_set_default_dpm_table,
3477 .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,
3478 .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
3479 .i2c_init = navi10_i2c_control_init,
3480 .i2c_fini = navi10_i2c_control_fini,
3481 .print_clk_levels = navi10_print_clk_levels,
3482 .emit_clk_levels = navi10_emit_clk_levels,
3483 .force_clk_levels = navi10_force_clk_levels,
3484 .populate_umd_state_clk = navi10_populate_umd_state_clk,
3485 .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
3486 .pre_display_config_changed = navi10_pre_display_config_changed,
3487 .display_config_changed = navi10_display_config_changed,
3488 .notify_smc_display_config = navi10_notify_smc_display_config,
3489 .is_dpm_running = navi10_is_dpm_running,
3490 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
3491 .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
3492 .get_power_profile_mode = navi10_get_power_profile_mode,
3493 .set_power_profile_mode = navi10_set_power_profile_mode,
3494 .set_watermarks_table = navi10_set_watermarks_table,
3495 .read_sensor = navi10_read_sensor,
3496 .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
3497 .set_performance_level = smu_v11_0_set_performance_level,
3498 .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
3499 .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
3500 .get_power_limit = navi10_get_power_limit,
3501 .update_pcie_parameters = navi10_update_pcie_parameters,
3502 .init_microcode = smu_v11_0_init_microcode,
3503 .load_microcode = smu_v11_0_load_microcode,
3504 .fini_microcode = smu_v11_0_fini_microcode,
3505 .init_smc_tables = navi10_init_smc_tables,
3506 .fini_smc_tables = smu_v11_0_fini_smc_tables,
3507 .init_power = smu_v11_0_init_power,
3508 .fini_power = smu_v11_0_fini_power,
3509 .check_fw_status = smu_v11_0_check_fw_status,
3510 .setup_pptable = navi10_setup_pptable,
3511 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
3512 .check_fw_version = smu_v11_0_check_fw_version,
3513 .write_pptable = smu_cmn_write_pptable,
3514 .set_driver_table_location = smu_v11_0_set_driver_table_location,
3515 .set_tool_table_location = smu_v11_0_set_tool_table_location,
3516 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
3517 .system_features_control = smu_v11_0_system_features_control,
3518 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3519 .send_smc_msg = smu_cmn_send_smc_msg,
3520 .init_display_count = smu_v11_0_init_display_count,
3521 .set_allowed_mask = smu_v11_0_set_allowed_mask,
3522 .get_enabled_mask = smu_cmn_get_enabled_mask,
3523 .feature_is_enabled = smu_cmn_feature_is_enabled,
3524 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
3525 .notify_display_change = smu_v11_0_notify_display_change,
3526 .set_power_limit = smu_v11_0_set_power_limit,
3527 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3528 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
3529 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
3530 .set_min_dcef_deep_sleep = smu_v11_0_set_min_deep_sleep_dcefclk,
3531 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3532 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3533 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
3534 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
3535 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
3536 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3537 .gfx_off_control = smu_v11_0_gfx_off_control,
3538 .register_irq_handler = smu_v11_0_register_irq_handler,
3539 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3540 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
3541 .baco_is_support = smu_v11_0_baco_is_support,
3542 .baco_enter = navi10_baco_enter,
3543 .baco_exit = navi10_baco_exit,
3544 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
3545 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
3546 .set_default_od_settings = navi10_set_default_od_settings,
3547 .od_edit_dpm_table = navi10_od_edit_dpm_table,
3548 .restore_user_od_settings = smu_v11_0_restore_user_od_settings,
3549 .run_btc = navi10_run_btc,
3550 .set_power_source = smu_v11_0_set_power_source,
3551 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3552 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
3553 .get_gpu_metrics = navi1x_get_gpu_metrics,
3554 .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
3555 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
3556 .deep_sleep_control = smu_v11_0_deep_sleep_control,
3557 .get_fan_parameters = navi10_get_fan_parameters,
3558 .post_init = navi10_post_smu_init,
3559 .interrupt_work = smu_v11_0_interrupt_work,
3560 .set_mp1_state = smu_cmn_set_mp1_state,
3561 .get_default_config_table_settings = navi10_get_default_config_table_settings,
3562 .set_config_table = navi10_set_config_table,
3563};
3564
3565void navi10_set_ppt_funcs(struct smu_context *smu)
3566{
3567 smu->ppt_funcs = &navi10_ppt_funcs;
3568 smu->message_map = navi10_message_map;
3569 smu->clock_map = navi10_clk_map;
3570 smu->feature_map = navi10_feature_mask_map;
3571 smu->table_map = navi10_table_map;
3572 smu->pwr_src_map = navi10_pwr_src_map;
3573 smu->workload_map = navi10_workload_map;
3574 smu_v11_0_set_smu_mailbox_registers(smu);
3575}