1// SPDX-License-Identifier: GPL-2.0 OR MIT
  2/*
  3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
  4 *
  5 * Permission is hereby granted, free of charge, to any person obtaining a
  6 * copy of this software and associated documentation files (the "Software"),
  7 * to deal in the Software without restriction, including without limitation
  8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9 * and/or sell copies of the Software, and to permit persons to whom the
 10 * Software is furnished to do so, subject to the following conditions:
 11 *
 12 * The above copyright notice and this permission notice shall be included in
 13 * all copies or substantial portions of the Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 21 * OTHER DEALINGS IN THE SOFTWARE.
 22 *
 23 */
 24
 25#include "kfd_device_queue_manager.h"
 26#include "cik_regs.h"
 27#include "oss/oss_2_4_sh_mask.h"
 28#include "gca/gfx_7_2_sh_mask.h"
 29
 30static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm,
 31				   struct qcm_process_device *qpd,
 32				   enum cache_policy default_policy,
 33				   enum cache_policy alternate_policy,
 34				   void __user *alternate_aperture_base,
 35				   uint64_t alternate_aperture_size);
 36static int update_qpd_cik(struct device_queue_manager *dqm,
 37			  struct qcm_process_device *qpd);
 38static void init_sdma_vm(struct device_queue_manager *dqm,
 39			 struct queue *q,
 40			 struct qcm_process_device *qpd);
 41
 42void device_queue_manager_init_cik(
 43	struct device_queue_manager_asic_ops *asic_ops)
 44{
 45	asic_ops->set_cache_memory_policy = set_cache_memory_policy_cik;
 46	asic_ops->update_qpd = update_qpd_cik;
 47	asic_ops->init_sdma_vm = init_sdma_vm;
 48	asic_ops->mqd_manager_init = mqd_manager_init_cik;
 49}
 50
 51static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble)
 52{
 53	/* In 64-bit mode, we can only control the top 3 bits of the LDS,
 54	 * scratch and GPUVM apertures.
 55	 * The hardware fills in the remaining 59 bits according to the
 56	 * following pattern:
 57	 * LDS:		X0000000'00000000 - X0000001'00000000 (4GB)
 58	 * Scratch:	X0000001'00000000 - X0000002'00000000 (4GB)
 59	 * GPUVM:	Y0010000'00000000 - Y0020000'00000000 (1TB)
 60	 *
 61	 * (where X/Y is the configurable nybble with the low-bit 0)
 62	 *
 63	 * LDS and scratch will have the same top nybble programmed in the
 64	 * top 3 bits of SH_MEM_BASES.PRIVATE_BASE.
 65	 * GPUVM can have a different top nybble programmed in the
 66	 * top 3 bits of SH_MEM_BASES.SHARED_BASE.
 67	 * We don't bother to support different top nybbles
 68	 * for LDS/Scratch and GPUVM.
 69	 */
 70
 71	WARN_ON((top_address_nybble & 1) || top_address_nybble > 0xE ||
 72		top_address_nybble == 0);
 73
 74	return PRIVATE_BASE(top_address_nybble << 12) |
 75			SHARED_BASE(top_address_nybble << 12);
 76}
 77
 78static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm,
 79				   struct qcm_process_device *qpd,
 80				   enum cache_policy default_policy,
 81				   enum cache_policy alternate_policy,
 82				   void __user *alternate_aperture_base,
 83				   uint64_t alternate_aperture_size)
 84{
 85	uint32_t default_mtype;
 86	uint32_t ape1_mtype;
 87
 88	default_mtype = (default_policy == cache_policy_coherent) ?
 89			MTYPE_NONCACHED :
 90			MTYPE_CACHED;
 91
 92	ape1_mtype = (alternate_policy == cache_policy_coherent) ?
 93			MTYPE_NONCACHED :
 94			MTYPE_CACHED;
 95
 96	qpd->sh_mem_config = (qpd->sh_mem_config & PTR32)
 97			| ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED)
 98			| DEFAULT_MTYPE(default_mtype)
 99			| APE1_MTYPE(ape1_mtype);
100
101	return true;
102}
103
104static int update_qpd_cik(struct device_queue_manager *dqm,
105			  struct qcm_process_device *qpd)
106{
107	struct kfd_process_device *pdd;
108	unsigned int temp;
109
110	pdd = qpd_to_pdd(qpd);
111
112	/* check if sh_mem_config register already configured */
113	if (qpd->sh_mem_config == 0) {
114		qpd->sh_mem_config =
115			ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) |
116			DEFAULT_MTYPE(MTYPE_NONCACHED) |
117			APE1_MTYPE(MTYPE_NONCACHED);
118		qpd->sh_mem_ape1_limit = 0;
119		qpd->sh_mem_ape1_base = 0;
120	}
121
122	/* On dGPU we're always in GPUVM64 addressing mode with 64-bit
123	 * aperture addresses.
124	 */
125	temp = get_sh_mem_bases_nybble_64(pdd);
126	qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp);
127
128	pr_debug("is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n",
129		qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases);
130
131	return 0;
132}
133
134static void init_sdma_vm(struct device_queue_manager *dqm,
135			 struct queue *q,
136			 struct qcm_process_device *qpd)
137{
138	/* On dGPU we're always in GPUVM64 addressing mode with 64-bit
139	 * aperture addresses.
140	 */
141	q->properties.sdma_vm_addr =
142		((get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd))) <<
143		 SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT) &
144		SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK;
145}