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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Cell Broadband Engine Performance Monitor
4 *
5 * (C) Copyright IBM Corporation 2001,2006
6 *
7 * Author:
8 * David Erb (djerb@us.ibm.com)
9 * Kevin Corry (kevcorry@us.ibm.com)
10 */
11
12#include <linux/interrupt.h>
13#include <linux/irqdomain.h>
14#include <linux/types.h>
15#include <linux/export.h>
16#include <asm/io.h>
17#include <asm/irq_regs.h>
18#include <asm/machdep.h>
19#include <asm/pmc.h>
20#include <asm/reg.h>
21#include <asm/spu.h>
22#include <asm/cell-regs.h>
23
24#include "interrupt.h"
25
26/*
27 * When writing to write-only mmio addresses, save a shadow copy. All of the
28 * registers are 32-bit, but stored in the upper-half of a 64-bit field in
29 * pmd_regs.
30 */
31
32#define WRITE_WO_MMIO(reg, x) \
33 do { \
34 u32 _x = (x); \
35 struct cbe_pmd_regs __iomem *pmd_regs; \
36 struct cbe_pmd_shadow_regs *shadow_regs; \
37 pmd_regs = cbe_get_cpu_pmd_regs(cpu); \
38 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \
39 out_be64(&(pmd_regs->reg), (((u64)_x) << 32)); \
40 shadow_regs->reg = _x; \
41 } while (0)
42
43#define READ_SHADOW_REG(val, reg) \
44 do { \
45 struct cbe_pmd_shadow_regs *shadow_regs; \
46 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \
47 (val) = shadow_regs->reg; \
48 } while (0)
49
50#define READ_MMIO_UPPER32(val, reg) \
51 do { \
52 struct cbe_pmd_regs __iomem *pmd_regs; \
53 pmd_regs = cbe_get_cpu_pmd_regs(cpu); \
54 (val) = (u32)(in_be64(&pmd_regs->reg) >> 32); \
55 } while (0)
56
57/*
58 * Physical counter registers.
59 * Each physical counter can act as one 32-bit counter or two 16-bit counters.
60 */
61
62u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr)
63{
64 u32 val_in_latch, val = 0;
65
66 if (phys_ctr < NR_PHYS_CTRS) {
67 READ_SHADOW_REG(val_in_latch, counter_value_in_latch);
68
69 /* Read the latch or the actual counter, whichever is newer. */
70 if (val_in_latch & (1 << phys_ctr)) {
71 READ_SHADOW_REG(val, pm_ctr[phys_ctr]);
72 } else {
73 READ_MMIO_UPPER32(val, pm_ctr[phys_ctr]);
74 }
75 }
76
77 return val;
78}
79EXPORT_SYMBOL_GPL(cbe_read_phys_ctr);
80
81void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val)
82{
83 struct cbe_pmd_shadow_regs *shadow_regs;
84 u32 pm_ctrl;
85
86 if (phys_ctr < NR_PHYS_CTRS) {
87 /* Writing to a counter only writes to a hardware latch.
88 * The new value is not propagated to the actual counter
89 * until the performance monitor is enabled.
90 */
91 WRITE_WO_MMIO(pm_ctr[phys_ctr], val);
92
93 pm_ctrl = cbe_read_pm(cpu, pm_control);
94 if (pm_ctrl & CBE_PM_ENABLE_PERF_MON) {
95 /* The counters are already active, so we need to
96 * rewrite the pm_control register to "re-enable"
97 * the PMU.
98 */
99 cbe_write_pm(cpu, pm_control, pm_ctrl);
100 } else {
101 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
102 shadow_regs->counter_value_in_latch |= (1 << phys_ctr);
103 }
104 }
105}
106EXPORT_SYMBOL_GPL(cbe_write_phys_ctr);
107
108/*
109 * "Logical" counter registers.
110 * These will read/write 16-bits or 32-bits depending on the
111 * current size of the counter. Counters 4 - 7 are always 16-bit.
112 */
113
114u32 cbe_read_ctr(u32 cpu, u32 ctr)
115{
116 u32 val;
117 u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1);
118
119 val = cbe_read_phys_ctr(cpu, phys_ctr);
120
121 if (cbe_get_ctr_size(cpu, phys_ctr) == 16)
122 val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff);
123
124 return val;
125}
126EXPORT_SYMBOL_GPL(cbe_read_ctr);
127
128void cbe_write_ctr(u32 cpu, u32 ctr, u32 val)
129{
130 u32 phys_ctr;
131 u32 phys_val;
132
133 phys_ctr = ctr & (NR_PHYS_CTRS - 1);
134
135 if (cbe_get_ctr_size(cpu, phys_ctr) == 16) {
136 phys_val = cbe_read_phys_ctr(cpu, phys_ctr);
137
138 if (ctr < NR_PHYS_CTRS)
139 val = (val << 16) | (phys_val & 0xffff);
140 else
141 val = (val & 0xffff) | (phys_val & 0xffff0000);
142 }
143
144 cbe_write_phys_ctr(cpu, phys_ctr, val);
145}
146EXPORT_SYMBOL_GPL(cbe_write_ctr);
147
148/*
149 * Counter-control registers.
150 * Each "logical" counter has a corresponding control register.
151 */
152
153u32 cbe_read_pm07_control(u32 cpu, u32 ctr)
154{
155 u32 pm07_control = 0;
156
157 if (ctr < NR_CTRS)
158 READ_SHADOW_REG(pm07_control, pm07_control[ctr]);
159
160 return pm07_control;
161}
162EXPORT_SYMBOL_GPL(cbe_read_pm07_control);
163
164void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val)
165{
166 if (ctr < NR_CTRS)
167 WRITE_WO_MMIO(pm07_control[ctr], val);
168}
169EXPORT_SYMBOL_GPL(cbe_write_pm07_control);
170
171/*
172 * Other PMU control registers. Most of these are write-only.
173 */
174
175u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg)
176{
177 u32 val = 0;
178
179 switch (reg) {
180 case group_control:
181 READ_SHADOW_REG(val, group_control);
182 break;
183
184 case debug_bus_control:
185 READ_SHADOW_REG(val, debug_bus_control);
186 break;
187
188 case trace_address:
189 READ_MMIO_UPPER32(val, trace_address);
190 break;
191
192 case ext_tr_timer:
193 READ_SHADOW_REG(val, ext_tr_timer);
194 break;
195
196 case pm_status:
197 READ_MMIO_UPPER32(val, pm_status);
198 break;
199
200 case pm_control:
201 READ_SHADOW_REG(val, pm_control);
202 break;
203
204 case pm_interval:
205 READ_MMIO_UPPER32(val, pm_interval);
206 break;
207
208 case pm_start_stop:
209 READ_SHADOW_REG(val, pm_start_stop);
210 break;
211 }
212
213 return val;
214}
215EXPORT_SYMBOL_GPL(cbe_read_pm);
216
217void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val)
218{
219 switch (reg) {
220 case group_control:
221 WRITE_WO_MMIO(group_control, val);
222 break;
223
224 case debug_bus_control:
225 WRITE_WO_MMIO(debug_bus_control, val);
226 break;
227
228 case trace_address:
229 WRITE_WO_MMIO(trace_address, val);
230 break;
231
232 case ext_tr_timer:
233 WRITE_WO_MMIO(ext_tr_timer, val);
234 break;
235
236 case pm_status:
237 WRITE_WO_MMIO(pm_status, val);
238 break;
239
240 case pm_control:
241 WRITE_WO_MMIO(pm_control, val);
242 break;
243
244 case pm_interval:
245 WRITE_WO_MMIO(pm_interval, val);
246 break;
247
248 case pm_start_stop:
249 WRITE_WO_MMIO(pm_start_stop, val);
250 break;
251 }
252}
253EXPORT_SYMBOL_GPL(cbe_write_pm);
254
255/*
256 * Get/set the size of a physical counter to either 16 or 32 bits.
257 */
258
259u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr)
260{
261 u32 pm_ctrl, size = 0;
262
263 if (phys_ctr < NR_PHYS_CTRS) {
264 pm_ctrl = cbe_read_pm(cpu, pm_control);
265 size = (pm_ctrl & CBE_PM_16BIT_CTR(phys_ctr)) ? 16 : 32;
266 }
267
268 return size;
269}
270EXPORT_SYMBOL_GPL(cbe_get_ctr_size);
271
272void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size)
273{
274 u32 pm_ctrl;
275
276 if (phys_ctr < NR_PHYS_CTRS) {
277 pm_ctrl = cbe_read_pm(cpu, pm_control);
278 switch (ctr_size) {
279 case 16:
280 pm_ctrl |= CBE_PM_16BIT_CTR(phys_ctr);
281 break;
282
283 case 32:
284 pm_ctrl &= ~CBE_PM_16BIT_CTR(phys_ctr);
285 break;
286 }
287 cbe_write_pm(cpu, pm_control, pm_ctrl);
288 }
289}
290EXPORT_SYMBOL_GPL(cbe_set_ctr_size);
291
292/*
293 * Enable/disable the entire performance monitoring unit.
294 * When we enable the PMU, all pending writes to counters get committed.
295 */
296
297void cbe_enable_pm(u32 cpu)
298{
299 struct cbe_pmd_shadow_regs *shadow_regs;
300 u32 pm_ctrl;
301
302 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
303 shadow_regs->counter_value_in_latch = 0;
304
305 pm_ctrl = cbe_read_pm(cpu, pm_control) | CBE_PM_ENABLE_PERF_MON;
306 cbe_write_pm(cpu, pm_control, pm_ctrl);
307}
308EXPORT_SYMBOL_GPL(cbe_enable_pm);
309
310void cbe_disable_pm(u32 cpu)
311{
312 u32 pm_ctrl;
313 pm_ctrl = cbe_read_pm(cpu, pm_control) & ~CBE_PM_ENABLE_PERF_MON;
314 cbe_write_pm(cpu, pm_control, pm_ctrl);
315}
316EXPORT_SYMBOL_GPL(cbe_disable_pm);
317
318/*
319 * Reading from the trace_buffer.
320 * The trace buffer is two 64-bit registers. Reading from
321 * the second half automatically increments the trace_address.
322 */
323
324void cbe_read_trace_buffer(u32 cpu, u64 *buf)
325{
326 struct cbe_pmd_regs __iomem *pmd_regs = cbe_get_cpu_pmd_regs(cpu);
327
328 *buf++ = in_be64(&pmd_regs->trace_buffer_0_63);
329 *buf++ = in_be64(&pmd_regs->trace_buffer_64_127);
330}
331EXPORT_SYMBOL_GPL(cbe_read_trace_buffer);
332
333/*
334 * Enabling/disabling interrupts for the entire performance monitoring unit.
335 */
336
337u32 cbe_get_and_clear_pm_interrupts(u32 cpu)
338{
339 /* Reading pm_status clears the interrupt bits. */
340 return cbe_read_pm(cpu, pm_status);
341}
342EXPORT_SYMBOL_GPL(cbe_get_and_clear_pm_interrupts);
343
344void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask)
345{
346 /* Set which node and thread will handle the next interrupt. */
347 iic_set_interrupt_routing(cpu, thread, 0);
348
349 /* Enable the interrupt bits in the pm_status register. */
350 if (mask)
351 cbe_write_pm(cpu, pm_status, mask);
352}
353EXPORT_SYMBOL_GPL(cbe_enable_pm_interrupts);
354
355void cbe_disable_pm_interrupts(u32 cpu)
356{
357 cbe_get_and_clear_pm_interrupts(cpu);
358 cbe_write_pm(cpu, pm_status, 0);
359}
360EXPORT_SYMBOL_GPL(cbe_disable_pm_interrupts);
361
362static irqreturn_t cbe_pm_irq(int irq, void *dev_id)
363{
364 perf_irq(get_irq_regs());
365 return IRQ_HANDLED;
366}
367
368static int __init cbe_init_pm_irq(void)
369{
370 unsigned int irq;
371 int rc, node;
372
373 for_each_online_node(node) {
374 irq = irq_create_mapping(NULL, IIC_IRQ_IOEX_PMI |
375 (node << IIC_IRQ_NODE_SHIFT));
376 if (!irq) {
377 printk("ERROR: Unable to allocate irq for node %d\n",
378 node);
379 return -EINVAL;
380 }
381
382 rc = request_irq(irq, cbe_pm_irq,
383 0, "cbe-pmu-0", NULL);
384 if (rc) {
385 printk("ERROR: Request for irq on node %d failed\n",
386 node);
387 return rc;
388 }
389 }
390
391 return 0;
392}
393machine_arch_initcall(cell, cbe_init_pm_irq);
394
395void cbe_sync_irq(int node)
396{
397 unsigned int irq;
398
399 irq = irq_find_mapping(NULL,
400 IIC_IRQ_IOEX_PMI
401 | (node << IIC_IRQ_NODE_SHIFT));
402
403 if (!irq) {
404 printk(KERN_WARNING "ERROR, unable to get existing irq %d " \
405 "for node %d\n", irq, node);
406 return;
407 }
408
409 synchronize_irq(irq);
410}
411EXPORT_SYMBOL_GPL(cbe_sync_irq);
412
1/*
2 * Cell Broadband Engine Performance Monitor
3 *
4 * (C) Copyright IBM Corporation 2001,2006
5 *
6 * Author:
7 * David Erb (djerb@us.ibm.com)
8 * Kevin Corry (kevcorry@us.ibm.com)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#include <linux/interrupt.h>
26#include <linux/types.h>
27#include <linux/export.h>
28#include <asm/io.h>
29#include <asm/irq_regs.h>
30#include <asm/machdep.h>
31#include <asm/pmc.h>
32#include <asm/reg.h>
33#include <asm/spu.h>
34#include <asm/cell-regs.h>
35
36#include "interrupt.h"
37
38/*
39 * When writing to write-only mmio addresses, save a shadow copy. All of the
40 * registers are 32-bit, but stored in the upper-half of a 64-bit field in
41 * pmd_regs.
42 */
43
44#define WRITE_WO_MMIO(reg, x) \
45 do { \
46 u32 _x = (x); \
47 struct cbe_pmd_regs __iomem *pmd_regs; \
48 struct cbe_pmd_shadow_regs *shadow_regs; \
49 pmd_regs = cbe_get_cpu_pmd_regs(cpu); \
50 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \
51 out_be64(&(pmd_regs->reg), (((u64)_x) << 32)); \
52 shadow_regs->reg = _x; \
53 } while (0)
54
55#define READ_SHADOW_REG(val, reg) \
56 do { \
57 struct cbe_pmd_shadow_regs *shadow_regs; \
58 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \
59 (val) = shadow_regs->reg; \
60 } while (0)
61
62#define READ_MMIO_UPPER32(val, reg) \
63 do { \
64 struct cbe_pmd_regs __iomem *pmd_regs; \
65 pmd_regs = cbe_get_cpu_pmd_regs(cpu); \
66 (val) = (u32)(in_be64(&pmd_regs->reg) >> 32); \
67 } while (0)
68
69/*
70 * Physical counter registers.
71 * Each physical counter can act as one 32-bit counter or two 16-bit counters.
72 */
73
74u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr)
75{
76 u32 val_in_latch, val = 0;
77
78 if (phys_ctr < NR_PHYS_CTRS) {
79 READ_SHADOW_REG(val_in_latch, counter_value_in_latch);
80
81 /* Read the latch or the actual counter, whichever is newer. */
82 if (val_in_latch & (1 << phys_ctr)) {
83 READ_SHADOW_REG(val, pm_ctr[phys_ctr]);
84 } else {
85 READ_MMIO_UPPER32(val, pm_ctr[phys_ctr]);
86 }
87 }
88
89 return val;
90}
91EXPORT_SYMBOL_GPL(cbe_read_phys_ctr);
92
93void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val)
94{
95 struct cbe_pmd_shadow_regs *shadow_regs;
96 u32 pm_ctrl;
97
98 if (phys_ctr < NR_PHYS_CTRS) {
99 /* Writing to a counter only writes to a hardware latch.
100 * The new value is not propagated to the actual counter
101 * until the performance monitor is enabled.
102 */
103 WRITE_WO_MMIO(pm_ctr[phys_ctr], val);
104
105 pm_ctrl = cbe_read_pm(cpu, pm_control);
106 if (pm_ctrl & CBE_PM_ENABLE_PERF_MON) {
107 /* The counters are already active, so we need to
108 * rewrite the pm_control register to "re-enable"
109 * the PMU.
110 */
111 cbe_write_pm(cpu, pm_control, pm_ctrl);
112 } else {
113 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
114 shadow_regs->counter_value_in_latch |= (1 << phys_ctr);
115 }
116 }
117}
118EXPORT_SYMBOL_GPL(cbe_write_phys_ctr);
119
120/*
121 * "Logical" counter registers.
122 * These will read/write 16-bits or 32-bits depending on the
123 * current size of the counter. Counters 4 - 7 are always 16-bit.
124 */
125
126u32 cbe_read_ctr(u32 cpu, u32 ctr)
127{
128 u32 val;
129 u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1);
130
131 val = cbe_read_phys_ctr(cpu, phys_ctr);
132
133 if (cbe_get_ctr_size(cpu, phys_ctr) == 16)
134 val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff);
135
136 return val;
137}
138EXPORT_SYMBOL_GPL(cbe_read_ctr);
139
140void cbe_write_ctr(u32 cpu, u32 ctr, u32 val)
141{
142 u32 phys_ctr;
143 u32 phys_val;
144
145 phys_ctr = ctr & (NR_PHYS_CTRS - 1);
146
147 if (cbe_get_ctr_size(cpu, phys_ctr) == 16) {
148 phys_val = cbe_read_phys_ctr(cpu, phys_ctr);
149
150 if (ctr < NR_PHYS_CTRS)
151 val = (val << 16) | (phys_val & 0xffff);
152 else
153 val = (val & 0xffff) | (phys_val & 0xffff0000);
154 }
155
156 cbe_write_phys_ctr(cpu, phys_ctr, val);
157}
158EXPORT_SYMBOL_GPL(cbe_write_ctr);
159
160/*
161 * Counter-control registers.
162 * Each "logical" counter has a corresponding control register.
163 */
164
165u32 cbe_read_pm07_control(u32 cpu, u32 ctr)
166{
167 u32 pm07_control = 0;
168
169 if (ctr < NR_CTRS)
170 READ_SHADOW_REG(pm07_control, pm07_control[ctr]);
171
172 return pm07_control;
173}
174EXPORT_SYMBOL_GPL(cbe_read_pm07_control);
175
176void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val)
177{
178 if (ctr < NR_CTRS)
179 WRITE_WO_MMIO(pm07_control[ctr], val);
180}
181EXPORT_SYMBOL_GPL(cbe_write_pm07_control);
182
183/*
184 * Other PMU control registers. Most of these are write-only.
185 */
186
187u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg)
188{
189 u32 val = 0;
190
191 switch (reg) {
192 case group_control:
193 READ_SHADOW_REG(val, group_control);
194 break;
195
196 case debug_bus_control:
197 READ_SHADOW_REG(val, debug_bus_control);
198 break;
199
200 case trace_address:
201 READ_MMIO_UPPER32(val, trace_address);
202 break;
203
204 case ext_tr_timer:
205 READ_SHADOW_REG(val, ext_tr_timer);
206 break;
207
208 case pm_status:
209 READ_MMIO_UPPER32(val, pm_status);
210 break;
211
212 case pm_control:
213 READ_SHADOW_REG(val, pm_control);
214 break;
215
216 case pm_interval:
217 READ_MMIO_UPPER32(val, pm_interval);
218 break;
219
220 case pm_start_stop:
221 READ_SHADOW_REG(val, pm_start_stop);
222 break;
223 }
224
225 return val;
226}
227EXPORT_SYMBOL_GPL(cbe_read_pm);
228
229void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val)
230{
231 switch (reg) {
232 case group_control:
233 WRITE_WO_MMIO(group_control, val);
234 break;
235
236 case debug_bus_control:
237 WRITE_WO_MMIO(debug_bus_control, val);
238 break;
239
240 case trace_address:
241 WRITE_WO_MMIO(trace_address, val);
242 break;
243
244 case ext_tr_timer:
245 WRITE_WO_MMIO(ext_tr_timer, val);
246 break;
247
248 case pm_status:
249 WRITE_WO_MMIO(pm_status, val);
250 break;
251
252 case pm_control:
253 WRITE_WO_MMIO(pm_control, val);
254 break;
255
256 case pm_interval:
257 WRITE_WO_MMIO(pm_interval, val);
258 break;
259
260 case pm_start_stop:
261 WRITE_WO_MMIO(pm_start_stop, val);
262 break;
263 }
264}
265EXPORT_SYMBOL_GPL(cbe_write_pm);
266
267/*
268 * Get/set the size of a physical counter to either 16 or 32 bits.
269 */
270
271u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr)
272{
273 u32 pm_ctrl, size = 0;
274
275 if (phys_ctr < NR_PHYS_CTRS) {
276 pm_ctrl = cbe_read_pm(cpu, pm_control);
277 size = (pm_ctrl & CBE_PM_16BIT_CTR(phys_ctr)) ? 16 : 32;
278 }
279
280 return size;
281}
282EXPORT_SYMBOL_GPL(cbe_get_ctr_size);
283
284void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size)
285{
286 u32 pm_ctrl;
287
288 if (phys_ctr < NR_PHYS_CTRS) {
289 pm_ctrl = cbe_read_pm(cpu, pm_control);
290 switch (ctr_size) {
291 case 16:
292 pm_ctrl |= CBE_PM_16BIT_CTR(phys_ctr);
293 break;
294
295 case 32:
296 pm_ctrl &= ~CBE_PM_16BIT_CTR(phys_ctr);
297 break;
298 }
299 cbe_write_pm(cpu, pm_control, pm_ctrl);
300 }
301}
302EXPORT_SYMBOL_GPL(cbe_set_ctr_size);
303
304/*
305 * Enable/disable the entire performance monitoring unit.
306 * When we enable the PMU, all pending writes to counters get committed.
307 */
308
309void cbe_enable_pm(u32 cpu)
310{
311 struct cbe_pmd_shadow_regs *shadow_regs;
312 u32 pm_ctrl;
313
314 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
315 shadow_regs->counter_value_in_latch = 0;
316
317 pm_ctrl = cbe_read_pm(cpu, pm_control) | CBE_PM_ENABLE_PERF_MON;
318 cbe_write_pm(cpu, pm_control, pm_ctrl);
319}
320EXPORT_SYMBOL_GPL(cbe_enable_pm);
321
322void cbe_disable_pm(u32 cpu)
323{
324 u32 pm_ctrl;
325 pm_ctrl = cbe_read_pm(cpu, pm_control) & ~CBE_PM_ENABLE_PERF_MON;
326 cbe_write_pm(cpu, pm_control, pm_ctrl);
327}
328EXPORT_SYMBOL_GPL(cbe_disable_pm);
329
330/*
331 * Reading from the trace_buffer.
332 * The trace buffer is two 64-bit registers. Reading from
333 * the second half automatically increments the trace_address.
334 */
335
336void cbe_read_trace_buffer(u32 cpu, u64 *buf)
337{
338 struct cbe_pmd_regs __iomem *pmd_regs = cbe_get_cpu_pmd_regs(cpu);
339
340 *buf++ = in_be64(&pmd_regs->trace_buffer_0_63);
341 *buf++ = in_be64(&pmd_regs->trace_buffer_64_127);
342}
343EXPORT_SYMBOL_GPL(cbe_read_trace_buffer);
344
345/*
346 * Enabling/disabling interrupts for the entire performance monitoring unit.
347 */
348
349u32 cbe_get_and_clear_pm_interrupts(u32 cpu)
350{
351 /* Reading pm_status clears the interrupt bits. */
352 return cbe_read_pm(cpu, pm_status);
353}
354EXPORT_SYMBOL_GPL(cbe_get_and_clear_pm_interrupts);
355
356void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask)
357{
358 /* Set which node and thread will handle the next interrupt. */
359 iic_set_interrupt_routing(cpu, thread, 0);
360
361 /* Enable the interrupt bits in the pm_status register. */
362 if (mask)
363 cbe_write_pm(cpu, pm_status, mask);
364}
365EXPORT_SYMBOL_GPL(cbe_enable_pm_interrupts);
366
367void cbe_disable_pm_interrupts(u32 cpu)
368{
369 cbe_get_and_clear_pm_interrupts(cpu);
370 cbe_write_pm(cpu, pm_status, 0);
371}
372EXPORT_SYMBOL_GPL(cbe_disable_pm_interrupts);
373
374static irqreturn_t cbe_pm_irq(int irq, void *dev_id)
375{
376 perf_irq(get_irq_regs());
377 return IRQ_HANDLED;
378}
379
380static int __init cbe_init_pm_irq(void)
381{
382 unsigned int irq;
383 int rc, node;
384
385 for_each_online_node(node) {
386 irq = irq_create_mapping(NULL, IIC_IRQ_IOEX_PMI |
387 (node << IIC_IRQ_NODE_SHIFT));
388 if (irq == NO_IRQ) {
389 printk("ERROR: Unable to allocate irq for node %d\n",
390 node);
391 return -EINVAL;
392 }
393
394 rc = request_irq(irq, cbe_pm_irq,
395 0, "cbe-pmu-0", NULL);
396 if (rc) {
397 printk("ERROR: Request for irq on node %d failed\n",
398 node);
399 return rc;
400 }
401 }
402
403 return 0;
404}
405machine_arch_initcall(cell, cbe_init_pm_irq);
406
407void cbe_sync_irq(int node)
408{
409 unsigned int irq;
410
411 irq = irq_find_mapping(NULL,
412 IIC_IRQ_IOEX_PMI
413 | (node << IIC_IRQ_NODE_SHIFT));
414
415 if (irq == NO_IRQ) {
416 printk(KERN_WARNING "ERROR, unable to get existing irq %d " \
417 "for node %d\n", irq, node);
418 return;
419 }
420
421 synchronize_irq(irq);
422}
423EXPORT_SYMBOL_GPL(cbe_sync_irq);
424