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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2013 - 2019 Intel Corporation. */
3
4#include <linux/bitfield.h>
5#include "fm10k_pf.h"
6#include "fm10k_vf.h"
7
8/**
9 * fm10k_reset_hw_pf - PF hardware reset
10 * @hw: pointer to hardware structure
11 *
12 * This function should return the hardware to a state similar to the
13 * one it is in after being powered on.
14 **/
15static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw)
16{
17 s32 err;
18 u32 reg;
19 u16 i;
20
21 /* Disable interrupts */
22 fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL));
23
24 /* Lock ITR2 reg 0 into itself and disable interrupt moderation */
25 fm10k_write_reg(hw, FM10K_ITR2(0), 0);
26 fm10k_write_reg(hw, FM10K_INT_CTRL, 0);
27
28 /* We assume here Tx and Rx queue 0 are owned by the PF */
29
30 /* Shut off VF access to their queues forcing them to queue 0 */
31 for (i = 0; i < FM10K_TQMAP_TABLE_SIZE; i++) {
32 fm10k_write_reg(hw, FM10K_TQMAP(i), 0);
33 fm10k_write_reg(hw, FM10K_RQMAP(i), 0);
34 }
35
36 /* shut down all rings */
37 err = fm10k_disable_queues_generic(hw, FM10K_MAX_QUEUES);
38 if (err == FM10K_ERR_REQUESTS_PENDING) {
39 hw->mac.reset_while_pending++;
40 goto force_reset;
41 } else if (err) {
42 return err;
43 }
44
45 /* Verify that DMA is no longer active */
46 reg = fm10k_read_reg(hw, FM10K_DMA_CTRL);
47 if (reg & (FM10K_DMA_CTRL_TX_ACTIVE | FM10K_DMA_CTRL_RX_ACTIVE))
48 return FM10K_ERR_DMA_PENDING;
49
50force_reset:
51 /* Inititate data path reset */
52 reg = FM10K_DMA_CTRL_DATAPATH_RESET;
53 fm10k_write_reg(hw, FM10K_DMA_CTRL, reg);
54
55 /* Flush write and allow 100us for reset to complete */
56 fm10k_write_flush(hw);
57 udelay(FM10K_RESET_TIMEOUT);
58
59 /* Verify we made it out of reset */
60 reg = fm10k_read_reg(hw, FM10K_IP);
61 if (!(reg & FM10K_IP_NOTINRESET))
62 return FM10K_ERR_RESET_FAILED;
63
64 return 0;
65}
66
67/**
68 * fm10k_is_ari_hierarchy_pf - Indicate ARI hierarchy support
69 * @hw: pointer to hardware structure
70 *
71 * Looks at the ARI hierarchy bit to determine whether ARI is supported or not.
72 **/
73static bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw *hw)
74{
75 u16 sriov_ctrl = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_SRIOV_CTRL);
76
77 return !!(sriov_ctrl & FM10K_PCIE_SRIOV_CTRL_VFARI);
78}
79
80/**
81 * fm10k_init_hw_pf - PF hardware initialization
82 * @hw: pointer to hardware structure
83 *
84 **/
85static s32 fm10k_init_hw_pf(struct fm10k_hw *hw)
86{
87 u32 dma_ctrl, txqctl;
88 u16 i;
89
90 /* Establish default VSI as valid */
91 fm10k_write_reg(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0);
92 fm10k_write_reg(hw, FM10K_DGLORTMAP(fm10k_dglort_default),
93 FM10K_DGLORTMAP_ANY);
94
95 /* Invalidate all other GLORT entries */
96 for (i = 1; i < FM10K_DGLORT_COUNT; i++)
97 fm10k_write_reg(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE);
98
99 /* reset ITR2(0) to point to itself */
100 fm10k_write_reg(hw, FM10K_ITR2(0), 0);
101
102 /* reset VF ITR2(0) to point to 0 avoid PF registers */
103 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0);
104
105 /* loop through all PF ITR2 registers pointing them to the previous */
106 for (i = 1; i < FM10K_ITR_REG_COUNT_PF; i++)
107 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1);
108
109 /* Enable interrupt moderator if not already enabled */
110 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
111
112 /* compute the default txqctl configuration */
113 txqctl = FM10K_TXQCTL_PF | FM10K_TXQCTL_UNLIMITED_BW |
114 (hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT);
115
116 for (i = 0; i < FM10K_MAX_QUEUES; i++) {
117 /* configure rings for 256 Queue / 32 Descriptor cache mode */
118 fm10k_write_reg(hw, FM10K_TQDLOC(i),
119 (i * FM10K_TQDLOC_BASE_32_DESC) |
120 FM10K_TQDLOC_SIZE_32_DESC);
121 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl);
122
123 /* configure rings to provide TPH processing hints */
124 fm10k_write_reg(hw, FM10K_TPH_TXCTRL(i),
125 FM10K_TPH_TXCTRL_DESC_TPHEN |
126 FM10K_TPH_TXCTRL_DESC_RROEN |
127 FM10K_TPH_TXCTRL_DESC_WROEN |
128 FM10K_TPH_TXCTRL_DATA_RROEN);
129 fm10k_write_reg(hw, FM10K_TPH_RXCTRL(i),
130 FM10K_TPH_RXCTRL_DESC_TPHEN |
131 FM10K_TPH_RXCTRL_DESC_RROEN |
132 FM10K_TPH_RXCTRL_DATA_WROEN |
133 FM10K_TPH_RXCTRL_HDR_WROEN);
134 }
135
136 /* set max hold interval to align with 1.024 usec in all modes and
137 * store ITR scale
138 */
139 switch (hw->bus.speed) {
140 case fm10k_bus_speed_2500:
141 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1;
142 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN1;
143 break;
144 case fm10k_bus_speed_5000:
145 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2;
146 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN2;
147 break;
148 case fm10k_bus_speed_8000:
149 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3;
150 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3;
151 break;
152 default:
153 dma_ctrl = 0;
154 /* just in case, assume Gen3 ITR scale */
155 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3;
156 break;
157 }
158
159 /* Configure TSO flags */
160 fm10k_write_reg(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW);
161 fm10k_write_reg(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI);
162
163 /* Enable DMA engine
164 * Set Rx Descriptor size to 32
165 * Set Minimum MSS to 64
166 * Set Maximum number of Rx queues to 256 / 32 Descriptor
167 */
168 dma_ctrl |= FM10K_DMA_CTRL_TX_ENABLE | FM10K_DMA_CTRL_RX_ENABLE |
169 FM10K_DMA_CTRL_RX_DESC_SIZE | FM10K_DMA_CTRL_MINMSS_64 |
170 FM10K_DMA_CTRL_32_DESC;
171
172 fm10k_write_reg(hw, FM10K_DMA_CTRL, dma_ctrl);
173
174 /* record maximum queue count, we limit ourselves to 128 */
175 hw->mac.max_queues = FM10K_MAX_QUEUES_PF;
176
177 /* We support either 64 VFs or 7 VFs depending on if we have ARI */
178 hw->iov.total_vfs = fm10k_is_ari_hierarchy_pf(hw) ? 64 : 7;
179
180 return 0;
181}
182
183/**
184 * fm10k_update_vlan_pf - Update status of VLAN ID in VLAN filter table
185 * @hw: pointer to hardware structure
186 * @vid: VLAN ID to add to table
187 * @vsi: Index indicating VF ID or PF ID in table
188 * @set: Indicates if this is a set or clear operation
189 *
190 * This function adds or removes the corresponding VLAN ID from the VLAN
191 * filter table for the corresponding function. In addition to the
192 * standard set/clear that supports one bit a multi-bit write is
193 * supported to set 64 bits at a time.
194 **/
195static s32 fm10k_update_vlan_pf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set)
196{
197 u32 vlan_table, reg, mask, bit, len;
198
199 /* verify the VSI index is valid */
200 if (vsi > FM10K_VLAN_TABLE_VSI_MAX)
201 return FM10K_ERR_PARAM;
202
203 /* VLAN multi-bit write:
204 * The multi-bit write has several parts to it.
205 * 24 16 8 0
206 * 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
207 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
208 * | RSVD0 | Length |C|RSVD0| VLAN ID |
209 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
210 *
211 * VLAN ID: Vlan Starting value
212 * RSVD0: Reserved section, must be 0
213 * C: Flag field, 0 is set, 1 is clear (Used in VF VLAN message)
214 * Length: Number of times to repeat the bit being set
215 */
216 len = vid >> 16;
217 vid = (vid << 17) >> 17;
218
219 /* verify the reserved 0 fields are 0 */
220 if (len >= FM10K_VLAN_TABLE_VID_MAX || vid >= FM10K_VLAN_TABLE_VID_MAX)
221 return FM10K_ERR_PARAM;
222
223 /* Loop through the table updating all required VLANs */
224 for (reg = FM10K_VLAN_TABLE(vsi, vid / 32), bit = vid % 32;
225 len < FM10K_VLAN_TABLE_VID_MAX;
226 len -= 32 - bit, reg++, bit = 0) {
227 /* record the initial state of the register */
228 vlan_table = fm10k_read_reg(hw, reg);
229
230 /* truncate mask if we are at the start or end of the run */
231 mask = (~(u32)0 >> ((len < 31) ? 31 - len : 0)) << bit;
232
233 /* make necessary modifications to the register */
234 mask &= set ? ~vlan_table : vlan_table;
235 if (mask)
236 fm10k_write_reg(hw, reg, vlan_table ^ mask);
237 }
238
239 return 0;
240}
241
242/**
243 * fm10k_read_mac_addr_pf - Read device MAC address
244 * @hw: pointer to the HW structure
245 *
246 * Reads the device MAC address from the SM_AREA and stores the value.
247 **/
248static s32 fm10k_read_mac_addr_pf(struct fm10k_hw *hw)
249{
250 u8 perm_addr[ETH_ALEN];
251 u32 serial_num;
252
253 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(1));
254
255 /* last byte should be all 1's */
256 if ((~serial_num) << 24)
257 return FM10K_ERR_INVALID_MAC_ADDR;
258
259 perm_addr[0] = (u8)(serial_num >> 24);
260 perm_addr[1] = (u8)(serial_num >> 16);
261 perm_addr[2] = (u8)(serial_num >> 8);
262
263 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(0));
264
265 /* first byte should be all 1's */
266 if ((~serial_num) >> 24)
267 return FM10K_ERR_INVALID_MAC_ADDR;
268
269 perm_addr[3] = (u8)(serial_num >> 16);
270 perm_addr[4] = (u8)(serial_num >> 8);
271 perm_addr[5] = (u8)(serial_num);
272
273 ether_addr_copy(hw->mac.perm_addr, perm_addr);
274 ether_addr_copy(hw->mac.addr, perm_addr);
275
276 return 0;
277}
278
279/**
280 * fm10k_glort_valid_pf - Validate that the provided glort is valid
281 * @hw: pointer to the HW structure
282 * @glort: base glort to be validated
283 *
284 * This function will return an error if the provided glort is invalid
285 **/
286bool fm10k_glort_valid_pf(struct fm10k_hw *hw, u16 glort)
287{
288 glort &= hw->mac.dglort_map >> FM10K_DGLORTMAP_MASK_SHIFT;
289
290 return glort == (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE);
291}
292
293/**
294 * fm10k_update_xc_addr_pf - Update device addresses
295 * @hw: pointer to the HW structure
296 * @glort: base resource tag for this request
297 * @mac: MAC address to add/remove from table
298 * @vid: VLAN ID to add/remove from table
299 * @add: Indicates if this is an add or remove operation
300 * @flags: flags field to indicate add and secure
301 *
302 * This function generates a message to the Switch API requesting
303 * that the given logical port add/remove the given L2 MAC/VLAN address.
304 **/
305static s32 fm10k_update_xc_addr_pf(struct fm10k_hw *hw, u16 glort,
306 const u8 *mac, u16 vid, bool add, u8 flags)
307{
308 struct fm10k_mbx_info *mbx = &hw->mbx;
309 struct fm10k_mac_update mac_update;
310 u32 msg[5];
311
312 /* clear set bit from VLAN ID */
313 vid &= ~FM10K_VLAN_CLEAR;
314
315 /* if glort or VLAN are not valid return error */
316 if (!fm10k_glort_valid_pf(hw, glort) || vid >= FM10K_VLAN_TABLE_VID_MAX)
317 return FM10K_ERR_PARAM;
318
319 /* record fields */
320 mac_update.mac_lower = cpu_to_le32(((u32)mac[2] << 24) |
321 ((u32)mac[3] << 16) |
322 ((u32)mac[4] << 8) |
323 ((u32)mac[5]));
324 mac_update.mac_upper = cpu_to_le16(((u16)mac[0] << 8) |
325 ((u16)mac[1]));
326 mac_update.vlan = cpu_to_le16(vid);
327 mac_update.glort = cpu_to_le16(glort);
328 mac_update.action = add ? 0 : 1;
329 mac_update.flags = flags;
330
331 /* populate mac_update fields */
332 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE);
333 fm10k_tlv_attr_put_le_struct(msg, FM10K_PF_ATTR_ID_MAC_UPDATE,
334 &mac_update, sizeof(mac_update));
335
336 /* load onto outgoing mailbox */
337 return mbx->ops.enqueue_tx(hw, mbx, msg);
338}
339
340/**
341 * fm10k_update_uc_addr_pf - Update device unicast addresses
342 * @hw: pointer to the HW structure
343 * @glort: base resource tag for this request
344 * @mac: MAC address to add/remove from table
345 * @vid: VLAN ID to add/remove from table
346 * @add: Indicates if this is an add or remove operation
347 * @flags: flags field to indicate add and secure
348 *
349 * This function is used to add or remove unicast addresses for
350 * the PF.
351 **/
352static s32 fm10k_update_uc_addr_pf(struct fm10k_hw *hw, u16 glort,
353 const u8 *mac, u16 vid, bool add, u8 flags)
354{
355 /* verify MAC address is valid */
356 if (!is_valid_ether_addr(mac))
357 return FM10K_ERR_PARAM;
358
359 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, flags);
360}
361
362/**
363 * fm10k_update_mc_addr_pf - Update device multicast addresses
364 * @hw: pointer to the HW structure
365 * @glort: base resource tag for this request
366 * @mac: MAC address to add/remove from table
367 * @vid: VLAN ID to add/remove from table
368 * @add: Indicates if this is an add or remove operation
369 *
370 * This function is used to add or remove multicast MAC addresses for
371 * the PF.
372 **/
373static s32 fm10k_update_mc_addr_pf(struct fm10k_hw *hw, u16 glort,
374 const u8 *mac, u16 vid, bool add)
375{
376 /* verify multicast address is valid */
377 if (!is_multicast_ether_addr(mac))
378 return FM10K_ERR_PARAM;
379
380 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, 0);
381}
382
383/**
384 * fm10k_update_xcast_mode_pf - Request update of multicast mode
385 * @hw: pointer to hardware structure
386 * @glort: base resource tag for this request
387 * @mode: integer value indicating mode being requested
388 *
389 * This function will attempt to request a higher mode for the port
390 * so that it can enable either multicast, multicast promiscuous, or
391 * promiscuous mode of operation.
392 **/
393static s32 fm10k_update_xcast_mode_pf(struct fm10k_hw *hw, u16 glort, u8 mode)
394{
395 struct fm10k_mbx_info *mbx = &hw->mbx;
396 u32 msg[3], xcast_mode;
397
398 if (mode > FM10K_XCAST_MODE_NONE)
399 return FM10K_ERR_PARAM;
400
401 /* if glort is not valid return error */
402 if (!fm10k_glort_valid_pf(hw, glort))
403 return FM10K_ERR_PARAM;
404
405 /* write xcast mode as a single u32 value,
406 * lower 16 bits: glort
407 * upper 16 bits: mode
408 */
409 xcast_mode = ((u32)mode << 16) | glort;
410
411 /* generate message requesting to change xcast mode */
412 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_XCAST_MODES);
413 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_XCAST_MODE, xcast_mode);
414
415 /* load onto outgoing mailbox */
416 return mbx->ops.enqueue_tx(hw, mbx, msg);
417}
418
419/**
420 * fm10k_update_int_moderator_pf - Update interrupt moderator linked list
421 * @hw: pointer to hardware structure
422 *
423 * This function walks through the MSI-X vector table to determine the
424 * number of active interrupts and based on that information updates the
425 * interrupt moderator linked list.
426 **/
427static void fm10k_update_int_moderator_pf(struct fm10k_hw *hw)
428{
429 u32 i;
430
431 /* Disable interrupt moderator */
432 fm10k_write_reg(hw, FM10K_INT_CTRL, 0);
433
434 /* loop through PF from last to first looking enabled vectors */
435 for (i = FM10K_ITR_REG_COUNT_PF - 1; i; i--) {
436 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i)))
437 break;
438 }
439
440 /* always reset VFITR2[0] to point to last enabled PF vector */
441 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i);
442
443 /* reset ITR2[0] to point to last enabled PF vector */
444 if (!hw->iov.num_vfs)
445 fm10k_write_reg(hw, FM10K_ITR2(0), i);
446
447 /* Enable interrupt moderator */
448 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
449}
450
451/**
452 * fm10k_update_lport_state_pf - Notify the switch of a change in port state
453 * @hw: pointer to the HW structure
454 * @glort: base resource tag for this request
455 * @count: number of logical ports being updated
456 * @enable: boolean value indicating enable or disable
457 *
458 * This function is used to add/remove a logical port from the switch.
459 **/
460static s32 fm10k_update_lport_state_pf(struct fm10k_hw *hw, u16 glort,
461 u16 count, bool enable)
462{
463 struct fm10k_mbx_info *mbx = &hw->mbx;
464 u32 msg[3], lport_msg;
465
466 /* do nothing if we are being asked to create or destroy 0 ports */
467 if (!count)
468 return 0;
469
470 /* if glort is not valid return error */
471 if (!fm10k_glort_valid_pf(hw, glort))
472 return FM10K_ERR_PARAM;
473
474 /* reset multicast mode if deleting lport */
475 if (!enable)
476 fm10k_update_xcast_mode_pf(hw, glort, FM10K_XCAST_MODE_NONE);
477
478 /* construct the lport message from the 2 pieces of data we have */
479 lport_msg = ((u32)count << 16) | glort;
480
481 /* generate lport create/delete message */
482 fm10k_tlv_msg_init(msg, enable ? FM10K_PF_MSG_ID_LPORT_CREATE :
483 FM10K_PF_MSG_ID_LPORT_DELETE);
484 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_PORT, lport_msg);
485
486 /* load onto outgoing mailbox */
487 return mbx->ops.enqueue_tx(hw, mbx, msg);
488}
489
490/**
491 * fm10k_configure_dglort_map_pf - Configures GLORT entry and queues
492 * @hw: pointer to hardware structure
493 * @dglort: pointer to dglort configuration structure
494 *
495 * Reads the configuration structure contained in dglort_cfg and uses
496 * that information to then populate a DGLORTMAP/DEC entry and the queues
497 * to which it has been assigned.
498 **/
499static s32 fm10k_configure_dglort_map_pf(struct fm10k_hw *hw,
500 struct fm10k_dglort_cfg *dglort)
501{
502 u16 glort, queue_count, vsi_count, pc_count;
503 u16 vsi, queue, pc, q_idx;
504 u32 txqctl, dglortdec, dglortmap;
505
506 /* verify the dglort pointer */
507 if (!dglort)
508 return FM10K_ERR_PARAM;
509
510 /* verify the dglort values */
511 if ((dglort->idx > 7) || (dglort->rss_l > 7) || (dglort->pc_l > 3) ||
512 (dglort->vsi_l > 6) || (dglort->vsi_b > 64) ||
513 (dglort->queue_l > 8) || (dglort->queue_b >= 256))
514 return FM10K_ERR_PARAM;
515
516 /* determine count of VSIs and queues */
517 queue_count = BIT(dglort->rss_l + dglort->pc_l);
518 vsi_count = BIT(dglort->vsi_l + dglort->queue_l);
519 glort = dglort->glort;
520 q_idx = dglort->queue_b;
521
522 /* configure SGLORT for queues */
523 for (vsi = 0; vsi < vsi_count; vsi++, glort++) {
524 for (queue = 0; queue < queue_count; queue++, q_idx++) {
525 if (q_idx >= FM10K_MAX_QUEUES)
526 break;
527
528 fm10k_write_reg(hw, FM10K_TX_SGLORT(q_idx), glort);
529 fm10k_write_reg(hw, FM10K_RX_SGLORT(q_idx), glort);
530 }
531 }
532
533 /* determine count of PCs and queues */
534 queue_count = BIT(dglort->queue_l + dglort->rss_l + dglort->vsi_l);
535 pc_count = BIT(dglort->pc_l);
536
537 /* configure PC for Tx queues */
538 for (pc = 0; pc < pc_count; pc++) {
539 q_idx = pc + dglort->queue_b;
540 for (queue = 0; queue < queue_count; queue++) {
541 if (q_idx >= FM10K_MAX_QUEUES)
542 break;
543
544 txqctl = fm10k_read_reg(hw, FM10K_TXQCTL(q_idx));
545 txqctl &= ~FM10K_TXQCTL_PC_MASK;
546 txqctl |= pc << FM10K_TXQCTL_PC_SHIFT;
547 fm10k_write_reg(hw, FM10K_TXQCTL(q_idx), txqctl);
548
549 q_idx += pc_count;
550 }
551 }
552
553 /* configure DGLORTDEC */
554 dglortdec = ((u32)(dglort->rss_l) << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) |
555 ((u32)(dglort->queue_b) << FM10K_DGLORTDEC_QBASE_SHIFT) |
556 ((u32)(dglort->pc_l) << FM10K_DGLORTDEC_PCLENGTH_SHIFT) |
557 ((u32)(dglort->vsi_b) << FM10K_DGLORTDEC_VSIBASE_SHIFT) |
558 ((u32)(dglort->vsi_l) << FM10K_DGLORTDEC_VSILENGTH_SHIFT) |
559 ((u32)(dglort->queue_l));
560 if (dglort->inner_rss)
561 dglortdec |= FM10K_DGLORTDEC_INNERRSS_ENABLE;
562
563 /* configure DGLORTMAP */
564 dglortmap = (dglort->idx == fm10k_dglort_default) ?
565 FM10K_DGLORTMAP_ANY : FM10K_DGLORTMAP_ZERO;
566 dglortmap <<= dglort->vsi_l + dglort->queue_l + dglort->shared_l;
567 dglortmap |= dglort->glort;
568
569 /* write values to hardware */
570 fm10k_write_reg(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec);
571 fm10k_write_reg(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap);
572
573 return 0;
574}
575
576u16 fm10k_queues_per_pool(struct fm10k_hw *hw)
577{
578 u16 num_pools = hw->iov.num_pools;
579
580 return (num_pools > 32) ? 2 : (num_pools > 16) ? 4 : (num_pools > 8) ?
581 8 : FM10K_MAX_QUEUES_POOL;
582}
583
584u16 fm10k_vf_queue_index(struct fm10k_hw *hw, u16 vf_idx)
585{
586 u16 num_vfs = hw->iov.num_vfs;
587 u16 vf_q_idx = FM10K_MAX_QUEUES;
588
589 vf_q_idx -= fm10k_queues_per_pool(hw) * (num_vfs - vf_idx);
590
591 return vf_q_idx;
592}
593
594static u16 fm10k_vectors_per_pool(struct fm10k_hw *hw)
595{
596 u16 num_pools = hw->iov.num_pools;
597
598 return (num_pools > 32) ? 8 : (num_pools > 16) ? 16 :
599 FM10K_MAX_VECTORS_POOL;
600}
601
602static u16 fm10k_vf_vector_index(struct fm10k_hw *hw, u16 vf_idx)
603{
604 u16 vf_v_idx = FM10K_MAX_VECTORS_PF;
605
606 vf_v_idx += fm10k_vectors_per_pool(hw) * vf_idx;
607
608 return vf_v_idx;
609}
610
611/**
612 * fm10k_iov_assign_resources_pf - Assign pool resources for virtualization
613 * @hw: pointer to the HW structure
614 * @num_vfs: number of VFs to be allocated
615 * @num_pools: number of virtualization pools to be allocated
616 *
617 * Allocates queues and traffic classes to virtualization entities to prepare
618 * the PF for SR-IOV and VMDq
619 **/
620static s32 fm10k_iov_assign_resources_pf(struct fm10k_hw *hw, u16 num_vfs,
621 u16 num_pools)
622{
623 u16 qmap_stride, qpp, vpp, vf_q_idx, vf_q_idx0, qmap_idx;
624 u32 vid = hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT;
625 int i, j;
626
627 /* hardware only supports up to 64 pools */
628 if (num_pools > 64)
629 return FM10K_ERR_PARAM;
630
631 /* the number of VFs cannot exceed the number of pools */
632 if ((num_vfs > num_pools) || (num_vfs > hw->iov.total_vfs))
633 return FM10K_ERR_PARAM;
634
635 /* record number of virtualization entities */
636 hw->iov.num_vfs = num_vfs;
637 hw->iov.num_pools = num_pools;
638
639 /* determine qmap offsets and counts */
640 qmap_stride = (num_vfs > 8) ? 32 : 256;
641 qpp = fm10k_queues_per_pool(hw);
642 vpp = fm10k_vectors_per_pool(hw);
643
644 /* calculate starting index for queues */
645 vf_q_idx = fm10k_vf_queue_index(hw, 0);
646 qmap_idx = 0;
647
648 /* establish TCs with -1 credits and no quanta to prevent transmit */
649 for (i = 0; i < num_vfs; i++) {
650 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(i), 0);
651 fm10k_write_reg(hw, FM10K_TC_RATE(i), 0);
652 fm10k_write_reg(hw, FM10K_TC_CREDIT(i),
653 FM10K_TC_CREDIT_CREDIT_MASK);
654 }
655
656 /* zero out all mbmem registers */
657 for (i = FM10K_VFMBMEM_LEN * num_vfs; i--;)
658 fm10k_write_reg(hw, FM10K_MBMEM(i), 0);
659
660 /* clear event notification of VF FLR */
661 fm10k_write_reg(hw, FM10K_PFVFLREC(0), ~0);
662 fm10k_write_reg(hw, FM10K_PFVFLREC(1), ~0);
663
664 /* loop through unallocated rings assigning them back to PF */
665 for (i = FM10K_MAX_QUEUES_PF; i < vf_q_idx; i++) {
666 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0);
667 fm10k_write_reg(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF |
668 FM10K_TXQCTL_UNLIMITED_BW | vid);
669 fm10k_write_reg(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF);
670 }
671
672 /* PF should have already updated VFITR2[0] */
673
674 /* update all ITR registers to flow to VFITR2[0] */
675 for (i = FM10K_ITR_REG_COUNT_PF + 1; i < FM10K_ITR_REG_COUNT; i++) {
676 if (!(i & (vpp - 1)))
677 fm10k_write_reg(hw, FM10K_ITR2(i), i - vpp);
678 else
679 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1);
680 }
681
682 /* update PF ITR2[0] to reference the last vector */
683 fm10k_write_reg(hw, FM10K_ITR2(0),
684 fm10k_vf_vector_index(hw, num_vfs - 1));
685
686 /* loop through rings populating rings and TCs */
687 for (i = 0; i < num_vfs; i++) {
688 /* record index for VF queue 0 for use in end of loop */
689 vf_q_idx0 = vf_q_idx;
690
691 for (j = 0; j < qpp; j++, qmap_idx++, vf_q_idx++) {
692 /* assign VF and locked TC to queues */
693 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0);
694 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx),
695 (i << FM10K_TXQCTL_TC_SHIFT) | i |
696 FM10K_TXQCTL_VF | vid);
697 fm10k_write_reg(hw, FM10K_RXDCTL(vf_q_idx),
698 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
699 FM10K_RXDCTL_DROP_ON_EMPTY);
700 fm10k_write_reg(hw, FM10K_RXQCTL(vf_q_idx),
701 (i << FM10K_RXQCTL_VF_SHIFT) |
702 FM10K_RXQCTL_VF);
703
704 /* map queue pair to VF */
705 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
706 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx);
707 }
708
709 /* repeat the first ring for all of the remaining VF rings */
710 for (; j < qmap_stride; j++, qmap_idx++) {
711 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0);
712 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0);
713 }
714 }
715
716 /* loop through remaining indexes assigning all to queue 0 */
717 while (qmap_idx < FM10K_TQMAP_TABLE_SIZE) {
718 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0);
719 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), 0);
720 qmap_idx++;
721 }
722
723 return 0;
724}
725
726/**
727 * fm10k_iov_configure_tc_pf - Configure the shaping group for VF
728 * @hw: pointer to the HW structure
729 * @vf_idx: index of VF receiving GLORT
730 * @rate: Rate indicated in Mb/s
731 *
732 * Configured the TC for a given VF to allow only up to a given number
733 * of Mb/s of outgoing Tx throughput.
734 **/
735static s32 fm10k_iov_configure_tc_pf(struct fm10k_hw *hw, u16 vf_idx, int rate)
736{
737 /* configure defaults */
738 u32 interval = FM10K_TC_RATE_INTERVAL_4US_GEN3;
739 u32 tc_rate = FM10K_TC_RATE_QUANTA_MASK;
740
741 /* verify vf is in range */
742 if (vf_idx >= hw->iov.num_vfs)
743 return FM10K_ERR_PARAM;
744
745 /* set interval to align with 4.096 usec in all modes */
746 switch (hw->bus.speed) {
747 case fm10k_bus_speed_2500:
748 interval = FM10K_TC_RATE_INTERVAL_4US_GEN1;
749 break;
750 case fm10k_bus_speed_5000:
751 interval = FM10K_TC_RATE_INTERVAL_4US_GEN2;
752 break;
753 default:
754 break;
755 }
756
757 if (rate) {
758 if (rate > FM10K_VF_TC_MAX || rate < FM10K_VF_TC_MIN)
759 return FM10K_ERR_PARAM;
760
761 /* The quanta is measured in Bytes per 4.096 or 8.192 usec
762 * The rate is provided in Mbits per second
763 * To tralslate from rate to quanta we need to multiply the
764 * rate by 8.192 usec and divide by 8 bits/byte. To avoid
765 * dealing with floating point we can round the values up
766 * to the nearest whole number ratio which gives us 128 / 125.
767 */
768 tc_rate = (rate * 128) / 125;
769
770 /* try to keep the rate limiting accurate by increasing
771 * the number of credits and interval for rates less than 4Gb/s
772 */
773 if (rate < 4000)
774 interval <<= 1;
775 else
776 tc_rate >>= 1;
777 }
778
779 /* update rate limiter with new values */
780 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval);
781 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
782 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
783
784 return 0;
785}
786
787/**
788 * fm10k_iov_assign_int_moderator_pf - Add VF interrupts to moderator list
789 * @hw: pointer to the HW structure
790 * @vf_idx: index of VF receiving GLORT
791 *
792 * Update the interrupt moderator linked list to include any MSI-X
793 * interrupts which the VF has enabled in the MSI-X vector table.
794 **/
795static s32 fm10k_iov_assign_int_moderator_pf(struct fm10k_hw *hw, u16 vf_idx)
796{
797 u16 vf_v_idx, vf_v_limit, i;
798
799 /* verify vf is in range */
800 if (vf_idx >= hw->iov.num_vfs)
801 return FM10K_ERR_PARAM;
802
803 /* determine vector offset and count */
804 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
805 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
806
807 /* search for first vector that is not masked */
808 for (i = vf_v_limit - 1; i > vf_v_idx; i--) {
809 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i)))
810 break;
811 }
812
813 /* reset linked list so it now includes our active vectors */
814 if (vf_idx == (hw->iov.num_vfs - 1))
815 fm10k_write_reg(hw, FM10K_ITR2(0), i);
816 else
817 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), i);
818
819 return 0;
820}
821
822/**
823 * fm10k_iov_assign_default_mac_vlan_pf - Assign a MAC and VLAN to VF
824 * @hw: pointer to the HW structure
825 * @vf_info: pointer to VF information structure
826 *
827 * Assign a MAC address and default VLAN to a VF and notify it of the update
828 **/
829static s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw,
830 struct fm10k_vf_info *vf_info)
831{
832 u16 qmap_stride, queues_per_pool, vf_q_idx, timeout, qmap_idx, i;
833 u32 msg[4], txdctl, txqctl, tdbal = 0, tdbah = 0;
834 s32 err = 0;
835 u16 vf_idx, vf_vid;
836
837 /* verify vf is in range */
838 if (!vf_info || vf_info->vf_idx >= hw->iov.num_vfs)
839 return FM10K_ERR_PARAM;
840
841 /* determine qmap offsets and counts */
842 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
843 queues_per_pool = fm10k_queues_per_pool(hw);
844
845 /* calculate starting index for queues */
846 vf_idx = vf_info->vf_idx;
847 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
848 qmap_idx = qmap_stride * vf_idx;
849
850 /* Determine correct default VLAN ID. The FM10K_VLAN_OVERRIDE bit is
851 * used here to indicate to the VF that it will not have privilege to
852 * write VLAN_TABLE. All policy is enforced on the PF but this allows
853 * the VF to correctly report errors to userspace requests.
854 */
855 if (vf_info->pf_vid)
856 vf_vid = vf_info->pf_vid | FM10K_VLAN_OVERRIDE;
857 else
858 vf_vid = vf_info->sw_vid;
859
860 /* generate MAC_ADDR request */
861 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);
862 fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_DEFAULT_MAC,
863 vf_info->mac, vf_vid);
864
865 /* Configure Queue control register with new VLAN ID. The TXQCTL
866 * register is RO from the VF, so the PF must do this even in the
867 * case of notifying the VF of a new VID via the mailbox.
868 */
869 txqctl = FIELD_PREP(FM10K_TXQCTL_VID_MASK, vf_vid);
870 txqctl |= (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
871 FM10K_TXQCTL_VF | vf_idx;
872
873 for (i = 0; i < queues_per_pool; i++)
874 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl);
875
876 /* try loading a message onto outgoing mailbox first */
877 if (vf_info->mbx.ops.enqueue_tx) {
878 err = vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
879 if (err != FM10K_MBX_ERR_NO_MBX)
880 return err;
881 err = 0;
882 }
883
884 /* If we aren't connected to a mailbox, this is most likely because
885 * the VF driver is not running. It should thus be safe to re-map
886 * queues and use the registers to pass the MAC address so that the VF
887 * driver gets correct information during its initialization.
888 */
889
890 /* MAP Tx queue back to 0 temporarily, and disable it */
891 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0);
892 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0);
893
894 /* verify ring has disabled before modifying base address registers */
895 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx));
896 for (timeout = 0; txdctl & FM10K_TXDCTL_ENABLE; timeout++) {
897 /* limit ourselves to a 1ms timeout */
898 if (timeout == 10) {
899 err = FM10K_ERR_DMA_PENDING;
900 goto err_out;
901 }
902
903 usleep_range(100, 200);
904 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx));
905 }
906
907 /* Update base address registers to contain MAC address */
908 if (is_valid_ether_addr(vf_info->mac)) {
909 tdbal = (((u32)vf_info->mac[3]) << 24) |
910 (((u32)vf_info->mac[4]) << 16) |
911 (((u32)vf_info->mac[5]) << 8);
912
913 tdbah = (((u32)0xFF) << 24) |
914 (((u32)vf_info->mac[0]) << 16) |
915 (((u32)vf_info->mac[1]) << 8) |
916 ((u32)vf_info->mac[2]);
917 }
918
919 /* Record the base address into queue 0 */
920 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx), tdbal);
921 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx), tdbah);
922
923 /* Provide the VF the ITR scale, using software-defined fields in TDLEN
924 * to pass the information during VF initialization. See definition of
925 * FM10K_TDLEN_ITR_SCALE_SHIFT for more details.
926 */
927 fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx), hw->mac.itr_scale <<
928 FM10K_TDLEN_ITR_SCALE_SHIFT);
929
930err_out:
931 /* restore the queue back to VF ownership */
932 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
933 return err;
934}
935
936/**
937 * fm10k_iov_reset_resources_pf - Reassign queues and interrupts to a VF
938 * @hw: pointer to the HW structure
939 * @vf_info: pointer to VF information structure
940 *
941 * Reassign the interrupts and queues to a VF following an FLR
942 **/
943static s32 fm10k_iov_reset_resources_pf(struct fm10k_hw *hw,
944 struct fm10k_vf_info *vf_info)
945{
946 u16 qmap_stride, queues_per_pool, vf_q_idx, qmap_idx;
947 u32 tdbal = 0, tdbah = 0, txqctl, rxqctl;
948 u16 vf_v_idx, vf_v_limit, vf_vid;
949 u8 vf_idx = vf_info->vf_idx;
950 int i;
951
952 /* verify vf is in range */
953 if (vf_idx >= hw->iov.num_vfs)
954 return FM10K_ERR_PARAM;
955
956 /* clear event notification of VF FLR */
957 fm10k_write_reg(hw, FM10K_PFVFLREC(vf_idx / 32), BIT(vf_idx % 32));
958
959 /* force timeout and then disconnect the mailbox */
960 vf_info->mbx.timeout = 0;
961 if (vf_info->mbx.ops.disconnect)
962 vf_info->mbx.ops.disconnect(hw, &vf_info->mbx);
963
964 /* determine vector offset and count */
965 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
966 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
967
968 /* determine qmap offsets and counts */
969 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
970 queues_per_pool = fm10k_queues_per_pool(hw);
971 qmap_idx = qmap_stride * vf_idx;
972
973 /* make all the queues inaccessible to the VF */
974 for (i = qmap_idx; i < (qmap_idx + qmap_stride); i++) {
975 fm10k_write_reg(hw, FM10K_TQMAP(i), 0);
976 fm10k_write_reg(hw, FM10K_RQMAP(i), 0);
977 }
978
979 /* calculate starting index for queues */
980 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
981
982 /* determine correct default VLAN ID */
983 if (vf_info->pf_vid)
984 vf_vid = vf_info->pf_vid;
985 else
986 vf_vid = vf_info->sw_vid;
987
988 /* configure Queue control register */
989 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) |
990 (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
991 FM10K_TXQCTL_VF | vf_idx;
992 rxqctl = (vf_idx << FM10K_RXQCTL_VF_SHIFT) | FM10K_RXQCTL_VF;
993
994 /* stop further DMA and reset queue ownership back to VF */
995 for (i = vf_q_idx; i < (queues_per_pool + vf_q_idx); i++) {
996 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0);
997 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl);
998 fm10k_write_reg(hw, FM10K_RXDCTL(i),
999 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
1000 FM10K_RXDCTL_DROP_ON_EMPTY);
1001 fm10k_write_reg(hw, FM10K_RXQCTL(i), rxqctl);
1002 }
1003
1004 /* reset TC with -1 credits and no quanta to prevent transmit */
1005 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), 0);
1006 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), 0);
1007 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx),
1008 FM10K_TC_CREDIT_CREDIT_MASK);
1009
1010 /* update our first entry in the table based on previous VF */
1011 if (!vf_idx)
1012 hw->mac.ops.update_int_moderator(hw);
1013 else
1014 hw->iov.ops.assign_int_moderator(hw, vf_idx - 1);
1015
1016 /* reset linked list so it now includes our active vectors */
1017 if (vf_idx == (hw->iov.num_vfs - 1))
1018 fm10k_write_reg(hw, FM10K_ITR2(0), vf_v_idx);
1019 else
1020 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), vf_v_idx);
1021
1022 /* link remaining vectors so that next points to previous */
1023 for (vf_v_idx++; vf_v_idx < vf_v_limit; vf_v_idx++)
1024 fm10k_write_reg(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1);
1025
1026 /* zero out MBMEM, VLAN_TABLE, RETA, RSSRK, and MRQC registers */
1027 for (i = FM10K_VFMBMEM_LEN; i--;)
1028 fm10k_write_reg(hw, FM10K_MBMEM_VF(vf_idx, i), 0);
1029 for (i = FM10K_VLAN_TABLE_SIZE; i--;)
1030 fm10k_write_reg(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0);
1031 for (i = FM10K_RETA_SIZE; i--;)
1032 fm10k_write_reg(hw, FM10K_RETA(vf_info->vsi, i), 0);
1033 for (i = FM10K_RSSRK_SIZE; i--;)
1034 fm10k_write_reg(hw, FM10K_RSSRK(vf_info->vsi, i), 0);
1035 fm10k_write_reg(hw, FM10K_MRQC(vf_info->vsi), 0);
1036
1037 /* Update base address registers to contain MAC address */
1038 if (is_valid_ether_addr(vf_info->mac)) {
1039 tdbal = (((u32)vf_info->mac[3]) << 24) |
1040 (((u32)vf_info->mac[4]) << 16) |
1041 (((u32)vf_info->mac[5]) << 8);
1042 tdbah = (((u32)0xFF) << 24) |
1043 (((u32)vf_info->mac[0]) << 16) |
1044 (((u32)vf_info->mac[1]) << 8) |
1045 ((u32)vf_info->mac[2]);
1046 }
1047
1048 /* map queue pairs back to VF from last to first */
1049 for (i = queues_per_pool; i--;) {
1050 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx + i), tdbal);
1051 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx + i), tdbah);
1052 /* See definition of FM10K_TDLEN_ITR_SCALE_SHIFT for an
1053 * explanation of how TDLEN is used.
1054 */
1055 fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx + i),
1056 hw->mac.itr_scale <<
1057 FM10K_TDLEN_ITR_SCALE_SHIFT);
1058 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i);
1059 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i);
1060 }
1061
1062 /* repeat the first ring for all the remaining VF rings */
1063 for (i = queues_per_pool; i < qmap_stride; i++) {
1064 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx);
1065 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx);
1066 }
1067
1068 return 0;
1069}
1070
1071/**
1072 * fm10k_iov_set_lport_pf - Assign and enable a logical port for a given VF
1073 * @hw: pointer to hardware structure
1074 * @vf_info: pointer to VF information structure
1075 * @lport_idx: Logical port offset from the hardware glort
1076 * @flags: Set of capability flags to extend port beyond basic functionality
1077 *
1078 * This function allows enabling a VF port by assigning it a GLORT and
1079 * setting the flags so that it can enable an Rx mode.
1080 **/
1081static s32 fm10k_iov_set_lport_pf(struct fm10k_hw *hw,
1082 struct fm10k_vf_info *vf_info,
1083 u16 lport_idx, u8 flags)
1084{
1085 u16 glort = (hw->mac.dglort_map + lport_idx) & FM10K_DGLORTMAP_NONE;
1086
1087 /* if glort is not valid return error */
1088 if (!fm10k_glort_valid_pf(hw, glort))
1089 return FM10K_ERR_PARAM;
1090
1091 vf_info->vf_flags = flags | FM10K_VF_FLAG_NONE_CAPABLE;
1092 vf_info->glort = glort;
1093
1094 return 0;
1095}
1096
1097/**
1098 * fm10k_iov_reset_lport_pf - Disable a logical port for a given VF
1099 * @hw: pointer to hardware structure
1100 * @vf_info: pointer to VF information structure
1101 *
1102 * This function disables a VF port by stripping it of a GLORT and
1103 * setting the flags so that it cannot enable any Rx mode.
1104 **/
1105static void fm10k_iov_reset_lport_pf(struct fm10k_hw *hw,
1106 struct fm10k_vf_info *vf_info)
1107{
1108 u32 msg[1];
1109
1110 /* need to disable the port if it is already enabled */
1111 if (FM10K_VF_FLAG_ENABLED(vf_info)) {
1112 /* notify switch that this port has been disabled */
1113 fm10k_update_lport_state_pf(hw, vf_info->glort, 1, false);
1114
1115 /* generate port state response to notify VF it is not ready */
1116 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1117 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
1118 }
1119
1120 /* clear flags and glort if it exists */
1121 vf_info->vf_flags = 0;
1122 vf_info->glort = 0;
1123}
1124
1125/**
1126 * fm10k_iov_update_stats_pf - Updates hardware related statistics for VFs
1127 * @hw: pointer to hardware structure
1128 * @q: stats for all queues of a VF
1129 * @vf_idx: index of VF
1130 *
1131 * This function collects queue stats for VFs.
1132 **/
1133static void fm10k_iov_update_stats_pf(struct fm10k_hw *hw,
1134 struct fm10k_hw_stats_q *q,
1135 u16 vf_idx)
1136{
1137 u32 idx, qpp;
1138
1139 /* get stats for all of the queues */
1140 qpp = fm10k_queues_per_pool(hw);
1141 idx = fm10k_vf_queue_index(hw, vf_idx);
1142 fm10k_update_hw_stats_q(hw, q, idx, qpp);
1143}
1144
1145/**
1146 * fm10k_iov_msg_msix_pf - Message handler for MSI-X request from VF
1147 * @hw: Pointer to hardware structure
1148 * @results: Pointer array to message, results[0] is pointer to message
1149 * @mbx: Pointer to mailbox information structure
1150 *
1151 * This function is a default handler for MSI-X requests from the VF. The
1152 * assumption is that in this case it is acceptable to just directly
1153 * hand off the message from the VF to the underlying shared code.
1154 **/
1155s32 fm10k_iov_msg_msix_pf(struct fm10k_hw *hw, u32 __always_unused **results,
1156 struct fm10k_mbx_info *mbx)
1157{
1158 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1159 u8 vf_idx = vf_info->vf_idx;
1160
1161 return hw->iov.ops.assign_int_moderator(hw, vf_idx);
1162}
1163
1164/**
1165 * fm10k_iov_select_vid - Select correct default VLAN ID
1166 * @vf_info: pointer to VF information structure
1167 * @vid: VLAN ID to correct
1168 *
1169 * Will report an error if the VLAN ID is out of range. For VID = 0, it will
1170 * return either the pf_vid or sw_vid depending on which one is set.
1171 */
1172s32 fm10k_iov_select_vid(struct fm10k_vf_info *vf_info, u16 vid)
1173{
1174 if (!vid)
1175 return vf_info->pf_vid ? vf_info->pf_vid : vf_info->sw_vid;
1176 else if (vf_info->pf_vid && vid != vf_info->pf_vid)
1177 return FM10K_ERR_PARAM;
1178 else
1179 return vid;
1180}
1181
1182/**
1183 * fm10k_iov_msg_mac_vlan_pf - Message handler for MAC/VLAN request from VF
1184 * @hw: Pointer to hardware structure
1185 * @results: Pointer array to message, results[0] is pointer to message
1186 * @mbx: Pointer to mailbox information structure
1187 *
1188 * This function is a default handler for MAC/VLAN requests from the VF.
1189 * The assumption is that in this case it is acceptable to just directly
1190 * hand off the message from the VF to the underlying shared code.
1191 **/
1192s32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *hw, u32 **results,
1193 struct fm10k_mbx_info *mbx)
1194{
1195 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1196 u8 mac[ETH_ALEN];
1197 u32 *result;
1198 int err = 0;
1199 bool set;
1200 u16 vlan;
1201 u32 vid;
1202
1203 /* we shouldn't be updating rules on a disabled interface */
1204 if (!FM10K_VF_FLAG_ENABLED(vf_info))
1205 err = FM10K_ERR_PARAM;
1206
1207 if (!err && !!results[FM10K_MAC_VLAN_MSG_VLAN]) {
1208 result = results[FM10K_MAC_VLAN_MSG_VLAN];
1209
1210 /* record VLAN id requested */
1211 err = fm10k_tlv_attr_get_u32(result, &vid);
1212 if (err)
1213 return err;
1214
1215 set = !(vid & FM10K_VLAN_CLEAR);
1216 vid &= ~FM10K_VLAN_CLEAR;
1217
1218 /* if the length field has been set, this is a multi-bit
1219 * update request. For multi-bit requests, simply disallow
1220 * them when the pf_vid has been set. In this case, the PF
1221 * should have already cleared the VLAN_TABLE, and if we
1222 * allowed them, it could allow a rogue VF to receive traffic
1223 * on a VLAN it was not assigned. In the single-bit case, we
1224 * need to modify requests for VLAN 0 to use the default PF or
1225 * SW vid when assigned.
1226 */
1227
1228 if (vid >> 16) {
1229 /* prevent multi-bit requests when PF has
1230 * administratively set the VLAN for this VF
1231 */
1232 if (vf_info->pf_vid)
1233 return FM10K_ERR_PARAM;
1234 } else {
1235 err = fm10k_iov_select_vid(vf_info, (u16)vid);
1236 if (err < 0)
1237 return err;
1238
1239 vid = err;
1240 }
1241
1242 /* update VSI info for VF in regards to VLAN table */
1243 err = hw->mac.ops.update_vlan(hw, vid, vf_info->vsi, set);
1244 }
1245
1246 if (!err && !!results[FM10K_MAC_VLAN_MSG_MAC]) {
1247 result = results[FM10K_MAC_VLAN_MSG_MAC];
1248
1249 /* record unicast MAC address requested */
1250 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1251 if (err)
1252 return err;
1253
1254 /* block attempts to set MAC for a locked device */
1255 if (is_valid_ether_addr(vf_info->mac) &&
1256 !ether_addr_equal(mac, vf_info->mac))
1257 return FM10K_ERR_PARAM;
1258
1259 set = !(vlan & FM10K_VLAN_CLEAR);
1260 vlan &= ~FM10K_VLAN_CLEAR;
1261
1262 err = fm10k_iov_select_vid(vf_info, vlan);
1263 if (err < 0)
1264 return err;
1265
1266 vlan = (u16)err;
1267
1268 /* notify switch of request for new unicast address */
1269 err = hw->mac.ops.update_uc_addr(hw, vf_info->glort,
1270 mac, vlan, set, 0);
1271 }
1272
1273 if (!err && !!results[FM10K_MAC_VLAN_MSG_MULTICAST]) {
1274 result = results[FM10K_MAC_VLAN_MSG_MULTICAST];
1275
1276 /* record multicast MAC address requested */
1277 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1278 if (err)
1279 return err;
1280
1281 /* verify that the VF is allowed to request multicast */
1282 if (!(vf_info->vf_flags & FM10K_VF_FLAG_MULTI_ENABLED))
1283 return FM10K_ERR_PARAM;
1284
1285 set = !(vlan & FM10K_VLAN_CLEAR);
1286 vlan &= ~FM10K_VLAN_CLEAR;
1287
1288 err = fm10k_iov_select_vid(vf_info, vlan);
1289 if (err < 0)
1290 return err;
1291
1292 vlan = (u16)err;
1293
1294 /* notify switch of request for new multicast address */
1295 err = hw->mac.ops.update_mc_addr(hw, vf_info->glort,
1296 mac, vlan, set);
1297 }
1298
1299 return err;
1300}
1301
1302/**
1303 * fm10k_iov_supported_xcast_mode_pf - Determine best match for xcast mode
1304 * @vf_info: VF info structure containing capability flags
1305 * @mode: Requested xcast mode
1306 *
1307 * This function outputs the mode that most closely matches the requested
1308 * mode. If not modes match it will request we disable the port
1309 **/
1310static u8 fm10k_iov_supported_xcast_mode_pf(struct fm10k_vf_info *vf_info,
1311 u8 mode)
1312{
1313 u8 vf_flags = vf_info->vf_flags;
1314
1315 /* match up mode to capabilities as best as possible */
1316 switch (mode) {
1317 case FM10K_XCAST_MODE_PROMISC:
1318 if (vf_flags & FM10K_VF_FLAG_PROMISC_CAPABLE)
1319 return FM10K_XCAST_MODE_PROMISC;
1320 fallthrough;
1321 case FM10K_XCAST_MODE_ALLMULTI:
1322 if (vf_flags & FM10K_VF_FLAG_ALLMULTI_CAPABLE)
1323 return FM10K_XCAST_MODE_ALLMULTI;
1324 fallthrough;
1325 case FM10K_XCAST_MODE_MULTI:
1326 if (vf_flags & FM10K_VF_FLAG_MULTI_CAPABLE)
1327 return FM10K_XCAST_MODE_MULTI;
1328 fallthrough;
1329 case FM10K_XCAST_MODE_NONE:
1330 if (vf_flags & FM10K_VF_FLAG_NONE_CAPABLE)
1331 return FM10K_XCAST_MODE_NONE;
1332 fallthrough;
1333 default:
1334 break;
1335 }
1336
1337 /* disable interface as it should not be able to request any */
1338 return FM10K_XCAST_MODE_DISABLE;
1339}
1340
1341/**
1342 * fm10k_iov_msg_lport_state_pf - Message handler for port state requests
1343 * @hw: Pointer to hardware structure
1344 * @results: Pointer array to message, results[0] is pointer to message
1345 * @mbx: Pointer to mailbox information structure
1346 *
1347 * This function is a default handler for port state requests. The port
1348 * state requests for now are basic and consist of enabling or disabling
1349 * the port.
1350 **/
1351s32 fm10k_iov_msg_lport_state_pf(struct fm10k_hw *hw, u32 **results,
1352 struct fm10k_mbx_info *mbx)
1353{
1354 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1355 s32 err = 0;
1356 u32 msg[2];
1357 u8 mode = 0;
1358
1359 /* verify VF is allowed to enable even minimal mode */
1360 if (!(vf_info->vf_flags & FM10K_VF_FLAG_NONE_CAPABLE))
1361 return FM10K_ERR_PARAM;
1362
1363 if (!!results[FM10K_LPORT_STATE_MSG_XCAST_MODE]) {
1364 u32 *result = results[FM10K_LPORT_STATE_MSG_XCAST_MODE];
1365
1366 /* XCAST mode update requested */
1367 err = fm10k_tlv_attr_get_u8(result, &mode);
1368 if (err)
1369 return FM10K_ERR_PARAM;
1370
1371 /* prep for possible demotion depending on capabilities */
1372 mode = fm10k_iov_supported_xcast_mode_pf(vf_info, mode);
1373
1374 /* if mode is not currently enabled, enable it */
1375 if (!(FM10K_VF_FLAG_ENABLED(vf_info) & BIT(mode)))
1376 fm10k_update_xcast_mode_pf(hw, vf_info->glort, mode);
1377
1378 /* swap mode back to a bit flag */
1379 mode = FM10K_VF_FLAG_SET_MODE(mode);
1380 } else if (!results[FM10K_LPORT_STATE_MSG_DISABLE]) {
1381 /* need to disable the port if it is already enabled */
1382 if (FM10K_VF_FLAG_ENABLED(vf_info))
1383 err = fm10k_update_lport_state_pf(hw, vf_info->glort,
1384 1, false);
1385
1386 /* we need to clear VF_FLAG_ENABLED flags in order to ensure
1387 * that we actually re-enable the LPORT state below. Note that
1388 * this has no impact if the VF is already disabled, as the
1389 * flags are already cleared.
1390 */
1391 if (!err)
1392 vf_info->vf_flags = FM10K_VF_FLAG_CAPABLE(vf_info);
1393
1394 /* when enabling the port we should reset the rate limiters */
1395 hw->iov.ops.configure_tc(hw, vf_info->vf_idx, vf_info->rate);
1396
1397 /* set mode for minimal functionality */
1398 mode = FM10K_VF_FLAG_SET_MODE_NONE;
1399
1400 /* generate port state response to notify VF it is ready */
1401 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1402 fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_READY);
1403 mbx->ops.enqueue_tx(hw, mbx, msg);
1404 }
1405
1406 /* if enable state toggled note the update */
1407 if (!err && (!FM10K_VF_FLAG_ENABLED(vf_info) != !mode))
1408 err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1,
1409 !!mode);
1410
1411 /* if state change succeeded, then update our stored state */
1412 mode |= FM10K_VF_FLAG_CAPABLE(vf_info);
1413 if (!err)
1414 vf_info->vf_flags = mode;
1415
1416 return err;
1417}
1418
1419/**
1420 * fm10k_update_hw_stats_pf - Updates hardware related statistics of PF
1421 * @hw: pointer to hardware structure
1422 * @stats: pointer to the stats structure to update
1423 *
1424 * This function collects and aggregates global and per queue hardware
1425 * statistics.
1426 **/
1427static void fm10k_update_hw_stats_pf(struct fm10k_hw *hw,
1428 struct fm10k_hw_stats *stats)
1429{
1430 u32 timeout, ur, ca, um, xec, vlan_drop, loopback_drop, nodesc_drop;
1431 u32 id, id_prev;
1432
1433 /* Use Tx queue 0 as a canary to detect a reset */
1434 id = fm10k_read_reg(hw, FM10K_TXQCTL(0));
1435
1436 /* Read Global Statistics */
1437 do {
1438 timeout = fm10k_read_hw_stats_32b(hw, FM10K_STATS_TIMEOUT,
1439 &stats->timeout);
1440 ur = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UR, &stats->ur);
1441 ca = fm10k_read_hw_stats_32b(hw, FM10K_STATS_CA, &stats->ca);
1442 um = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UM, &stats->um);
1443 xec = fm10k_read_hw_stats_32b(hw, FM10K_STATS_XEC, &stats->xec);
1444 vlan_drop = fm10k_read_hw_stats_32b(hw, FM10K_STATS_VLAN_DROP,
1445 &stats->vlan_drop);
1446 loopback_drop =
1447 fm10k_read_hw_stats_32b(hw,
1448 FM10K_STATS_LOOPBACK_DROP,
1449 &stats->loopback_drop);
1450 nodesc_drop = fm10k_read_hw_stats_32b(hw,
1451 FM10K_STATS_NODESC_DROP,
1452 &stats->nodesc_drop);
1453
1454 /* if value has not changed then we have consistent data */
1455 id_prev = id;
1456 id = fm10k_read_reg(hw, FM10K_TXQCTL(0));
1457 } while ((id ^ id_prev) & FM10K_TXQCTL_ID_MASK);
1458
1459 /* drop non-ID bits and set VALID ID bit */
1460 id &= FM10K_TXQCTL_ID_MASK;
1461 id |= FM10K_STAT_VALID;
1462
1463 /* Update Global Statistics */
1464 if (stats->stats_idx == id) {
1465 stats->timeout.count += timeout;
1466 stats->ur.count += ur;
1467 stats->ca.count += ca;
1468 stats->um.count += um;
1469 stats->xec.count += xec;
1470 stats->vlan_drop.count += vlan_drop;
1471 stats->loopback_drop.count += loopback_drop;
1472 stats->nodesc_drop.count += nodesc_drop;
1473 }
1474
1475 /* Update bases and record current PF id */
1476 fm10k_update_hw_base_32b(&stats->timeout, timeout);
1477 fm10k_update_hw_base_32b(&stats->ur, ur);
1478 fm10k_update_hw_base_32b(&stats->ca, ca);
1479 fm10k_update_hw_base_32b(&stats->um, um);
1480 fm10k_update_hw_base_32b(&stats->xec, xec);
1481 fm10k_update_hw_base_32b(&stats->vlan_drop, vlan_drop);
1482 fm10k_update_hw_base_32b(&stats->loopback_drop, loopback_drop);
1483 fm10k_update_hw_base_32b(&stats->nodesc_drop, nodesc_drop);
1484 stats->stats_idx = id;
1485
1486 /* Update Queue Statistics */
1487 fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues);
1488}
1489
1490/**
1491 * fm10k_rebind_hw_stats_pf - Resets base for hardware statistics of PF
1492 * @hw: pointer to hardware structure
1493 * @stats: pointer to the stats structure to update
1494 *
1495 * This function resets the base for global and per queue hardware
1496 * statistics.
1497 **/
1498static void fm10k_rebind_hw_stats_pf(struct fm10k_hw *hw,
1499 struct fm10k_hw_stats *stats)
1500{
1501 /* Unbind Global Statistics */
1502 fm10k_unbind_hw_stats_32b(&stats->timeout);
1503 fm10k_unbind_hw_stats_32b(&stats->ur);
1504 fm10k_unbind_hw_stats_32b(&stats->ca);
1505 fm10k_unbind_hw_stats_32b(&stats->um);
1506 fm10k_unbind_hw_stats_32b(&stats->xec);
1507 fm10k_unbind_hw_stats_32b(&stats->vlan_drop);
1508 fm10k_unbind_hw_stats_32b(&stats->loopback_drop);
1509 fm10k_unbind_hw_stats_32b(&stats->nodesc_drop);
1510
1511 /* Unbind Queue Statistics */
1512 fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues);
1513
1514 /* Reinitialize bases for all stats */
1515 fm10k_update_hw_stats_pf(hw, stats);
1516}
1517
1518/**
1519 * fm10k_set_dma_mask_pf - Configures PhyAddrSpace to limit DMA to system
1520 * @hw: pointer to hardware structure
1521 * @dma_mask: 64 bit DMA mask required for platform
1522 *
1523 * This function sets the PHYADDR.PhyAddrSpace bits for the endpoint in order
1524 * to limit the access to memory beyond what is physically in the system.
1525 **/
1526static void fm10k_set_dma_mask_pf(struct fm10k_hw *hw, u64 dma_mask)
1527{
1528 /* we need to write the upper 32 bits of DMA mask to PhyAddrSpace */
1529 u32 phyaddr = (u32)(dma_mask >> 32);
1530
1531 fm10k_write_reg(hw, FM10K_PHYADDR, phyaddr);
1532}
1533
1534/**
1535 * fm10k_get_fault_pf - Record a fault in one of the interface units
1536 * @hw: pointer to hardware structure
1537 * @type: pointer to fault type register offset
1538 * @fault: pointer to memory location to record the fault
1539 *
1540 * Record the fault register contents to the fault data structure and
1541 * clear the entry from the register.
1542 *
1543 * Returns ERR_PARAM if invalid register is specified or no error is present.
1544 **/
1545static s32 fm10k_get_fault_pf(struct fm10k_hw *hw, int type,
1546 struct fm10k_fault *fault)
1547{
1548 u32 func;
1549
1550 /* verify the fault register is in range and is aligned */
1551 switch (type) {
1552 case FM10K_PCA_FAULT:
1553 case FM10K_THI_FAULT:
1554 case FM10K_FUM_FAULT:
1555 break;
1556 default:
1557 return FM10K_ERR_PARAM;
1558 }
1559
1560 /* only service faults that are valid */
1561 func = fm10k_read_reg(hw, type + FM10K_FAULT_FUNC);
1562 if (!(func & FM10K_FAULT_FUNC_VALID))
1563 return FM10K_ERR_PARAM;
1564
1565 /* read remaining fields */
1566 fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_HI);
1567 fault->address <<= 32;
1568 fault->address |= fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_LO);
1569 fault->specinfo = fm10k_read_reg(hw, type + FM10K_FAULT_SPECINFO);
1570
1571 /* clear valid bit to allow for next error */
1572 fm10k_write_reg(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID);
1573
1574 /* Record which function triggered the error */
1575 if (func & FM10K_FAULT_FUNC_PF)
1576 fault->func = 0;
1577 else
1578 fault->func = 1 + FIELD_GET(FM10K_FAULT_FUNC_VF_MASK, func);
1579
1580 /* record fault type */
1581 fault->type = func & FM10K_FAULT_FUNC_TYPE_MASK;
1582
1583 return 0;
1584}
1585
1586/**
1587 * fm10k_request_lport_map_pf - Request LPORT map from the switch API
1588 * @hw: pointer to hardware structure
1589 *
1590 **/
1591static s32 fm10k_request_lport_map_pf(struct fm10k_hw *hw)
1592{
1593 struct fm10k_mbx_info *mbx = &hw->mbx;
1594 u32 msg[1];
1595
1596 /* issue request asking for LPORT map */
1597 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_LPORT_MAP);
1598
1599 /* load onto outgoing mailbox */
1600 return mbx->ops.enqueue_tx(hw, mbx, msg);
1601}
1602
1603/**
1604 * fm10k_get_host_state_pf - Returns the state of the switch and mailbox
1605 * @hw: pointer to hardware structure
1606 * @switch_ready: pointer to boolean value that will record switch state
1607 *
1608 * This function will check the DMA_CTRL2 register and mailbox in order
1609 * to determine if the switch is ready for the PF to begin requesting
1610 * addresses and mapping traffic to the local interface.
1611 **/
1612static s32 fm10k_get_host_state_pf(struct fm10k_hw *hw, bool *switch_ready)
1613{
1614 u32 dma_ctrl2;
1615
1616 /* verify the switch is ready for interaction */
1617 dma_ctrl2 = fm10k_read_reg(hw, FM10K_DMA_CTRL2);
1618 if (!(dma_ctrl2 & FM10K_DMA_CTRL2_SWITCH_READY))
1619 return 0;
1620
1621 /* retrieve generic host state info */
1622 return fm10k_get_host_state_generic(hw, switch_ready);
1623}
1624
1625/* This structure defines the attibutes to be parsed below */
1626const struct fm10k_tlv_attr fm10k_lport_map_msg_attr[] = {
1627 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR,
1628 sizeof(struct fm10k_swapi_error)),
1629 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_LPORT_MAP),
1630 FM10K_TLV_ATTR_LAST
1631};
1632
1633/**
1634 * fm10k_msg_lport_map_pf - Message handler for lport_map message from SM
1635 * @hw: Pointer to hardware structure
1636 * @results: pointer array containing parsed data
1637 * @mbx: Pointer to mailbox information structure
1638 *
1639 * This handler configures the lport mapping based on the reply from the
1640 * switch API.
1641 **/
1642s32 fm10k_msg_lport_map_pf(struct fm10k_hw *hw, u32 **results,
1643 struct fm10k_mbx_info __always_unused *mbx)
1644{
1645 u16 glort, mask;
1646 u32 dglort_map;
1647 s32 err;
1648
1649 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_LPORT_MAP],
1650 &dglort_map);
1651 if (err)
1652 return err;
1653
1654 /* extract values out of the header */
1655 glort = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_GLORT);
1656 mask = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_MASK);
1657
1658 /* verify mask is set and none of the masked bits in glort are set */
1659 if (!mask || (glort & ~mask))
1660 return FM10K_ERR_PARAM;
1661
1662 /* verify the mask is contiguous, and that it is 1's followed by 0's */
1663 if (((~(mask - 1) & mask) + mask) & FM10K_DGLORTMAP_NONE)
1664 return FM10K_ERR_PARAM;
1665
1666 /* record the glort, mask, and port count */
1667 hw->mac.dglort_map = dglort_map;
1668
1669 return 0;
1670}
1671
1672const struct fm10k_tlv_attr fm10k_update_pvid_msg_attr[] = {
1673 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_UPDATE_PVID),
1674 FM10K_TLV_ATTR_LAST
1675};
1676
1677/**
1678 * fm10k_msg_update_pvid_pf - Message handler for port VLAN message from SM
1679 * @hw: Pointer to hardware structure
1680 * @results: pointer array containing parsed data
1681 * @mbx: Pointer to mailbox information structure
1682 *
1683 * This handler configures the default VLAN for the PF
1684 **/
1685static s32 fm10k_msg_update_pvid_pf(struct fm10k_hw *hw, u32 **results,
1686 struct fm10k_mbx_info __always_unused *mbx)
1687{
1688 u16 glort, pvid;
1689 u32 pvid_update;
1690 s32 err;
1691
1692 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID],
1693 &pvid_update);
1694 if (err)
1695 return err;
1696
1697 /* extract values from the pvid update */
1698 glort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT);
1699 pvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID);
1700
1701 /* if glort is not valid return error */
1702 if (!fm10k_glort_valid_pf(hw, glort))
1703 return FM10K_ERR_PARAM;
1704
1705 /* verify VLAN ID is valid */
1706 if (pvid >= FM10K_VLAN_TABLE_VID_MAX)
1707 return FM10K_ERR_PARAM;
1708
1709 /* record the port VLAN ID value */
1710 hw->mac.default_vid = pvid;
1711
1712 return 0;
1713}
1714
1715/**
1716 * fm10k_record_global_table_data - Move global table data to swapi table info
1717 * @from: pointer to source table data structure
1718 * @to: pointer to destination table info structure
1719 *
1720 * This function is will copy table_data to the table_info contained in
1721 * the hw struct.
1722 **/
1723static void fm10k_record_global_table_data(struct fm10k_global_table_data *from,
1724 struct fm10k_swapi_table_info *to)
1725{
1726 /* convert from le32 struct to CPU byte ordered values */
1727 to->used = le32_to_cpu(from->used);
1728 to->avail = le32_to_cpu(from->avail);
1729}
1730
1731const struct fm10k_tlv_attr fm10k_err_msg_attr[] = {
1732 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR,
1733 sizeof(struct fm10k_swapi_error)),
1734 FM10K_TLV_ATTR_LAST
1735};
1736
1737/**
1738 * fm10k_msg_err_pf - Message handler for error reply
1739 * @hw: Pointer to hardware structure
1740 * @results: pointer array containing parsed data
1741 * @mbx: Pointer to mailbox information structure
1742 *
1743 * This handler will capture the data for any error replies to previous
1744 * messages that the PF has sent.
1745 **/
1746s32 fm10k_msg_err_pf(struct fm10k_hw *hw, u32 **results,
1747 struct fm10k_mbx_info __always_unused *mbx)
1748{
1749 struct fm10k_swapi_error err_msg;
1750 s32 err;
1751
1752 /* extract structure from message */
1753 err = fm10k_tlv_attr_get_le_struct(results[FM10K_PF_ATTR_ID_ERR],
1754 &err_msg, sizeof(err_msg));
1755 if (err)
1756 return err;
1757
1758 /* record table status */
1759 fm10k_record_global_table_data(&err_msg.mac, &hw->swapi.mac);
1760 fm10k_record_global_table_data(&err_msg.nexthop, &hw->swapi.nexthop);
1761 fm10k_record_global_table_data(&err_msg.ffu, &hw->swapi.ffu);
1762
1763 /* record SW API status value */
1764 hw->swapi.status = le32_to_cpu(err_msg.status);
1765
1766 return 0;
1767}
1768
1769static const struct fm10k_msg_data fm10k_msg_data_pf[] = {
1770 FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf),
1771 FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf),
1772 FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf),
1773 FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf),
1774 FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf),
1775 FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf),
1776 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
1777};
1778
1779static const struct fm10k_mac_ops mac_ops_pf = {
1780 .get_bus_info = fm10k_get_bus_info_generic,
1781 .reset_hw = fm10k_reset_hw_pf,
1782 .init_hw = fm10k_init_hw_pf,
1783 .start_hw = fm10k_start_hw_generic,
1784 .stop_hw = fm10k_stop_hw_generic,
1785 .update_vlan = fm10k_update_vlan_pf,
1786 .read_mac_addr = fm10k_read_mac_addr_pf,
1787 .update_uc_addr = fm10k_update_uc_addr_pf,
1788 .update_mc_addr = fm10k_update_mc_addr_pf,
1789 .update_xcast_mode = fm10k_update_xcast_mode_pf,
1790 .update_int_moderator = fm10k_update_int_moderator_pf,
1791 .update_lport_state = fm10k_update_lport_state_pf,
1792 .update_hw_stats = fm10k_update_hw_stats_pf,
1793 .rebind_hw_stats = fm10k_rebind_hw_stats_pf,
1794 .configure_dglort_map = fm10k_configure_dglort_map_pf,
1795 .set_dma_mask = fm10k_set_dma_mask_pf,
1796 .get_fault = fm10k_get_fault_pf,
1797 .get_host_state = fm10k_get_host_state_pf,
1798 .request_lport_map = fm10k_request_lport_map_pf,
1799};
1800
1801static const struct fm10k_iov_ops iov_ops_pf = {
1802 .assign_resources = fm10k_iov_assign_resources_pf,
1803 .configure_tc = fm10k_iov_configure_tc_pf,
1804 .assign_int_moderator = fm10k_iov_assign_int_moderator_pf,
1805 .assign_default_mac_vlan = fm10k_iov_assign_default_mac_vlan_pf,
1806 .reset_resources = fm10k_iov_reset_resources_pf,
1807 .set_lport = fm10k_iov_set_lport_pf,
1808 .reset_lport = fm10k_iov_reset_lport_pf,
1809 .update_stats = fm10k_iov_update_stats_pf,
1810};
1811
1812static s32 fm10k_get_invariants_pf(struct fm10k_hw *hw)
1813{
1814 fm10k_get_invariants_generic(hw);
1815
1816 return fm10k_sm_mbx_init(hw, &hw->mbx, fm10k_msg_data_pf);
1817}
1818
1819const struct fm10k_info fm10k_pf_info = {
1820 .mac = fm10k_mac_pf,
1821 .get_invariants = fm10k_get_invariants_pf,
1822 .mac_ops = &mac_ops_pf,
1823 .iov_ops = &iov_ops_pf,
1824};