Loading...
Note: File does not exist in v3.1.
1/*
2 * Copyright 2019-2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27#include "dm_services.h"
28#include "dc.h"
29
30#include "dcn301/dcn301_init.h"
31
32#include "resource.h"
33#include "include/irq_service_interface.h"
34#include "dcn30/dcn30_resource.h"
35#include "dcn301_resource.h"
36
37#include "dcn20/dcn20_resource.h"
38
39#include "dcn10/dcn10_ipp.h"
40#include "dcn301/dcn301_hubbub.h"
41#include "dcn30/dcn30_mpc.h"
42#include "dcn30/dcn30_hubp.h"
43#include "irq/dcn30/irq_service_dcn30.h"
44#include "dcn30/dcn30_dpp.h"
45#include "dcn301/dcn301_optc.h"
46#include "dcn20/dcn20_hwseq.h"
47#include "dcn30/dcn30_hwseq.h"
48#include "dce110/dce110_hwseq.h"
49#include "dcn30/dcn30_opp.h"
50#include "dcn20/dcn20_dsc.h"
51#include "dcn30/dcn30_vpg.h"
52#include "dcn30/dcn30_afmt.h"
53#include "dce/dce_clock_source.h"
54#include "dce/dce_audio.h"
55#include "dce/dce_hwseq.h"
56#include "clk_mgr.h"
57#include "virtual/virtual_stream_encoder.h"
58#include "dce110/dce110_resource.h"
59#include "dml/display_mode_vba.h"
60#include "dcn301/dcn301_dccg.h"
61#include "dcn10/dcn10_resource.h"
62#include "dcn30/dcn30_dio_stream_encoder.h"
63#include "dcn301/dcn301_dio_link_encoder.h"
64#include "dcn301/dcn301_panel_cntl.h"
65
66#include "vangogh_ip_offset.h"
67
68#include "dcn30/dcn30_dwb.h"
69#include "dcn30/dcn30_mmhubbub.h"
70
71#include "dcn/dcn_3_0_1_offset.h"
72#include "dcn/dcn_3_0_1_sh_mask.h"
73
74#include "nbio/nbio_7_2_0_offset.h"
75
76#include "dpcs/dpcs_3_0_0_offset.h"
77#include "dpcs/dpcs_3_0_0_sh_mask.h"
78
79#include "reg_helper.h"
80#include "dce/dmub_abm.h"
81#include "dce/dce_aux.h"
82#include "dce/dce_i2c.h"
83
84#include "dml/dcn30/dcn30_fpu.h"
85
86#include "dml/dcn30/display_mode_vba_30.h"
87#include "dml/dcn301/dcn301_fpu.h"
88#include "vm_helper.h"
89#include "dcn20/dcn20_vmid.h"
90#include "amdgpu_socbb.h"
91
92#define TO_DCN301_RES_POOL(pool)\
93 container_of(pool, struct dcn301_resource_pool, base)
94
95#define DC_LOGGER \
96 dc->ctx->logger
97#define DC_LOGGER_INIT(logger)
98
99enum dcn301_clk_src_array_id {
100 DCN301_CLK_SRC_PLL0,
101 DCN301_CLK_SRC_PLL1,
102 DCN301_CLK_SRC_PLL2,
103 DCN301_CLK_SRC_PLL3,
104 DCN301_CLK_SRC_TOTAL
105};
106
107/* begin *********************
108 * macros to expend register list macro defined in HW object header file
109 */
110
111/* DCN */
112#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
113
114#define BASE(seg) BASE_INNER(seg)
115
116#define SR(reg_name)\
117 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
118 mm ## reg_name
119
120#define SRI(reg_name, block, id)\
121 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
122 mm ## block ## id ## _ ## reg_name
123
124#define SRI2(reg_name, block, id)\
125 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
126 mm ## reg_name
127
128#define SRIR(var_name, reg_name, block, id)\
129 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
130 mm ## block ## id ## _ ## reg_name
131
132#define SRII(reg_name, block, id)\
133 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 mm ## block ## id ## _ ## reg_name
135
136#define SRII2(reg_name_pre, reg_name_post, id)\
137 .reg_name_pre ## _ ## reg_name_post[id] = BASE(mm ## reg_name_pre \
138 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
139 mm ## reg_name_pre ## id ## _ ## reg_name_post
140
141#define SRII_MPC_RMU(reg_name, block, id)\
142 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 mm ## block ## id ## _ ## reg_name
144
145#define SRII_DWB(reg_name, temp_name, block, id)\
146 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
147 mm ## block ## id ## _ ## temp_name
148
149#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
150 .field_name = reg_name ## __ ## field_name ## post_fix
151
152#define DCCG_SRII(reg_name, block, id)\
153 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 mm ## block ## id ## _ ## reg_name
155
156#define VUPDATE_SRII(reg_name, block, id)\
157 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
158 mm ## reg_name ## _ ## block ## id
159
160/* NBIO */
161#define NBIO_BASE_INNER(seg) \
162 NBIO_BASE__INST0_SEG ## seg
163
164#define NBIO_BASE(seg) \
165 NBIO_BASE_INNER(seg)
166
167#define NBIO_SR(reg_name)\
168 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
169 regBIF_BX0_ ## reg_name
170
171/* MMHUB */
172#define MMHUB_BASE_INNER(seg) \
173 MMHUB_BASE__INST0_SEG ## seg
174
175#define MMHUB_BASE(seg) \
176 MMHUB_BASE_INNER(seg)
177
178#define MMHUB_SR(reg_name)\
179 .reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \
180 regMM ## reg_name
181
182/* CLOCK */
183#define CLK_BASE_INNER(seg) \
184 CLK_BASE__INST0_SEG ## seg
185
186#define CLK_BASE(seg) \
187 CLK_BASE_INNER(seg)
188
189#define CLK_SRI(reg_name, block, inst)\
190 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
191 mm ## block ## _ ## inst ## _ ## reg_name
192
193static const struct bios_registers bios_regs = {
194 NBIO_SR(BIOS_SCRATCH_3),
195 NBIO_SR(BIOS_SCRATCH_6)
196};
197
198#define clk_src_regs(index, pllid)\
199[index] = {\
200 CS_COMMON_REG_LIST_DCN3_01(index, pllid),\
201}
202
203static const struct dce110_clk_src_regs clk_src_regs[] = {
204 clk_src_regs(0, A),
205 clk_src_regs(1, B),
206 clk_src_regs(2, C),
207 clk_src_regs(3, D)
208};
209
210static const struct dce110_clk_src_shift cs_shift = {
211 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
212};
213
214static const struct dce110_clk_src_mask cs_mask = {
215 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
216};
217
218#define abm_regs(id)\
219[id] = {\
220 ABM_DCN301_REG_LIST(id)\
221}
222
223static const struct dce_abm_registers abm_regs[] = {
224 abm_regs(0),
225 abm_regs(1),
226 abm_regs(2),
227 abm_regs(3),
228};
229
230static const struct dce_abm_shift abm_shift = {
231 ABM_MASK_SH_LIST_DCN30(__SHIFT)
232};
233
234static const struct dce_abm_mask abm_mask = {
235 ABM_MASK_SH_LIST_DCN30(_MASK)
236};
237
238#define audio_regs(id)\
239[id] = {\
240 AUD_COMMON_REG_LIST(id)\
241}
242
243static const struct dce_audio_registers audio_regs[] = {
244 audio_regs(0),
245 audio_regs(1),
246 audio_regs(2),
247 audio_regs(3),
248 audio_regs(4),
249 audio_regs(5),
250 audio_regs(6)
251};
252
253#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
254 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
255 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
256 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
257
258static const struct dce_audio_shift audio_shift = {
259 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
260};
261
262static const struct dce_audio_mask audio_mask = {
263 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
264};
265
266#define vpg_regs(id)\
267[id] = {\
268 VPG_DCN3_REG_LIST(id)\
269}
270
271static const struct dcn30_vpg_registers vpg_regs[] = {
272 vpg_regs(0),
273 vpg_regs(1),
274 vpg_regs(2),
275 vpg_regs(3),
276};
277
278static const struct dcn30_vpg_shift vpg_shift = {
279 DCN3_VPG_MASK_SH_LIST(__SHIFT)
280};
281
282static const struct dcn30_vpg_mask vpg_mask = {
283 DCN3_VPG_MASK_SH_LIST(_MASK)
284};
285
286#define afmt_regs(id)\
287[id] = {\
288 AFMT_DCN3_REG_LIST(id)\
289}
290
291static const struct dcn30_afmt_registers afmt_regs[] = {
292 afmt_regs(0),
293 afmt_regs(1),
294 afmt_regs(2),
295 afmt_regs(3),
296};
297
298static const struct dcn30_afmt_shift afmt_shift = {
299 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
300};
301
302static const struct dcn30_afmt_mask afmt_mask = {
303 DCN3_AFMT_MASK_SH_LIST(_MASK)
304};
305
306#define stream_enc_regs(id)\
307[id] = {\
308 SE_DCN3_REG_LIST(id)\
309}
310
311static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
312 stream_enc_regs(0),
313 stream_enc_regs(1),
314 stream_enc_regs(2),
315 stream_enc_regs(3),
316};
317
318static const struct dcn10_stream_encoder_shift se_shift = {
319 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
320};
321
322static const struct dcn10_stream_encoder_mask se_mask = {
323 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
324};
325
326
327#define aux_regs(id)\
328[id] = {\
329 DCN2_AUX_REG_LIST(id)\
330}
331
332static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
333 aux_regs(0),
334 aux_regs(1),
335 aux_regs(2),
336 aux_regs(3),
337};
338
339#define hpd_regs(id)\
340[id] = {\
341 HPD_REG_LIST(id)\
342}
343
344static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
345 hpd_regs(0),
346 hpd_regs(1),
347 hpd_regs(2),
348 hpd_regs(3),
349};
350
351
352#define link_regs(id, phyid)\
353[id] = {\
354 LE_DCN301_REG_LIST(id), \
355 UNIPHY_DCN2_REG_LIST(phyid), \
356 DPCS_DCN2_REG_LIST(id), \
357 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
358}
359
360static const struct dce110_aux_registers_shift aux_shift = {
361 DCN_AUX_MASK_SH_LIST(__SHIFT)
362};
363
364static const struct dce110_aux_registers_mask aux_mask = {
365 DCN_AUX_MASK_SH_LIST(_MASK)
366};
367
368static const struct dcn10_link_enc_registers link_enc_regs[] = {
369 link_regs(0, A),
370 link_regs(1, B),
371 link_regs(2, C),
372 link_regs(3, D),
373};
374
375static const struct dcn10_link_enc_shift le_shift = {
376 LINK_ENCODER_MASK_SH_LIST_DCN301(__SHIFT),\
377 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
378};
379
380static const struct dcn10_link_enc_mask le_mask = {
381 LINK_ENCODER_MASK_SH_LIST_DCN301(_MASK),\
382 DPCS_DCN2_MASK_SH_LIST(_MASK)
383};
384
385#define panel_cntl_regs(id)\
386[id] = {\
387 DCN301_PANEL_CNTL_REG_LIST(id),\
388}
389
390static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
391 panel_cntl_regs(0),
392 panel_cntl_regs(1),
393};
394
395static const struct dcn301_panel_cntl_shift panel_cntl_shift = {
396 DCN301_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
397};
398
399static const struct dcn301_panel_cntl_mask panel_cntl_mask = {
400 DCN301_PANEL_CNTL_MASK_SH_LIST(_MASK)
401};
402
403#define dpp_regs(id)\
404[id] = {\
405 DPP_REG_LIST_DCN30(id),\
406}
407
408static const struct dcn3_dpp_registers dpp_regs[] = {
409 dpp_regs(0),
410 dpp_regs(1),
411 dpp_regs(2),
412 dpp_regs(3),
413};
414
415static const struct dcn3_dpp_shift tf_shift = {
416 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
417};
418
419static const struct dcn3_dpp_mask tf_mask = {
420 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
421};
422
423#define opp_regs(id)\
424[id] = {\
425 OPP_REG_LIST_DCN30(id),\
426}
427
428static const struct dcn20_opp_registers opp_regs[] = {
429 opp_regs(0),
430 opp_regs(1),
431 opp_regs(2),
432 opp_regs(3),
433};
434
435static const struct dcn20_opp_shift opp_shift = {
436 OPP_MASK_SH_LIST_DCN20(__SHIFT)
437};
438
439static const struct dcn20_opp_mask opp_mask = {
440 OPP_MASK_SH_LIST_DCN20(_MASK)
441};
442
443#define aux_engine_regs(id)\
444[id] = {\
445 AUX_COMMON_REG_LIST0(id), \
446 .AUXN_IMPCAL = 0, \
447 .AUXP_IMPCAL = 0, \
448 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
449}
450
451static const struct dce110_aux_registers aux_engine_regs[] = {
452 aux_engine_regs(0),
453 aux_engine_regs(1),
454 aux_engine_regs(2),
455 aux_engine_regs(3),
456};
457
458#define dwbc_regs_dcn3(id)\
459[id] = {\
460 DWBC_COMMON_REG_LIST_DCN30(id),\
461}
462
463static const struct dcn30_dwbc_registers dwbc30_regs[] = {
464 dwbc_regs_dcn3(0),
465};
466
467static const struct dcn30_dwbc_shift dwbc30_shift = {
468 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
469};
470
471static const struct dcn30_dwbc_mask dwbc30_mask = {
472 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
473};
474
475#define mcif_wb_regs_dcn3(id)\
476[id] = {\
477 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
478}
479
480static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
481 mcif_wb_regs_dcn3(0)
482};
483
484static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
485 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
486};
487
488static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
489 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
490};
491
492#define dsc_regsDCN20(id)\
493[id] = {\
494 DSC_REG_LIST_DCN20(id)\
495}
496
497static const struct dcn20_dsc_registers dsc_regs[] = {
498 dsc_regsDCN20(0),
499 dsc_regsDCN20(1),
500 dsc_regsDCN20(2),
501};
502
503static const struct dcn20_dsc_shift dsc_shift = {
504 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
505};
506
507static const struct dcn20_dsc_mask dsc_mask = {
508 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
509};
510
511static const struct dcn30_mpc_registers mpc_regs = {
512 MPC_REG_LIST_DCN3_0(0),
513 MPC_REG_LIST_DCN3_0(1),
514 MPC_REG_LIST_DCN3_0(2),
515 MPC_REG_LIST_DCN3_0(3),
516 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
517 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
518 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
519 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
520 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
521 MPC_RMU_REG_LIST_DCN3AG(0),
522 MPC_RMU_REG_LIST_DCN3AG(1),
523 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
524};
525
526static const struct dcn30_mpc_shift mpc_shift = {
527 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
528};
529
530static const struct dcn30_mpc_mask mpc_mask = {
531 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
532};
533
534#define optc_regs(id)\
535[id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
536
537
538static const struct dcn_optc_registers optc_regs[] = {
539 optc_regs(0),
540 optc_regs(1),
541 optc_regs(2),
542 optc_regs(3),
543};
544
545static const struct dcn_optc_shift optc_shift = {
546 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
547};
548
549static const struct dcn_optc_mask optc_mask = {
550 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
551};
552
553#define hubp_regs(id)\
554[id] = {\
555 HUBP_REG_LIST_DCN30(id)\
556}
557
558static const struct dcn_hubp2_registers hubp_regs[] = {
559 hubp_regs(0),
560 hubp_regs(1),
561 hubp_regs(2),
562 hubp_regs(3),
563};
564
565static const struct dcn_hubp2_shift hubp_shift = {
566 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
567};
568
569static const struct dcn_hubp2_mask hubp_mask = {
570 HUBP_MASK_SH_LIST_DCN30(_MASK)
571};
572
573static const struct dcn_hubbub_registers hubbub_reg = {
574 HUBBUB_REG_LIST_DCN301(0)
575};
576
577static const struct dcn_hubbub_shift hubbub_shift = {
578 HUBBUB_MASK_SH_LIST_DCN301(__SHIFT)
579};
580
581static const struct dcn_hubbub_mask hubbub_mask = {
582 HUBBUB_MASK_SH_LIST_DCN301(_MASK)
583};
584
585static const struct dccg_registers dccg_regs = {
586 DCCG_REG_LIST_DCN301()
587};
588
589static const struct dccg_shift dccg_shift = {
590 DCCG_MASK_SH_LIST_DCN301(__SHIFT)
591};
592
593static const struct dccg_mask dccg_mask = {
594 DCCG_MASK_SH_LIST_DCN301(_MASK)
595};
596
597static const struct dce_hwseq_registers hwseq_reg = {
598 HWSEQ_DCN301_REG_LIST()
599};
600
601static const struct dce_hwseq_shift hwseq_shift = {
602 HWSEQ_DCN301_MASK_SH_LIST(__SHIFT)
603};
604
605static const struct dce_hwseq_mask hwseq_mask = {
606 HWSEQ_DCN301_MASK_SH_LIST(_MASK)
607};
608#define vmid_regs(id)\
609[id] = {\
610 DCN20_VMID_REG_LIST(id)\
611}
612
613static const struct dcn_vmid_registers vmid_regs[] = {
614 vmid_regs(0),
615 vmid_regs(1),
616 vmid_regs(2),
617 vmid_regs(3),
618 vmid_regs(4),
619 vmid_regs(5),
620 vmid_regs(6),
621 vmid_regs(7),
622 vmid_regs(8),
623 vmid_regs(9),
624 vmid_regs(10),
625 vmid_regs(11),
626 vmid_regs(12),
627 vmid_regs(13),
628 vmid_regs(14),
629 vmid_regs(15)
630};
631
632static const struct dcn20_vmid_shift vmid_shifts = {
633 DCN20_VMID_MASK_SH_LIST(__SHIFT)
634};
635
636static const struct dcn20_vmid_mask vmid_masks = {
637 DCN20_VMID_MASK_SH_LIST(_MASK)
638};
639
640static struct resource_caps res_cap_dcn301 = {
641 .num_timing_generator = 4,
642 .num_opp = 4,
643 .num_video_plane = 4,
644 .num_audio = 4,
645 .num_stream_encoder = 4,
646 .num_pll = 4,
647 .num_dwb = 1,
648 .num_ddc = 4,
649 .num_vmid = 16,
650 .num_mpc_3dlut = 2,
651 .num_dsc = 3,
652};
653
654static const struct dc_plane_cap plane_cap = {
655 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
656 .per_pixel_alpha = true,
657
658 .pixel_format_support = {
659 .argb8888 = true,
660 .nv12 = true,
661 .fp16 = true,
662 .p010 = true,
663 .ayuv = false,
664 },
665
666 .max_upscale_factor = {
667 .argb8888 = 16000,
668 .nv12 = 16000,
669 .fp16 = 16000
670 },
671
672 /* 6:1 downscaling ratio: 1000/6 = 166.666 */
673 .max_downscale_factor = {
674 .argb8888 = 167,
675 .nv12 = 167,
676 .fp16 = 167
677 },
678 64,
679 64
680};
681
682static const struct dc_debug_options debug_defaults_drv = {
683 .disable_dmcu = true,
684 .force_abm_enable = false,
685 .timing_trace = false,
686 .clock_trace = true,
687 .disable_dpp_power_gate = false,
688 .disable_hubp_power_gate = false,
689 .disable_clock_gate = true,
690 .disable_pplib_clock_request = true,
691 .disable_pplib_wm_range = true,
692 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
693 .force_single_disp_pipe_split = false,
694 .disable_dcc = DCC_ENABLE,
695 .vsr_support = true,
696 .performance_trace = false,
697 .max_downscale_src_width = 7680,/*upto 8K*/
698 .scl_reset_length10 = true,
699 .sanity_checks = false,
700 .underflow_assert_delay_us = 0xFFFFFFFF,
701 .dwb_fi_phase = -1, // -1 = disable
702 .dmub_command_table = true,
703 .use_max_lb = false,
704 .exit_idle_opt_for_cursor_updates = true,
705 .using_dml2 = false,
706};
707
708static void dcn301_dpp_destroy(struct dpp **dpp)
709{
710 kfree(TO_DCN20_DPP(*dpp));
711 *dpp = NULL;
712}
713
714static struct dpp *dcn301_dpp_create(struct dc_context *ctx, uint32_t inst)
715{
716 struct dcn3_dpp *dpp =
717 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
718
719 if (!dpp)
720 return NULL;
721
722 if (dpp3_construct(dpp, ctx, inst,
723 &dpp_regs[inst], &tf_shift, &tf_mask))
724 return &dpp->base;
725
726 BREAK_TO_DEBUGGER();
727 kfree(dpp);
728 return NULL;
729}
730static struct output_pixel_processor *dcn301_opp_create(struct dc_context *ctx,
731 uint32_t inst)
732{
733 struct dcn20_opp *opp =
734 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
735
736 if (!opp) {
737 BREAK_TO_DEBUGGER();
738 return NULL;
739 }
740
741 dcn20_opp_construct(opp, ctx, inst,
742 &opp_regs[inst], &opp_shift, &opp_mask);
743 return &opp->base;
744}
745
746static struct dce_aux *dcn301_aux_engine_create(struct dc_context *ctx, uint32_t inst)
747{
748 struct aux_engine_dce110 *aux_engine =
749 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
750
751 if (!aux_engine)
752 return NULL;
753
754 dce110_aux_engine_construct(aux_engine, ctx, inst,
755 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
756 &aux_engine_regs[inst],
757 &aux_mask,
758 &aux_shift,
759 ctx->dc->caps.extended_aux_timeout_support);
760
761 return &aux_engine->base;
762}
763#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
764
765static const struct dce_i2c_registers i2c_hw_regs[] = {
766 i2c_inst_regs(1),
767 i2c_inst_regs(2),
768 i2c_inst_regs(3),
769 i2c_inst_regs(4),
770};
771
772static const struct dce_i2c_shift i2c_shifts = {
773 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
774};
775
776static const struct dce_i2c_mask i2c_masks = {
777 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
778};
779
780static struct dce_i2c_hw *dcn301_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
781{
782 struct dce_i2c_hw *dce_i2c_hw =
783 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
784
785 if (!dce_i2c_hw)
786 return NULL;
787
788 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
789 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
790
791 return dce_i2c_hw;
792}
793static struct mpc *dcn301_mpc_create(
794 struct dc_context *ctx,
795 int num_mpcc,
796 int num_rmu)
797{
798 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
799 GFP_KERNEL);
800
801 if (!mpc30)
802 return NULL;
803
804 dcn30_mpc_construct(mpc30, ctx,
805 &mpc_regs,
806 &mpc_shift,
807 &mpc_mask,
808 num_mpcc,
809 num_rmu);
810
811 return &mpc30->base;
812}
813
814static struct hubbub *dcn301_hubbub_create(struct dc_context *ctx)
815{
816 int i;
817
818 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
819 GFP_KERNEL);
820
821 if (!hubbub3)
822 return NULL;
823
824 hubbub301_construct(hubbub3, ctx,
825 &hubbub_reg,
826 &hubbub_shift,
827 &hubbub_mask);
828
829
830 for (i = 0; i < res_cap_dcn301.num_vmid; i++) {
831 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
832
833 vmid->ctx = ctx;
834
835 vmid->regs = &vmid_regs[i];
836 vmid->shifts = &vmid_shifts;
837 vmid->masks = &vmid_masks;
838 }
839
840 hubbub3->num_vmid = res_cap_dcn301.num_vmid;
841
842 return &hubbub3->base;
843}
844
845static struct timing_generator *dcn301_timing_generator_create(
846 struct dc_context *ctx, uint32_t instance)
847{
848 struct optc *tgn10 =
849 kzalloc(sizeof(struct optc), GFP_KERNEL);
850
851 if (!tgn10)
852 return NULL;
853
854 tgn10->base.inst = instance;
855 tgn10->base.ctx = ctx;
856
857 tgn10->tg_regs = &optc_regs[instance];
858 tgn10->tg_shift = &optc_shift;
859 tgn10->tg_mask = &optc_mask;
860
861 dcn301_timing_generator_init(tgn10);
862
863 return &tgn10->base;
864}
865
866static const struct encoder_feature_support link_enc_feature = {
867 .max_hdmi_deep_color = COLOR_DEPTH_121212,
868 .max_hdmi_pixel_clock = 600000,
869 .hdmi_ycbcr420_supported = true,
870 .dp_ycbcr420_supported = true,
871 .fec_supported = true,
872 .flags.bits.IS_HBR2_CAPABLE = true,
873 .flags.bits.IS_HBR3_CAPABLE = true,
874 .flags.bits.IS_TPS3_CAPABLE = true,
875 .flags.bits.IS_TPS4_CAPABLE = true
876};
877
878static struct link_encoder *dcn301_link_encoder_create(
879 struct dc_context *ctx,
880 const struct encoder_init_data *enc_init_data)
881{
882 struct dcn20_link_encoder *enc20 =
883 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
884
885 if (!enc20)
886 return NULL;
887
888 dcn301_link_encoder_construct(enc20,
889 enc_init_data,
890 &link_enc_feature,
891 &link_enc_regs[enc_init_data->transmitter],
892 &link_enc_aux_regs[enc_init_data->channel - 1],
893 &link_enc_hpd_regs[enc_init_data->hpd_source],
894 &le_shift,
895 &le_mask);
896
897 return &enc20->enc10.base;
898}
899
900static struct panel_cntl *dcn301_panel_cntl_create(const struct panel_cntl_init_data *init_data)
901{
902 struct dcn301_panel_cntl *panel_cntl =
903 kzalloc(sizeof(struct dcn301_panel_cntl), GFP_KERNEL);
904
905 if (!panel_cntl)
906 return NULL;
907
908 dcn301_panel_cntl_construct(panel_cntl,
909 init_data,
910 &panel_cntl_regs[init_data->inst],
911 &panel_cntl_shift,
912 &panel_cntl_mask);
913
914 return &panel_cntl->base;
915}
916
917
918#define CTX ctx
919
920#define REG(reg_name) \
921 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
922
923static uint32_t read_pipe_fuses(struct dc_context *ctx)
924{
925 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
926 /* RV1 support max 4 pipes */
927 value = value & 0xf;
928 return value;
929}
930
931
932static void read_dce_straps(
933 struct dc_context *ctx,
934 struct resource_straps *straps)
935{
936 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
937 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
938
939}
940
941static struct audio *dcn301_create_audio(
942 struct dc_context *ctx, unsigned int inst)
943{
944 return dce_audio_create(ctx, inst,
945 &audio_regs[inst], &audio_shift, &audio_mask);
946}
947
948static struct vpg *dcn301_vpg_create(
949 struct dc_context *ctx,
950 uint32_t inst)
951{
952 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
953
954 if (!vpg3)
955 return NULL;
956
957 vpg3_construct(vpg3, ctx, inst,
958 &vpg_regs[inst],
959 &vpg_shift,
960 &vpg_mask);
961
962 return &vpg3->base;
963}
964
965static struct afmt *dcn301_afmt_create(
966 struct dc_context *ctx,
967 uint32_t inst)
968{
969 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
970
971 if (!afmt3)
972 return NULL;
973
974 afmt3_construct(afmt3, ctx, inst,
975 &afmt_regs[inst],
976 &afmt_shift,
977 &afmt_mask);
978
979 return &afmt3->base;
980}
981
982static struct stream_encoder *dcn301_stream_encoder_create(enum engine_id eng_id,
983 struct dc_context *ctx)
984{
985 struct dcn10_stream_encoder *enc1;
986 struct vpg *vpg;
987 struct afmt *afmt;
988 int vpg_inst;
989 int afmt_inst;
990
991 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
992 if (eng_id <= ENGINE_ID_DIGF) {
993 vpg_inst = eng_id;
994 afmt_inst = eng_id;
995 } else
996 return NULL;
997
998 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
999 vpg = dcn301_vpg_create(ctx, vpg_inst);
1000 afmt = dcn301_afmt_create(ctx, afmt_inst);
1001
1002 if (!enc1 || !vpg || !afmt || eng_id >= ARRAY_SIZE(stream_enc_regs)) {
1003 kfree(enc1);
1004 kfree(vpg);
1005 kfree(afmt);
1006 return NULL;
1007 }
1008
1009 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1010 eng_id, vpg, afmt,
1011 &stream_enc_regs[eng_id],
1012 &se_shift, &se_mask);
1013
1014 return &enc1->base;
1015}
1016
1017static struct dce_hwseq *dcn301_hwseq_create(struct dc_context *ctx)
1018{
1019 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1020
1021 if (hws) {
1022 hws->ctx = ctx;
1023 hws->regs = &hwseq_reg;
1024 hws->shifts = &hwseq_shift;
1025 hws->masks = &hwseq_mask;
1026 }
1027 return hws;
1028}
1029static const struct resource_create_funcs res_create_funcs = {
1030 .read_dce_straps = read_dce_straps,
1031 .create_audio = dcn301_create_audio,
1032 .create_stream_encoder = dcn301_stream_encoder_create,
1033 .create_hwseq = dcn301_hwseq_create,
1034};
1035
1036static void dcn301_destruct(struct dcn301_resource_pool *pool)
1037{
1038 unsigned int i;
1039
1040 for (i = 0; i < pool->base.stream_enc_count; i++) {
1041 if (pool->base.stream_enc[i] != NULL) {
1042 if (pool->base.stream_enc[i]->vpg != NULL) {
1043 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1044 pool->base.stream_enc[i]->vpg = NULL;
1045 }
1046 if (pool->base.stream_enc[i]->afmt != NULL) {
1047 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1048 pool->base.stream_enc[i]->afmt = NULL;
1049 }
1050 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1051 pool->base.stream_enc[i] = NULL;
1052 }
1053 }
1054
1055 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1056 if (pool->base.dscs[i] != NULL)
1057 dcn20_dsc_destroy(&pool->base.dscs[i]);
1058 }
1059
1060 if (pool->base.mpc != NULL) {
1061 kfree(TO_DCN20_MPC(pool->base.mpc));
1062 pool->base.mpc = NULL;
1063 }
1064 if (pool->base.hubbub != NULL) {
1065 kfree(pool->base.hubbub);
1066 pool->base.hubbub = NULL;
1067 }
1068 for (i = 0; i < pool->base.pipe_count; i++) {
1069 if (pool->base.dpps[i] != NULL)
1070 dcn301_dpp_destroy(&pool->base.dpps[i]);
1071
1072 if (pool->base.ipps[i] != NULL)
1073 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1074
1075 if (pool->base.hubps[i] != NULL) {
1076 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1077 pool->base.hubps[i] = NULL;
1078 }
1079
1080 if (pool->base.irqs != NULL) {
1081 dal_irq_service_destroy(&pool->base.irqs);
1082 }
1083 }
1084
1085 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1086 if (pool->base.engines[i] != NULL)
1087 dce110_engine_destroy(&pool->base.engines[i]);
1088 if (pool->base.hw_i2cs[i] != NULL) {
1089 kfree(pool->base.hw_i2cs[i]);
1090 pool->base.hw_i2cs[i] = NULL;
1091 }
1092 if (pool->base.sw_i2cs[i] != NULL) {
1093 kfree(pool->base.sw_i2cs[i]);
1094 pool->base.sw_i2cs[i] = NULL;
1095 }
1096 }
1097
1098 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1099 if (pool->base.opps[i] != NULL)
1100 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1101 }
1102
1103 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1104 if (pool->base.timing_generators[i] != NULL) {
1105 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1106 pool->base.timing_generators[i] = NULL;
1107 }
1108 }
1109
1110 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1111 if (pool->base.dwbc[i] != NULL) {
1112 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1113 pool->base.dwbc[i] = NULL;
1114 }
1115 if (pool->base.mcif_wb[i] != NULL) {
1116 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1117 pool->base.mcif_wb[i] = NULL;
1118 }
1119 }
1120
1121 for (i = 0; i < pool->base.audio_count; i++) {
1122 if (pool->base.audios[i])
1123 dce_aud_destroy(&pool->base.audios[i]);
1124 }
1125
1126 for (i = 0; i < pool->base.clk_src_count; i++) {
1127 if (pool->base.clock_sources[i] != NULL) {
1128 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1129 pool->base.clock_sources[i] = NULL;
1130 }
1131 }
1132
1133 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1134 if (pool->base.mpc_lut[i] != NULL) {
1135 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1136 pool->base.mpc_lut[i] = NULL;
1137 }
1138 if (pool->base.mpc_shaper[i] != NULL) {
1139 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1140 pool->base.mpc_shaper[i] = NULL;
1141 }
1142 }
1143
1144 if (pool->base.dp_clock_source != NULL) {
1145 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1146 pool->base.dp_clock_source = NULL;
1147 }
1148
1149 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1150 if (pool->base.multiple_abms[i] != NULL)
1151 dce_abm_destroy(&pool->base.multiple_abms[i]);
1152 }
1153
1154 if (pool->base.dccg != NULL)
1155 dcn_dccg_destroy(&pool->base.dccg);
1156}
1157
1158static struct hubp *dcn301_hubp_create(struct dc_context *ctx, uint32_t inst)
1159{
1160 struct dcn20_hubp *hubp2 =
1161 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1162
1163 if (!hubp2)
1164 return NULL;
1165
1166 if (hubp3_construct(hubp2, ctx, inst,
1167 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1168 return &hubp2->base;
1169
1170 BREAK_TO_DEBUGGER();
1171 kfree(hubp2);
1172 return NULL;
1173}
1174
1175static bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1176{
1177 int i;
1178 uint32_t pipe_count = pool->res_cap->num_dwb;
1179
1180 for (i = 0; i < pipe_count; i++) {
1181 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1182 GFP_KERNEL);
1183
1184 if (!dwbc30) {
1185 dm_error("DC: failed to create dwbc30!\n");
1186 return false;
1187 }
1188
1189 dcn30_dwbc_construct(dwbc30, ctx,
1190 &dwbc30_regs[i],
1191 &dwbc30_shift,
1192 &dwbc30_mask,
1193 i);
1194
1195 pool->dwbc[i] = &dwbc30->base;
1196 }
1197 return true;
1198}
1199
1200static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1201{
1202 int i;
1203 uint32_t pipe_count = pool->res_cap->num_dwb;
1204
1205 for (i = 0; i < pipe_count; i++) {
1206 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1207 GFP_KERNEL);
1208
1209 if (!mcif_wb30) {
1210 dm_error("DC: failed to create mcif_wb30!\n");
1211 return false;
1212 }
1213
1214 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1215 &mcif_wb30_regs[i],
1216 &mcif_wb30_shift,
1217 &mcif_wb30_mask,
1218 i);
1219
1220 pool->mcif_wb[i] = &mcif_wb30->base;
1221 }
1222 return true;
1223}
1224
1225static struct display_stream_compressor *dcn301_dsc_create(
1226 struct dc_context *ctx, uint32_t inst)
1227{
1228 struct dcn20_dsc *dsc =
1229 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1230
1231 if (!dsc) {
1232 BREAK_TO_DEBUGGER();
1233 return NULL;
1234 }
1235
1236 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1237 return &dsc->base;
1238}
1239
1240
1241static void dcn301_destroy_resource_pool(struct resource_pool **pool)
1242{
1243 struct dcn301_resource_pool *dcn301_pool = TO_DCN301_RES_POOL(*pool);
1244
1245 dcn301_destruct(dcn301_pool);
1246 kfree(dcn301_pool);
1247 *pool = NULL;
1248}
1249
1250static struct clock_source *dcn301_clock_source_create(
1251 struct dc_context *ctx,
1252 struct dc_bios *bios,
1253 enum clock_source_id id,
1254 const struct dce110_clk_src_regs *regs,
1255 bool dp_clk_src)
1256{
1257 struct dce110_clk_src *clk_src =
1258 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1259
1260 if (!clk_src)
1261 return NULL;
1262
1263 if (dcn301_clk_src_construct(clk_src, ctx, bios, id,
1264 regs, &cs_shift, &cs_mask)) {
1265 clk_src->base.dp_clk_src = dp_clk_src;
1266 return &clk_src->base;
1267 }
1268
1269 kfree(clk_src);
1270 BREAK_TO_DEBUGGER();
1271 return NULL;
1272}
1273
1274static struct dc_cap_funcs cap_funcs = {
1275 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1276};
1277
1278
1279static bool is_soc_bounding_box_valid(struct dc *dc)
1280{
1281 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1282
1283 if (ASICREV_IS_VANGOGH(hw_internal_rev))
1284 return true;
1285
1286 return false;
1287}
1288
1289static bool init_soc_bounding_box(struct dc *dc,
1290 struct dcn301_resource_pool *pool)
1291{
1292 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_01_soc;
1293 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_01_ip;
1294
1295 DC_LOGGER_INIT(dc->ctx->logger);
1296
1297 if (!is_soc_bounding_box_valid(dc)) {
1298 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1299 return false;
1300 }
1301
1302 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1303 loaded_ip->max_num_dpp = pool->base.pipe_count;
1304 DC_FP_START();
1305 dcn20_patch_bounding_box(dc, loaded_bb);
1306 DC_FP_END();
1307
1308 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1309 struct bp_soc_bb_info bb_info = {0};
1310
1311 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1312 DC_FP_START();
1313 dcn301_fpu_init_soc_bounding_box(bb_info);
1314 DC_FP_END();
1315 }
1316 }
1317
1318 return true;
1319}
1320
1321
1322static void set_wm_ranges(
1323 struct pp_smu_funcs *pp_smu,
1324 struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
1325{
1326 struct pp_smu_wm_range_sets ranges = {0};
1327 int i;
1328
1329 ranges.num_reader_wm_sets = 0;
1330
1331 if (loaded_bb->num_states == 1) {
1332 ranges.reader_wm_sets[0].wm_inst = 0;
1333 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1334 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1335 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1336 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1337
1338 ranges.num_reader_wm_sets = 1;
1339 } else if (loaded_bb->num_states > 1) {
1340 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
1341 ranges.reader_wm_sets[i].wm_inst = i;
1342 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1343 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1344 DC_FP_START();
1345 dcn301_fpu_set_wm_ranges(i, &ranges, loaded_bb);
1346 DC_FP_END();
1347 ranges.num_reader_wm_sets = i + 1;
1348 }
1349
1350 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1351 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1352 }
1353
1354 ranges.num_writer_wm_sets = 1;
1355
1356 ranges.writer_wm_sets[0].wm_inst = 0;
1357 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1358 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1359 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1360 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1361
1362 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1363 pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges);
1364}
1365
1366static void dcn301_calculate_wm_and_dlg(
1367 struct dc *dc, struct dc_state *context,
1368 display_e2e_pipe_params_st *pipes,
1369 int pipe_cnt,
1370 int vlevel)
1371{
1372 DC_FP_START();
1373 dcn301_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1374 DC_FP_END();
1375}
1376
1377static struct resource_funcs dcn301_res_pool_funcs = {
1378 .destroy = dcn301_destroy_resource_pool,
1379 .link_enc_create = dcn301_link_encoder_create,
1380 .panel_cntl_create = dcn301_panel_cntl_create,
1381 .validate_bandwidth = dcn30_validate_bandwidth,
1382 .calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg,
1383 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1384 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1385 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1386 .release_pipe = dcn20_release_pipe,
1387 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1388 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1389 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1390 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1391 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1392 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1393 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1394 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1395 .update_bw_bounding_box = dcn301_update_bw_bounding_box,
1396 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state
1397};
1398
1399static bool dcn301_resource_construct(
1400 uint8_t num_virtual_links,
1401 struct dc *dc,
1402 struct dcn301_resource_pool *pool)
1403{
1404 int i, j;
1405 struct dc_context *ctx = dc->ctx;
1406 struct irq_service_init_data init_data;
1407 uint32_t pipe_fuses = read_pipe_fuses(ctx);
1408 uint32_t num_pipes = 0;
1409
1410 DC_LOGGER_INIT(dc->ctx->logger);
1411
1412 ctx->dc_bios->regs = &bios_regs;
1413
1414 if (dc->ctx->asic_id.chip_id == DEVICE_ID_VGH_1435)
1415 res_cap_dcn301.num_pll = 2;
1416 pool->base.res_cap = &res_cap_dcn301;
1417
1418 pool->base.funcs = &dcn301_res_pool_funcs;
1419
1420 /*************************************************
1421 * Resource + asic cap harcoding *
1422 *************************************************/
1423 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1424 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1425 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1426 dc->caps.max_downscale_ratio = 600;
1427 dc->caps.i2c_speed_in_khz = 100;
1428 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a enabled by default*/
1429 dc->caps.max_cursor_size = 256;
1430 dc->caps.min_horizontal_blanking_period = 80;
1431 dc->caps.dmdata_alloc_size = 2048;
1432 dc->caps.max_slave_planes = 2;
1433 dc->caps.max_slave_yuv_planes = 2;
1434 dc->caps.max_slave_rgb_planes = 2;
1435 dc->caps.is_apu = true;
1436 dc->caps.post_blend_color_processing = true;
1437 dc->caps.force_dp_tps4_for_cp2520 = true;
1438 dc->caps.extended_aux_timeout_support = true;
1439 dc->caps.dmcub_support = true;
1440
1441 /* Color pipeline capabilities */
1442 dc->caps.color.dpp.dcn_arch = 1;
1443 dc->caps.color.dpp.input_lut_shared = 0;
1444 dc->caps.color.dpp.icsc = 1;
1445 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1446 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1447 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1448 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1449 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1450 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1451 dc->caps.color.dpp.post_csc = 1;
1452 dc->caps.color.dpp.gamma_corr = 1;
1453 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1454
1455 dc->caps.color.dpp.hw_3d_lut = 1;
1456 dc->caps.color.dpp.ogam_ram = 1;
1457 // no OGAM ROM on DCN301
1458 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1459 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1460 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1461 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1462 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1463 dc->caps.color.dpp.ocsc = 0;
1464
1465 dc->caps.color.mpc.gamut_remap = 1;
1466 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1467 dc->caps.color.mpc.ogam_ram = 1;
1468 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1469 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1470 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1471 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1472 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1473 dc->caps.color.mpc.ocsc = 1;
1474
1475 dc->caps.dp_hdmi21_pcon_support = true;
1476
1477 /* read VBIOS LTTPR caps */
1478 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1479 enum bp_result bp_query_result;
1480 uint8_t is_vbios_lttpr_enable = 0;
1481
1482 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1483 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1484 }
1485
1486 if (ctx->dc_bios->funcs->get_lttpr_interop) {
1487 enum bp_result bp_query_result;
1488 uint8_t is_vbios_interop_enabled = 0;
1489
1490 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled);
1491 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
1492 }
1493
1494 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1495 dc->debug = debug_defaults_drv;
1496
1497 // Init the vm_helper
1498 if (dc->vm_helper)
1499 vm_helper_init(dc->vm_helper, 16);
1500
1501 /*************************************************
1502 * Create resources *
1503 *************************************************/
1504
1505 /* Clock Sources for Pixel Clock*/
1506 pool->base.clock_sources[DCN301_CLK_SRC_PLL0] =
1507 dcn301_clock_source_create(ctx, ctx->dc_bios,
1508 CLOCK_SOURCE_COMBO_PHY_PLL0,
1509 &clk_src_regs[0], false);
1510 pool->base.clock_sources[DCN301_CLK_SRC_PLL1] =
1511 dcn301_clock_source_create(ctx, ctx->dc_bios,
1512 CLOCK_SOURCE_COMBO_PHY_PLL1,
1513 &clk_src_regs[1], false);
1514 pool->base.clock_sources[DCN301_CLK_SRC_PLL2] =
1515 dcn301_clock_source_create(ctx, ctx->dc_bios,
1516 CLOCK_SOURCE_COMBO_PHY_PLL2,
1517 &clk_src_regs[2], false);
1518 pool->base.clock_sources[DCN301_CLK_SRC_PLL3] =
1519 dcn301_clock_source_create(ctx, ctx->dc_bios,
1520 CLOCK_SOURCE_COMBO_PHY_PLL3,
1521 &clk_src_regs[3], false);
1522
1523 pool->base.clk_src_count = DCN301_CLK_SRC_TOTAL;
1524
1525 /* todo: not reuse phy_pll registers */
1526 pool->base.dp_clock_source =
1527 dcn301_clock_source_create(ctx, ctx->dc_bios,
1528 CLOCK_SOURCE_ID_DP_DTO,
1529 &clk_src_regs[0], true);
1530
1531 for (i = 0; i < pool->base.clk_src_count; i++) {
1532 if (pool->base.clock_sources[i] == NULL) {
1533 dm_error("DC: failed to create clock sources!\n");
1534 BREAK_TO_DEBUGGER();
1535 goto create_fail;
1536 }
1537 }
1538
1539 /* DCCG */
1540 pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1541 if (pool->base.dccg == NULL) {
1542 dm_error("DC: failed to create dccg!\n");
1543 BREAK_TO_DEBUGGER();
1544 goto create_fail;
1545 }
1546
1547 init_soc_bounding_box(dc, pool);
1548
1549 if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges)
1550 set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc);
1551
1552 num_pipes = dcn3_01_ip.max_num_dpp;
1553
1554 for (i = 0; i < dcn3_01_ip.max_num_dpp; i++)
1555 if (pipe_fuses & 1 << i)
1556 num_pipes--;
1557 dcn3_01_ip.max_num_dpp = num_pipes;
1558 dcn3_01_ip.max_num_otg = num_pipes;
1559
1560
1561 dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);
1562
1563 /* IRQ */
1564 init_data.ctx = dc->ctx;
1565 pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
1566 if (!pool->base.irqs)
1567 goto create_fail;
1568
1569 /* HUBBUB */
1570 pool->base.hubbub = dcn301_hubbub_create(ctx);
1571 if (pool->base.hubbub == NULL) {
1572 BREAK_TO_DEBUGGER();
1573 dm_error("DC: failed to create hubbub!\n");
1574 goto create_fail;
1575 }
1576
1577 j = 0;
1578 /* HUBPs, DPPs, OPPs and TGs */
1579 for (i = 0; i < pool->base.pipe_count; i++) {
1580
1581 /* if pipe is disabled, skip instance of HW pipe,
1582 * i.e, skip ASIC register instance
1583 */
1584 if ((pipe_fuses & (1 << i)) != 0) {
1585 DC_LOG_DEBUG("%s: fusing pipe %d\n", __func__, i);
1586 continue;
1587 }
1588
1589 pool->base.hubps[j] = dcn301_hubp_create(ctx, i);
1590 if (pool->base.hubps[j] == NULL) {
1591 BREAK_TO_DEBUGGER();
1592 dm_error(
1593 "DC: failed to create hubps!\n");
1594 goto create_fail;
1595 }
1596
1597 pool->base.dpps[j] = dcn301_dpp_create(ctx, i);
1598 if (pool->base.dpps[j] == NULL) {
1599 BREAK_TO_DEBUGGER();
1600 dm_error(
1601 "DC: failed to create dpps!\n");
1602 goto create_fail;
1603 }
1604
1605 pool->base.opps[j] = dcn301_opp_create(ctx, i);
1606 if (pool->base.opps[j] == NULL) {
1607 BREAK_TO_DEBUGGER();
1608 dm_error(
1609 "DC: failed to create output pixel processor!\n");
1610 goto create_fail;
1611 }
1612
1613 pool->base.timing_generators[j] = dcn301_timing_generator_create(ctx, i);
1614 if (pool->base.timing_generators[j] == NULL) {
1615 BREAK_TO_DEBUGGER();
1616 dm_error("DC: failed to create tg!\n");
1617 goto create_fail;
1618 }
1619 j++;
1620 }
1621 pool->base.timing_generator_count = j;
1622 pool->base.pipe_count = j;
1623 pool->base.mpcc_count = j;
1624
1625 /* ABM (or ABMs for NV2x) */
1626 /* TODO: */
1627 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1628 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
1629 &abm_regs[i],
1630 &abm_shift,
1631 &abm_mask);
1632 if (pool->base.multiple_abms[i] == NULL) {
1633 dm_error("DC: failed to create abm for pipe %d!\n", i);
1634 BREAK_TO_DEBUGGER();
1635 goto create_fail;
1636 }
1637 }
1638
1639 /* MPC and DSC */
1640 pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
1641 if (pool->base.mpc == NULL) {
1642 BREAK_TO_DEBUGGER();
1643 dm_error("DC: failed to create mpc!\n");
1644 goto create_fail;
1645 }
1646
1647 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1648 pool->base.dscs[i] = dcn301_dsc_create(ctx, i);
1649 if (pool->base.dscs[i] == NULL) {
1650 BREAK_TO_DEBUGGER();
1651 dm_error("DC: failed to create display stream compressor %d!\n", i);
1652 goto create_fail;
1653 }
1654 }
1655
1656 /* DWB and MMHUBBUB */
1657 if (!dcn301_dwbc_create(ctx, &pool->base)) {
1658 BREAK_TO_DEBUGGER();
1659 dm_error("DC: failed to create dwbc!\n");
1660 goto create_fail;
1661 }
1662
1663 if (!dcn301_mmhubbub_create(ctx, &pool->base)) {
1664 BREAK_TO_DEBUGGER();
1665 dm_error("DC: failed to create mcif_wb!\n");
1666 goto create_fail;
1667 }
1668
1669 /* AUX and I2C */
1670 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1671 pool->base.engines[i] = dcn301_aux_engine_create(ctx, i);
1672 if (pool->base.engines[i] == NULL) {
1673 BREAK_TO_DEBUGGER();
1674 dm_error(
1675 "DC:failed to create aux engine!!\n");
1676 goto create_fail;
1677 }
1678 pool->base.hw_i2cs[i] = dcn301_i2c_hw_create(ctx, i);
1679 if (pool->base.hw_i2cs[i] == NULL) {
1680 BREAK_TO_DEBUGGER();
1681 dm_error(
1682 "DC:failed to create hw i2c!!\n");
1683 goto create_fail;
1684 }
1685 pool->base.sw_i2cs[i] = NULL;
1686 }
1687
1688 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1689 if (!resource_construct(num_virtual_links, dc, &pool->base,
1690 &res_create_funcs))
1691 goto create_fail;
1692
1693 /* HW Sequencer and Plane caps */
1694 dcn301_hw_sequencer_construct(dc);
1695
1696 dc->caps.max_planes = pool->base.pipe_count;
1697
1698 for (i = 0; i < dc->caps.max_planes; ++i)
1699 dc->caps.planes[i] = plane_cap;
1700
1701 dc->cap_funcs = cap_funcs;
1702
1703 return true;
1704
1705create_fail:
1706
1707 dcn301_destruct(pool);
1708
1709 return false;
1710}
1711
1712struct resource_pool *dcn301_create_resource_pool(
1713 const struct dc_init_data *init_data,
1714 struct dc *dc)
1715{
1716 struct dcn301_resource_pool *pool =
1717 kzalloc(sizeof(struct dcn301_resource_pool), GFP_KERNEL);
1718
1719 if (!pool)
1720 return NULL;
1721
1722 if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool))
1723 return &pool->base;
1724
1725 BREAK_TO_DEBUGGER();
1726 kfree(pool);
1727 return NULL;
1728}