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1/*
2* Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
27#include "dc.h"
28
29#include "dcn10/dcn10_init.h"
30
31#include "resource.h"
32#include "include/irq_service_interface.h"
33#include "dcn10/dcn10_resource.h"
34#include "dcn10/dcn10_ipp.h"
35#include "dcn10/dcn10_mpc.h"
36
37#include "dcn10/dcn10_dwb.h"
38
39#include "irq/dcn10/irq_service_dcn10.h"
40#include "dcn10/dcn10_dpp.h"
41#include "dcn10/dcn10_optc.h"
42#include "dcn10/dcn10_hwseq.h"
43#include "dce110/dce110_hwseq.h"
44#include "dcn10/dcn10_opp.h"
45#include "dcn10/dcn10_link_encoder.h"
46#include "dcn10/dcn10_stream_encoder.h"
47#include "dce/dce_clock_source.h"
48#include "dce/dce_audio.h"
49#include "dce/dce_hwseq.h"
50#include "virtual/virtual_stream_encoder.h"
51#include "dce110/dce110_resource.h"
52#include "dce112/dce112_resource.h"
53#include "dcn10/dcn10_hubp.h"
54#include "dcn10/dcn10_hubbub.h"
55#include "dce/dce_panel_cntl.h"
56
57#include "soc15_hw_ip.h"
58#include "vega10_ip_offset.h"
59
60#include "dcn/dcn_1_0_offset.h"
61#include "dcn/dcn_1_0_sh_mask.h"
62
63#include "nbio/nbio_7_0_offset.h"
64
65#include "mmhub/mmhub_9_1_offset.h"
66#include "mmhub/mmhub_9_1_sh_mask.h"
67
68#include "reg_helper.h"
69#include "dce/dce_abm.h"
70#include "dce/dce_dmcu.h"
71#include "dce/dce_aux.h"
72#include "dce/dce_i2c.h"
73
74#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
75 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
76 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
77 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
78 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
79 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
80 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
81 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
82 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
83 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
84 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
85 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
86 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
87 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
88 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
89#endif
90
91
92enum dcn10_clk_src_array_id {
93 DCN10_CLK_SRC_PLL0,
94 DCN10_CLK_SRC_PLL1,
95 DCN10_CLK_SRC_PLL2,
96 DCN10_CLK_SRC_PLL3,
97 DCN10_CLK_SRC_TOTAL,
98 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
99};
100
101/* begin *********************
102 * macros to expend register list macro defined in HW object header file */
103
104/* DCN */
105#define BASE_INNER(seg) \
106 DCE_BASE__INST0_SEG ## seg
107
108#define BASE(seg) \
109 BASE_INNER(seg)
110
111#define SR(reg_name)\
112 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
113 mm ## reg_name
114
115#define SRI(reg_name, block, id)\
116 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
117 mm ## block ## id ## _ ## reg_name
118
119
120#define SRII(reg_name, block, id)\
121 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
122 mm ## block ## id ## _ ## reg_name
123
124#define VUPDATE_SRII(reg_name, block, id)\
125 .reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \
126 mm ## reg_name ## 0 ## _ ## block ## id
127
128/* set field/register/bitfield name */
129#define SFRB(field_name, reg_name, bitfield, post_fix)\
130 .field_name = reg_name ## __ ## bitfield ## post_fix
131
132/* NBIO */
133#define NBIO_BASE_INNER(seg) \
134 NBIF_BASE__INST0_SEG ## seg
135
136#define NBIO_BASE(seg) \
137 NBIO_BASE_INNER(seg)
138
139#define NBIO_SR(reg_name)\
140 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
141 mm ## reg_name
142
143/* MMHUB */
144#define MMHUB_BASE_INNER(seg) \
145 MMHUB_BASE__INST0_SEG ## seg
146
147#define MMHUB_BASE(seg) \
148 MMHUB_BASE_INNER(seg)
149
150#define MMHUB_SR(reg_name)\
151 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
152 mm ## reg_name
153
154/* macros to expend register list macro defined in HW object header file
155 * end *********************/
156
157
158static const struct dce_dmcu_registers dmcu_regs = {
159 DMCU_DCN10_REG_LIST()
160};
161
162static const struct dce_dmcu_shift dmcu_shift = {
163 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
164};
165
166static const struct dce_dmcu_mask dmcu_mask = {
167 DMCU_MASK_SH_LIST_DCN10(_MASK)
168};
169
170static const struct dce_abm_registers abm_regs = {
171 ABM_DCN10_REG_LIST(0)
172};
173
174static const struct dce_abm_shift abm_shift = {
175 ABM_MASK_SH_LIST_DCN10(__SHIFT)
176};
177
178static const struct dce_abm_mask abm_mask = {
179 ABM_MASK_SH_LIST_DCN10(_MASK)
180};
181
182#define stream_enc_regs(id)\
183[id] = {\
184 SE_DCN_REG_LIST(id)\
185}
186
187static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
188 stream_enc_regs(0),
189 stream_enc_regs(1),
190 stream_enc_regs(2),
191 stream_enc_regs(3),
192};
193
194static const struct dcn10_stream_encoder_shift se_shift = {
195 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
196};
197
198static const struct dcn10_stream_encoder_mask se_mask = {
199 SE_COMMON_MASK_SH_LIST_DCN10(_MASK)
200};
201
202#define audio_regs(id)\
203[id] = {\
204 AUD_COMMON_REG_LIST(id)\
205}
206
207static const struct dce_audio_registers audio_regs[] = {
208 audio_regs(0),
209 audio_regs(1),
210 audio_regs(2),
211 audio_regs(3),
212};
213
214#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
215 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
216 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
217 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
218
219static const struct dce_audio_shift audio_shift = {
220 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
221};
222
223static const struct dce_audio_mask audio_mask = {
224 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
225};
226
227#define aux_regs(id)\
228[id] = {\
229 AUX_REG_LIST(id)\
230}
231
232static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
233 aux_regs(0),
234 aux_regs(1),
235 aux_regs(2),
236 aux_regs(3)
237};
238
239#define hpd_regs(id)\
240[id] = {\
241 HPD_REG_LIST(id)\
242}
243
244static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
245 hpd_regs(0),
246 hpd_regs(1),
247 hpd_regs(2),
248 hpd_regs(3)
249};
250
251#define link_regs(id)\
252[id] = {\
253 LE_DCN10_REG_LIST(id), \
254 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
255}
256
257static const struct dcn10_link_enc_registers link_enc_regs[] = {
258 link_regs(0),
259 link_regs(1),
260 link_regs(2),
261 link_regs(3)
262};
263
264static const struct dcn10_link_enc_shift le_shift = {
265 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT)
266};
267
268static const struct dcn10_link_enc_mask le_mask = {
269 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
270};
271
272static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
273 { DCN_PANEL_CNTL_REG_LIST() }
274};
275
276static const struct dce_panel_cntl_shift panel_cntl_shift = {
277 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
278};
279
280static const struct dce_panel_cntl_mask panel_cntl_mask = {
281 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
282};
283
284static const struct dce110_aux_registers_shift aux_shift = {
285 DCN10_AUX_MASK_SH_LIST(__SHIFT)
286};
287
288static const struct dce110_aux_registers_mask aux_mask = {
289 DCN10_AUX_MASK_SH_LIST(_MASK)
290};
291
292#define ipp_regs(id)\
293[id] = {\
294 IPP_REG_LIST_DCN10(id),\
295}
296
297static const struct dcn10_ipp_registers ipp_regs[] = {
298 ipp_regs(0),
299 ipp_regs(1),
300 ipp_regs(2),
301 ipp_regs(3),
302};
303
304static const struct dcn10_ipp_shift ipp_shift = {
305 IPP_MASK_SH_LIST_DCN10(__SHIFT)
306};
307
308static const struct dcn10_ipp_mask ipp_mask = {
309 IPP_MASK_SH_LIST_DCN10(_MASK),
310};
311
312#define opp_regs(id)\
313[id] = {\
314 OPP_REG_LIST_DCN10(id),\
315}
316
317static const struct dcn10_opp_registers opp_regs[] = {
318 opp_regs(0),
319 opp_regs(1),
320 opp_regs(2),
321 opp_regs(3),
322};
323
324static const struct dcn10_opp_shift opp_shift = {
325 OPP_MASK_SH_LIST_DCN10(__SHIFT)
326};
327
328static const struct dcn10_opp_mask opp_mask = {
329 OPP_MASK_SH_LIST_DCN10(_MASK),
330};
331
332#define aux_engine_regs(id)\
333[id] = {\
334 AUX_COMMON_REG_LIST(id), \
335 .AUX_RESET_MASK = 0 \
336}
337
338static const struct dce110_aux_registers aux_engine_regs[] = {
339 aux_engine_regs(0),
340 aux_engine_regs(1),
341 aux_engine_regs(2),
342 aux_engine_regs(3),
343 aux_engine_regs(4),
344 aux_engine_regs(5)
345};
346
347#define tf_regs(id)\
348[id] = {\
349 TF_REG_LIST_DCN10(id),\
350}
351
352static const struct dcn_dpp_registers tf_regs[] = {
353 tf_regs(0),
354 tf_regs(1),
355 tf_regs(2),
356 tf_regs(3),
357};
358
359static const struct dcn_dpp_shift tf_shift = {
360 TF_REG_LIST_SH_MASK_DCN10(__SHIFT),
361 TF_DEBUG_REG_LIST_SH_DCN10
362
363};
364
365static const struct dcn_dpp_mask tf_mask = {
366 TF_REG_LIST_SH_MASK_DCN10(_MASK),
367 TF_DEBUG_REG_LIST_MASK_DCN10
368};
369
370static const struct dcn_mpc_registers mpc_regs = {
371 MPC_COMMON_REG_LIST_DCN1_0(0),
372 MPC_COMMON_REG_LIST_DCN1_0(1),
373 MPC_COMMON_REG_LIST_DCN1_0(2),
374 MPC_COMMON_REG_LIST_DCN1_0(3),
375 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0),
376 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1),
377 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2),
378 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3)
379};
380
381static const struct dcn_mpc_shift mpc_shift = {
382 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT),\
383 SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, __SHIFT)
384};
385
386static const struct dcn_mpc_mask mpc_mask = {
387 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),\
388 SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, _MASK)
389};
390
391#define tg_regs(id)\
392[id] = {TG_COMMON_REG_LIST_DCN1_0(id)}
393
394static const struct dcn_optc_registers tg_regs[] = {
395 tg_regs(0),
396 tg_regs(1),
397 tg_regs(2),
398 tg_regs(3),
399};
400
401static const struct dcn_optc_shift tg_shift = {
402 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
403};
404
405static const struct dcn_optc_mask tg_mask = {
406 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
407};
408
409static const struct bios_registers bios_regs = {
410 NBIO_SR(BIOS_SCRATCH_3),
411 NBIO_SR(BIOS_SCRATCH_6)
412};
413
414#define hubp_regs(id)\
415[id] = {\
416 HUBP_REG_LIST_DCN10(id)\
417}
418
419static const struct dcn_mi_registers hubp_regs[] = {
420 hubp_regs(0),
421 hubp_regs(1),
422 hubp_regs(2),
423 hubp_regs(3),
424};
425
426static const struct dcn_mi_shift hubp_shift = {
427 HUBP_MASK_SH_LIST_DCN10(__SHIFT)
428};
429
430static const struct dcn_mi_mask hubp_mask = {
431 HUBP_MASK_SH_LIST_DCN10(_MASK)
432};
433
434static const struct dcn_hubbub_registers hubbub_reg = {
435 HUBBUB_REG_LIST_DCN10(0)
436};
437
438static const struct dcn_hubbub_shift hubbub_shift = {
439 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT)
440};
441
442static const struct dcn_hubbub_mask hubbub_mask = {
443 HUBBUB_MASK_SH_LIST_DCN10(_MASK)
444};
445
446static int map_transmitter_id_to_phy_instance(
447 enum transmitter transmitter)
448{
449 switch (transmitter) {
450 case TRANSMITTER_UNIPHY_A:
451 return 0;
452 break;
453 case TRANSMITTER_UNIPHY_B:
454 return 1;
455 break;
456 case TRANSMITTER_UNIPHY_C:
457 return 2;
458 break;
459 case TRANSMITTER_UNIPHY_D:
460 return 3;
461 break;
462 default:
463 ASSERT(0);
464 return 0;
465 }
466}
467
468#define clk_src_regs(index, pllid)\
469[index] = {\
470 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\
471}
472
473static const struct dce110_clk_src_regs clk_src_regs[] = {
474 clk_src_regs(0, A),
475 clk_src_regs(1, B),
476 clk_src_regs(2, C),
477 clk_src_regs(3, D)
478};
479
480static const struct dce110_clk_src_shift cs_shift = {
481 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
482};
483
484static const struct dce110_clk_src_mask cs_mask = {
485 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
486};
487
488static const struct resource_caps res_cap = {
489 .num_timing_generator = 4,
490 .num_opp = 4,
491 .num_video_plane = 4,
492 .num_audio = 4,
493 .num_stream_encoder = 4,
494 .num_pll = 4,
495 .num_ddc = 4,
496};
497
498static const struct resource_caps rv2_res_cap = {
499 .num_timing_generator = 3,
500 .num_opp = 3,
501 .num_video_plane = 3,
502 .num_audio = 3,
503 .num_stream_encoder = 3,
504 .num_pll = 3,
505 .num_ddc = 4,
506};
507
508static const struct dc_plane_cap plane_cap = {
509 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
510 .per_pixel_alpha = true,
511
512 .pixel_format_support = {
513 .argb8888 = true,
514 .nv12 = true,
515 .fp16 = true,
516 .p010 = true
517 },
518
519 .max_upscale_factor = {
520 .argb8888 = 16000,
521 .nv12 = 16000,
522 .fp16 = 1
523 },
524
525 .max_downscale_factor = {
526 .argb8888 = 250,
527 .nv12 = 250,
528 .fp16 = 1
529 }
530};
531
532static const struct dc_debug_options debug_defaults_drv = {
533 .sanity_checks = true,
534 .disable_dmcu = false,
535 .force_abm_enable = false,
536 .timing_trace = false,
537 .clock_trace = true,
538
539 /* raven smu dones't allow 0 disp clk,
540 * smu min disp clk limit is 50Mhz
541 * keep min disp clk 100Mhz avoid smu hang
542 */
543 .min_disp_clk_khz = 100000,
544
545 .disable_pplib_clock_request = false,
546 .disable_pplib_wm_range = false,
547 .pplib_wm_report_mode = WM_REPORT_DEFAULT,
548 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
549 .force_single_disp_pipe_split = true,
550 .disable_dcc = DCC_ENABLE,
551 .voltage_align_fclk = true,
552 .disable_stereo_support = true,
553 .vsr_support = true,
554 .performance_trace = false,
555 .az_endpoint_mute_only = true,
556 .recovery_enabled = false, /*enable this by default after testing.*/
557 .max_downscale_src_width = 3840,
558 .underflow_assert_delay_us = 0xFFFFFFFF,
559 .enable_legacy_fast_update = true,
560 .using_dml2 = false,
561};
562
563static const struct dc_debug_options debug_defaults_diags = {
564 .disable_dmcu = false,
565 .force_abm_enable = false,
566 .timing_trace = true,
567 .clock_trace = true,
568 .disable_stutter = true,
569 .disable_pplib_clock_request = true,
570 .disable_pplib_wm_range = true,
571 .underflow_assert_delay_us = 0xFFFFFFFF,
572};
573
574static void dcn10_dpp_destroy(struct dpp **dpp)
575{
576 kfree(TO_DCN10_DPP(*dpp));
577 *dpp = NULL;
578}
579
580static struct dpp *dcn10_dpp_create(
581 struct dc_context *ctx,
582 uint32_t inst)
583{
584 struct dcn10_dpp *dpp =
585 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL);
586
587 if (!dpp)
588 return NULL;
589
590 dpp1_construct(dpp, ctx, inst,
591 &tf_regs[inst], &tf_shift, &tf_mask);
592 return &dpp->base;
593}
594
595static struct input_pixel_processor *dcn10_ipp_create(
596 struct dc_context *ctx, uint32_t inst)
597{
598 struct dcn10_ipp *ipp =
599 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
600
601 if (!ipp) {
602 BREAK_TO_DEBUGGER();
603 return NULL;
604 }
605
606 dcn10_ipp_construct(ipp, ctx, inst,
607 &ipp_regs[inst], &ipp_shift, &ipp_mask);
608 return &ipp->base;
609}
610
611
612static struct output_pixel_processor *dcn10_opp_create(
613 struct dc_context *ctx, uint32_t inst)
614{
615 struct dcn10_opp *opp =
616 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL);
617
618 if (!opp) {
619 BREAK_TO_DEBUGGER();
620 return NULL;
621 }
622
623 dcn10_opp_construct(opp, ctx, inst,
624 &opp_regs[inst], &opp_shift, &opp_mask);
625 return &opp->base;
626}
627
628static struct dce_aux *dcn10_aux_engine_create(struct dc_context *ctx,
629 uint32_t inst)
630{
631 struct aux_engine_dce110 *aux_engine =
632 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
633
634 if (!aux_engine)
635 return NULL;
636
637 dce110_aux_engine_construct(aux_engine, ctx, inst,
638 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
639 &aux_engine_regs[inst],
640 &aux_mask,
641 &aux_shift,
642 ctx->dc->caps.extended_aux_timeout_support);
643
644 return &aux_engine->base;
645}
646#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
647
648static const struct dce_i2c_registers i2c_hw_regs[] = {
649 i2c_inst_regs(1),
650 i2c_inst_regs(2),
651 i2c_inst_regs(3),
652 i2c_inst_regs(4),
653 i2c_inst_regs(5),
654 i2c_inst_regs(6),
655};
656
657static const struct dce_i2c_shift i2c_shifts = {
658 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
659};
660
661static const struct dce_i2c_mask i2c_masks = {
662 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
663};
664
665static struct dce_i2c_hw *dcn10_i2c_hw_create(struct dc_context *ctx,
666 uint32_t inst)
667{
668 struct dce_i2c_hw *dce_i2c_hw =
669 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
670
671 if (!dce_i2c_hw)
672 return NULL;
673
674 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst,
675 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
676
677 return dce_i2c_hw;
678}
679static struct mpc *dcn10_mpc_create(struct dc_context *ctx)
680{
681 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc),
682 GFP_KERNEL);
683
684 if (!mpc10)
685 return NULL;
686
687 dcn10_mpc_construct(mpc10, ctx,
688 &mpc_regs,
689 &mpc_shift,
690 &mpc_mask,
691 4);
692
693 return &mpc10->base;
694}
695
696static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx)
697{
698 struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub),
699 GFP_KERNEL);
700
701 if (!dcn10_hubbub)
702 return NULL;
703
704 hubbub1_construct(&dcn10_hubbub->base, ctx,
705 &hubbub_reg,
706 &hubbub_shift,
707 &hubbub_mask);
708
709 return &dcn10_hubbub->base;
710}
711
712static struct timing_generator *dcn10_timing_generator_create(
713 struct dc_context *ctx,
714 uint32_t instance)
715{
716 struct optc *tgn10 =
717 kzalloc(sizeof(struct optc), GFP_KERNEL);
718
719 if (!tgn10)
720 return NULL;
721
722 tgn10->base.inst = instance;
723 tgn10->base.ctx = ctx;
724
725 tgn10->tg_regs = &tg_regs[instance];
726 tgn10->tg_shift = &tg_shift;
727 tgn10->tg_mask = &tg_mask;
728
729 dcn10_timing_generator_init(tgn10);
730
731 return &tgn10->base;
732}
733
734static const struct encoder_feature_support link_enc_feature = {
735 .max_hdmi_deep_color = COLOR_DEPTH_121212,
736 .max_hdmi_pixel_clock = 600000,
737 .hdmi_ycbcr420_supported = true,
738 .dp_ycbcr420_supported = true,
739 .flags.bits.IS_HBR2_CAPABLE = true,
740 .flags.bits.IS_HBR3_CAPABLE = true,
741 .flags.bits.IS_TPS3_CAPABLE = true,
742 .flags.bits.IS_TPS4_CAPABLE = true
743};
744
745static struct link_encoder *dcn10_link_encoder_create(
746 struct dc_context *ctx,
747 const struct encoder_init_data *enc_init_data)
748{
749 struct dcn10_link_encoder *enc10 =
750 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL);
751 int link_regs_id;
752
753 if (!enc10)
754 return NULL;
755
756 link_regs_id =
757 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
758
759 dcn10_link_encoder_construct(enc10,
760 enc_init_data,
761 &link_enc_feature,
762 &link_enc_regs[link_regs_id],
763 &link_enc_aux_regs[enc_init_data->channel - 1],
764 &link_enc_hpd_regs[enc_init_data->hpd_source],
765 &le_shift,
766 &le_mask);
767
768 return &enc10->base;
769}
770
771static struct panel_cntl *dcn10_panel_cntl_create(const struct panel_cntl_init_data *init_data)
772{
773 struct dce_panel_cntl *panel_cntl =
774 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
775
776 if (!panel_cntl)
777 return NULL;
778
779 dce_panel_cntl_construct(panel_cntl,
780 init_data,
781 &panel_cntl_regs[init_data->inst],
782 &panel_cntl_shift,
783 &panel_cntl_mask);
784
785 return &panel_cntl->base;
786}
787
788static struct clock_source *dcn10_clock_source_create(
789 struct dc_context *ctx,
790 struct dc_bios *bios,
791 enum clock_source_id id,
792 const struct dce110_clk_src_regs *regs,
793 bool dp_clk_src)
794{
795 struct dce110_clk_src *clk_src =
796 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
797
798 if (!clk_src)
799 return NULL;
800
801 if (dce112_clk_src_construct(clk_src, ctx, bios, id,
802 regs, &cs_shift, &cs_mask)) {
803 clk_src->base.dp_clk_src = dp_clk_src;
804 return &clk_src->base;
805 }
806
807 kfree(clk_src);
808 BREAK_TO_DEBUGGER();
809 return NULL;
810}
811
812static void read_dce_straps(
813 struct dc_context *ctx,
814 struct resource_straps *straps)
815{
816 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
817 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
818}
819
820static struct audio *create_audio(
821 struct dc_context *ctx, unsigned int inst)
822{
823 return dce_audio_create(ctx, inst,
824 &audio_regs[inst], &audio_shift, &audio_mask);
825}
826
827static struct stream_encoder *dcn10_stream_encoder_create(
828 enum engine_id eng_id,
829 struct dc_context *ctx)
830{
831 struct dcn10_stream_encoder *enc1 =
832 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
833
834 if (!enc1)
835 return NULL;
836
837 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
838 &stream_enc_regs[eng_id],
839 &se_shift, &se_mask);
840 return &enc1->base;
841}
842
843static const struct dce_hwseq_registers hwseq_reg = {
844 HWSEQ_DCN1_REG_LIST()
845};
846
847static const struct dce_hwseq_shift hwseq_shift = {
848 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT)
849};
850
851static const struct dce_hwseq_mask hwseq_mask = {
852 HWSEQ_DCN1_MASK_SH_LIST(_MASK)
853};
854
855static struct dce_hwseq *dcn10_hwseq_create(
856 struct dc_context *ctx)
857{
858 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
859
860 if (hws) {
861 hws->ctx = ctx;
862 hws->regs = &hwseq_reg;
863 hws->shifts = &hwseq_shift;
864 hws->masks = &hwseq_mask;
865 hws->wa.DEGVIDCN10_253 = true;
866 hws->wa.false_optc_underflow = true;
867 hws->wa.DEGVIDCN10_254 = true;
868
869 if ((ctx->asic_id.chip_family == FAMILY_RV) &&
870 ASICREV_IS_RAVEN2(ctx->asic_id.hw_internal_rev))
871 switch (ctx->asic_id.pci_revision_id) {
872 case PRID_POLLOCK_94:
873 case PRID_POLLOCK_95:
874 case PRID_POLLOCK_E9:
875 case PRID_POLLOCK_EA:
876 case PRID_POLLOCK_EB:
877 hws->wa.wait_hubpret_read_start_during_mpo_transition = true;
878 break;
879 default:
880 hws->wa.wait_hubpret_read_start_during_mpo_transition = false;
881 break;
882 }
883 }
884 return hws;
885}
886
887static const struct resource_create_funcs res_create_funcs = {
888 .read_dce_straps = read_dce_straps,
889 .create_audio = create_audio,
890 .create_stream_encoder = dcn10_stream_encoder_create,
891 .create_hwseq = dcn10_hwseq_create,
892};
893
894static void dcn10_clock_source_destroy(struct clock_source **clk_src)
895{
896 kfree(TO_DCE110_CLK_SRC(*clk_src));
897 *clk_src = NULL;
898}
899
900static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx)
901{
902 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
903
904 if (!pp_smu)
905 return pp_smu;
906
907 dm_pp_get_funcs(ctx, pp_smu);
908 return pp_smu;
909}
910
911static void dcn10_resource_destruct(struct dcn10_resource_pool *pool)
912{
913 unsigned int i;
914
915 for (i = 0; i < pool->base.stream_enc_count; i++) {
916 if (pool->base.stream_enc[i] != NULL) {
917 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
918 pool->base.stream_enc[i] = NULL;
919 }
920 }
921
922 if (pool->base.mpc != NULL) {
923 kfree(TO_DCN10_MPC(pool->base.mpc));
924 pool->base.mpc = NULL;
925 }
926
927 kfree(pool->base.hubbub);
928 pool->base.hubbub = NULL;
929
930 for (i = 0; i < pool->base.pipe_count; i++) {
931 if (pool->base.opps[i] != NULL)
932 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
933
934 if (pool->base.dpps[i] != NULL)
935 dcn10_dpp_destroy(&pool->base.dpps[i]);
936
937 if (pool->base.ipps[i] != NULL)
938 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
939
940 if (pool->base.hubps[i] != NULL) {
941 kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
942 pool->base.hubps[i] = NULL;
943 }
944
945 if (pool->base.irqs != NULL) {
946 dal_irq_service_destroy(&pool->base.irqs);
947 }
948
949 if (pool->base.timing_generators[i] != NULL) {
950 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
951 pool->base.timing_generators[i] = NULL;
952 }
953 }
954
955 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
956 if (pool->base.engines[i] != NULL)
957 dce110_engine_destroy(&pool->base.engines[i]);
958 kfree(pool->base.hw_i2cs[i]);
959 pool->base.hw_i2cs[i] = NULL;
960 kfree(pool->base.sw_i2cs[i]);
961 pool->base.sw_i2cs[i] = NULL;
962 }
963
964 for (i = 0; i < pool->base.audio_count; i++) {
965 if (pool->base.audios[i])
966 dce_aud_destroy(&pool->base.audios[i]);
967 }
968
969 for (i = 0; i < pool->base.clk_src_count; i++) {
970 if (pool->base.clock_sources[i] != NULL) {
971 dcn10_clock_source_destroy(&pool->base.clock_sources[i]);
972 pool->base.clock_sources[i] = NULL;
973 }
974 }
975
976 if (pool->base.dp_clock_source != NULL) {
977 dcn10_clock_source_destroy(&pool->base.dp_clock_source);
978 pool->base.dp_clock_source = NULL;
979 }
980
981 if (pool->base.abm != NULL)
982 dce_abm_destroy(&pool->base.abm);
983
984 if (pool->base.dmcu != NULL)
985 dce_dmcu_destroy(&pool->base.dmcu);
986
987 kfree(pool->base.pp_smu);
988}
989
990static struct hubp *dcn10_hubp_create(
991 struct dc_context *ctx,
992 uint32_t inst)
993{
994 struct dcn10_hubp *hubp1 =
995 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL);
996
997 if (!hubp1)
998 return NULL;
999
1000 dcn10_hubp_construct(hubp1, ctx, inst,
1001 &hubp_regs[inst], &hubp_shift, &hubp_mask);
1002 return &hubp1->base;
1003}
1004
1005static void get_pixel_clock_parameters(
1006 const struct pipe_ctx *pipe_ctx,
1007 struct pixel_clk_params *pixel_clk_params)
1008{
1009 const struct dc_stream_state *stream = pipe_ctx->stream;
1010 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1011 pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1012 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1013 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1014 /* TODO: un-hardcode*/
1015 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1016 LINK_RATE_REF_FREQ_IN_KHZ;
1017 pixel_clk_params->flags.ENABLE_SS = 0;
1018 pixel_clk_params->color_depth =
1019 stream->timing.display_color_depth;
1020 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1021 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1022
1023 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1024 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1025
1026 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1027 pixel_clk_params->requested_pix_clk_100hz /= 2;
1028 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1029 pixel_clk_params->requested_pix_clk_100hz *= 2;
1030
1031}
1032
1033static void build_clamping_params(struct dc_stream_state *stream)
1034{
1035 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1036 stream->clamping.c_depth = stream->timing.display_color_depth;
1037 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1038}
1039
1040static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1041{
1042
1043 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1044
1045 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1046 pipe_ctx->clock_source,
1047 &pipe_ctx->stream_res.pix_clk_params,
1048 &pipe_ctx->pll_settings);
1049
1050 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1051
1052 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1053 &pipe_ctx->stream->bit_depth_params);
1054 build_clamping_params(pipe_ctx->stream);
1055}
1056
1057static enum dc_status build_mapped_resource(
1058 const struct dc *dc,
1059 struct dc_state *context,
1060 struct dc_stream_state *stream)
1061{
1062 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
1063
1064 if (!pipe_ctx)
1065 return DC_ERROR_UNEXPECTED;
1066
1067 build_pipe_hw_param(pipe_ctx);
1068 return DC_OK;
1069}
1070
1071static enum dc_status dcn10_add_stream_to_ctx(
1072 struct dc *dc,
1073 struct dc_state *new_ctx,
1074 struct dc_stream_state *dc_stream)
1075{
1076 enum dc_status result = DC_ERROR_UNEXPECTED;
1077
1078 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1079
1080 if (result == DC_OK)
1081 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1082
1083
1084 if (result == DC_OK)
1085 result = build_mapped_resource(dc, new_ctx, dc_stream);
1086
1087 return result;
1088}
1089
1090static struct pipe_ctx *dcn10_acquire_free_pipe_for_layer(
1091 const struct dc_state *cur_ctx,
1092 struct dc_state *new_ctx,
1093 const struct resource_pool *pool,
1094 const struct pipe_ctx *opp_head_pipe)
1095{
1096 struct resource_context *res_ctx = &new_ctx->res_ctx;
1097 struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream);
1098 struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe);
1099
1100 if (!head_pipe) {
1101 ASSERT(0);
1102 return NULL;
1103 }
1104
1105 if (!idle_pipe)
1106 return NULL;
1107
1108 idle_pipe->stream = head_pipe->stream;
1109 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
1110 idle_pipe->stream_res.abm = head_pipe->stream_res.abm;
1111 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
1112
1113 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
1114 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1115 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
1116 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
1117
1118 return idle_pipe;
1119}
1120
1121static bool dcn10_get_dcc_compression_cap(const struct dc *dc,
1122 const struct dc_dcc_surface_param *input,
1123 struct dc_surface_dcc_cap *output)
1124{
1125 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
1126 dc->res_pool->hubbub,
1127 input,
1128 output);
1129}
1130
1131static void dcn10_destroy_resource_pool(struct resource_pool **pool)
1132{
1133 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
1134
1135 dcn10_resource_destruct(dcn10_pool);
1136 kfree(dcn10_pool);
1137 *pool = NULL;
1138}
1139
1140static bool dcn10_validate_bandwidth(
1141 struct dc *dc,
1142 struct dc_state *context,
1143 bool fast_validate)
1144{
1145 bool voltage_supported;
1146
1147 DC_FP_START();
1148 voltage_supported = dcn_validate_bandwidth(dc, context, fast_validate);
1149 DC_FP_END();
1150
1151 return voltage_supported;
1152}
1153
1154static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
1155{
1156 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1157 && caps->max_video_width != 0
1158 && plane_state->src_rect.width > caps->max_video_width)
1159 return DC_FAIL_SURFACE_VALIDATE;
1160
1161 return DC_OK;
1162}
1163
1164static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context)
1165{
1166 int i, j;
1167 bool video_down_scaled = false;
1168 bool video_large = false;
1169 bool desktop_large = false;
1170 bool dcc_disabled = false;
1171 bool mpo_enabled = false;
1172
1173 for (i = 0; i < context->stream_count; i++) {
1174 if (context->stream_status[i].plane_count == 0)
1175 continue;
1176
1177 if (context->stream_status[i].plane_count > 2)
1178 return DC_FAIL_UNSUPPORTED_1;
1179
1180 if (context->stream_status[i].plane_count > 1)
1181 mpo_enabled = true;
1182
1183 for (j = 0; j < context->stream_status[i].plane_count; j++) {
1184 struct dc_plane_state *plane =
1185 context->stream_status[i].plane_states[j];
1186
1187
1188 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1189
1190 if (plane->src_rect.width > plane->dst_rect.width ||
1191 plane->src_rect.height > plane->dst_rect.height)
1192 video_down_scaled = true;
1193
1194 if (plane->src_rect.width >= 3840)
1195 video_large = true;
1196
1197 } else {
1198 if (plane->src_rect.width >= 3840)
1199 desktop_large = true;
1200 if (!plane->dcc.enable)
1201 dcc_disabled = true;
1202 }
1203 }
1204 }
1205
1206 /* Disable MPO in multi-display configurations. */
1207 if (context->stream_count > 1 && mpo_enabled)
1208 return DC_FAIL_UNSUPPORTED_1;
1209
1210 /*
1211 * Workaround: On DCN10 there is UMC issue that causes underflow when
1212 * playing 4k video on 4k desktop with video downscaled and single channel
1213 * memory
1214 */
1215 if (video_large && desktop_large && video_down_scaled && dcc_disabled &&
1216 dc->dcn_soc->number_of_channels == 1)
1217 return DC_FAIL_SURFACE_VALIDATE;
1218
1219 return DC_OK;
1220}
1221
1222static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1223{
1224 enum surface_pixel_format surf_pix_format = plane_state->format;
1225 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
1226
1227 enum swizzle_mode_values swizzle = DC_SW_LINEAR;
1228
1229 if (bpp == 64)
1230 swizzle = DC_SW_64KB_D;
1231 else
1232 swizzle = DC_SW_64KB_S;
1233
1234 plane_state->tiling_info.gfx9.swizzle = swizzle;
1235 return DC_OK;
1236}
1237
1238struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
1239 struct resource_context *res_ctx,
1240 const struct resource_pool *pool,
1241 struct dc_stream_state *stream)
1242{
1243 int i;
1244 int j = -1;
1245 struct dc_link *link = stream->link;
1246
1247 for (i = 0; i < pool->stream_enc_count; i++) {
1248 if (!res_ctx->is_stream_enc_acquired[i] &&
1249 pool->stream_enc[i]) {
1250 /* Store first available for MST second display
1251 * in daisy chain use case
1252 */
1253
1254 if (pool->stream_enc[i]->id != ENGINE_ID_VIRTUAL)
1255 j = i;
1256
1257 if (link->ep_type == DISPLAY_ENDPOINT_PHY && pool->stream_enc[i]->id ==
1258 link->link_enc->preferred_engine)
1259 return pool->stream_enc[i];
1260 }
1261 }
1262
1263 /*
1264 * For CZ and later, we can allow DIG FE and BE to differ for all display types
1265 */
1266
1267 if (j >= 0)
1268 return pool->stream_enc[j];
1269
1270 return NULL;
1271}
1272
1273static const struct dc_cap_funcs cap_funcs = {
1274 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap
1275};
1276
1277static const struct resource_funcs dcn10_res_pool_funcs = {
1278 .destroy = dcn10_destroy_resource_pool,
1279 .link_enc_create = dcn10_link_encoder_create,
1280 .panel_cntl_create = dcn10_panel_cntl_create,
1281 .validate_bandwidth = dcn10_validate_bandwidth,
1282 .acquire_free_pipe_as_secondary_dpp_pipe = dcn10_acquire_free_pipe_for_layer,
1283 .validate_plane = dcn10_validate_plane,
1284 .validate_global = dcn10_validate_global,
1285 .add_stream_to_ctx = dcn10_add_stream_to_ctx,
1286 .patch_unknown_plane_state = dcn10_patch_unknown_plane_state,
1287 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
1288};
1289
1290static uint32_t read_pipe_fuses(struct dc_context *ctx)
1291{
1292 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
1293 /* RV1 support max 4 pipes */
1294 value = value & 0xf;
1295 return value;
1296}
1297
1298static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks)
1299{
1300 int i;
1301
1302 if (clks->num_levels == 0)
1303 return false;
1304
1305 for (i = 0; i < clks->num_levels; i++)
1306 /* Ensure that the result is sane */
1307 if (clks->data[i].clocks_in_khz == 0)
1308 return false;
1309
1310 return true;
1311}
1312
1313static bool dcn10_resource_construct(
1314 uint8_t num_virtual_links,
1315 struct dc *dc,
1316 struct dcn10_resource_pool *pool)
1317{
1318 int i;
1319 int j;
1320 struct dc_context *ctx = dc->ctx;
1321 uint32_t pipe_fuses = read_pipe_fuses(ctx);
1322 struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0};
1323 int min_fclk_khz, min_dcfclk_khz, socclk_khz;
1324 bool res;
1325
1326 ctx->dc_bios->regs = &bios_regs;
1327
1328 if (ctx->dce_version == DCN_VERSION_1_01)
1329 pool->base.res_cap = &rv2_res_cap;
1330 else
1331 pool->base.res_cap = &res_cap;
1332 pool->base.funcs = &dcn10_res_pool_funcs;
1333
1334 /*
1335 * TODO fill in from actual raven resource when we create
1336 * more than virtual encoder
1337 */
1338
1339 /*************************************************
1340 * Resource + asic cap harcoding *
1341 *************************************************/
1342 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1343
1344 /* max pipe num for ASIC before check pipe fuses */
1345 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1346
1347 if (dc->ctx->dce_version == DCN_VERSION_1_01)
1348 pool->base.pipe_count = 3;
1349 dc->caps.max_video_width = 3840;
1350 dc->caps.max_downscale_ratio = 200;
1351 dc->caps.i2c_speed_in_khz = 100;
1352 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
1353 dc->caps.max_cursor_size = 256;
1354 dc->caps.min_horizontal_blanking_period = 80;
1355 dc->caps.max_slave_planes = 1;
1356 dc->caps.max_slave_yuv_planes = 1;
1357 dc->caps.max_slave_rgb_planes = 0;
1358 dc->caps.is_apu = true;
1359 dc->caps.post_blend_color_processing = false;
1360 dc->caps.extended_aux_timeout_support = false;
1361
1362 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */
1363 dc->caps.force_dp_tps4_for_cp2520 = true;
1364
1365 /* Color pipeline capabilities */
1366 dc->caps.color.dpp.dcn_arch = 1;
1367 dc->caps.color.dpp.input_lut_shared = 1;
1368 dc->caps.color.dpp.icsc = 1;
1369 dc->caps.color.dpp.dgam_ram = 1;
1370 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1371 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1372 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1373 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1374 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1375 dc->caps.color.dpp.post_csc = 0;
1376 dc->caps.color.dpp.gamma_corr = 0;
1377 dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1378
1379 dc->caps.color.dpp.hw_3d_lut = 0;
1380 dc->caps.color.dpp.ogam_ram = 1; // RGAM on DCN1
1381 dc->caps.color.dpp.ogam_rom_caps.srgb = 1;
1382 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 1;
1383 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1384 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1385 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1386 dc->caps.color.dpp.ocsc = 1;
1387
1388 /* no post-blend color operations */
1389 dc->caps.color.mpc.gamut_remap = 0;
1390 dc->caps.color.mpc.num_3dluts = 0;
1391 dc->caps.color.mpc.shared_3d_lut = 0;
1392 dc->caps.color.mpc.ogam_ram = 0;
1393 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1394 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1395 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1396 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1397 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1398 dc->caps.color.mpc.ocsc = 0;
1399
1400 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1401 dc->debug = debug_defaults_drv;
1402 else
1403 dc->debug = debug_defaults_diags;
1404
1405 /*************************************************
1406 * Create resources *
1407 *************************************************/
1408
1409 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] =
1410 dcn10_clock_source_create(ctx, ctx->dc_bios,
1411 CLOCK_SOURCE_COMBO_PHY_PLL0,
1412 &clk_src_regs[0], false);
1413 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] =
1414 dcn10_clock_source_create(ctx, ctx->dc_bios,
1415 CLOCK_SOURCE_COMBO_PHY_PLL1,
1416 &clk_src_regs[1], false);
1417 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] =
1418 dcn10_clock_source_create(ctx, ctx->dc_bios,
1419 CLOCK_SOURCE_COMBO_PHY_PLL2,
1420 &clk_src_regs[2], false);
1421
1422 if (dc->ctx->dce_version == DCN_VERSION_1_0) {
1423 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
1424 dcn10_clock_source_create(ctx, ctx->dc_bios,
1425 CLOCK_SOURCE_COMBO_PHY_PLL3,
1426 &clk_src_regs[3], false);
1427 }
1428
1429 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
1430
1431 if (dc->ctx->dce_version == DCN_VERSION_1_01)
1432 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
1433
1434 pool->base.dp_clock_source =
1435 dcn10_clock_source_create(ctx, ctx->dc_bios,
1436 CLOCK_SOURCE_ID_DP_DTO,
1437 /* todo: not reuse phy_pll registers */
1438 &clk_src_regs[0], true);
1439
1440 for (i = 0; i < pool->base.clk_src_count; i++) {
1441 if (pool->base.clock_sources[i] == NULL) {
1442 dm_error("DC: failed to create clock sources!\n");
1443 BREAK_TO_DEBUGGER();
1444 goto fail;
1445 }
1446 }
1447
1448 pool->base.dmcu = dcn10_dmcu_create(ctx,
1449 &dmcu_regs,
1450 &dmcu_shift,
1451 &dmcu_mask);
1452 if (pool->base.dmcu == NULL) {
1453 dm_error("DC: failed to create dmcu!\n");
1454 BREAK_TO_DEBUGGER();
1455 goto fail;
1456 }
1457
1458 pool->base.abm = dce_abm_create(ctx,
1459 &abm_regs,
1460 &abm_shift,
1461 &abm_mask);
1462 if (pool->base.abm == NULL) {
1463 dm_error("DC: failed to create abm!\n");
1464 BREAK_TO_DEBUGGER();
1465 goto fail;
1466 }
1467
1468 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1);
1469 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
1470 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
1471
1472 DC_FP_START();
1473 dcn10_resource_construct_fp(dc);
1474 DC_FP_END();
1475
1476 if (!dc->config.is_vmin_only_asic)
1477 if (ASICREV_IS_RAVEN2(dc->ctx->asic_id.hw_internal_rev))
1478 switch (dc->ctx->asic_id.pci_revision_id) {
1479 case PRID_DALI_DE:
1480 case PRID_DALI_DF:
1481 case PRID_DALI_E3:
1482 case PRID_DALI_E4:
1483 case PRID_POLLOCK_94:
1484 case PRID_POLLOCK_95:
1485 case PRID_POLLOCK_E9:
1486 case PRID_POLLOCK_EA:
1487 case PRID_POLLOCK_EB:
1488 dc->config.is_vmin_only_asic = true;
1489 break;
1490 default:
1491 break;
1492 }
1493
1494 pool->base.pp_smu = dcn10_pp_smu_create(ctx);
1495
1496 /*
1497 * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification *
1498 * implemented. So AZ D3 should work.For issue 197007. *
1499 */
1500 if (pool->base.pp_smu != NULL
1501 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL)
1502 dc->debug.az_endpoint_mute_only = false;
1503
1504
1505 if (!dc->debug.disable_pplib_clock_request) {
1506 /*
1507 * TODO: This is not the proper way to obtain
1508 * fabric_and_dram_bandwidth, should be min(fclk, memclk).
1509 */
1510 res = dm_pp_get_clock_levels_by_type_with_voltage(
1511 ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
1512
1513 DC_FP_START();
1514
1515 if (res)
1516 res = verify_clock_values(&fclks);
1517
1518 if (res)
1519 dcn_bw_update_from_pplib_fclks(dc, &fclks);
1520 else
1521 BREAK_TO_DEBUGGER();
1522
1523 DC_FP_END();
1524
1525 res = dm_pp_get_clock_levels_by_type_with_voltage(
1526 ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
1527
1528 DC_FP_START();
1529
1530 if (res)
1531 res = verify_clock_values(&dcfclks);
1532
1533 if (res)
1534 dcn_bw_update_from_pplib_dcfclks(dc, &dcfclks);
1535 else
1536 BREAK_TO_DEBUGGER();
1537
1538 DC_FP_END();
1539 }
1540
1541 dcn_bw_sync_calcs_and_dml(dc);
1542 if (!dc->debug.disable_pplib_wm_range) {
1543 dc->res_pool = &pool->base;
1544 DC_FP_START();
1545 dcn_get_soc_clks(
1546 dc, &min_fclk_khz, &min_dcfclk_khz, &socclk_khz);
1547 DC_FP_END();
1548 dcn_bw_notify_pplib_of_wm_ranges(
1549 dc, min_fclk_khz, min_dcfclk_khz, socclk_khz);
1550 }
1551
1552 {
1553 struct irq_service_init_data init_data;
1554 init_data.ctx = dc->ctx;
1555 pool->base.irqs = dal_irq_service_dcn10_create(&init_data);
1556 if (!pool->base.irqs)
1557 goto fail;
1558 }
1559
1560 /* index to valid pipe resource */
1561 j = 0;
1562 /* mem input -> ipp -> dpp -> opp -> TG */
1563 for (i = 0; i < pool->base.pipe_count; i++) {
1564 /* if pipe is disabled, skip instance of HW pipe,
1565 * i.e, skip ASIC register instance
1566 */
1567 if ((pipe_fuses & (1 << i)) != 0)
1568 continue;
1569
1570 pool->base.hubps[j] = dcn10_hubp_create(ctx, i);
1571 if (pool->base.hubps[j] == NULL) {
1572 BREAK_TO_DEBUGGER();
1573 dm_error(
1574 "DC: failed to create memory input!\n");
1575 goto fail;
1576 }
1577
1578 pool->base.ipps[j] = dcn10_ipp_create(ctx, i);
1579 if (pool->base.ipps[j] == NULL) {
1580 BREAK_TO_DEBUGGER();
1581 dm_error(
1582 "DC: failed to create input pixel processor!\n");
1583 goto fail;
1584 }
1585
1586 pool->base.dpps[j] = dcn10_dpp_create(ctx, i);
1587 if (pool->base.dpps[j] == NULL) {
1588 BREAK_TO_DEBUGGER();
1589 dm_error(
1590 "DC: failed to create dpp!\n");
1591 goto fail;
1592 }
1593
1594 pool->base.opps[j] = dcn10_opp_create(ctx, i);
1595 if (pool->base.opps[j] == NULL) {
1596 BREAK_TO_DEBUGGER();
1597 dm_error(
1598 "DC: failed to create output pixel processor!\n");
1599 goto fail;
1600 }
1601
1602 pool->base.timing_generators[j] = dcn10_timing_generator_create(
1603 ctx, i);
1604 if (pool->base.timing_generators[j] == NULL) {
1605 BREAK_TO_DEBUGGER();
1606 dm_error("DC: failed to create tg!\n");
1607 goto fail;
1608 }
1609 /* check next valid pipe */
1610 j++;
1611 }
1612
1613 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1614 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);
1615 if (pool->base.engines[i] == NULL) {
1616 BREAK_TO_DEBUGGER();
1617 dm_error(
1618 "DC:failed to create aux engine!!\n");
1619 goto fail;
1620 }
1621 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i);
1622 if (pool->base.hw_i2cs[i] == NULL) {
1623 BREAK_TO_DEBUGGER();
1624 dm_error(
1625 "DC:failed to create hw i2c!!\n");
1626 goto fail;
1627 }
1628 pool->base.sw_i2cs[i] = NULL;
1629 }
1630
1631 /* valid pipe num */
1632 pool->base.pipe_count = j;
1633 pool->base.timing_generator_count = j;
1634
1635 /* within dml lib, it is hard code to 4. If ASIC pipe is fused,
1636 * the value may be changed
1637 */
1638 dc->dml.ip.max_num_dpp = pool->base.pipe_count;
1639 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
1640
1641 pool->base.mpc = dcn10_mpc_create(ctx);
1642 if (pool->base.mpc == NULL) {
1643 BREAK_TO_DEBUGGER();
1644 dm_error("DC: failed to create mpc!\n");
1645 goto fail;
1646 }
1647
1648 pool->base.hubbub = dcn10_hubbub_create(ctx);
1649 if (pool->base.hubbub == NULL) {
1650 BREAK_TO_DEBUGGER();
1651 dm_error("DC: failed to create hubbub!\n");
1652 goto fail;
1653 }
1654
1655 if (!resource_construct(num_virtual_links, dc, &pool->base,
1656 &res_create_funcs))
1657 goto fail;
1658
1659 dcn10_hw_sequencer_construct(dc);
1660 dc->caps.max_planes = pool->base.pipe_count;
1661
1662 for (i = 0; i < dc->caps.max_planes; ++i)
1663 dc->caps.planes[i] = plane_cap;
1664
1665 dc->cap_funcs = cap_funcs;
1666
1667 return true;
1668
1669fail:
1670
1671 dcn10_resource_destruct(pool);
1672
1673 return false;
1674}
1675
1676struct resource_pool *dcn10_create_resource_pool(
1677 const struct dc_init_data *init_data,
1678 struct dc *dc)
1679{
1680 struct dcn10_resource_pool *pool =
1681 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL);
1682
1683 if (!pool)
1684 return NULL;
1685
1686 if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool))
1687 return &pool->base;
1688
1689 kfree(pool);
1690 BREAK_TO_DEBUGGER();
1691 return NULL;
1692}