1/*
  2 *  linux/arch/arm/common/gic.c
  3 *
  4 *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
  5 *
  6 * This program is free software; you can redistribute it and/or modify
  7 * it under the terms of the GNU General Public License version 2 as
  8 * published by the Free Software Foundation.
  9 *
 10 * Interrupt architecture for the GIC:
 11 *
 12 * o There is one Interrupt Distributor, which receives interrupts
 13 *   from system devices and sends them to the Interrupt Controllers.
 14 *
 15 * o There is one CPU Interface per CPU, which sends interrupts sent
 16 *   by the Distributor, and interrupts generated locally, to the
 17 *   associated CPU. The base address of the CPU interface is usually
 18 *   aliased so that the same address points to different chips depending
 19 *   on the CPU it is accessed from.
 20 *
 21 * Note that IRQs 0-31 are special - they are local to each CPU.
 22 * As such, the enable set/clear, pending set/clear and active bit
 23 * registers are banked per-cpu for these sources.
 24 */
 25#include <linux/init.h>
 26#include <linux/kernel.h>
 27#include <linux/list.h>
 28#include <linux/smp.h>
 29#include <linux/cpumask.h>
 30#include <linux/io.h>
 31
 32#include <asm/irq.h>
 33#include <asm/mach/irq.h>
 34#include <asm/hardware/gic.h>
 35
 36static DEFINE_SPINLOCK(irq_controller_lock);
 37
 38/* Address of GIC 0 CPU interface */
 39void __iomem *gic_cpu_base_addr __read_mostly;
 40
 41/*
 42 * Supported arch specific GIC irq extension.
 43 * Default make them NULL.
 44 */
 45struct irq_chip gic_arch_extn = {
 46	.irq_eoi	= NULL,
 47	.irq_mask	= NULL,
 48	.irq_unmask	= NULL,
 49	.irq_retrigger	= NULL,
 50	.irq_set_type	= NULL,
 51	.irq_set_wake	= NULL,
 52};
 53
 54#ifndef MAX_GIC_NR
 55#define MAX_GIC_NR	1
 56#endif
 57
 58static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
 59
 60static inline void __iomem *gic_dist_base(struct irq_data *d)
 61{
 62	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 63	return gic_data->dist_base;
 64}
 65
 66static inline void __iomem *gic_cpu_base(struct irq_data *d)
 67{
 68	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 69	return gic_data->cpu_base;
 70}
 71
 72static inline unsigned int gic_irq(struct irq_data *d)
 73{
 74	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 75	return d->irq - gic_data->irq_offset;
 76}
 77
 78/*
 79 * Routines to acknowledge, disable and enable interrupts
 80 */
 81static void gic_mask_irq(struct irq_data *d)
 82{
 83	u32 mask = 1 << (d->irq % 32);
 84
 85	spin_lock(&irq_controller_lock);
 86	writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
 87	if (gic_arch_extn.irq_mask)
 88		gic_arch_extn.irq_mask(d);
 89	spin_unlock(&irq_controller_lock);
 90}
 91
 92static void gic_unmask_irq(struct irq_data *d)
 93{
 94	u32 mask = 1 << (d->irq % 32);
 95
 96	spin_lock(&irq_controller_lock);
 97	if (gic_arch_extn.irq_unmask)
 98		gic_arch_extn.irq_unmask(d);
 99	writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
100	spin_unlock(&irq_controller_lock);
101}
102
103static void gic_eoi_irq(struct irq_data *d)
104{
105	if (gic_arch_extn.irq_eoi) {
106		spin_lock(&irq_controller_lock);
107		gic_arch_extn.irq_eoi(d);
108		spin_unlock(&irq_controller_lock);
109	}
110
111	writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
112}
113
114static int gic_set_type(struct irq_data *d, unsigned int type)
115{
116	void __iomem *base = gic_dist_base(d);
117	unsigned int gicirq = gic_irq(d);
118	u32 enablemask = 1 << (gicirq % 32);
119	u32 enableoff = (gicirq / 32) * 4;
120	u32 confmask = 0x2 << ((gicirq % 16) * 2);
121	u32 confoff = (gicirq / 16) * 4;
122	bool enabled = false;
123	u32 val;
124
125	/* Interrupt configuration for SGIs can't be changed */
126	if (gicirq < 16)
127		return -EINVAL;
128
129	if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
130		return -EINVAL;
131
132	spin_lock(&irq_controller_lock);
133
134	if (gic_arch_extn.irq_set_type)
135		gic_arch_extn.irq_set_type(d, type);
136
137	val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
138	if (type == IRQ_TYPE_LEVEL_HIGH)
139		val &= ~confmask;
140	else if (type == IRQ_TYPE_EDGE_RISING)
141		val |= confmask;
142
143	/*
144	 * As recommended by the spec, disable the interrupt before changing
145	 * the configuration
146	 */
147	if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
148		writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
149		enabled = true;
150	}
151
152	writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
153
154	if (enabled)
155		writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
156
157	spin_unlock(&irq_controller_lock);
158
159	return 0;
160}
161
162static int gic_retrigger(struct irq_data *d)
163{
164	if (gic_arch_extn.irq_retrigger)
165		return gic_arch_extn.irq_retrigger(d);
166
167	return -ENXIO;
168}
169
170#ifdef CONFIG_SMP
171static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
172			    bool force)
173{
174	void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
175	unsigned int shift = (d->irq % 4) * 8;
176	unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
177	u32 val, mask, bit;
178
179	if (cpu >= 8 || cpu >= nr_cpu_ids)
180		return -EINVAL;
181
182	mask = 0xff << shift;
183	bit = 1 << (cpu + shift);
184
185	spin_lock(&irq_controller_lock);
186	val = readl_relaxed(reg) & ~mask;
187	writel_relaxed(val | bit, reg);
188	spin_unlock(&irq_controller_lock);
189
190	return IRQ_SET_MASK_OK;
191}
192#endif
193
194#ifdef CONFIG_PM
195static int gic_set_wake(struct irq_data *d, unsigned int on)
196{
197	int ret = -ENXIO;
198
199	if (gic_arch_extn.irq_set_wake)
200		ret = gic_arch_extn.irq_set_wake(d, on);
201
202	return ret;
203}
204
205#else
206#define gic_set_wake	NULL
207#endif
208
209static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
210{
211	struct gic_chip_data *chip_data = irq_get_handler_data(irq);
212	struct irq_chip *chip = irq_get_chip(irq);
213	unsigned int cascade_irq, gic_irq;
214	unsigned long status;
215
216	chained_irq_enter(chip, desc);
217
218	spin_lock(&irq_controller_lock);
219	status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);
220	spin_unlock(&irq_controller_lock);
221
222	gic_irq = (status & 0x3ff);
223	if (gic_irq == 1023)
224		goto out;
225
226	cascade_irq = gic_irq + chip_data->irq_offset;
227	if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
228		do_bad_IRQ(cascade_irq, desc);
229	else
230		generic_handle_irq(cascade_irq);
231
232 out:
233	chained_irq_exit(chip, desc);
234}
235
236static struct irq_chip gic_chip = {
237	.name			= "GIC",
238	.irq_mask		= gic_mask_irq,
239	.irq_unmask		= gic_unmask_irq,
240	.irq_eoi		= gic_eoi_irq,
241	.irq_set_type		= gic_set_type,
242	.irq_retrigger		= gic_retrigger,
243#ifdef CONFIG_SMP
244	.irq_set_affinity	= gic_set_affinity,
245#endif
246	.irq_set_wake		= gic_set_wake,
247};
248
249void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
250{
251	if (gic_nr >= MAX_GIC_NR)
252		BUG();
253	if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
254		BUG();
255	irq_set_chained_handler(irq, gic_handle_cascade_irq);
256}
257
258static void __init gic_dist_init(struct gic_chip_data *gic,
259	unsigned int irq_start)
260{
261	unsigned int gic_irqs, irq_limit, i;
262	void __iomem *base = gic->dist_base;
263	u32 cpumask = 1 << smp_processor_id();
264
265	cpumask |= cpumask << 8;
266	cpumask |= cpumask << 16;
267
268	writel_relaxed(0, base + GIC_DIST_CTRL);
269
270	/*
271	 * Find out how many interrupts are supported.
272	 * The GIC only supports up to 1020 interrupt sources.
273	 */
274	gic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f;
275	gic_irqs = (gic_irqs + 1) * 32;
276	if (gic_irqs > 1020)
277		gic_irqs = 1020;
278
279	/*
280	 * Set all global interrupts to be level triggered, active low.
281	 */
282	for (i = 32; i < gic_irqs; i += 16)
283		writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
284
285	/*
286	 * Set all global interrupts to this CPU only.
287	 */
288	for (i = 32; i < gic_irqs; i += 4)
289		writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
290
291	/*
292	 * Set priority on all global interrupts.
293	 */
294	for (i = 32; i < gic_irqs; i += 4)
295		writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
296
297	/*
298	 * Disable all interrupts.  Leave the PPI and SGIs alone
299	 * as these enables are banked registers.
300	 */
301	for (i = 32; i < gic_irqs; i += 32)
302		writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
303
304	/*
305	 * Limit number of interrupts registered to the platform maximum
306	 */
307	irq_limit = gic->irq_offset + gic_irqs;
308	if (WARN_ON(irq_limit > NR_IRQS))
309		irq_limit = NR_IRQS;
310
311	/*
312	 * Setup the Linux IRQ subsystem.
313	 */
314	for (i = irq_start; i < irq_limit; i++) {
315		irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq);
316		irq_set_chip_data(i, gic);
317		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
318	}
319
320	writel_relaxed(1, base + GIC_DIST_CTRL);
321}
322
323static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
324{
325	void __iomem *dist_base = gic->dist_base;
326	void __iomem *base = gic->cpu_base;
327	int i;
328
329	/*
330	 * Deal with the banked PPI and SGI interrupts - disable all
331	 * PPI interrupts, ensure all SGI interrupts are enabled.
332	 */
333	writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
334	writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
335
336	/*
337	 * Set priority on PPI and SGI interrupts
338	 */
339	for (i = 0; i < 32; i += 4)
340		writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
341
342	writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
343	writel_relaxed(1, base + GIC_CPU_CTRL);
344}
345
346void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
347	void __iomem *dist_base, void __iomem *cpu_base)
348{
349	struct gic_chip_data *gic;
350
351	BUG_ON(gic_nr >= MAX_GIC_NR);
352
353	gic = &gic_data[gic_nr];
354	gic->dist_base = dist_base;
355	gic->cpu_base = cpu_base;
356	gic->irq_offset = (irq_start - 1) & ~31;
357
358	if (gic_nr == 0)
359		gic_cpu_base_addr = cpu_base;
360
361	gic_dist_init(gic, irq_start);
362	gic_cpu_init(gic);
363}
364
365void __cpuinit gic_secondary_init(unsigned int gic_nr)
366{
367	BUG_ON(gic_nr >= MAX_GIC_NR);
368
369	gic_cpu_init(&gic_data[gic_nr]);
370}
371
372void __cpuinit gic_enable_ppi(unsigned int irq)
373{
374	unsigned long flags;
375
376	local_irq_save(flags);
377	irq_set_status_flags(irq, IRQ_NOPROBE);
378	gic_unmask_irq(irq_get_irq_data(irq));
379	local_irq_restore(flags);
380}
381
382#ifdef CONFIG_SMP
383void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
384{
385	unsigned long map = *cpus_addr(*mask);
386
387	/*
388	 * Ensure that stores to Normal memory are visible to the
389	 * other CPUs before issuing the IPI.
390	 */
391	dsb();
392
393	/* this always happens on GIC0 */
394	writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
395}
396#endif