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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2016 Intel Corporation
4 */
5
6#include <linux/string_helpers.h>
7
8#include <drm/drm_print.h>
9
10#include "gem/i915_gem_context.h"
11#include "gem/i915_gem_internal.h"
12#include "gt/intel_gt_print.h"
13#include "gt/intel_gt_regs.h"
14
15#include "i915_cmd_parser.h"
16#include "i915_drv.h"
17#include "i915_irq.h"
18#include "i915_reg.h"
19#include "intel_breadcrumbs.h"
20#include "intel_context.h"
21#include "intel_engine.h"
22#include "intel_engine_pm.h"
23#include "intel_engine_regs.h"
24#include "intel_engine_user.h"
25#include "intel_execlists_submission.h"
26#include "intel_gt.h"
27#include "intel_gt_mcr.h"
28#include "intel_gt_pm.h"
29#include "intel_gt_requests.h"
30#include "intel_lrc.h"
31#include "intel_lrc_reg.h"
32#include "intel_reset.h"
33#include "intel_ring.h"
34#include "uc/intel_guc_submission.h"
35
36/* Haswell does have the CXT_SIZE register however it does not appear to be
37 * valid. Now, docs explain in dwords what is in the context object. The full
38 * size is 70720 bytes, however, the power context and execlist context will
39 * never be saved (power context is stored elsewhere, and execlists don't work
40 * on HSW) - so the final size, including the extra state required for the
41 * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
42 */
43#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
44
45#define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
46#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
47#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
48#define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE)
49
50#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
51
52#define MAX_MMIO_BASES 3
53struct engine_info {
54 u8 class;
55 u8 instance;
56 /* mmio bases table *must* be sorted in reverse graphics_ver order */
57 struct engine_mmio_base {
58 u32 graphics_ver : 8;
59 u32 base : 24;
60 } mmio_bases[MAX_MMIO_BASES];
61};
62
63static const struct engine_info intel_engines[] = {
64 [RCS0] = {
65 .class = RENDER_CLASS,
66 .instance = 0,
67 .mmio_bases = {
68 { .graphics_ver = 1, .base = RENDER_RING_BASE }
69 },
70 },
71 [BCS0] = {
72 .class = COPY_ENGINE_CLASS,
73 .instance = 0,
74 .mmio_bases = {
75 { .graphics_ver = 6, .base = BLT_RING_BASE }
76 },
77 },
78 [BCS1] = {
79 .class = COPY_ENGINE_CLASS,
80 .instance = 1,
81 .mmio_bases = {
82 { .graphics_ver = 12, .base = XEHPC_BCS1_RING_BASE }
83 },
84 },
85 [BCS2] = {
86 .class = COPY_ENGINE_CLASS,
87 .instance = 2,
88 .mmio_bases = {
89 { .graphics_ver = 12, .base = XEHPC_BCS2_RING_BASE }
90 },
91 },
92 [BCS3] = {
93 .class = COPY_ENGINE_CLASS,
94 .instance = 3,
95 .mmio_bases = {
96 { .graphics_ver = 12, .base = XEHPC_BCS3_RING_BASE }
97 },
98 },
99 [BCS4] = {
100 .class = COPY_ENGINE_CLASS,
101 .instance = 4,
102 .mmio_bases = {
103 { .graphics_ver = 12, .base = XEHPC_BCS4_RING_BASE }
104 },
105 },
106 [BCS5] = {
107 .class = COPY_ENGINE_CLASS,
108 .instance = 5,
109 .mmio_bases = {
110 { .graphics_ver = 12, .base = XEHPC_BCS5_RING_BASE }
111 },
112 },
113 [BCS6] = {
114 .class = COPY_ENGINE_CLASS,
115 .instance = 6,
116 .mmio_bases = {
117 { .graphics_ver = 12, .base = XEHPC_BCS6_RING_BASE }
118 },
119 },
120 [BCS7] = {
121 .class = COPY_ENGINE_CLASS,
122 .instance = 7,
123 .mmio_bases = {
124 { .graphics_ver = 12, .base = XEHPC_BCS7_RING_BASE }
125 },
126 },
127 [BCS8] = {
128 .class = COPY_ENGINE_CLASS,
129 .instance = 8,
130 .mmio_bases = {
131 { .graphics_ver = 12, .base = XEHPC_BCS8_RING_BASE }
132 },
133 },
134 [VCS0] = {
135 .class = VIDEO_DECODE_CLASS,
136 .instance = 0,
137 .mmio_bases = {
138 { .graphics_ver = 11, .base = GEN11_BSD_RING_BASE },
139 { .graphics_ver = 6, .base = GEN6_BSD_RING_BASE },
140 { .graphics_ver = 4, .base = BSD_RING_BASE }
141 },
142 },
143 [VCS1] = {
144 .class = VIDEO_DECODE_CLASS,
145 .instance = 1,
146 .mmio_bases = {
147 { .graphics_ver = 11, .base = GEN11_BSD2_RING_BASE },
148 { .graphics_ver = 8, .base = GEN8_BSD2_RING_BASE }
149 },
150 },
151 [VCS2] = {
152 .class = VIDEO_DECODE_CLASS,
153 .instance = 2,
154 .mmio_bases = {
155 { .graphics_ver = 11, .base = GEN11_BSD3_RING_BASE }
156 },
157 },
158 [VCS3] = {
159 .class = VIDEO_DECODE_CLASS,
160 .instance = 3,
161 .mmio_bases = {
162 { .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE }
163 },
164 },
165 [VCS4] = {
166 .class = VIDEO_DECODE_CLASS,
167 .instance = 4,
168 .mmio_bases = {
169 { .graphics_ver = 12, .base = XEHP_BSD5_RING_BASE }
170 },
171 },
172 [VCS5] = {
173 .class = VIDEO_DECODE_CLASS,
174 .instance = 5,
175 .mmio_bases = {
176 { .graphics_ver = 12, .base = XEHP_BSD6_RING_BASE }
177 },
178 },
179 [VCS6] = {
180 .class = VIDEO_DECODE_CLASS,
181 .instance = 6,
182 .mmio_bases = {
183 { .graphics_ver = 12, .base = XEHP_BSD7_RING_BASE }
184 },
185 },
186 [VCS7] = {
187 .class = VIDEO_DECODE_CLASS,
188 .instance = 7,
189 .mmio_bases = {
190 { .graphics_ver = 12, .base = XEHP_BSD8_RING_BASE }
191 },
192 },
193 [VECS0] = {
194 .class = VIDEO_ENHANCEMENT_CLASS,
195 .instance = 0,
196 .mmio_bases = {
197 { .graphics_ver = 11, .base = GEN11_VEBOX_RING_BASE },
198 { .graphics_ver = 7, .base = VEBOX_RING_BASE }
199 },
200 },
201 [VECS1] = {
202 .class = VIDEO_ENHANCEMENT_CLASS,
203 .instance = 1,
204 .mmio_bases = {
205 { .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE }
206 },
207 },
208 [VECS2] = {
209 .class = VIDEO_ENHANCEMENT_CLASS,
210 .instance = 2,
211 .mmio_bases = {
212 { .graphics_ver = 12, .base = XEHP_VEBOX3_RING_BASE }
213 },
214 },
215 [VECS3] = {
216 .class = VIDEO_ENHANCEMENT_CLASS,
217 .instance = 3,
218 .mmio_bases = {
219 { .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }
220 },
221 },
222 [CCS0] = {
223 .class = COMPUTE_CLASS,
224 .instance = 0,
225 .mmio_bases = {
226 { .graphics_ver = 12, .base = GEN12_COMPUTE0_RING_BASE }
227 }
228 },
229 [CCS1] = {
230 .class = COMPUTE_CLASS,
231 .instance = 1,
232 .mmio_bases = {
233 { .graphics_ver = 12, .base = GEN12_COMPUTE1_RING_BASE }
234 }
235 },
236 [CCS2] = {
237 .class = COMPUTE_CLASS,
238 .instance = 2,
239 .mmio_bases = {
240 { .graphics_ver = 12, .base = GEN12_COMPUTE2_RING_BASE }
241 }
242 },
243 [CCS3] = {
244 .class = COMPUTE_CLASS,
245 .instance = 3,
246 .mmio_bases = {
247 { .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
248 }
249 },
250 [GSC0] = {
251 .class = OTHER_CLASS,
252 .instance = OTHER_GSC_INSTANCE,
253 .mmio_bases = {
254 { .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
255 }
256 },
257};
258
259/**
260 * intel_engine_context_size() - return the size of the context for an engine
261 * @gt: the gt
262 * @class: engine class
263 *
264 * Each engine class may require a different amount of space for a context
265 * image.
266 *
267 * Return: size (in bytes) of an engine class specific context image
268 *
269 * Note: this size includes the HWSP, which is part of the context image
270 * in LRC mode, but does not include the "shared data page" used with
271 * GuC submission. The caller should account for this if using the GuC.
272 */
273u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
274{
275 struct intel_uncore *uncore = gt->uncore;
276 u32 cxt_size;
277
278 BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
279
280 switch (class) {
281 case COMPUTE_CLASS:
282 fallthrough;
283 case RENDER_CLASS:
284 switch (GRAPHICS_VER(gt->i915)) {
285 default:
286 MISSING_CASE(GRAPHICS_VER(gt->i915));
287 return DEFAULT_LR_CONTEXT_RENDER_SIZE;
288 case 12:
289 case 11:
290 return GEN11_LR_CONTEXT_RENDER_SIZE;
291 case 9:
292 return GEN9_LR_CONTEXT_RENDER_SIZE;
293 case 8:
294 return GEN8_LR_CONTEXT_RENDER_SIZE;
295 case 7:
296 if (IS_HASWELL(gt->i915))
297 return HSW_CXT_TOTAL_SIZE;
298
299 cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE);
300 return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
301 PAGE_SIZE);
302 case 6:
303 cxt_size = intel_uncore_read(uncore, CXT_SIZE);
304 return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
305 PAGE_SIZE);
306 case 5:
307 case 4:
308 /*
309 * There is a discrepancy here between the size reported
310 * by the register and the size of the context layout
311 * in the docs. Both are described as authorative!
312 *
313 * The discrepancy is on the order of a few cachelines,
314 * but the total is under one page (4k), which is our
315 * minimum allocation anyway so it should all come
316 * out in the wash.
317 */
318 cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
319 gt_dbg(gt, "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n",
320 GRAPHICS_VER(gt->i915), cxt_size * 64,
321 cxt_size - 1);
322 return round_up(cxt_size * 64, PAGE_SIZE);
323 case 3:
324 case 2:
325 /* For the special day when i810 gets merged. */
326 case 1:
327 return 0;
328 }
329 break;
330 default:
331 MISSING_CASE(class);
332 fallthrough;
333 case VIDEO_DECODE_CLASS:
334 case VIDEO_ENHANCEMENT_CLASS:
335 case COPY_ENGINE_CLASS:
336 case OTHER_CLASS:
337 if (GRAPHICS_VER(gt->i915) < 8)
338 return 0;
339 return GEN8_LR_CONTEXT_OTHER_SIZE;
340 }
341}
342
343static u32 __engine_mmio_base(struct drm_i915_private *i915,
344 const struct engine_mmio_base *bases)
345{
346 int i;
347
348 for (i = 0; i < MAX_MMIO_BASES; i++)
349 if (GRAPHICS_VER(i915) >= bases[i].graphics_ver)
350 break;
351
352 GEM_BUG_ON(i == MAX_MMIO_BASES);
353 GEM_BUG_ON(!bases[i].base);
354
355 return bases[i].base;
356}
357
358static void __sprint_engine_name(struct intel_engine_cs *engine)
359{
360 /*
361 * Before we know what the uABI name for this engine will be,
362 * we still would like to keep track of this engine in the debug logs.
363 * We throw in a ' here as a reminder that this isn't its final name.
364 */
365 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u",
366 intel_engine_class_repr(engine->class),
367 engine->instance) >= sizeof(engine->name));
368}
369
370void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
371{
372 /*
373 * Though they added more rings on g4x/ilk, they did not add
374 * per-engine HWSTAM until gen6.
375 */
376 if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS)
377 return;
378
379 if (GRAPHICS_VER(engine->i915) >= 3)
380 ENGINE_WRITE(engine, RING_HWSTAM, mask);
381 else
382 ENGINE_WRITE16(engine, RING_HWSTAM, mask);
383}
384
385static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
386{
387 /* Mask off all writes into the unknown HWSP */
388 intel_engine_set_hwsp_writemask(engine, ~0u);
389}
390
391static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir)
392{
393 GEM_DEBUG_WARN_ON(iir);
394}
395
396static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
397{
398 u32 reset_domain;
399
400 if (ver >= 11) {
401 static const u32 engine_reset_domains[] = {
402 [RCS0] = GEN11_GRDOM_RENDER,
403 [BCS0] = GEN11_GRDOM_BLT,
404 [BCS1] = XEHPC_GRDOM_BLT1,
405 [BCS2] = XEHPC_GRDOM_BLT2,
406 [BCS3] = XEHPC_GRDOM_BLT3,
407 [BCS4] = XEHPC_GRDOM_BLT4,
408 [BCS5] = XEHPC_GRDOM_BLT5,
409 [BCS6] = XEHPC_GRDOM_BLT6,
410 [BCS7] = XEHPC_GRDOM_BLT7,
411 [BCS8] = XEHPC_GRDOM_BLT8,
412 [VCS0] = GEN11_GRDOM_MEDIA,
413 [VCS1] = GEN11_GRDOM_MEDIA2,
414 [VCS2] = GEN11_GRDOM_MEDIA3,
415 [VCS3] = GEN11_GRDOM_MEDIA4,
416 [VCS4] = GEN11_GRDOM_MEDIA5,
417 [VCS5] = GEN11_GRDOM_MEDIA6,
418 [VCS6] = GEN11_GRDOM_MEDIA7,
419 [VCS7] = GEN11_GRDOM_MEDIA8,
420 [VECS0] = GEN11_GRDOM_VECS,
421 [VECS1] = GEN11_GRDOM_VECS2,
422 [VECS2] = GEN11_GRDOM_VECS3,
423 [VECS3] = GEN11_GRDOM_VECS4,
424 [CCS0] = GEN11_GRDOM_RENDER,
425 [CCS1] = GEN11_GRDOM_RENDER,
426 [CCS2] = GEN11_GRDOM_RENDER,
427 [CCS3] = GEN11_GRDOM_RENDER,
428 [GSC0] = GEN12_GRDOM_GSC,
429 };
430 GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
431 !engine_reset_domains[id]);
432 reset_domain = engine_reset_domains[id];
433 } else {
434 static const u32 engine_reset_domains[] = {
435 [RCS0] = GEN6_GRDOM_RENDER,
436 [BCS0] = GEN6_GRDOM_BLT,
437 [VCS0] = GEN6_GRDOM_MEDIA,
438 [VCS1] = GEN8_GRDOM_MEDIA2,
439 [VECS0] = GEN6_GRDOM_VECS,
440 };
441 GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
442 !engine_reset_domains[id]);
443 reset_domain = engine_reset_domains[id];
444 }
445
446 return reset_domain;
447}
448
449static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,
450 u8 logical_instance)
451{
452 const struct engine_info *info = &intel_engines[id];
453 struct drm_i915_private *i915 = gt->i915;
454 struct intel_engine_cs *engine;
455 u8 guc_class;
456
457 BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
458 BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
459 BUILD_BUG_ON(I915_MAX_VCS > (MAX_ENGINE_INSTANCE + 1));
460 BUILD_BUG_ON(I915_MAX_VECS > (MAX_ENGINE_INSTANCE + 1));
461
462 if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))
463 return -EINVAL;
464
465 if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS))
466 return -EINVAL;
467
468 if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
469 return -EINVAL;
470
471 if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance]))
472 return -EINVAL;
473
474 engine = kzalloc(sizeof(*engine), GFP_KERNEL);
475 if (!engine)
476 return -ENOMEM;
477
478 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
479
480 INIT_LIST_HEAD(&engine->pinned_contexts_list);
481 engine->id = id;
482 engine->legacy_idx = INVALID_ENGINE;
483 engine->mask = BIT(id);
484 engine->reset_domain = get_reset_domain(GRAPHICS_VER(gt->i915),
485 id);
486 engine->i915 = i915;
487 engine->gt = gt;
488 engine->uncore = gt->uncore;
489 guc_class = engine_class_to_guc_class(info->class);
490 engine->guc_id = MAKE_GUC_ID(guc_class, info->instance);
491 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
492
493 engine->irq_handler = nop_irq_handler;
494
495 engine->class = info->class;
496 engine->instance = info->instance;
497 engine->logical_mask = BIT(logical_instance);
498 __sprint_engine_name(engine);
499
500 if ((engine->class == COMPUTE_CLASS && !RCS_MASK(engine->gt) &&
501 __ffs(CCS_MASK(engine->gt)) == engine->instance) ||
502 engine->class == RENDER_CLASS)
503 engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE;
504
505 /* features common between engines sharing EUs */
506 if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
507 engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
508 engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
509 }
510
511 engine->props.heartbeat_interval_ms =
512 CONFIG_DRM_I915_HEARTBEAT_INTERVAL;
513 engine->props.max_busywait_duration_ns =
514 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT;
515 engine->props.preempt_timeout_ms =
516 CONFIG_DRM_I915_PREEMPT_TIMEOUT;
517 engine->props.stop_timeout_ms =
518 CONFIG_DRM_I915_STOP_TIMEOUT;
519 engine->props.timeslice_duration_ms =
520 CONFIG_DRM_I915_TIMESLICE_DURATION;
521
522 /*
523 * Mid-thread pre-emption is not available in Gen12. Unfortunately,
524 * some compute workloads run quite long threads. That means they get
525 * reset due to not pre-empting in a timely manner. So, bump the
526 * pre-emption timeout value to be much higher for compute engines.
527 */
528 if (GRAPHICS_VER(i915) == 12 && (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE))
529 engine->props.preempt_timeout_ms = CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE;
530
531 /* Cap properties according to any system limits */
532#define CLAMP_PROP(field) \
533 do { \
534 u64 clamp = intel_clamp_##field(engine, engine->props.field); \
535 if (clamp != engine->props.field) { \
536 drm_notice(&engine->i915->drm, \
537 "Warning, clamping %s to %lld to prevent overflow\n", \
538 #field, clamp); \
539 engine->props.field = clamp; \
540 } \
541 } while (0)
542
543 CLAMP_PROP(heartbeat_interval_ms);
544 CLAMP_PROP(max_busywait_duration_ns);
545 CLAMP_PROP(preempt_timeout_ms);
546 CLAMP_PROP(stop_timeout_ms);
547 CLAMP_PROP(timeslice_duration_ms);
548
549#undef CLAMP_PROP
550
551 engine->defaults = engine->props; /* never to change again */
552
553 engine->context_size = intel_engine_context_size(gt, engine->class);
554 if (WARN_ON(engine->context_size > BIT(20)))
555 engine->context_size = 0;
556 if (engine->context_size)
557 DRIVER_CAPS(i915)->has_logical_contexts = true;
558
559 ewma__engine_latency_init(&engine->latency);
560
561 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
562
563 /* Scrub mmio state on takeover */
564 intel_engine_sanitize_mmio(engine);
565
566 gt->engine_class[info->class][info->instance] = engine;
567 gt->engine[id] = engine;
568
569 return 0;
570}
571
572u64 intel_clamp_heartbeat_interval_ms(struct intel_engine_cs *engine, u64 value)
573{
574 value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
575
576 return value;
577}
578
579u64 intel_clamp_max_busywait_duration_ns(struct intel_engine_cs *engine, u64 value)
580{
581 value = min(value, jiffies_to_nsecs(2));
582
583 return value;
584}
585
586u64 intel_clamp_preempt_timeout_ms(struct intel_engine_cs *engine, u64 value)
587{
588 /*
589 * NB: The GuC API only supports 32bit values. However, the limit is further
590 * reduced due to internal calculations which would otherwise overflow.
591 */
592 if (intel_guc_submission_is_wanted(&engine->gt->uc.guc))
593 value = min_t(u64, value, guc_policy_max_preempt_timeout_ms());
594
595 value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
596
597 return value;
598}
599
600u64 intel_clamp_stop_timeout_ms(struct intel_engine_cs *engine, u64 value)
601{
602 value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
603
604 return value;
605}
606
607u64 intel_clamp_timeslice_duration_ms(struct intel_engine_cs *engine, u64 value)
608{
609 /*
610 * NB: The GuC API only supports 32bit values. However, the limit is further
611 * reduced due to internal calculations which would otherwise overflow.
612 */
613 if (intel_guc_submission_is_wanted(&engine->gt->uc.guc))
614 value = min_t(u64, value, guc_policy_max_exec_quantum_ms());
615
616 value = min_t(u64, value, jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT));
617
618 return value;
619}
620
621static void __setup_engine_capabilities(struct intel_engine_cs *engine)
622{
623 struct drm_i915_private *i915 = engine->i915;
624
625 if (engine->class == VIDEO_DECODE_CLASS) {
626 /*
627 * HEVC support is present on first engine instance
628 * before Gen11 and on all instances afterwards.
629 */
630 if (GRAPHICS_VER(i915) >= 11 ||
631 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
632 engine->uabi_capabilities |=
633 I915_VIDEO_CLASS_CAPABILITY_HEVC;
634
635 /*
636 * SFC block is present only on even logical engine
637 * instances.
638 */
639 if ((GRAPHICS_VER(i915) >= 11 &&
640 (engine->gt->info.vdbox_sfc_access &
641 BIT(engine->instance))) ||
642 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
643 engine->uabi_capabilities |=
644 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
645 } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
646 if (GRAPHICS_VER(i915) >= 9 &&
647 engine->gt->info.sfc_mask & BIT(engine->instance))
648 engine->uabi_capabilities |=
649 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
650 }
651}
652
653static void intel_setup_engine_capabilities(struct intel_gt *gt)
654{
655 struct intel_engine_cs *engine;
656 enum intel_engine_id id;
657
658 for_each_engine(engine, gt, id)
659 __setup_engine_capabilities(engine);
660}
661
662/**
663 * intel_engines_release() - free the resources allocated for Command Streamers
664 * @gt: pointer to struct intel_gt
665 */
666void intel_engines_release(struct intel_gt *gt)
667{
668 struct intel_engine_cs *engine;
669 enum intel_engine_id id;
670
671 /*
672 * Before we release the resources held by engine, we must be certain
673 * that the HW is no longer accessing them -- having the GPU scribble
674 * to or read from a page being used for something else causes no end
675 * of fun.
676 *
677 * The GPU should be reset by this point, but assume the worst just
678 * in case we aborted before completely initialising the engines.
679 */
680 GEM_BUG_ON(intel_gt_pm_is_awake(gt));
681 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
682 __intel_gt_reset(gt, ALL_ENGINES);
683
684 /* Decouple the backend; but keep the layout for late GPU resets */
685 for_each_engine(engine, gt, id) {
686 if (!engine->release)
687 continue;
688
689 intel_wakeref_wait_for_idle(&engine->wakeref);
690 GEM_BUG_ON(intel_engine_pm_is_awake(engine));
691
692 engine->release(engine);
693 engine->release = NULL;
694
695 memset(&engine->reset, 0, sizeof(engine->reset));
696 }
697}
698
699void intel_engine_free_request_pool(struct intel_engine_cs *engine)
700{
701 if (!engine->request_pool)
702 return;
703
704 kmem_cache_free(i915_request_slab_cache(), engine->request_pool);
705}
706
707void intel_engines_free(struct intel_gt *gt)
708{
709 struct intel_engine_cs *engine;
710 enum intel_engine_id id;
711
712 /* Free the requests! dma-resv keeps fences around for an eternity */
713 rcu_barrier();
714
715 for_each_engine(engine, gt, id) {
716 intel_engine_free_request_pool(engine);
717 kfree(engine);
718 gt->engine[id] = NULL;
719 }
720}
721
722static
723bool gen11_vdbox_has_sfc(struct intel_gt *gt,
724 unsigned int physical_vdbox,
725 unsigned int logical_vdbox, u16 vdbox_mask)
726{
727 struct drm_i915_private *i915 = gt->i915;
728
729 /*
730 * In Gen11, only even numbered logical VDBOXes are hooked
731 * up to an SFC (Scaler & Format Converter) unit.
732 * In Gen12, Even numbered physical instance always are connected
733 * to an SFC. Odd numbered physical instances have SFC only if
734 * previous even instance is fused off.
735 *
736 * Starting with Xe_HP, there's also a dedicated SFC_ENABLE field
737 * in the fuse register that tells us whether a specific SFC is present.
738 */
739 if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
740 return false;
741 else if (MEDIA_VER(i915) >= 12)
742 return (physical_vdbox % 2 == 0) ||
743 !(BIT(physical_vdbox - 1) & vdbox_mask);
744 else if (MEDIA_VER(i915) == 11)
745 return logical_vdbox % 2 == 0;
746
747 return false;
748}
749
750static void engine_mask_apply_media_fuses(struct intel_gt *gt)
751{
752 struct drm_i915_private *i915 = gt->i915;
753 unsigned int logical_vdbox = 0;
754 unsigned int i;
755 u32 media_fuse, fuse1;
756 u16 vdbox_mask;
757 u16 vebox_mask;
758
759 if (MEDIA_VER(gt->i915) < 11)
760 return;
761
762 /*
763 * On newer platforms the fusing register is called 'enable' and has
764 * enable semantics, while on older platforms it is called 'disable'
765 * and bits have disable semantices.
766 */
767 media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
768 if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
769 media_fuse = ~media_fuse;
770
771 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
772 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
773 GEN11_GT_VEBOX_DISABLE_SHIFT;
774
775 if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
776 fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
777 gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
778 } else {
779 gt->info.sfc_mask = ~0;
780 }
781
782 for (i = 0; i < I915_MAX_VCS; i++) {
783 if (!HAS_ENGINE(gt, _VCS(i))) {
784 vdbox_mask &= ~BIT(i);
785 continue;
786 }
787
788 if (!(BIT(i) & vdbox_mask)) {
789 gt->info.engine_mask &= ~BIT(_VCS(i));
790 gt_dbg(gt, "vcs%u fused off\n", i);
791 continue;
792 }
793
794 if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
795 gt->info.vdbox_sfc_access |= BIT(i);
796 logical_vdbox++;
797 }
798 gt_dbg(gt, "vdbox enable: %04x, instances: %04lx\n", vdbox_mask, VDBOX_MASK(gt));
799 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
800
801 for (i = 0; i < I915_MAX_VECS; i++) {
802 if (!HAS_ENGINE(gt, _VECS(i))) {
803 vebox_mask &= ~BIT(i);
804 continue;
805 }
806
807 if (!(BIT(i) & vebox_mask)) {
808 gt->info.engine_mask &= ~BIT(_VECS(i));
809 gt_dbg(gt, "vecs%u fused off\n", i);
810 }
811 }
812 gt_dbg(gt, "vebox enable: %04x, instances: %04lx\n", vebox_mask, VEBOX_MASK(gt));
813 GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
814}
815
816static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
817{
818 struct drm_i915_private *i915 = gt->i915;
819 struct intel_gt_info *info = >->info;
820 int ss_per_ccs = info->sseu.max_subslices / I915_MAX_CCS;
821 unsigned long ccs_mask;
822 unsigned int i;
823
824 if (GRAPHICS_VER(i915) < 11)
825 return;
826
827 if (hweight32(CCS_MASK(gt)) <= 1)
828 return;
829
830 ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
831 ss_per_ccs);
832 /*
833 * If all DSS in a quadrant are fused off, the corresponding CCS
834 * engine is not available for use.
835 */
836 for_each_clear_bit(i, &ccs_mask, I915_MAX_CCS) {
837 info->engine_mask &= ~BIT(_CCS(i));
838 gt_dbg(gt, "ccs%u fused off\n", i);
839 }
840}
841
842static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
843{
844 struct drm_i915_private *i915 = gt->i915;
845 struct intel_gt_info *info = >->info;
846 unsigned long meml3_mask;
847 unsigned long quad;
848
849 if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
850 GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
851 return;
852
853 meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
854 meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
855
856 /*
857 * Link Copy engines may be fused off according to meml3_mask. Each
858 * bit is a quad that houses 2 Link Copy and two Sub Copy engines.
859 */
860 for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) {
861 unsigned int instance = quad * 2 + 1;
862 intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
863 _BCS(instance));
864
865 if (mask & info->engine_mask) {
866 gt_dbg(gt, "bcs%u fused off\n", instance);
867 gt_dbg(gt, "bcs%u fused off\n", instance + 1);
868
869 info->engine_mask &= ~mask;
870 }
871 }
872}
873
874/*
875 * Determine which engines are fused off in our particular hardware.
876 * Note that we have a catch-22 situation where we need to be able to access
877 * the blitter forcewake domain to read the engine fuses, but at the same time
878 * we need to know which engines are available on the system to know which
879 * forcewake domains are present. We solve this by intializing the forcewake
880 * domains based on the full engine mask in the platform capabilities before
881 * calling this function and pruning the domains for fused-off engines
882 * afterwards.
883 */
884static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
885{
886 struct intel_gt_info *info = >->info;
887
888 GEM_BUG_ON(!info->engine_mask);
889
890 engine_mask_apply_media_fuses(gt);
891 engine_mask_apply_compute_fuses(gt);
892 engine_mask_apply_copy_fuses(gt);
893
894 /*
895 * The only use of the GSC CS is to load and communicate with the GSC
896 * FW, so we have no use for it if we don't have the FW.
897 *
898 * IMPORTANT: in cases where we don't have the GSC FW, we have a
899 * catch-22 situation that breaks media C6 due to 2 requirements:
900 * 1) once turned on, the GSC power well will not go to sleep unless the
901 * GSC FW is loaded.
902 * 2) to enable idling (which is required for media C6) we need to
903 * initialize the IDLE_MSG register for the GSC CS and do at least 1
904 * submission, which will wake up the GSC power well.
905 */
906 if (__HAS_ENGINE(info->engine_mask, GSC0) && !intel_uc_wants_gsc_uc(>->uc)) {
907 gt_notice(gt, "No GSC FW selected, disabling GSC CS and media C6\n");
908 info->engine_mask &= ~BIT(GSC0);
909 }
910
911 /*
912 * Do not create the command streamer for CCS slices beyond the first.
913 * All the workload submitted to the first engine will be shared among
914 * all the slices.
915 *
916 * Once the user will be allowed to customize the CCS mode, then this
917 * check needs to be removed.
918 */
919 if (IS_DG2(gt->i915)) {
920 u8 first_ccs = __ffs(CCS_MASK(gt));
921
922 /*
923 * Store the number of active cslices before
924 * changing the CCS engine configuration
925 */
926 gt->ccs.cslices = CCS_MASK(gt);
927
928 /* Mask off all the CCS engine */
929 info->engine_mask &= ~GENMASK(CCS3, CCS0);
930 /* Put back in the first CCS engine */
931 info->engine_mask |= BIT(_CCS(first_ccs));
932 }
933
934 return info->engine_mask;
935}
936
937static void populate_logical_ids(struct intel_gt *gt, u8 *logical_ids,
938 u8 class, const u8 *map, u8 num_instances)
939{
940 int i, j;
941 u8 current_logical_id = 0;
942
943 for (j = 0; j < num_instances; ++j) {
944 for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) {
945 if (!HAS_ENGINE(gt, i) ||
946 intel_engines[i].class != class)
947 continue;
948
949 if (intel_engines[i].instance == map[j]) {
950 logical_ids[intel_engines[i].instance] =
951 current_logical_id++;
952 break;
953 }
954 }
955 }
956}
957
958static void setup_logical_ids(struct intel_gt *gt, u8 *logical_ids, u8 class)
959{
960 /*
961 * Logical to physical mapping is needed for proper support
962 * to split-frame feature.
963 */
964 if (MEDIA_VER(gt->i915) >= 11 && class == VIDEO_DECODE_CLASS) {
965 const u8 map[] = { 0, 2, 4, 6, 1, 3, 5, 7 };
966
967 populate_logical_ids(gt, logical_ids, class,
968 map, ARRAY_SIZE(map));
969 } else {
970 int i;
971 u8 map[MAX_ENGINE_INSTANCE + 1];
972
973 for (i = 0; i < MAX_ENGINE_INSTANCE + 1; ++i)
974 map[i] = i;
975 populate_logical_ids(gt, logical_ids, class,
976 map, ARRAY_SIZE(map));
977 }
978}
979
980/**
981 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
982 * @gt: pointer to struct intel_gt
983 *
984 * Return: non-zero if the initialization failed.
985 */
986int intel_engines_init_mmio(struct intel_gt *gt)
987{
988 struct drm_i915_private *i915 = gt->i915;
989 const unsigned int engine_mask = init_engine_mask(gt);
990 unsigned int mask = 0;
991 unsigned int i, class;
992 u8 logical_ids[MAX_ENGINE_INSTANCE + 1];
993 int err;
994
995 drm_WARN_ON(&i915->drm, engine_mask == 0);
996 drm_WARN_ON(&i915->drm, engine_mask &
997 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
998
999 if (i915_inject_probe_failure(i915))
1000 return -ENODEV;
1001
1002 for (class = 0; class < MAX_ENGINE_CLASS + 1; ++class) {
1003 setup_logical_ids(gt, logical_ids, class);
1004
1005 for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) {
1006 u8 instance = intel_engines[i].instance;
1007
1008 if (intel_engines[i].class != class ||
1009 !HAS_ENGINE(gt, i))
1010 continue;
1011
1012 err = intel_engine_setup(gt, i,
1013 logical_ids[instance]);
1014 if (err)
1015 goto cleanup;
1016
1017 mask |= BIT(i);
1018 }
1019 }
1020
1021 /*
1022 * Catch failures to update intel_engines table when the new engines
1023 * are added to the driver by a warning and disabling the forgotten
1024 * engines.
1025 */
1026 if (drm_WARN_ON(&i915->drm, mask != engine_mask))
1027 gt->info.engine_mask = mask;
1028
1029 gt->info.num_engines = hweight32(mask);
1030
1031 intel_gt_check_and_clear_faults(gt);
1032
1033 intel_setup_engine_capabilities(gt);
1034
1035 intel_uncore_prune_engine_fw_domains(gt->uncore, gt);
1036
1037 return 0;
1038
1039cleanup:
1040 intel_engines_free(gt);
1041 return err;
1042}
1043
1044void intel_engine_init_execlists(struct intel_engine_cs *engine)
1045{
1046 struct intel_engine_execlists * const execlists = &engine->execlists;
1047
1048 execlists->port_mask = 1;
1049 GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists)));
1050 GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
1051
1052 memset(execlists->pending, 0, sizeof(execlists->pending));
1053 execlists->active =
1054 memset(execlists->inflight, 0, sizeof(execlists->inflight));
1055}
1056
1057static void cleanup_status_page(struct intel_engine_cs *engine)
1058{
1059 struct i915_vma *vma;
1060
1061 /* Prevent writes into HWSP after returning the page to the system */
1062 intel_engine_set_hwsp_writemask(engine, ~0u);
1063
1064 vma = fetch_and_zero(&engine->status_page.vma);
1065 if (!vma)
1066 return;
1067
1068 if (!HWS_NEEDS_PHYSICAL(engine->i915))
1069 i915_vma_unpin(vma);
1070
1071 i915_gem_object_unpin_map(vma->obj);
1072 i915_gem_object_put(vma->obj);
1073}
1074
1075static int pin_ggtt_status_page(struct intel_engine_cs *engine,
1076 struct i915_gem_ww_ctx *ww,
1077 struct i915_vma *vma)
1078{
1079 unsigned int flags;
1080
1081 if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt))
1082 /*
1083 * On g33, we cannot place HWS above 256MiB, so
1084 * restrict its pinning to the low mappable arena.
1085 * Though this restriction is not documented for
1086 * gen4, gen5, or byt, they also behave similarly
1087 * and hang if the HWS is placed at the top of the
1088 * GTT. To generalise, it appears that all !llc
1089 * platforms have issues with us placing the HWS
1090 * above the mappable region (even though we never
1091 * actually map it).
1092 */
1093 flags = PIN_MAPPABLE;
1094 else
1095 flags = PIN_HIGH;
1096
1097 return i915_ggtt_pin(vma, ww, 0, flags);
1098}
1099
1100static int init_status_page(struct intel_engine_cs *engine)
1101{
1102 struct drm_i915_gem_object *obj;
1103 struct i915_gem_ww_ctx ww;
1104 struct i915_vma *vma;
1105 void *vaddr;
1106 int ret;
1107
1108 INIT_LIST_HEAD(&engine->status_page.timelines);
1109
1110 /*
1111 * Though the HWS register does support 36bit addresses, historically
1112 * we have had hangs and corruption reported due to wild writes if
1113 * the HWS is placed above 4G. We only allow objects to be allocated
1114 * in GFP_DMA32 for i965, and no earlier physical address users had
1115 * access to more than 4G.
1116 */
1117 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
1118 if (IS_ERR(obj)) {
1119 gt_err(engine->gt, "Failed to allocate status page\n");
1120 return PTR_ERR(obj);
1121 }
1122
1123 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
1124
1125 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
1126 if (IS_ERR(vma)) {
1127 ret = PTR_ERR(vma);
1128 goto err_put;
1129 }
1130
1131 i915_gem_ww_ctx_init(&ww, true);
1132retry:
1133 ret = i915_gem_object_lock(obj, &ww);
1134 if (!ret && !HWS_NEEDS_PHYSICAL(engine->i915))
1135 ret = pin_ggtt_status_page(engine, &ww, vma);
1136 if (ret)
1137 goto err;
1138
1139 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
1140 if (IS_ERR(vaddr)) {
1141 ret = PTR_ERR(vaddr);
1142 goto err_unpin;
1143 }
1144
1145 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
1146 engine->status_page.vma = vma;
1147
1148err_unpin:
1149 if (ret)
1150 i915_vma_unpin(vma);
1151err:
1152 if (ret == -EDEADLK) {
1153 ret = i915_gem_ww_ctx_backoff(&ww);
1154 if (!ret)
1155 goto retry;
1156 }
1157 i915_gem_ww_ctx_fini(&ww);
1158err_put:
1159 if (ret)
1160 i915_gem_object_put(obj);
1161 return ret;
1162}
1163
1164static int intel_engine_init_tlb_invalidation(struct intel_engine_cs *engine)
1165{
1166 static const union intel_engine_tlb_inv_reg gen8_regs[] = {
1167 [RENDER_CLASS].reg = GEN8_RTCR,
1168 [VIDEO_DECODE_CLASS].reg = GEN8_M1TCR, /* , GEN8_M2TCR */
1169 [VIDEO_ENHANCEMENT_CLASS].reg = GEN8_VTCR,
1170 [COPY_ENGINE_CLASS].reg = GEN8_BTCR,
1171 };
1172 static const union intel_engine_tlb_inv_reg gen12_regs[] = {
1173 [RENDER_CLASS].reg = GEN12_GFX_TLB_INV_CR,
1174 [VIDEO_DECODE_CLASS].reg = GEN12_VD_TLB_INV_CR,
1175 [VIDEO_ENHANCEMENT_CLASS].reg = GEN12_VE_TLB_INV_CR,
1176 [COPY_ENGINE_CLASS].reg = GEN12_BLT_TLB_INV_CR,
1177 [COMPUTE_CLASS].reg = GEN12_COMPCTX_TLB_INV_CR,
1178 };
1179 static const union intel_engine_tlb_inv_reg xehp_regs[] = {
1180 [RENDER_CLASS].mcr_reg = XEHP_GFX_TLB_INV_CR,
1181 [VIDEO_DECODE_CLASS].mcr_reg = XEHP_VD_TLB_INV_CR,
1182 [VIDEO_ENHANCEMENT_CLASS].mcr_reg = XEHP_VE_TLB_INV_CR,
1183 [COPY_ENGINE_CLASS].mcr_reg = XEHP_BLT_TLB_INV_CR,
1184 [COMPUTE_CLASS].mcr_reg = XEHP_COMPCTX_TLB_INV_CR,
1185 };
1186 static const union intel_engine_tlb_inv_reg xelpmp_regs[] = {
1187 [VIDEO_DECODE_CLASS].reg = GEN12_VD_TLB_INV_CR,
1188 [VIDEO_ENHANCEMENT_CLASS].reg = GEN12_VE_TLB_INV_CR,
1189 [OTHER_CLASS].reg = XELPMP_GSC_TLB_INV_CR,
1190 };
1191 struct drm_i915_private *i915 = engine->i915;
1192 const unsigned int instance = engine->instance;
1193 const unsigned int class = engine->class;
1194 const union intel_engine_tlb_inv_reg *regs;
1195 union intel_engine_tlb_inv_reg reg;
1196 unsigned int num = 0;
1197 u32 val;
1198
1199 /*
1200 * New platforms should not be added with catch-all-newer (>=)
1201 * condition so that any later platform added triggers the below warning
1202 * and in turn mandates a human cross-check of whether the invalidation
1203 * flows have compatible semantics.
1204 *
1205 * For instance with the 11.00 -> 12.00 transition three out of five
1206 * respective engine registers were moved to masked type. Then after the
1207 * 12.00 -> 12.50 transition multi cast handling is required too.
1208 */
1209
1210 if (engine->gt->type == GT_MEDIA) {
1211 if (MEDIA_VER_FULL(i915) == IP_VER(13, 0)) {
1212 regs = xelpmp_regs;
1213 num = ARRAY_SIZE(xelpmp_regs);
1214 }
1215 } else {
1216 if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 74) ||
1217 GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) ||
1218 GRAPHICS_VER_FULL(i915) == IP_VER(12, 70) ||
1219 GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) ||
1220 GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) {
1221 regs = xehp_regs;
1222 num = ARRAY_SIZE(xehp_regs);
1223 } else if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 0) ||
1224 GRAPHICS_VER_FULL(i915) == IP_VER(12, 10)) {
1225 regs = gen12_regs;
1226 num = ARRAY_SIZE(gen12_regs);
1227 } else if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) <= 11) {
1228 regs = gen8_regs;
1229 num = ARRAY_SIZE(gen8_regs);
1230 } else if (GRAPHICS_VER(i915) < 8) {
1231 return 0;
1232 }
1233 }
1234
1235 if (gt_WARN_ONCE(engine->gt, !num,
1236 "Platform does not implement TLB invalidation!"))
1237 return -ENODEV;
1238
1239 if (gt_WARN_ON_ONCE(engine->gt,
1240 class >= num ||
1241 (!regs[class].reg.reg &&
1242 !regs[class].mcr_reg.reg)))
1243 return -ERANGE;
1244
1245 reg = regs[class];
1246
1247 if (regs == xelpmp_regs && class == OTHER_CLASS) {
1248 /*
1249 * There's only a single GSC instance, but it uses register bit
1250 * 1 instead of either 0 or OTHER_GSC_INSTANCE.
1251 */
1252 GEM_WARN_ON(instance != OTHER_GSC_INSTANCE);
1253 val = 1;
1254 } else if (regs == gen8_regs && class == VIDEO_DECODE_CLASS && instance == 1) {
1255 reg.reg = GEN8_M2TCR;
1256 val = 0;
1257 } else {
1258 val = instance;
1259 }
1260
1261 val = BIT(val);
1262
1263 engine->tlb_inv.mcr = regs == xehp_regs;
1264 engine->tlb_inv.reg = reg;
1265 engine->tlb_inv.done = val;
1266
1267 if (GRAPHICS_VER(i915) >= 12 &&
1268 (engine->class == VIDEO_DECODE_CLASS ||
1269 engine->class == VIDEO_ENHANCEMENT_CLASS ||
1270 engine->class == COMPUTE_CLASS ||
1271 engine->class == OTHER_CLASS))
1272 engine->tlb_inv.request = _MASKED_BIT_ENABLE(val);
1273 else
1274 engine->tlb_inv.request = val;
1275
1276 return 0;
1277}
1278
1279static int engine_setup_common(struct intel_engine_cs *engine)
1280{
1281 int err;
1282
1283 init_llist_head(&engine->barrier_tasks);
1284
1285 err = intel_engine_init_tlb_invalidation(engine);
1286 if (err)
1287 return err;
1288
1289 err = init_status_page(engine);
1290 if (err)
1291 return err;
1292
1293 engine->breadcrumbs = intel_breadcrumbs_create(engine);
1294 if (!engine->breadcrumbs) {
1295 err = -ENOMEM;
1296 goto err_status;
1297 }
1298
1299 engine->sched_engine = i915_sched_engine_create(ENGINE_PHYSICAL);
1300 if (!engine->sched_engine) {
1301 err = -ENOMEM;
1302 goto err_sched_engine;
1303 }
1304 engine->sched_engine->private_data = engine;
1305
1306 err = intel_engine_init_cmd_parser(engine);
1307 if (err)
1308 goto err_cmd_parser;
1309
1310 intel_engine_init_execlists(engine);
1311 intel_engine_init__pm(engine);
1312 intel_engine_init_retire(engine);
1313
1314 /* Use the whole device by default */
1315 engine->sseu =
1316 intel_sseu_from_device_info(&engine->gt->info.sseu);
1317
1318 intel_engine_init_workarounds(engine);
1319 intel_engine_init_whitelist(engine);
1320 intel_engine_init_ctx_wa(engine);
1321
1322 if (GRAPHICS_VER(engine->i915) >= 12)
1323 engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
1324
1325 return 0;
1326
1327err_cmd_parser:
1328 i915_sched_engine_put(engine->sched_engine);
1329err_sched_engine:
1330 intel_breadcrumbs_put(engine->breadcrumbs);
1331err_status:
1332 cleanup_status_page(engine);
1333 return err;
1334}
1335
1336struct measure_breadcrumb {
1337 struct i915_request rq;
1338 struct intel_ring ring;
1339 u32 cs[2048];
1340};
1341
1342static int measure_breadcrumb_dw(struct intel_context *ce)
1343{
1344 struct intel_engine_cs *engine = ce->engine;
1345 struct measure_breadcrumb *frame;
1346 int dw;
1347
1348 GEM_BUG_ON(!engine->gt->scratch);
1349
1350 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1351 if (!frame)
1352 return -ENOMEM;
1353
1354 frame->rq.i915 = engine->i915;
1355 frame->rq.engine = engine;
1356 frame->rq.context = ce;
1357 rcu_assign_pointer(frame->rq.timeline, ce->timeline);
1358 frame->rq.hwsp_seqno = ce->timeline->hwsp_seqno;
1359
1360 frame->ring.vaddr = frame->cs;
1361 frame->ring.size = sizeof(frame->cs);
1362 frame->ring.wrap =
1363 BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size);
1364 frame->ring.effective_size = frame->ring.size;
1365 intel_ring_update_space(&frame->ring);
1366 frame->rq.ring = &frame->ring;
1367
1368 mutex_lock(&ce->timeline->mutex);
1369 spin_lock_irq(&engine->sched_engine->lock);
1370
1371 dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
1372
1373 spin_unlock_irq(&engine->sched_engine->lock);
1374 mutex_unlock(&ce->timeline->mutex);
1375
1376 GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */
1377
1378 kfree(frame);
1379 return dw;
1380}
1381
1382struct intel_context *
1383intel_engine_create_pinned_context(struct intel_engine_cs *engine,
1384 struct i915_address_space *vm,
1385 unsigned int ring_size,
1386 unsigned int hwsp,
1387 struct lock_class_key *key,
1388 const char *name)
1389{
1390 struct intel_context *ce;
1391 int err;
1392
1393 ce = intel_context_create(engine);
1394 if (IS_ERR(ce))
1395 return ce;
1396
1397 __set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
1398 ce->timeline = page_pack_bits(NULL, hwsp);
1399 ce->ring = NULL;
1400 ce->ring_size = ring_size;
1401
1402 i915_vm_put(ce->vm);
1403 ce->vm = i915_vm_get(vm);
1404
1405 err = intel_context_pin(ce); /* perma-pin so it is always available */
1406 if (err) {
1407 intel_context_put(ce);
1408 return ERR_PTR(err);
1409 }
1410
1411 list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list);
1412
1413 /*
1414 * Give our perma-pinned kernel timelines a separate lockdep class,
1415 * so that we can use them from within the normal user timelines
1416 * should we need to inject GPU operations during their request
1417 * construction.
1418 */
1419 lockdep_set_class_and_name(&ce->timeline->mutex, key, name);
1420
1421 return ce;
1422}
1423
1424void intel_engine_destroy_pinned_context(struct intel_context *ce)
1425{
1426 struct intel_engine_cs *engine = ce->engine;
1427 struct i915_vma *hwsp = engine->status_page.vma;
1428
1429 GEM_BUG_ON(ce->timeline->hwsp_ggtt != hwsp);
1430
1431 mutex_lock(&hwsp->vm->mutex);
1432 list_del(&ce->timeline->engine_link);
1433 mutex_unlock(&hwsp->vm->mutex);
1434
1435 list_del(&ce->pinned_contexts_link);
1436 intel_context_unpin(ce);
1437 intel_context_put(ce);
1438}
1439
1440static struct intel_context *
1441create_ggtt_bind_context(struct intel_engine_cs *engine)
1442{
1443 static struct lock_class_key kernel;
1444
1445 /*
1446 * MI_UPDATE_GTT can insert up to 511 PTE entries and there could be multiple
1447 * bind requets at a time so get a bigger ring.
1448 */
1449 return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_512K,
1450 I915_GEM_HWS_GGTT_BIND_ADDR,
1451 &kernel, "ggtt_bind_context");
1452}
1453
1454static struct intel_context *
1455create_kernel_context(struct intel_engine_cs *engine)
1456{
1457 static struct lock_class_key kernel;
1458
1459 return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,
1460 I915_GEM_HWS_SEQNO_ADDR,
1461 &kernel, "kernel_context");
1462}
1463
1464/*
1465 * engine_init_common - initialize engine state which might require hw access
1466 * @engine: Engine to initialize.
1467 *
1468 * Initializes @engine@ structure members shared between legacy and execlists
1469 * submission modes which do require hardware access.
1470 *
1471 * Typcally done at later stages of submission mode specific engine setup.
1472 *
1473 * Returns zero on success or an error code on failure.
1474 */
1475static int engine_init_common(struct intel_engine_cs *engine)
1476{
1477 struct intel_context *ce, *bce = NULL;
1478 int ret;
1479
1480 engine->set_default_submission(engine);
1481
1482 /*
1483 * We may need to do things with the shrinker which
1484 * require us to immediately switch back to the default
1485 * context. This can cause a problem as pinning the
1486 * default context also requires GTT space which may not
1487 * be available. To avoid this we always pin the default
1488 * context.
1489 */
1490 ce = create_kernel_context(engine);
1491 if (IS_ERR(ce))
1492 return PTR_ERR(ce);
1493 /*
1494 * Create a separate pinned context for GGTT update with blitter engine
1495 * if a platform require such service. MI_UPDATE_GTT works on other
1496 * engines as well but BCS should be less busy engine so pick that for
1497 * GGTT updates.
1498 */
1499 if (i915_ggtt_require_binder(engine->i915) && engine->id == BCS0) {
1500 bce = create_ggtt_bind_context(engine);
1501 if (IS_ERR(bce)) {
1502 ret = PTR_ERR(bce);
1503 goto err_ce_context;
1504 }
1505 }
1506
1507 ret = measure_breadcrumb_dw(ce);
1508 if (ret < 0)
1509 goto err_bce_context;
1510
1511 engine->emit_fini_breadcrumb_dw = ret;
1512 engine->kernel_context = ce;
1513 engine->bind_context = bce;
1514
1515 return 0;
1516
1517err_bce_context:
1518 if (bce)
1519 intel_engine_destroy_pinned_context(bce);
1520err_ce_context:
1521 intel_engine_destroy_pinned_context(ce);
1522 return ret;
1523}
1524
1525int intel_engines_init(struct intel_gt *gt)
1526{
1527 int (*setup)(struct intel_engine_cs *engine);
1528 struct intel_engine_cs *engine;
1529 enum intel_engine_id id;
1530 int err;
1531
1532 if (intel_uc_uses_guc_submission(>->uc)) {
1533 gt->submission_method = INTEL_SUBMISSION_GUC;
1534 setup = intel_guc_submission_setup;
1535 } else if (HAS_EXECLISTS(gt->i915)) {
1536 gt->submission_method = INTEL_SUBMISSION_ELSP;
1537 setup = intel_execlists_submission_setup;
1538 } else {
1539 gt->submission_method = INTEL_SUBMISSION_RING;
1540 setup = intel_ring_submission_setup;
1541 }
1542
1543 for_each_engine(engine, gt, id) {
1544 err = engine_setup_common(engine);
1545 if (err)
1546 return err;
1547
1548 err = setup(engine);
1549 if (err) {
1550 intel_engine_cleanup_common(engine);
1551 return err;
1552 }
1553
1554 /* The backend should now be responsible for cleanup */
1555 GEM_BUG_ON(engine->release == NULL);
1556
1557 err = engine_init_common(engine);
1558 if (err)
1559 return err;
1560
1561 intel_engine_add_user(engine);
1562 }
1563
1564 return 0;
1565}
1566
1567/**
1568 * intel_engine_cleanup_common - cleans up the engine state created by
1569 * the common initiailizers.
1570 * @engine: Engine to cleanup.
1571 *
1572 * This cleans up everything created by the common helpers.
1573 */
1574void intel_engine_cleanup_common(struct intel_engine_cs *engine)
1575{
1576 GEM_BUG_ON(!list_empty(&engine->sched_engine->requests));
1577
1578 i915_sched_engine_put(engine->sched_engine);
1579 intel_breadcrumbs_put(engine->breadcrumbs);
1580
1581 intel_engine_fini_retire(engine);
1582 intel_engine_cleanup_cmd_parser(engine);
1583
1584 if (engine->default_state)
1585 fput(engine->default_state);
1586
1587 if (engine->kernel_context)
1588 intel_engine_destroy_pinned_context(engine->kernel_context);
1589
1590 if (engine->bind_context)
1591 intel_engine_destroy_pinned_context(engine->bind_context);
1592
1593
1594 GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
1595 cleanup_status_page(engine);
1596
1597 intel_wa_list_free(&engine->ctx_wa_list);
1598 intel_wa_list_free(&engine->wa_list);
1599 intel_wa_list_free(&engine->whitelist);
1600}
1601
1602/**
1603 * intel_engine_resume - re-initializes the HW state of the engine
1604 * @engine: Engine to resume.
1605 *
1606 * Returns zero on success or an error code on failure.
1607 */
1608int intel_engine_resume(struct intel_engine_cs *engine)
1609{
1610 intel_engine_apply_workarounds(engine);
1611 intel_engine_apply_whitelist(engine);
1612
1613 return engine->resume(engine);
1614}
1615
1616u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
1617{
1618 struct drm_i915_private *i915 = engine->i915;
1619
1620 u64 acthd;
1621
1622 if (GRAPHICS_VER(i915) >= 8)
1623 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
1624 else if (GRAPHICS_VER(i915) >= 4)
1625 acthd = ENGINE_READ(engine, RING_ACTHD);
1626 else
1627 acthd = ENGINE_READ(engine, ACTHD);
1628
1629 return acthd;
1630}
1631
1632u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
1633{
1634 u64 bbaddr;
1635
1636 if (GRAPHICS_VER(engine->i915) >= 8)
1637 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
1638 else
1639 bbaddr = ENGINE_READ(engine, RING_BBADDR);
1640
1641 return bbaddr;
1642}
1643
1644static unsigned long stop_timeout(const struct intel_engine_cs *engine)
1645{
1646 if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */
1647 return 0;
1648
1649 /*
1650 * If we are doing a normal GPU reset, we can take our time and allow
1651 * the engine to quiesce. We've stopped submission to the engine, and
1652 * if we wait long enough an innocent context should complete and
1653 * leave the engine idle. So they should not be caught unaware by
1654 * the forthcoming GPU reset (which usually follows the stop_cs)!
1655 */
1656 return READ_ONCE(engine->props.stop_timeout_ms);
1657}
1658
1659static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
1660 int fast_timeout_us,
1661 int slow_timeout_ms)
1662{
1663 struct intel_uncore *uncore = engine->uncore;
1664 const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);
1665 int err;
1666
1667 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
1668
1669 /*
1670 * Wa_22011802037: Prior to doing a reset, ensure CS is
1671 * stopped, set ring stop bit and prefetch disable bit to halt CS
1672 */
1673 if (intel_engine_reset_needs_wa_22011802037(engine->gt))
1674 intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
1675 _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
1676
1677 err = __intel_wait_for_register_fw(engine->uncore, mode,
1678 MODE_IDLE, MODE_IDLE,
1679 fast_timeout_us,
1680 slow_timeout_ms,
1681 NULL);
1682
1683 /* A final mmio read to let GPU writes be hopefully flushed to memory */
1684 intel_uncore_posting_read_fw(uncore, mode);
1685 return err;
1686}
1687
1688int intel_engine_stop_cs(struct intel_engine_cs *engine)
1689{
1690 int err = 0;
1691
1692 if (GRAPHICS_VER(engine->i915) < 3)
1693 return -ENODEV;
1694
1695 ENGINE_TRACE(engine, "\n");
1696 /*
1697 * TODO: Find out why occasionally stopping the CS times out. Seen
1698 * especially with gem_eio tests.
1699 *
1700 * Occasionally trying to stop the cs times out, but does not adversely
1701 * affect functionality. The timeout is set as a config parameter that
1702 * defaults to 100ms. In most cases the follow up operation is to wait
1703 * for pending MI_FORCE_WAKES. The assumption is that this timeout is
1704 * sufficient for any pending MI_FORCEWAKEs to complete. Once root
1705 * caused, the caller must check and handle the return from this
1706 * function.
1707 */
1708 if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
1709 ENGINE_TRACE(engine,
1710 "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n",
1711 ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR,
1712 ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR);
1713
1714 /*
1715 * Sometimes we observe that the idle flag is not
1716 * set even though the ring is empty. So double
1717 * check before giving up.
1718 */
1719 if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) !=
1720 (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR))
1721 err = -ETIMEDOUT;
1722 }
1723
1724 return err;
1725}
1726
1727void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
1728{
1729 ENGINE_TRACE(engine, "\n");
1730
1731 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
1732}
1733
1734static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
1735{
1736 static const i915_reg_t _reg[I915_NUM_ENGINES] = {
1737 [RCS0] = MSG_IDLE_CS,
1738 [BCS0] = MSG_IDLE_BCS,
1739 [VCS0] = MSG_IDLE_VCS0,
1740 [VCS1] = MSG_IDLE_VCS1,
1741 [VCS2] = MSG_IDLE_VCS2,
1742 [VCS3] = MSG_IDLE_VCS3,
1743 [VCS4] = MSG_IDLE_VCS4,
1744 [VCS5] = MSG_IDLE_VCS5,
1745 [VCS6] = MSG_IDLE_VCS6,
1746 [VCS7] = MSG_IDLE_VCS7,
1747 [VECS0] = MSG_IDLE_VECS0,
1748 [VECS1] = MSG_IDLE_VECS1,
1749 [VECS2] = MSG_IDLE_VECS2,
1750 [VECS3] = MSG_IDLE_VECS3,
1751 [CCS0] = MSG_IDLE_CS,
1752 [CCS1] = MSG_IDLE_CS,
1753 [CCS2] = MSG_IDLE_CS,
1754 [CCS3] = MSG_IDLE_CS,
1755 };
1756 u32 val;
1757
1758 if (!_reg[engine->id].reg)
1759 return 0;
1760
1761 val = intel_uncore_read(engine->uncore, _reg[engine->id]);
1762
1763 /* bits[29:25] & bits[13:9] >> shift */
1764 return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
1765}
1766
1767static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
1768{
1769 int ret;
1770
1771 /* Ensure GPM receives fw up/down after CS is stopped */
1772 udelay(1);
1773
1774 /* Wait for forcewake request to complete in GPM */
1775 ret = __intel_wait_for_register_fw(gt->uncore,
1776 GEN9_PWRGT_DOMAIN_STATUS,
1777 fw_mask, fw_mask, 5000, 0, NULL);
1778
1779 /* Ensure CS receives fw ack from GPM */
1780 udelay(1);
1781
1782 if (ret)
1783 GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
1784}
1785
1786/*
1787 * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
1788 * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
1789 * pending status is indicated by bits[13:9] (masked by bits[29:25]) in the
1790 * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
1791 * are concerned only with the gt reset here, we use a logical OR of pending
1792 * forcewakeups from all reset domains and then wait for them to complete by
1793 * querying PWRGT_DOMAIN_STATUS.
1794 */
1795void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine)
1796{
1797 u32 fw_pending = __cs_pending_mi_force_wakes(engine);
1798
1799 if (fw_pending)
1800 __gpm_wait_for_fw_complete(engine->gt, fw_pending);
1801}
1802
1803/* NB: please notice the memset */
1804void intel_engine_get_instdone(const struct intel_engine_cs *engine,
1805 struct intel_instdone *instdone)
1806{
1807 struct drm_i915_private *i915 = engine->i915;
1808 struct intel_uncore *uncore = engine->uncore;
1809 u32 mmio_base = engine->mmio_base;
1810 int slice;
1811 int subslice;
1812 int iter;
1813
1814 memset(instdone, 0, sizeof(*instdone));
1815
1816 if (GRAPHICS_VER(i915) >= 8) {
1817 instdone->instdone =
1818 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1819
1820 if (engine->id != RCS0)
1821 return;
1822
1823 instdone->slice_common =
1824 intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1825 if (GRAPHICS_VER(i915) >= 12) {
1826 instdone->slice_common_extra[0] =
1827 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
1828 instdone->slice_common_extra[1] =
1829 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2);
1830 }
1831
1832 for_each_ss_steering(iter, engine->gt, slice, subslice) {
1833 instdone->sampler[slice][subslice] =
1834 intel_gt_mcr_read(engine->gt,
1835 GEN8_SAMPLER_INSTDONE,
1836 slice, subslice);
1837 instdone->row[slice][subslice] =
1838 intel_gt_mcr_read(engine->gt,
1839 GEN8_ROW_INSTDONE,
1840 slice, subslice);
1841 }
1842
1843 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
1844 for_each_ss_steering(iter, engine->gt, slice, subslice)
1845 instdone->geom_svg[slice][subslice] =
1846 intel_gt_mcr_read(engine->gt,
1847 XEHPG_INSTDONE_GEOM_SVG,
1848 slice, subslice);
1849 }
1850 } else if (GRAPHICS_VER(i915) >= 7) {
1851 instdone->instdone =
1852 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1853
1854 if (engine->id != RCS0)
1855 return;
1856
1857 instdone->slice_common =
1858 intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1859 instdone->sampler[0][0] =
1860 intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE);
1861 instdone->row[0][0] =
1862 intel_uncore_read(uncore, GEN7_ROW_INSTDONE);
1863 } else if (GRAPHICS_VER(i915) >= 4) {
1864 instdone->instdone =
1865 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1866 if (engine->id == RCS0)
1867 /* HACK: Using the wrong struct member */
1868 instdone->slice_common =
1869 intel_uncore_read(uncore, GEN4_INSTDONE1);
1870 } else {
1871 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE);
1872 }
1873}
1874
1875static bool ring_is_idle(struct intel_engine_cs *engine)
1876{
1877 bool idle = true;
1878
1879 if (I915_SELFTEST_ONLY(!engine->mmio_base))
1880 return true;
1881
1882 if (!intel_engine_pm_get_if_awake(engine))
1883 return true;
1884
1885 /* First check that no commands are left in the ring */
1886 if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) !=
1887 (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR))
1888 idle = false;
1889
1890 /* No bit for gen2, so assume the CS parser is idle */
1891 if (GRAPHICS_VER(engine->i915) > 2 &&
1892 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
1893 idle = false;
1894
1895 intel_engine_pm_put(engine);
1896
1897 return idle;
1898}
1899
1900void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync)
1901{
1902 struct tasklet_struct *t = &engine->sched_engine->tasklet;
1903
1904 if (!t->callback)
1905 return;
1906
1907 local_bh_disable();
1908 if (tasklet_trylock(t)) {
1909 /* Must wait for any GPU reset in progress. */
1910 if (__tasklet_is_enabled(t))
1911 t->callback(t);
1912 tasklet_unlock(t);
1913 }
1914 local_bh_enable();
1915
1916 /* Synchronise and wait for the tasklet on another CPU */
1917 if (sync)
1918 tasklet_unlock_wait(t);
1919}
1920
1921/**
1922 * intel_engine_is_idle() - Report if the engine has finished process all work
1923 * @engine: the intel_engine_cs
1924 *
1925 * Return true if there are no requests pending, nothing left to be submitted
1926 * to hardware, and that the engine is idle.
1927 */
1928bool intel_engine_is_idle(struct intel_engine_cs *engine)
1929{
1930 /* More white lies, if wedged, hw state is inconsistent */
1931 if (intel_gt_is_wedged(engine->gt))
1932 return true;
1933
1934 if (!intel_engine_pm_is_awake(engine))
1935 return true;
1936
1937 /* Waiting to drain ELSP? */
1938 intel_synchronize_hardirq(engine->i915);
1939 intel_engine_flush_submission(engine);
1940
1941 /* ELSP is empty, but there are ready requests? E.g. after reset */
1942 if (!i915_sched_engine_is_empty(engine->sched_engine))
1943 return false;
1944
1945 /* Ring stopped? */
1946 return ring_is_idle(engine);
1947}
1948
1949bool intel_engines_are_idle(struct intel_gt *gt)
1950{
1951 struct intel_engine_cs *engine;
1952 enum intel_engine_id id;
1953
1954 /*
1955 * If the driver is wedged, HW state may be very inconsistent and
1956 * report that it is still busy, even though we have stopped using it.
1957 */
1958 if (intel_gt_is_wedged(gt))
1959 return true;
1960
1961 /* Already parked (and passed an idleness test); must still be idle */
1962 if (!READ_ONCE(gt->awake))
1963 return true;
1964
1965 for_each_engine(engine, gt, id) {
1966 if (!intel_engine_is_idle(engine))
1967 return false;
1968 }
1969
1970 return true;
1971}
1972
1973bool intel_engine_irq_enable(struct intel_engine_cs *engine)
1974{
1975 if (!engine->irq_enable)
1976 return false;
1977
1978 /* Caller disables interrupts */
1979 spin_lock(engine->gt->irq_lock);
1980 engine->irq_enable(engine);
1981 spin_unlock(engine->gt->irq_lock);
1982
1983 return true;
1984}
1985
1986void intel_engine_irq_disable(struct intel_engine_cs *engine)
1987{
1988 if (!engine->irq_disable)
1989 return;
1990
1991 /* Caller disables interrupts */
1992 spin_lock(engine->gt->irq_lock);
1993 engine->irq_disable(engine);
1994 spin_unlock(engine->gt->irq_lock);
1995}
1996
1997void intel_engines_reset_default_submission(struct intel_gt *gt)
1998{
1999 struct intel_engine_cs *engine;
2000 enum intel_engine_id id;
2001
2002 for_each_engine(engine, gt, id) {
2003 if (engine->sanitize)
2004 engine->sanitize(engine);
2005
2006 engine->set_default_submission(engine);
2007 }
2008}
2009
2010bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
2011{
2012 switch (GRAPHICS_VER(engine->i915)) {
2013 case 2:
2014 return false; /* uses physical not virtual addresses */
2015 case 3:
2016 /* maybe only uses physical not virtual addresses */
2017 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
2018 case 4:
2019 return !IS_I965G(engine->i915); /* who knows! */
2020 case 6:
2021 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
2022 default:
2023 return true;
2024 }
2025}
2026
2027static struct intel_timeline *get_timeline(struct i915_request *rq)
2028{
2029 struct intel_timeline *tl;
2030
2031 /*
2032 * Even though we are holding the engine->sched_engine->lock here, there
2033 * is no control over the submission queue per-se and we are
2034 * inspecting the active state at a random point in time, with an
2035 * unknown queue. Play safe and make sure the timeline remains valid.
2036 * (Only being used for pretty printing, one extra kref shouldn't
2037 * cause a camel stampede!)
2038 */
2039 rcu_read_lock();
2040 tl = rcu_dereference(rq->timeline);
2041 if (!kref_get_unless_zero(&tl->kref))
2042 tl = NULL;
2043 rcu_read_unlock();
2044
2045 return tl;
2046}
2047
2048static int print_ring(char *buf, int sz, struct i915_request *rq)
2049{
2050 int len = 0;
2051
2052 if (!i915_request_signaled(rq)) {
2053 struct intel_timeline *tl = get_timeline(rq);
2054
2055 len = scnprintf(buf, sz,
2056 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ",
2057 i915_ggtt_offset(rq->ring->vma),
2058 tl ? tl->hwsp_offset : 0,
2059 hwsp_seqno(rq),
2060 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context),
2061 1000 * 1000));
2062
2063 if (tl)
2064 intel_timeline_put(tl);
2065 }
2066
2067 return len;
2068}
2069
2070static void hexdump(struct drm_printer *m, const void *buf, size_t len)
2071{
2072 const size_t rowsize = 8 * sizeof(u32);
2073 const void *prev = NULL;
2074 bool skip = false;
2075 size_t pos;
2076
2077 for (pos = 0; pos < len; pos += rowsize) {
2078 char line[128];
2079
2080 if (prev && !memcmp(prev, buf + pos, rowsize)) {
2081 if (!skip) {
2082 drm_printf(m, "*\n");
2083 skip = true;
2084 }
2085 continue;
2086 }
2087
2088 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
2089 rowsize, sizeof(u32),
2090 line, sizeof(line),
2091 false) >= sizeof(line));
2092 drm_printf(m, "[%04zx] %s\n", pos, line);
2093
2094 prev = buf + pos;
2095 skip = false;
2096 }
2097}
2098
2099static const char *repr_timer(const struct timer_list *t)
2100{
2101 if (!READ_ONCE(t->expires))
2102 return "inactive";
2103
2104 if (timer_pending(t))
2105 return "active";
2106
2107 return "expired";
2108}
2109
2110static void intel_engine_print_registers(struct intel_engine_cs *engine,
2111 struct drm_printer *m)
2112{
2113 struct drm_i915_private *i915 = engine->i915;
2114 struct intel_engine_execlists * const execlists = &engine->execlists;
2115 u64 addr;
2116
2117 if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(i915, 4, 7))
2118 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
2119 if (HAS_EXECLISTS(i915)) {
2120 drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
2121 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
2122 drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
2123 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));
2124 }
2125 drm_printf(m, "\tRING_START: 0x%08x\n",
2126 ENGINE_READ(engine, RING_START));
2127 drm_printf(m, "\tRING_HEAD: 0x%08x\n",
2128 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR);
2129 drm_printf(m, "\tRING_TAIL: 0x%08x\n",
2130 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR);
2131 drm_printf(m, "\tRING_CTL: 0x%08x%s\n",
2132 ENGINE_READ(engine, RING_CTL),
2133 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
2134 if (GRAPHICS_VER(engine->i915) > 2) {
2135 drm_printf(m, "\tRING_MODE: 0x%08x%s\n",
2136 ENGINE_READ(engine, RING_MI_MODE),
2137 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
2138 }
2139
2140 if (GRAPHICS_VER(i915) >= 6) {
2141 drm_printf(m, "\tRING_IMR: 0x%08x\n",
2142 ENGINE_READ(engine, RING_IMR));
2143 drm_printf(m, "\tRING_ESR: 0x%08x\n",
2144 ENGINE_READ(engine, RING_ESR));
2145 drm_printf(m, "\tRING_EMR: 0x%08x\n",
2146 ENGINE_READ(engine, RING_EMR));
2147 drm_printf(m, "\tRING_EIR: 0x%08x\n",
2148 ENGINE_READ(engine, RING_EIR));
2149 }
2150
2151 addr = intel_engine_get_active_head(engine);
2152 drm_printf(m, "\tACTHD: 0x%08x_%08x\n",
2153 upper_32_bits(addr), lower_32_bits(addr));
2154 addr = intel_engine_get_last_batch_head(engine);
2155 drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
2156 upper_32_bits(addr), lower_32_bits(addr));
2157 if (GRAPHICS_VER(i915) >= 8)
2158 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
2159 else if (GRAPHICS_VER(i915) >= 4)
2160 addr = ENGINE_READ(engine, RING_DMA_FADD);
2161 else
2162 addr = ENGINE_READ(engine, DMA_FADD_I8XX);
2163 drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
2164 upper_32_bits(addr), lower_32_bits(addr));
2165 if (GRAPHICS_VER(i915) >= 4) {
2166 drm_printf(m, "\tIPEIR: 0x%08x\n",
2167 ENGINE_READ(engine, RING_IPEIR));
2168 drm_printf(m, "\tIPEHR: 0x%08x\n",
2169 ENGINE_READ(engine, RING_IPEHR));
2170 } else {
2171 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR));
2172 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
2173 }
2174
2175 if (HAS_EXECLISTS(i915) && !intel_engine_uses_guc(engine)) {
2176 struct i915_request * const *port, *rq;
2177 const u32 *hws =
2178 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
2179 const u8 num_entries = execlists->csb_size;
2180 unsigned int idx;
2181 u8 read, write;
2182
2183 drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n",
2184 str_yes_no(test_bit(TASKLET_STATE_SCHED, &engine->sched_engine->tasklet.state)),
2185 str_enabled_disabled(!atomic_read(&engine->sched_engine->tasklet.count)),
2186 repr_timer(&engine->execlists.preempt),
2187 repr_timer(&engine->execlists.timer));
2188
2189 read = execlists->csb_head;
2190 write = READ_ONCE(*execlists->csb_write);
2191
2192 drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n",
2193 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),
2194 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI),
2195 read, write, num_entries);
2196
2197 if (read >= num_entries)
2198 read = 0;
2199 if (write >= num_entries)
2200 write = 0;
2201 if (read > write)
2202 write += num_entries;
2203 while (read < write) {
2204 idx = ++read % num_entries;
2205 drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
2206 idx, hws[idx * 2], hws[idx * 2 + 1]);
2207 }
2208
2209 i915_sched_engine_active_lock_bh(engine->sched_engine);
2210 rcu_read_lock();
2211 for (port = execlists->active; (rq = *port); port++) {
2212 char hdr[160];
2213 int len;
2214
2215 len = scnprintf(hdr, sizeof(hdr),
2216 "\t\tActive[%d]: ccid:%08x%s%s, ",
2217 (int)(port - execlists->active),
2218 rq->context->lrc.ccid,
2219 intel_context_is_closed(rq->context) ? "!" : "",
2220 intel_context_is_banned(rq->context) ? "*" : "");
2221 len += print_ring(hdr + len, sizeof(hdr) - len, rq);
2222 scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
2223 i915_request_show(m, rq, hdr, 0);
2224 }
2225 for (port = execlists->pending; (rq = *port); port++) {
2226 char hdr[160];
2227 int len;
2228
2229 len = scnprintf(hdr, sizeof(hdr),
2230 "\t\tPending[%d]: ccid:%08x%s%s, ",
2231 (int)(port - execlists->pending),
2232 rq->context->lrc.ccid,
2233 intel_context_is_closed(rq->context) ? "!" : "",
2234 intel_context_is_banned(rq->context) ? "*" : "");
2235 len += print_ring(hdr + len, sizeof(hdr) - len, rq);
2236 scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
2237 i915_request_show(m, rq, hdr, 0);
2238 }
2239 rcu_read_unlock();
2240 i915_sched_engine_active_unlock_bh(engine->sched_engine);
2241 } else if (GRAPHICS_VER(i915) > 6) {
2242 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
2243 ENGINE_READ(engine, RING_PP_DIR_BASE));
2244 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
2245 ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
2246 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
2247 ENGINE_READ(engine, RING_PP_DIR_DCLV));
2248 }
2249}
2250
2251static void print_request_ring(struct drm_printer *m, struct i915_request *rq)
2252{
2253 struct i915_vma_resource *vma_res = rq->batch_res;
2254 void *ring;
2255 int size;
2256
2257 drm_printf(m,
2258 "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
2259 rq->head, rq->postfix, rq->tail,
2260 vma_res ? upper_32_bits(vma_res->start) : ~0u,
2261 vma_res ? lower_32_bits(vma_res->start) : ~0u);
2262
2263 size = rq->tail - rq->head;
2264 if (rq->tail < rq->head)
2265 size += rq->ring->size;
2266
2267 ring = kmalloc(size, GFP_ATOMIC);
2268 if (ring) {
2269 const void *vaddr = rq->ring->vaddr;
2270 unsigned int head = rq->head;
2271 unsigned int len = 0;
2272
2273 if (rq->tail < head) {
2274 len = rq->ring->size - head;
2275 memcpy(ring, vaddr + head, len);
2276 head = 0;
2277 }
2278 memcpy(ring + len, vaddr + head, size - len);
2279
2280 hexdump(m, ring, size);
2281 kfree(ring);
2282 }
2283}
2284
2285static unsigned long read_ul(void *p, size_t x)
2286{
2287 return *(unsigned long *)(p + x);
2288}
2289
2290static void print_properties(struct intel_engine_cs *engine,
2291 struct drm_printer *m)
2292{
2293 static const struct pmap {
2294 size_t offset;
2295 const char *name;
2296 } props[] = {
2297#define P(x) { \
2298 .offset = offsetof(typeof(engine->props), x), \
2299 .name = #x \
2300}
2301 P(heartbeat_interval_ms),
2302 P(max_busywait_duration_ns),
2303 P(preempt_timeout_ms),
2304 P(stop_timeout_ms),
2305 P(timeslice_duration_ms),
2306
2307 {},
2308#undef P
2309 };
2310 const struct pmap *p;
2311
2312 drm_printf(m, "\tProperties:\n");
2313 for (p = props; p->name; p++)
2314 drm_printf(m, "\t\t%s: %lu [default %lu]\n",
2315 p->name,
2316 read_ul(&engine->props, p->offset),
2317 read_ul(&engine->defaults, p->offset));
2318}
2319
2320static void engine_dump_request(struct i915_request *rq, struct drm_printer *m, const char *msg)
2321{
2322 struct intel_timeline *tl = get_timeline(rq);
2323
2324 i915_request_show(m, rq, msg, 0);
2325
2326 drm_printf(m, "\t\tring->start: 0x%08x\n",
2327 i915_ggtt_offset(rq->ring->vma));
2328 drm_printf(m, "\t\tring->head: 0x%08x\n",
2329 rq->ring->head);
2330 drm_printf(m, "\t\tring->tail: 0x%08x\n",
2331 rq->ring->tail);
2332 drm_printf(m, "\t\tring->emit: 0x%08x\n",
2333 rq->ring->emit);
2334 drm_printf(m, "\t\tring->space: 0x%08x\n",
2335 rq->ring->space);
2336
2337 if (tl) {
2338 drm_printf(m, "\t\tring->hwsp: 0x%08x\n",
2339 tl->hwsp_offset);
2340 intel_timeline_put(tl);
2341 }
2342
2343 print_request_ring(m, rq);
2344
2345 if (rq->context->lrc_reg_state) {
2346 drm_printf(m, "Logical Ring Context:\n");
2347 hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE);
2348 }
2349}
2350
2351void intel_engine_dump_active_requests(struct list_head *requests,
2352 struct i915_request *hung_rq,
2353 struct drm_printer *m)
2354{
2355 struct i915_request *rq;
2356 const char *msg;
2357 enum i915_request_state state;
2358
2359 list_for_each_entry(rq, requests, sched.link) {
2360 if (rq == hung_rq)
2361 continue;
2362
2363 state = i915_test_request_state(rq);
2364 if (state < I915_REQUEST_QUEUED)
2365 continue;
2366
2367 if (state == I915_REQUEST_ACTIVE)
2368 msg = "\t\tactive on engine";
2369 else
2370 msg = "\t\tactive in queue";
2371
2372 engine_dump_request(rq, m, msg);
2373 }
2374}
2375
2376static void engine_dump_active_requests(struct intel_engine_cs *engine,
2377 struct drm_printer *m)
2378{
2379 struct intel_context *hung_ce = NULL;
2380 struct i915_request *hung_rq = NULL;
2381
2382 /*
2383 * No need for an engine->irq_seqno_barrier() before the seqno reads.
2384 * The GPU is still running so requests are still executing and any
2385 * hardware reads will be out of date by the time they are reported.
2386 * But the intention here is just to report an instantaneous snapshot
2387 * so that's fine.
2388 */
2389 intel_engine_get_hung_entity(engine, &hung_ce, &hung_rq);
2390
2391 drm_printf(m, "\tRequests:\n");
2392
2393 if (hung_rq)
2394 engine_dump_request(hung_rq, m, "\t\thung");
2395 else if (hung_ce)
2396 drm_printf(m, "\t\tGot hung ce but no hung rq!\n");
2397
2398 if (intel_uc_uses_guc_submission(&engine->gt->uc))
2399 intel_guc_dump_active_requests(engine, hung_rq, m);
2400 else
2401 intel_execlists_dump_active_requests(engine, hung_rq, m);
2402
2403 if (hung_rq)
2404 i915_request_put(hung_rq);
2405}
2406
2407void intel_engine_dump(struct intel_engine_cs *engine,
2408 struct drm_printer *m,
2409 const char *header, ...)
2410{
2411 struct i915_gpu_error * const error = &engine->i915->gpu_error;
2412 struct i915_request *rq;
2413 intel_wakeref_t wakeref;
2414 ktime_t dummy;
2415
2416 if (header) {
2417 va_list ap;
2418
2419 va_start(ap, header);
2420 drm_vprintf(m, header, &ap);
2421 va_end(ap);
2422 }
2423
2424 if (intel_gt_is_wedged(engine->gt))
2425 drm_printf(m, "*** WEDGED ***\n");
2426
2427 drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));
2428 drm_printf(m, "\tBarriers?: %s\n",
2429 str_yes_no(!llist_empty(&engine->barrier_tasks)));
2430 drm_printf(m, "\tLatency: %luus\n",
2431 ewma__engine_latency_read(&engine->latency));
2432 if (intel_engine_supports_stats(engine))
2433 drm_printf(m, "\tRuntime: %llums\n",
2434 ktime_to_ms(intel_engine_get_busy_time(engine,
2435 &dummy)));
2436 drm_printf(m, "\tForcewake: %x domains, %d active\n",
2437 engine->fw_domain, READ_ONCE(engine->fw_active));
2438
2439 rcu_read_lock();
2440 rq = READ_ONCE(engine->heartbeat.systole);
2441 if (rq)
2442 drm_printf(m, "\tHeartbeat: %d ms ago\n",
2443 jiffies_to_msecs(jiffies - rq->emitted_jiffies));
2444 rcu_read_unlock();
2445 drm_printf(m, "\tReset count: %d (global %d)\n",
2446 i915_reset_engine_count(error, engine),
2447 i915_reset_count(error));
2448 print_properties(engine, m);
2449
2450 engine_dump_active_requests(engine, m);
2451
2452 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base);
2453 wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm);
2454 if (wakeref) {
2455 intel_engine_print_registers(engine, m);
2456 intel_runtime_pm_put(engine->uncore->rpm, wakeref);
2457 } else {
2458 drm_printf(m, "\tDevice is asleep; skipping register dump\n");
2459 }
2460
2461 intel_execlists_show_requests(engine, m, i915_request_show, 8);
2462
2463 drm_printf(m, "HWSP:\n");
2464 hexdump(m, engine->status_page.addr, PAGE_SIZE);
2465
2466 drm_printf(m, "Idle? %s\n", str_yes_no(intel_engine_is_idle(engine)));
2467
2468 intel_engine_print_breadcrumbs(engine, m);
2469}
2470
2471/**
2472 * intel_engine_get_busy_time() - Return current accumulated engine busyness
2473 * @engine: engine to report on
2474 * @now: monotonic timestamp of sampling
2475 *
2476 * Returns accumulated time @engine was busy since engine stats were enabled.
2477 */
2478ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now)
2479{
2480 return engine->busyness(engine, now);
2481}
2482
2483struct intel_context *
2484intel_engine_create_virtual(struct intel_engine_cs **siblings,
2485 unsigned int count, unsigned long flags)
2486{
2487 if (count == 0)
2488 return ERR_PTR(-EINVAL);
2489
2490 if (count == 1 && !(flags & FORCE_VIRTUAL))
2491 return intel_context_create(siblings[0]);
2492
2493 GEM_BUG_ON(!siblings[0]->cops->create_virtual);
2494 return siblings[0]->cops->create_virtual(siblings, count, flags);
2495}
2496
2497static struct i915_request *engine_execlist_find_hung_request(struct intel_engine_cs *engine)
2498{
2499 struct i915_request *request, *active = NULL;
2500
2501 /*
2502 * This search does not work in GuC submission mode. However, the GuC
2503 * will report the hanging context directly to the driver itself. So
2504 * the driver should never get here when in GuC mode.
2505 */
2506 GEM_BUG_ON(intel_uc_uses_guc_submission(&engine->gt->uc));
2507
2508 /*
2509 * We are called by the error capture, reset and to dump engine
2510 * state at random points in time. In particular, note that neither is
2511 * crucially ordered with an interrupt. After a hang, the GPU is dead
2512 * and we assume that no more writes can happen (we waited long enough
2513 * for all writes that were in transaction to be flushed) - adding an
2514 * extra delay for a recent interrupt is pointless. Hence, we do
2515 * not need an engine->irq_seqno_barrier() before the seqno reads.
2516 * At all other times, we must assume the GPU is still running, but
2517 * we only care about the snapshot of this moment.
2518 */
2519 lockdep_assert_held(&engine->sched_engine->lock);
2520
2521 rcu_read_lock();
2522 request = execlists_active(&engine->execlists);
2523 if (request) {
2524 struct intel_timeline *tl = request->context->timeline;
2525
2526 list_for_each_entry_from_reverse(request, &tl->requests, link) {
2527 if (__i915_request_is_complete(request))
2528 break;
2529
2530 active = request;
2531 }
2532 }
2533 rcu_read_unlock();
2534 if (active)
2535 return active;
2536
2537 list_for_each_entry(request, &engine->sched_engine->requests,
2538 sched.link) {
2539 if (i915_test_request_state(request) != I915_REQUEST_ACTIVE)
2540 continue;
2541
2542 active = request;
2543 break;
2544 }
2545
2546 return active;
2547}
2548
2549void intel_engine_get_hung_entity(struct intel_engine_cs *engine,
2550 struct intel_context **ce, struct i915_request **rq)
2551{
2552 unsigned long flags;
2553
2554 *ce = intel_engine_get_hung_context(engine);
2555 if (*ce) {
2556 intel_engine_clear_hung_context(engine);
2557
2558 *rq = intel_context_get_active_request(*ce);
2559 return;
2560 }
2561
2562 /*
2563 * Getting here with GuC enabled means it is a forced error capture
2564 * with no actual hang. So, no need to attempt the execlist search.
2565 */
2566 if (intel_uc_uses_guc_submission(&engine->gt->uc))
2567 return;
2568
2569 spin_lock_irqsave(&engine->sched_engine->lock, flags);
2570 *rq = engine_execlist_find_hung_request(engine);
2571 if (*rq)
2572 *rq = i915_request_get_rcu(*rq);
2573 spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
2574}
2575
2576void xehp_enable_ccs_engines(struct intel_engine_cs *engine)
2577{
2578 /*
2579 * If there are any non-fused-off CCS engines, we need to enable CCS
2580 * support in the RCU_MODE register. This only needs to be done once,
2581 * so for simplicity we'll take care of this in the RCS engine's
2582 * resume handler; since the RCS and all CCS engines belong to the
2583 * same reset domain and are reset together, this will also take care
2584 * of re-applying the setting after i915-triggered resets.
2585 */
2586 if (!CCS_MASK(engine->gt))
2587 return;
2588
2589 intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
2590 _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
2591}
2592
2593#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2594#include "mock_engine.c"
2595#include "selftest_engine.c"
2596#include "selftest_engine_cs.c"
2597#endif