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1/* SPDX-License-Identifier: GPL-1.0+ */
2
3/* Generic NS8390 register definitions. */
4
5/* This file is part of Donald Becker's 8390 drivers, and is distributed
6 * under the same license. Auto-loading of 8390.o only in v2.2 - Paul G.
7 * Some of these names and comments originated from the Crynwr
8 * packet drivers, which are distributed under the GPL.
9 */
10
11#ifndef _8390_h
12#define _8390_h
13
14#include <linux/if_ether.h>
15#include <linux/ioport.h>
16#include <linux/irqreturn.h>
17#include <linux/skbuff.h>
18
19#define TX_PAGES 12 /* Two Tx slots */
20
21/* The 8390 specific per-packet-header format. */
22struct e8390_pkt_hdr {
23 unsigned char status; /* status */
24 unsigned char next; /* pointer to next packet. */
25 unsigned short count; /* header + packet length in bytes */
26};
27
28#ifdef CONFIG_NET_POLL_CONTROLLER
29void ei_poll(struct net_device *dev);
30void eip_poll(struct net_device *dev);
31#endif
32
33
34/* Without I/O delay - non ISA or later chips */
35void NS8390_init(struct net_device *dev, int startp);
36int ei_open(struct net_device *dev);
37int ei_close(struct net_device *dev);
38irqreturn_t ei_interrupt(int irq, void *dev_id);
39void ei_tx_timeout(struct net_device *dev, unsigned int txqueue);
40netdev_tx_t ei_start_xmit(struct sk_buff *skb, struct net_device *dev);
41void ei_set_multicast_list(struct net_device *dev);
42struct net_device_stats *ei_get_stats(struct net_device *dev);
43
44extern const struct net_device_ops ei_netdev_ops;
45
46struct net_device *__alloc_ei_netdev(int size);
47static inline struct net_device *alloc_ei_netdev(void)
48{
49 return __alloc_ei_netdev(0);
50}
51
52/* With I/O delay form */
53void NS8390p_init(struct net_device *dev, int startp);
54int eip_open(struct net_device *dev);
55int eip_close(struct net_device *dev);
56irqreturn_t eip_interrupt(int irq, void *dev_id);
57void eip_tx_timeout(struct net_device *dev, unsigned int txqueue);
58netdev_tx_t eip_start_xmit(struct sk_buff *skb, struct net_device *dev);
59void eip_set_multicast_list(struct net_device *dev);
60struct net_device_stats *eip_get_stats(struct net_device *dev);
61
62extern const struct net_device_ops eip_netdev_ops;
63
64struct net_device *__alloc_eip_netdev(int size);
65static inline struct net_device *alloc_eip_netdev(void)
66{
67 return __alloc_eip_netdev(0);
68}
69
70/* You have one of these per-board */
71struct ei_device {
72 const char *name;
73 void (*reset_8390)(struct net_device *dev);
74 void (*get_8390_hdr)(struct net_device *dev,
75 struct e8390_pkt_hdr *hdr, int ring_page);
76 void (*block_output)(struct net_device *dev, int count,
77 const unsigned char *buf, int start_page);
78 void (*block_input)(struct net_device *dev, int count,
79 struct sk_buff *skb, int ring_offset);
80 unsigned long rmem_start;
81 unsigned long rmem_end;
82 void __iomem *mem;
83 unsigned char mcfilter[8];
84 unsigned open:1;
85 unsigned word16:1; /* We have the 16-bit (vs 8-bit)
86 * version of the card.
87 */
88 unsigned bigendian:1; /* 16-bit big endian mode. Do NOT
89 * set this on random 8390 clones!
90 */
91 unsigned txing:1; /* Transmit Active */
92 unsigned irqlock:1; /* 8390's intrs disabled when '1'. */
93 unsigned dmaing:1; /* Remote DMA Active */
94 unsigned char tx_start_page, rx_start_page, stop_page;
95 unsigned char current_page; /* Read pointer in buffer */
96 unsigned char interface_num; /* Net port (AUI, 10bT.) to use. */
97 unsigned char txqueue; /* Tx Packet buffer queue length. */
98 short tx1, tx2; /* Packet lengths for ping-pong tx. */
99 short lasttx; /* Alpha version consistency check. */
100 unsigned char reg0; /* Register '0' in a WD8013 */
101 unsigned char reg5; /* Register '5' in a WD8013 */
102 unsigned char saved_irq; /* Original dev->irq value. */
103 u32 *reg_offset; /* Register mapping table */
104 spinlock_t page_lock; /* Page register locks */
105 unsigned long priv; /* Private field to store bus IDs etc. */
106 u32 msg_enable; /* debug message level */
107#ifdef AX88796_PLATFORM
108 unsigned char rxcr_base; /* default value for RXCR */
109#endif
110};
111
112/* The maximum number of 8390 interrupt service routines called per IRQ. */
113#define MAX_SERVICE 12
114
115/* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */
116#define TX_TIMEOUT (20*HZ/100)
117
118#define ei_status (*(struct ei_device *)netdev_priv(dev))
119
120/* Some generic ethernet register configurations. */
121#define E8390_TX_IRQ_MASK 0xa /* For register EN0_ISR */
122#define E8390_RX_IRQ_MASK 0x5
123
124#ifdef AX88796_PLATFORM
125#define E8390_RXCONFIG (ei_status.rxcr_base | 0x04)
126#define E8390_RXOFF (ei_status.rxcr_base | 0x20)
127#else
128/* EN0_RXCR: broadcasts, no multicast,errors */
129#define E8390_RXCONFIG 0x4
130/* EN0_RXCR: Accept no packets */
131#define E8390_RXOFF 0x20
132#endif
133
134/* EN0_TXCR: Normal transmit mode */
135#define E8390_TXCONFIG 0x00
136/* EN0_TXCR: Transmitter off */
137#define E8390_TXOFF 0x02
138
139
140/* Register accessed at EN_CMD, the 8390 base addr. */
141#define E8390_STOP 0x01 /* Stop and reset the chip */
142#define E8390_START 0x02 /* Start the chip, clear reset */
143#define E8390_TRANS 0x04 /* Transmit a frame */
144#define E8390_RREAD 0x08 /* Remote read */
145#define E8390_RWRITE 0x10 /* Remote write */
146#define E8390_NODMA 0x20 /* Remote DMA */
147#define E8390_PAGE0 0x00 /* Select page chip registers */
148#define E8390_PAGE1 0x40 /* using the two high-order bits */
149#define E8390_PAGE2 0x80 /* Page 3 is invalid. */
150
151/* Only generate indirect loads given a machine that needs them.
152 * - removed AMIGA_PCMCIA from this list, handled as ISA io now
153 * - the _p for generates no delay by default 8390p.c overrides this.
154 */
155
156#ifndef ei_inb
157#define ei_inb(_p) inb(_p)
158#define ei_outb(_v, _p) outb(_v, _p)
159#define ei_inb_p(_p) inb(_p)
160#define ei_outb_p(_v, _p) outb(_v, _p)
161#endif
162
163#ifndef EI_SHIFT
164#define EI_SHIFT(x) (x)
165#endif
166
167#define E8390_CMD EI_SHIFT(0x00) /* The command register (for all pages) */
168/* Page 0 register offsets. */
169#define EN0_CLDALO EI_SHIFT(0x01) /* Low byte of current local dma addr RD */
170#define EN0_STARTPG EI_SHIFT(0x01) /* Starting page of ring bfr WR */
171#define EN0_CLDAHI EI_SHIFT(0x02) /* High byte of current local dma addr RD */
172#define EN0_STOPPG EI_SHIFT(0x02) /* Ending page +1 of ring bfr WR */
173#define EN0_BOUNDARY EI_SHIFT(0x03) /* Boundary page of ring bfr RD WR */
174#define EN0_TSR EI_SHIFT(0x04) /* Transmit status reg RD */
175#define EN0_TPSR EI_SHIFT(0x04) /* Transmit starting page WR */
176#define EN0_NCR EI_SHIFT(0x05) /* Number of collision reg RD */
177#define EN0_TCNTLO EI_SHIFT(0x05) /* Low byte of tx byte count WR */
178#define EN0_FIFO EI_SHIFT(0x06) /* FIFO RD */
179#define EN0_TCNTHI EI_SHIFT(0x06) /* High byte of tx byte count WR */
180#define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */
181#define EN0_CRDALO EI_SHIFT(0x08) /* low byte of current remote dma address RD */
182#define EN0_RSARLO EI_SHIFT(0x08) /* Remote start address reg 0 */
183#define EN0_CRDAHI EI_SHIFT(0x09) /* high byte, current remote dma address RD */
184#define EN0_RSARHI EI_SHIFT(0x09) /* Remote start address reg 1 */
185#define EN0_RCNTLO EI_SHIFT(0x0a) /* Remote byte count reg WR */
186#define EN0_RCNTHI EI_SHIFT(0x0b) /* Remote byte count reg WR */
187#define EN0_RSR EI_SHIFT(0x0c) /* rx status reg RD */
188#define EN0_RXCR EI_SHIFT(0x0c) /* RX configuration reg WR */
189#define EN0_TXCR EI_SHIFT(0x0d) /* TX configuration reg WR */
190#define EN0_COUNTER0 EI_SHIFT(0x0d) /* Rcv alignment error counter RD */
191#define EN0_DCFG EI_SHIFT(0x0e) /* Data configuration reg WR */
192#define EN0_COUNTER1 EI_SHIFT(0x0e) /* Rcv CRC error counter RD */
193#define EN0_IMR EI_SHIFT(0x0f) /* Interrupt mask reg WR */
194#define EN0_COUNTER2 EI_SHIFT(0x0f) /* Rcv missed frame error counter RD */
195
196/* Bits in EN0_ISR - Interrupt status register */
197#define ENISR_RX 0x01 /* Receiver, no error */
198#define ENISR_TX 0x02 /* Transmitter, no error */
199#define ENISR_RX_ERR 0x04 /* Receiver, with error */
200#define ENISR_TX_ERR 0x08 /* Transmitter, with error */
201#define ENISR_OVER 0x10 /* Receiver overwrote the ring */
202#define ENISR_COUNTERS 0x20 /* Counters need emptying */
203#define ENISR_RDC 0x40 /* remote dma complete */
204#define ENISR_RESET 0x80 /* Reset completed */
205#define ENISR_ALL 0x3f /* Interrupts we will enable */
206
207/* Bits in EN0_DCFG - Data config register */
208#define ENDCFG_WTS 0x01 /* word transfer mode selection */
209#define ENDCFG_BOS 0x02 /* byte order selection */
210
211/* Page 1 register offsets. */
212#define EN1_PHYS EI_SHIFT(0x01) /* This board's physical enet addr RD WR */
213#define EN1_PHYS_SHIFT(i) EI_SHIFT(i+1) /* Get and set mac address */
214#define EN1_CURPAG EI_SHIFT(0x07) /* Current memory page RD WR */
215#define EN1_MULT EI_SHIFT(0x08) /* Multicast filter mask array (8 bytes) RD WR */
216#define EN1_MULT_SHIFT(i) EI_SHIFT(8+i) /* Get and set multicast filter */
217
218/* Bits in received packet status byte and EN0_RSR*/
219#define ENRSR_RXOK 0x01 /* Received a good packet */
220#define ENRSR_CRC 0x02 /* CRC error */
221#define ENRSR_FAE 0x04 /* frame alignment error */
222#define ENRSR_FO 0x08 /* FIFO overrun */
223#define ENRSR_MPA 0x10 /* missed pkt */
224#define ENRSR_PHY 0x20 /* physical/multicast address */
225#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
226#define ENRSR_DEF 0x80 /* deferring */
227
228/* Transmitted packet status, EN0_TSR. */
229#define ENTSR_PTX 0x01 /* Packet transmitted without error */
230#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
231#define ENTSR_COL 0x04 /* The transmit collided at least once. */
232#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
233#define ENTSR_CRS 0x10 /* The carrier sense was lost. */
234#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
235#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
236#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
237
238#endif /* _8390_h */