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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 | /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2023 MediaTek Inc. * Author: Yunfei Dong <yunfei.dong@mediatek.com> */ #ifndef _MTK_VCODEC_COM_DRV_H_ #define _MTK_VCODEC_COM_DRV_H_ #include <linux/platform_device.h> #include <linux/videodev2.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> #include <media/v4l2-ioctl.h> #include <media/v4l2-mem2mem.h> #include <media/videobuf2-core.h> #define MTK_VCODEC_MAX_PLANES 3 #define WAIT_INTR_TIMEOUT_MS 1000 /* * enum mtk_q_type - Type of queue */ enum mtk_q_type { MTK_Q_DATA_SRC = 0, MTK_Q_DATA_DST = 1, }; /* * enum mtk_hw_reg_idx - MTK hw register base index */ enum mtk_hw_reg_idx { VDEC_SYS, VDEC_MISC, VDEC_LD, VDEC_TOP, VDEC_CM, VDEC_AD, VDEC_AV, VDEC_PP, VDEC_HWD, VDEC_HWQ, VDEC_HWB, VDEC_HWG, NUM_MAX_VDEC_REG_BASE, /* h264 encoder */ VENC_SYS = NUM_MAX_VDEC_REG_BASE, /* vp8 encoder */ VENC_LT_SYS, NUM_MAX_VCODEC_REG_BASE }; /* * struct mtk_vcodec_clk_info - Structure used to store clock name */ struct mtk_vcodec_clk_info { const char *clk_name; struct clk *vcodec_clk; }; /* * struct mtk_vcodec_clk - Structure used to store vcodec clock information */ struct mtk_vcodec_clk { struct mtk_vcodec_clk_info *clk_info; int clk_num; }; /* * struct mtk_vcodec_pm - Power management data structure */ struct mtk_vcodec_pm { struct mtk_vcodec_clk vdec_clk; struct mtk_vcodec_clk venc_clk; struct device *dev; }; /* * enum mtk_vdec_hw_id - Hardware index used to separate * different hardware */ enum mtk_vdec_hw_id { MTK_VDEC_CORE, MTK_VDEC_LAT0, MTK_VDEC_LAT1, MTK_VDEC_LAT_SOC, MTK_VDEC_HW_MAX, }; /** * enum mtk_instance_state - The state of an MTK Vcodec instance. * @MTK_STATE_FREE: default state when instance is created * @MTK_STATE_INIT: vcodec instance is initialized * @MTK_STATE_HEADER: vdec had sps/pps header parsed or venc * had sps/pps header encoded * @MTK_STATE_FLUSH: vdec is flushing. Only used by decoder * @MTK_STATE_ABORT: vcodec should be aborted */ enum mtk_instance_state { MTK_STATE_FREE = 0, MTK_STATE_INIT = 1, MTK_STATE_HEADER = 2, MTK_STATE_FLUSH = 3, MTK_STATE_ABORT = 4, }; enum mtk_fmt_type { MTK_FMT_DEC = 0, MTK_FMT_ENC = 1, MTK_FMT_FRAME = 2, }; /* * struct mtk_video_fmt - Structure used to store information about pixelformats */ struct mtk_video_fmt { u32 fourcc; enum mtk_fmt_type type; u32 num_planes; u32 flags; struct v4l2_frmsize_stepwise frmsize; }; /* * struct mtk_q_data - Structure used to store information about queue */ struct mtk_q_data { unsigned int visible_width; unsigned int visible_height; unsigned int coded_width; unsigned int coded_height; enum v4l2_field field; unsigned int bytesperline[MTK_VCODEC_MAX_PLANES]; unsigned int sizeimage[MTK_VCODEC_MAX_PLANES]; const struct mtk_video_fmt *fmt; }; /* * enum mtk_instance_type - The type of an MTK Vcodec instance. */ enum mtk_instance_type { MTK_INST_DECODER = 0, MTK_INST_ENCODER = 1, }; #endif /* _MTK_VCODEC_COM_DRV_H_ */ |