1Freescale Peripheral Management Access Unit (PAMU) Device Tree Binding
  2
  3DESCRIPTION
  4
  5The PAMU is an I/O MMU that provides device-to-memory access control and
  6address translation capabilities.
  7
  8Required properties:
  9
 10- compatible	: <string>
 11		  First entry is a version-specific string, such as
 12		  "fsl,pamu-v1.0".  The second is "fsl,pamu".
 13- ranges	: <prop-encoded-array>
 14		  A standard property. Utilized to describe the memory mapped
 15		  I/O space utilized by the controller.  The size should
 16		  be set to the total size of the register space of all
 17		  physically present PAMU controllers.  For example, for
 18		  PAMU v1.0, on an SOC that has five PAMU devices, the size
 19		  is 0x5000.
 20- interrupts	: <prop-encoded-array>
 21		  Interrupt mappings.  The first tuple is the normal PAMU
 22		  interrupt, used for reporting access violations.  The second
 23		  is for PAMU hardware errors, such as PAMU operation errors
 24		  and ECC errors.
 25- #address-cells: <u32>
 26		  A standard property.
 27- #size-cells	: <u32>
 28		  A standard property.
 29
 30Optional properties:
 31- reg		: <prop-encoded-array>
 32		  A standard property.   It represents the CCSR registers of
 33		  all child PAMUs combined.  Include it to provide support
 34		  for legacy drivers.
 35- fsl,portid-mapping : <u32>
 36		  The Coherency Subdomain ID Port Mapping Registers and
 37		  Snoop ID Port Mapping registers, which are part of the
 38		  CoreNet Coherency fabric (CCF), provide a CoreNet
 39		  Coherency Subdomain ID/CoreNet Snoop ID to pamu mapping
 40		  functions.  Certain bits from these registers should be
 41		  set if PAMUs should be snooped.  This property defines
 42		  a bitmask which selects the bits that should be set if
 43		  PAMUs should be snooped.
 44
 45Child nodes:
 46
 47Each child node represents one PAMU controller.  Each SOC device that is
 48connected to a specific PAMU device should have a "fsl,pamu-phandle" property
 49that links to the corresponding specific child PAMU controller.
 50
 51- reg		: <prop-encoded-array>
 52		  A standard property.  Specifies the physical address and
 53		  length (relative to the parent 'ranges' property) of this
 54		  PAMU controller's configuration registers.  The size should
 55		  be set to the size of this PAMU controllers's register space.
 56		  For PAMU v1.0, this size is 0x1000.
 57- fsl,primary-cache-geometry
 58		: <prop-encoded-array>
 59		  Two cells that specify the geometry of the primary PAMU
 60		  cache.  The first is the number of cache lines, and the
 61		  second is the number of "ways".  For direct-mapped caches,
 62		  specify a value of 1.
 63- fsl,secondary-cache-geometry
 64		: <prop-encoded-array>
 65		  Two cells that specify the geometry of the secondary PAMU
 66		  cache.  The first is the number of cache lines, and the
 67		  second is the number of "ways".  For direct-mapped caches,
 68		  specify a value of 1.
 69
 70Device nodes:
 71
 72Devices that have LIODNs need to specify links to the parent PAMU controller
 73(the actual PAMU controller that this device is connected to) and a pointer to
 74the LIODN register, if applicable.
 75
 76- fsl,iommu-parent
 77		: <phandle>
 78		Phandle to the single, specific PAMU controller node to which
 79		this device is connect.  The PAMU topology is represented in
 80		the device tree to assist code that dynamically determines the
 81		best LIODN values to minimize PAMU cache thrashing.
 82
 83- fsl,liodn-reg : <prop-encoded-array>
 84		  Two cells that specify the location of the LIODN register
 85		  for this device.  Required for devices that have a single
 86		  LIODN.  The first cell is a phandle to a node that contains
 87		  the registers where the LIODN is to be set.  The second is
 88		  the offset from the first "reg" resource of the node where
 89		  the specific LIODN register is located.
 90
 91
 92Example:
 93
 94	iommu@20000 {
 95		compatible = "fsl,pamu-v1.0", "fsl,pamu";
 96		reg = <0x20000 0x5000>;
 97		ranges = <0 0x20000 0x5000>;
 98		fsl,portid-mapping = <0xf80000>;
 99		#address-cells = <1>;
100		#size-cells = <1>;
101		interrupts = <
102			24 2 0 0
103			16 2 1 30>;
104
105		pamu0: pamu@0 {
106			reg = <0 0x1000>;
107			fsl,primary-cache-geometry = <32 1>;
108			fsl,secondary-cache-geometry = <128 2>;
109		};
110
111		pamu1: pamu@1000 {
112			reg = <0x1000 0x1000>;
113			fsl,primary-cache-geometry = <32 1>;
114			fsl,secondary-cache-geometry = <128 2>;
115		};
116
117		pamu2: pamu@2000 {
118			reg = <0x2000 0x1000>;
119			fsl,primary-cache-geometry = <32 1>;
120			fsl,secondary-cache-geometry = <128 2>;
121		};
122
123		pamu3: pamu@3000 {
124			reg = <0x3000 0x1000>;
125			fsl,primary-cache-geometry = <32 1>;
126			fsl,secondary-cache-geometry = <128 2>;
127		};
128
129		pamu4: pamu@4000 {
130			reg = <0x4000 0x1000>;
131			fsl,primary-cache-geometry = <32 1>;
132			fsl,secondary-cache-geometry = <128 2>;
133		};
134	};
135
136	guts: global-utilities@e0000 {
137		compatible = "fsl,qoriq-device-config-1.0";
138		reg = <0xe0000 0xe00>;
139		fsl,has-rstcr;
140		#sleep-cells = <1>;
141		fsl,liodn-bits = <12>;
142	};
143
144/include/ "qoriq-dma-0.dtsi"
145	dma@100300 {
146		fsl,iommu-parent = <&pamu0>;
147		fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
148	};