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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Thunderbolt driver - NHI registers
4 *
5 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
6 * Copyright (C) 2018, Intel Corporation
7 */
8
9#ifndef NHI_REGS_H_
10#define NHI_REGS_H_
11
12#include <linux/types.h>
13
14enum ring_flags {
15 RING_FLAG_ISOCH_ENABLE = 1 << 27, /* TX only? */
16 RING_FLAG_E2E_FLOW_CONTROL = 1 << 28,
17 RING_FLAG_PCI_NO_SNOOP = 1 << 29,
18 RING_FLAG_RAW = 1 << 30, /* ignore EOF/SOF mask, include checksum */
19 RING_FLAG_ENABLE = 1 << 31,
20};
21
22/**
23 * struct ring_desc - TX/RX ring entry
24 *
25 * For TX set length/eof/sof.
26 * For RX length/eof/sof are set by the NHI.
27 */
28struct ring_desc {
29 u64 phys;
30 u32 length:12;
31 u32 eof:4;
32 u32 sof:4;
33 enum ring_desc_flags flags:12;
34 u32 time; /* write zero */
35} __packed;
36
37/* NHI registers in bar 0 */
38
39/*
40 * 16 bytes per entry, one entry for every hop (REG_CAPS)
41 * 00: physical pointer to an array of struct ring_desc
42 * 08: ring tail (set by NHI)
43 * 10: ring head (index of first non posted descriptor)
44 * 12: descriptor count
45 */
46#define REG_TX_RING_BASE 0x00000
47
48/*
49 * 16 bytes per entry, one entry for every hop (REG_CAPS)
50 * 00: physical pointer to an array of struct ring_desc
51 * 08: ring head (index of first not posted descriptor)
52 * 10: ring tail (set by NHI)
53 * 12: descriptor count
54 * 14: max frame sizes (anything larger than 0x100 has no effect)
55 */
56#define REG_RX_RING_BASE 0x08000
57
58/*
59 * 32 bytes per entry, one entry for every hop (REG_CAPS)
60 * 00: enum_ring_flags
61 * 04: isoch time stamp ?? (write 0)
62 * ..: unknown
63 */
64#define REG_TX_OPTIONS_BASE 0x19800
65
66/*
67 * 32 bytes per entry, one entry for every hop (REG_CAPS)
68 * 00: enum ring_flags
69 * If RING_FLAG_E2E_FLOW_CONTROL is set then bits 13-23 must be set to
70 * the corresponding TX hop id.
71 * 04: EOF/SOF mask (ignored for RING_FLAG_RAW rings)
72 * ..: unknown
73 */
74#define REG_RX_OPTIONS_BASE 0x29800
75#define REG_RX_OPTIONS_E2E_HOP_MASK GENMASK(22, 12)
76#define REG_RX_OPTIONS_E2E_HOP_SHIFT 12
77
78/*
79 * three bitfields: tx, rx, rx overflow
80 * Every bitfield contains one bit for every hop (REG_CAPS).
81 * New interrupts are fired only after ALL registers have been
82 * read (even those containing only disabled rings).
83 */
84#define REG_RING_NOTIFY_BASE 0x37800
85#define RING_NOTIFY_REG_COUNT(nhi) ((31 + 3 * nhi->hop_count) / 32)
86#define REG_RING_INT_CLEAR 0x37808
87
88/*
89 * two bitfields: rx, tx
90 * Both bitfields contains one bit for every hop (REG_CAPS). To
91 * enable/disable interrupts set/clear the corresponding bits.
92 */
93#define REG_RING_INTERRUPT_BASE 0x38200
94#define RING_INTERRUPT_REG_COUNT(nhi) ((31 + 2 * nhi->hop_count) / 32)
95
96#define REG_RING_INTERRUPT_MASK_CLEAR_BASE 0x38208
97
98#define REG_INT_THROTTLING_RATE 0x38c00
99
100/* Interrupt Vector Allocation */
101#define REG_INT_VEC_ALLOC_BASE 0x38c40
102#define REG_INT_VEC_ALLOC_BITS 4
103#define REG_INT_VEC_ALLOC_MASK GENMASK(3, 0)
104#define REG_INT_VEC_ALLOC_REGS (32 / REG_INT_VEC_ALLOC_BITS)
105
106/* The last 11 bits contain the number of hops supported by the NHI port. */
107#define REG_CAPS 0x39640
108#define REG_CAPS_VERSION_MASK GENMASK(23, 16)
109#define REG_CAPS_VERSION_2 0x40
110
111#define REG_DMA_MISC 0x39864
112#define REG_DMA_MISC_INT_AUTO_CLEAR BIT(2)
113#define REG_DMA_MISC_DISABLE_AUTO_CLEAR BIT(17)
114
115#define REG_RESET 0x39898
116#define REG_RESET_HRR BIT(0)
117
118#define REG_INMAIL_DATA 0x39900
119
120#define REG_INMAIL_CMD 0x39904
121#define REG_INMAIL_CMD_MASK GENMASK(7, 0)
122#define REG_INMAIL_ERROR BIT(30)
123#define REG_INMAIL_OP_REQUEST BIT(31)
124
125#define REG_OUTMAIL_CMD 0x3990c
126#define REG_OUTMAIL_CMD_OPMODE_SHIFT 8
127#define REG_OUTMAIL_CMD_OPMODE_MASK GENMASK(11, 8)
128
129#define REG_FW_STS 0x39944
130#define REG_FW_STS_NVM_AUTH_DONE BIT(31)
131#define REG_FW_STS_CIO_RESET_REQ BIT(30)
132#define REG_FW_STS_ICM_EN_CPU BIT(2)
133#define REG_FW_STS_ICM_EN_INVERT BIT(1)
134#define REG_FW_STS_ICM_EN BIT(0)
135
136/* ICL NHI VSEC registers */
137
138/* FW ready */
139#define VS_CAP_9 0xc8
140#define VS_CAP_9_FW_READY BIT(31)
141/* UUID */
142#define VS_CAP_10 0xcc
143#define VS_CAP_11 0xd0
144/* LTR */
145#define VS_CAP_15 0xe0
146#define VS_CAP_16 0xe4
147/* TBT2PCIe */
148#define VS_CAP_18 0xec
149#define VS_CAP_18_DONE BIT(0)
150/* PCIe2TBT */
151#define VS_CAP_19 0xf0
152#define VS_CAP_19_VALID BIT(0)
153#define VS_CAP_19_CMD_SHIFT 1
154#define VS_CAP_19_CMD_MASK GENMASK(7, 1)
155/* Force power */
156#define VS_CAP_22 0xfc
157#define VS_CAP_22_FORCE_POWER BIT(1)
158#define VS_CAP_22_DMA_DELAY_MASK GENMASK(31, 24)
159#define VS_CAP_22_DMA_DELAY_SHIFT 24
160
161/**
162 * enum icl_lc_mailbox_cmd - ICL specific LC mailbox commands
163 * @ICL_LC_GO2SX: Ask LC to enter Sx without wake
164 * @ICL_LC_GO2SX_NO_WAKE: Ask LC to enter Sx with wake
165 * @ICL_LC_PREPARE_FOR_RESET: Prepare LC for reset
166 */
167enum icl_lc_mailbox_cmd {
168 ICL_LC_GO2SX = 0x02,
169 ICL_LC_GO2SX_NO_WAKE = 0x03,
170 ICL_LC_PREPARE_FOR_RESET = 0x21,
171};
172
173#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Thunderbolt driver - NHI registers
4 *
5 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
6 * Copyright (C) 2018, Intel Corporation
7 */
8
9#ifndef NHI_REGS_H_
10#define NHI_REGS_H_
11
12#include <linux/types.h>
13
14enum ring_flags {
15 RING_FLAG_ISOCH_ENABLE = 1 << 27, /* TX only? */
16 RING_FLAG_E2E_FLOW_CONTROL = 1 << 28,
17 RING_FLAG_PCI_NO_SNOOP = 1 << 29,
18 RING_FLAG_RAW = 1 << 30, /* ignore EOF/SOF mask, include checksum */
19 RING_FLAG_ENABLE = 1 << 31,
20};
21
22/**
23 * struct ring_desc - TX/RX ring entry
24 *
25 * For TX set length/eof/sof.
26 * For RX length/eof/sof are set by the NHI.
27 */
28struct ring_desc {
29 u64 phys;
30 u32 length:12;
31 u32 eof:4;
32 u32 sof:4;
33 enum ring_desc_flags flags:12;
34 u32 time; /* write zero */
35} __packed;
36
37/* NHI registers in bar 0 */
38
39/*
40 * 16 bytes per entry, one entry for every hop (REG_CAPS)
41 * 00: physical pointer to an array of struct ring_desc
42 * 08: ring tail (set by NHI)
43 * 10: ring head (index of first non posted descriptor)
44 * 12: descriptor count
45 */
46#define REG_TX_RING_BASE 0x00000
47
48/*
49 * 16 bytes per entry, one entry for every hop (REG_CAPS)
50 * 00: physical pointer to an array of struct ring_desc
51 * 08: ring head (index of first not posted descriptor)
52 * 10: ring tail (set by NHI)
53 * 12: descriptor count
54 * 14: max frame sizes (anything larger than 0x100 has no effect)
55 */
56#define REG_RX_RING_BASE 0x08000
57
58/*
59 * 32 bytes per entry, one entry for every hop (REG_CAPS)
60 * 00: enum_ring_flags
61 * 04: isoch time stamp ?? (write 0)
62 * ..: unknown
63 */
64#define REG_TX_OPTIONS_BASE 0x19800
65
66/*
67 * 32 bytes per entry, one entry for every hop (REG_CAPS)
68 * 00: enum ring_flags
69 * If RING_FLAG_E2E_FLOW_CONTROL is set then bits 13-23 must be set to
70 * the corresponding TX hop id.
71 * 04: EOF/SOF mask (ignored for RING_FLAG_RAW rings)
72 * ..: unknown
73 */
74#define REG_RX_OPTIONS_BASE 0x29800
75#define REG_RX_OPTIONS_E2E_HOP_MASK GENMASK(22, 12)
76#define REG_RX_OPTIONS_E2E_HOP_SHIFT 12
77
78/*
79 * three bitfields: tx, rx, rx overflow
80 * Every bitfield contains one bit for every hop (REG_CAPS).
81 * New interrupts are fired only after ALL registers have been
82 * read (even those containing only disabled rings).
83 */
84#define REG_RING_NOTIFY_BASE 0x37800
85#define RING_NOTIFY_REG_COUNT(nhi) ((31 + 3 * nhi->hop_count) / 32)
86#define REG_RING_INT_CLEAR 0x37808
87
88/*
89 * two bitfields: rx, tx
90 * Both bitfields contains one bit for every hop (REG_CAPS). To
91 * enable/disable interrupts set/clear the corresponding bits.
92 */
93#define REG_RING_INTERRUPT_BASE 0x38200
94#define RING_INTERRUPT_REG_COUNT(nhi) ((31 + 2 * nhi->hop_count) / 32)
95
96#define REG_RING_INTERRUPT_MASK_CLEAR_BASE 0x38208
97
98#define REG_INT_THROTTLING_RATE 0x38c00
99
100/* Interrupt Vector Allocation */
101#define REG_INT_VEC_ALLOC_BASE 0x38c40
102#define REG_INT_VEC_ALLOC_BITS 4
103#define REG_INT_VEC_ALLOC_MASK GENMASK(3, 0)
104#define REG_INT_VEC_ALLOC_REGS (32 / REG_INT_VEC_ALLOC_BITS)
105
106/* The last 11 bits contain the number of hops supported by the NHI port. */
107#define REG_CAPS 0x39640
108#define REG_CAPS_VERSION_MASK GENMASK(23, 16)
109#define REG_CAPS_VERSION_2 0x40
110
111#define REG_DMA_MISC 0x39864
112#define REG_DMA_MISC_INT_AUTO_CLEAR BIT(2)
113#define REG_DMA_MISC_DISABLE_AUTO_CLEAR BIT(17)
114
115#define REG_RESET 0x39898
116#define REG_RESET_HRR BIT(0)
117
118#define REG_INMAIL_DATA 0x39900
119
120#define REG_INMAIL_CMD 0x39904
121#define REG_INMAIL_CMD_MASK GENMASK(7, 0)
122#define REG_INMAIL_ERROR BIT(30)
123#define REG_INMAIL_OP_REQUEST BIT(31)
124
125#define REG_OUTMAIL_CMD 0x3990c
126#define REG_OUTMAIL_CMD_OPMODE_SHIFT 8
127#define REG_OUTMAIL_CMD_OPMODE_MASK GENMASK(11, 8)
128
129#define REG_FW_STS 0x39944
130#define REG_FW_STS_NVM_AUTH_DONE BIT(31)
131#define REG_FW_STS_CIO_RESET_REQ BIT(30)
132#define REG_FW_STS_ICM_EN_CPU BIT(2)
133#define REG_FW_STS_ICM_EN_INVERT BIT(1)
134#define REG_FW_STS_ICM_EN BIT(0)
135
136/* ICL NHI VSEC registers */
137
138/* FW ready */
139#define VS_CAP_9 0xc8
140#define VS_CAP_9_FW_READY BIT(31)
141/* UUID */
142#define VS_CAP_10 0xcc
143#define VS_CAP_11 0xd0
144/* LTR */
145#define VS_CAP_15 0xe0
146#define VS_CAP_16 0xe4
147/* TBT2PCIe */
148#define VS_CAP_18 0xec
149#define VS_CAP_18_DONE BIT(0)
150/* PCIe2TBT */
151#define VS_CAP_19 0xf0
152#define VS_CAP_19_VALID BIT(0)
153#define VS_CAP_19_CMD_SHIFT 1
154#define VS_CAP_19_CMD_MASK GENMASK(7, 1)
155/* Force power */
156#define VS_CAP_22 0xfc
157#define VS_CAP_22_FORCE_POWER BIT(1)
158#define VS_CAP_22_DMA_DELAY_MASK GENMASK(31, 24)
159#define VS_CAP_22_DMA_DELAY_SHIFT 24
160
161/**
162 * enum icl_lc_mailbox_cmd - ICL specific LC mailbox commands
163 * @ICL_LC_GO2SX: Ask LC to enter Sx without wake
164 * @ICL_LC_GO2SX_NO_WAKE: Ask LC to enter Sx with wake
165 * @ICL_LC_PREPARE_FOR_RESET: Prepare LC for reset
166 */
167enum icl_lc_mailbox_cmd {
168 ICL_LC_GO2SX = 0x02,
169 ICL_LC_GO2SX_NO_WAKE = 0x03,
170 ICL_LC_PREPARE_FOR_RESET = 0x21,
171};
172
173#endif