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1/* SPDX-License-Identifier: ISC */
2/*
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2016 Qualcomm Atheros, Inc.
5 */
6
7#ifndef __TARGADDRS_H__
8#define __TARGADDRS_H__
9
10#include "hw.h"
11
12/*
13 * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
14 * host_interest structure. It must match the address of the _host_interest
15 * symbol (see linker script).
16 *
17 * Host Interest is shared between Host and Target in order to coordinate
18 * between the two, and is intended to remain constant (with additions only
19 * at the end) across software releases.
20 *
21 * All addresses are available here so that it's possible to
22 * write a single binary that works with all Target Types.
23 * May be used in assembler code as well as C.
24 */
25#define QCA988X_HOST_INTEREST_ADDRESS 0x00400800
26#define HOST_INTEREST_MAX_SIZE 0x200
27
28/*
29 * These are items that the Host may need to access via BMI or via the
30 * Diagnostic Window. The position of items in this structure must remain
31 * constant across firmware revisions! Types for each item must be fixed
32 * size across target and host platforms. More items may be added at the end.
33 */
34struct host_interest {
35 /*
36 * Pointer to application-defined area, if any.
37 * Set by Target application during startup.
38 */
39 u32 hi_app_host_interest; /* 0x00 */
40
41 /* Pointer to register dump area, valid after Target crash. */
42 u32 hi_failure_state; /* 0x04 */
43
44 /* Pointer to debug logging header */
45 u32 hi_dbglog_hdr; /* 0x08 */
46
47 u32 hi_unused0c; /* 0x0c */
48
49 /*
50 * General-purpose flag bits, similar to SOC_OPTION_* flags.
51 * Can be used by application rather than by OS.
52 */
53 u32 hi_option_flag; /* 0x10 */
54
55 /*
56 * Boolean that determines whether or not to
57 * display messages on the serial port.
58 */
59 u32 hi_serial_enable; /* 0x14 */
60
61 /* Start address of DataSet index, if any */
62 u32 hi_dset_list_head; /* 0x18 */
63
64 /* Override Target application start address */
65 u32 hi_app_start; /* 0x1c */
66
67 /* Clock and voltage tuning */
68 u32 hi_skip_clock_init; /* 0x20 */
69 u32 hi_core_clock_setting; /* 0x24 */
70 u32 hi_cpu_clock_setting; /* 0x28 */
71 u32 hi_system_sleep_setting; /* 0x2c */
72 u32 hi_xtal_control_setting; /* 0x30 */
73 u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
74 u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
75 u32 hi_ref_voltage_trim_setting; /* 0x3c */
76 u32 hi_clock_info; /* 0x40 */
77
78 /* Host uses BE CPU or not */
79 u32 hi_be; /* 0x44 */
80
81 u32 hi_stack; /* normal stack */ /* 0x48 */
82 u32 hi_err_stack; /* error stack */ /* 0x4c */
83 u32 hi_desired_cpu_speed_hz; /* 0x50 */
84
85 /* Pointer to Board Data */
86 u32 hi_board_data; /* 0x54 */
87
88 /*
89 * Indication of Board Data state:
90 * 0: board data is not yet initialized.
91 * 1: board data is initialized; unknown size
92 * >1: number of bytes of initialized board data
93 */
94 u32 hi_board_data_initialized; /* 0x58 */
95
96 u32 hi_dset_ram_index_table; /* 0x5c */
97
98 u32 hi_desired_baud_rate; /* 0x60 */
99 u32 hi_dbglog_config; /* 0x64 */
100 u32 hi_end_ram_reserve_sz; /* 0x68 */
101 u32 hi_mbox_io_block_sz; /* 0x6c */
102
103 u32 hi_num_bpatch_streams; /* 0x70 -- unused */
104 u32 hi_mbox_isr_yield_limit; /* 0x74 */
105
106 u32 hi_refclk_hz; /* 0x78 */
107 u32 hi_ext_clk_detected; /* 0x7c */
108 u32 hi_dbg_uart_txpin; /* 0x80 */
109 u32 hi_dbg_uart_rxpin; /* 0x84 */
110 u32 hi_hci_uart_baud; /* 0x88 */
111 u32 hi_hci_uart_pin_assignments; /* 0x8C */
112
113 u32 hi_hci_uart_baud_scale_val; /* 0x90 */
114 u32 hi_hci_uart_baud_step_val; /* 0x94 */
115
116 u32 hi_allocram_start; /* 0x98 */
117 u32 hi_allocram_sz; /* 0x9c */
118 u32 hi_hci_bridge_flags; /* 0xa0 */
119 u32 hi_hci_uart_support_pins; /* 0xa4 */
120
121 u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
122
123 /*
124 * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
125 * [31:16]: wakeup timeout in ms
126 */
127 /* Pointer to extended board Data */
128 u32 hi_board_ext_data; /* 0xac */
129 u32 hi_board_ext_data_config; /* 0xb0 */
130 /*
131 * Bit [0] : valid
132 * Bit[31:16: size
133 */
134 /*
135 * hi_reset_flag is used to do some stuff when target reset.
136 * such as restore app_start after warm reset or
137 * preserve host Interest area, or preserve ROM data, literals etc.
138 */
139 u32 hi_reset_flag; /* 0xb4 */
140 /* indicate hi_reset_flag is valid */
141 u32 hi_reset_flag_valid; /* 0xb8 */
142 u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */
143 /* 0xbc - [31:0]: idle timeout in ms */
144 /* ACS flags */
145 u32 hi_acs_flags; /* 0xc0 */
146 u32 hi_console_flags; /* 0xc4 */
147 u32 hi_nvram_state; /* 0xc8 */
148 u32 hi_option_flag2; /* 0xcc */
149
150 /* If non-zero, override values sent to Host in WMI_READY event. */
151 u32 hi_sw_version_override; /* 0xd0 */
152 u32 hi_abi_version_override; /* 0xd4 */
153
154 /*
155 * Percentage of high priority RX traffic to total expected RX traffic
156 * applicable only to ar6004
157 */
158 u32 hi_hp_rx_traffic_ratio; /* 0xd8 */
159
160 /* test applications flags */
161 u32 hi_test_apps_related; /* 0xdc */
162 /* location of test script */
163 u32 hi_ota_testscript; /* 0xe0 */
164 /* location of CAL data */
165 u32 hi_cal_data; /* 0xe4 */
166
167 /* Number of packet log buffers */
168 u32 hi_pktlog_num_buffers; /* 0xe8 */
169
170 /* wow extension configuration */
171 u32 hi_wow_ext_config; /* 0xec */
172 u32 hi_pwr_save_flags; /* 0xf0 */
173
174 /* Spatial Multiplexing Power Save (SMPS) options */
175 u32 hi_smps_options; /* 0xf4 */
176
177 /* Interconnect-specific state */
178 u32 hi_interconnect_state; /* 0xf8 */
179
180 /* Coex configuration flags */
181 u32 hi_coex_config; /* 0xfc */
182
183 /* Early allocation support */
184 u32 hi_early_alloc; /* 0x100 */
185 /* FW swap field */
186 /*
187 * Bits of this 32bit word will be used to pass specific swap
188 * instruction to FW
189 */
190 /*
191 * Bit 0 -- AP Nart descriptor no swap. When this bit is set
192 * FW will not swap TX descriptor. Meaning packets are formed
193 * on the target processor.
194 */
195 /* Bit 1 - unused */
196 u32 hi_fw_swap; /* 0x104 */
197
198 /* global arenas pointer address, used by host driver debug */
199 u32 hi_dynamic_mem_arenas_addr; /* 0x108 */
200
201 /* allocated bytes of DRAM use by allocated */
202 u32 hi_dynamic_mem_allocated; /* 0x10C */
203
204 /* remaining bytes of DRAM */
205 u32 hi_dynamic_mem_remaining; /* 0x110 */
206
207 /* memory track count, configured by host */
208 u32 hi_dynamic_mem_track_max; /* 0x114 */
209
210 /* minidump buffer */
211 u32 hi_minidump; /* 0x118 */
212
213 /* bdata's sig and key addr */
214 u32 hi_bd_sig_key; /* 0x11c */
215} __packed;
216
217#define HI_ITEM(item) offsetof(struct host_interest, item)
218
219/* Bits defined in hi_option_flag */
220
221/* Enable timer workaround */
222#define HI_OPTION_TIMER_WAR 0x01
223/* Limit BMI command credits */
224#define HI_OPTION_BMI_CRED_LIMIT 0x02
225/* Relay Dot11 hdr to/from host */
226#define HI_OPTION_RELAY_DOT11_HDR 0x04
227/* MAC addr method 0-locally administred 1-globally unique addrs */
228#define HI_OPTION_MAC_ADDR_METHOD 0x08
229/* Firmware Bridging */
230#define HI_OPTION_FW_BRIDGE 0x10
231/* Enable CPU profiling */
232#define HI_OPTION_ENABLE_PROFILE 0x20
233/* Disable debug logging */
234#define HI_OPTION_DISABLE_DBGLOG 0x40
235/* Skip Era Tracking */
236#define HI_OPTION_SKIP_ERA_TRACKING 0x80
237/* Disable PAPRD (debug) */
238#define HI_OPTION_PAPRD_DISABLE 0x100
239#define HI_OPTION_NUM_DEV_LSB 0x200
240#define HI_OPTION_NUM_DEV_MSB 0x800
241#define HI_OPTION_DEV_MODE_LSB 0x1000
242#define HI_OPTION_DEV_MODE_MSB 0x8000000
243/* Disable LowFreq Timer Stabilization */
244#define HI_OPTION_NO_LFT_STBL 0x10000000
245/* Skip regulatory scan */
246#define HI_OPTION_SKIP_REG_SCAN 0x20000000
247/*
248 * Do regulatory scan during init before
249 * sending WMI ready event to host
250 */
251#define HI_OPTION_INIT_REG_SCAN 0x40000000
252
253/* REV6: Do not adjust memory map */
254#define HI_OPTION_SKIP_MEMMAP 0x80000000
255
256#define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3
257
258/* 2 bits of hi_option_flag are used to represent 3 modes */
259#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */
260#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
261#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */
262#define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */
263
264/* 2 bits of hi_option flag are usedto represent 4 submodes */
265#define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */
266#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */
267#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */
268#define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */
269
270/* Num dev Mask */
271#define HI_OPTION_NUM_DEV_MASK 0x7
272#define HI_OPTION_NUM_DEV_SHIFT 0x9
273
274/* firmware bridging */
275#define HI_OPTION_FW_BRIDGE_SHIFT 0x04
276
277/*
278 * Fw Mode/SubMode Mask
279 *-----------------------------------------------------------------------------
280 * SUB | SUB | SUB | SUB | | | |
281 *MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0]
282 * (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2)
283 *-----------------------------------------------------------------------------
284 */
285#define HI_OPTION_FW_MODE_BITS 0x2
286#define HI_OPTION_FW_MODE_MASK 0x3
287#define HI_OPTION_FW_MODE_SHIFT 0xC
288#define HI_OPTION_ALL_FW_MODE_MASK 0xFF
289
290#define HI_OPTION_FW_SUBMODE_BITS 0x2
291#define HI_OPTION_FW_SUBMODE_MASK 0x3
292#define HI_OPTION_FW_SUBMODE_SHIFT 0x14
293#define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00
294#define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8
295
296/* hi_option_flag2 options */
297#define HI_OPTION_OFFLOAD_AMSDU 0x01
298#define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */
299#define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature*/
300#define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */
301#define HI_OPTION_EARLY_CFG_DONE 0x10 /* Early configuration is complete */
302
303#define HI_OPTION_RF_KILL_SHIFT 0x2
304#define HI_OPTION_RF_KILL_MASK 0x1
305
306/* hi_reset_flag */
307/* preserve App Start address */
308#define HI_RESET_FLAG_PRESERVE_APP_START 0x01
309/* preserve host interest */
310#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02
311/* preserve ROM data */
312#define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04
313#define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08
314#define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10
315#define HI_RESET_FLAG_WARM_RESET 0x20
316
317/* define hi_fw_swap bits */
318#define HI_DESC_IN_FW_BIT 0x01
319
320/* indicate the reset flag is valid */
321#define HI_RESET_FLAG_IS_VALID 0x12345678
322
323/* ACS is enabled */
324#define HI_ACS_FLAGS_ENABLED (1 << 0)
325/* Use physical WWAN device */
326#define HI_ACS_FLAGS_USE_WWAN (1 << 1)
327/* Use test VAP */
328#define HI_ACS_FLAGS_TEST_VAP (1 << 2)
329/* SDIO/mailbox ACS flag definitions */
330#define HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET (1 << 0)
331#define HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET (1 << 1)
332#define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE (1 << 2)
333#define HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_FW_ACK (1 << 16)
334#define HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_FW_ACK (1 << 17)
335
336/*
337 * If both SDIO_CRASH_DUMP_ENHANCEMENT_HOST and SDIO_CRASH_DUMP_ENHANCEMENT_FW
338 * flags are set, then crashdump upload will be done using the BMI host/target
339 * communication channel.
340 */
341/* HOST to support using BMI dump FW memory when hit assert */
342#define HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST 0x400
343
344/* FW to support using BMI dump FW memory when hit assert */
345#define HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_FW 0x800
346
347/*
348 * CONSOLE FLAGS
349 *
350 * Bit Range Meaning
351 * --------- --------------------------------
352 * 2..0 UART ID (0 = Default)
353 * 3 Baud Select (0 = 9600, 1 = 115200)
354 * 30..4 Reserved
355 * 31 Enable Console
356 *
357 */
358
359#define HI_CONSOLE_FLAGS_ENABLE (1 << 31)
360#define HI_CONSOLE_FLAGS_UART_MASK (0x7)
361#define HI_CONSOLE_FLAGS_UART_SHIFT 0
362#define HI_CONSOLE_FLAGS_BAUD_SELECT (1 << 3)
363
364/* SM power save options */
365#define HI_SMPS_ALLOW_MASK (0x00000001)
366#define HI_SMPS_MODE_MASK (0x00000002)
367#define HI_SMPS_MODE_STATIC (0x00000000)
368#define HI_SMPS_MODE_DYNAMIC (0x00000002)
369#define HI_SMPS_DISABLE_AUTO_MODE (0x00000004)
370#define HI_SMPS_DATA_THRESH_MASK (0x000007f8)
371#define HI_SMPS_DATA_THRESH_SHIFT (3)
372#define HI_SMPS_RSSI_THRESH_MASK (0x0007f800)
373#define HI_SMPS_RSSI_THRESH_SHIFT (11)
374#define HI_SMPS_LOWPWR_CM_MASK (0x00380000)
375#define HI_SMPS_LOWPWR_CM_SHIFT (15)
376#define HI_SMPS_HIPWR_CM_MASK (0x03c00000)
377#define HI_SMPS_HIPWR_CM_SHIFT (19)
378
379/*
380 * WOW Extension configuration
381 *
382 * Bit Range Meaning
383 * --------- --------------------------------
384 * 8..0 Size of each WOW pattern (max 511)
385 * 15..9 Number of patterns per list (max 127)
386 * 17..16 Number of lists (max 4)
387 * 30..18 Reserved
388 * 31 Enabled
389 *
390 * set values (except enable) to zeros for default settings
391 */
392
393#define HI_WOW_EXT_ENABLED_MASK (1 << 31)
394#define HI_WOW_EXT_NUM_LIST_SHIFT 16
395#define HI_WOW_EXT_NUM_LIST_MASK (0x3 << HI_WOW_EXT_NUM_LIST_SHIFT)
396#define HI_WOW_EXT_NUM_PATTERNS_SHIFT 9
397#define HI_WOW_EXT_NUM_PATTERNS_MASK (0x7F << HI_WOW_EXT_NUM_PATTERNS_SHIFT)
398#define HI_WOW_EXT_PATTERN_SIZE_SHIFT 0
399#define HI_WOW_EXT_PATTERN_SIZE_MASK (0x1FF << HI_WOW_EXT_PATTERN_SIZE_SHIFT)
400
401#define HI_WOW_EXT_MAKE_CONFIG(num_lists, count, size) \
402 ((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & \
403 HI_WOW_EXT_NUM_LIST_MASK) | \
404 (((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & \
405 HI_WOW_EXT_NUM_PATTERNS_MASK) | \
406 (((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & \
407 HI_WOW_EXT_PATTERN_SIZE_MASK))
408
409#define HI_WOW_EXT_GET_NUM_LISTS(config) \
410 (((config) & HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT)
411#define HI_WOW_EXT_GET_NUM_PATTERNS(config) \
412 (((config) & HI_WOW_EXT_NUM_PATTERNS_MASK) >> \
413 HI_WOW_EXT_NUM_PATTERNS_SHIFT)
414#define HI_WOW_EXT_GET_PATTERN_SIZE(config) \
415 (((config) & HI_WOW_EXT_PATTERN_SIZE_MASK) >> \
416 HI_WOW_EXT_PATTERN_SIZE_SHIFT)
417
418/*
419 * Early allocation configuration
420 * Support RAM bank configuration before BMI done and this eases the memory
421 * allocation at very early stage
422 * Bit Range Meaning
423 * --------- ----------------------------------
424 * [0:3] number of bank assigned to be IRAM
425 * [4:15] reserved
426 * [16:31] magic number
427 *
428 * Note:
429 * 1. target firmware would check magic number and if it's a match, firmware
430 * would consider the bits[0:15] are valid and base on that to calculate
431 * the end of DRAM. Early allocation would be located at that area and
432 * may be reclaimed when necessary
433 * 2. if no magic number is found, early allocation would happen at "_end"
434 * symbol of ROM which is located before the app-data and might NOT be
435 * re-claimable. If this is adopted, link script should keep this in
436 * mind to avoid data corruption.
437 */
438#define HI_EARLY_ALLOC_MAGIC 0x6d8a
439#define HI_EARLY_ALLOC_MAGIC_MASK 0xffff0000
440#define HI_EARLY_ALLOC_MAGIC_SHIFT 16
441#define HI_EARLY_ALLOC_IRAM_BANKS_MASK 0x0000000f
442#define HI_EARLY_ALLOC_IRAM_BANKS_SHIFT 0
443
444#define HI_EARLY_ALLOC_VALID() \
445 ((((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_MAGIC_MASK) >> \
446 HI_EARLY_ALLOC_MAGIC_SHIFT) == (HI_EARLY_ALLOC_MAGIC))
447#define HI_EARLY_ALLOC_GET_IRAM_BANKS() \
448 (((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_IRAM_BANKS_MASK) \
449 >> HI_EARLY_ALLOC_IRAM_BANKS_SHIFT)
450
451/*power save flag bit definitions*/
452#define HI_PWR_SAVE_LPL_ENABLED 0x1
453/*b1-b3 reserved*/
454/*b4-b5 : dev0 LPL type : 0 - none
455 * 1- Reduce Pwr Search
456 * 2- Reduce Pwr Listen
457 */
458/*b6-b7 : dev1 LPL type and so on for Max 8 devices*/
459#define HI_PWR_SAVE_LPL_DEV0_LSB 4
460#define HI_PWR_SAVE_LPL_DEV_MASK 0x3
461/*power save related utility macros*/
462#define HI_LPL_ENABLED() \
463 ((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED))
464#define HI_DEV_LPL_TYPE_GET(_devix) \
465 (HOST_INTEREST->hi_pwr_save_flags & ((HI_PWR_SAVE_LPL_DEV_MASK) << \
466 (HI_PWR_SAVE_LPL_DEV0_LSB + (_devix) * 2)))
467
468#define HOST_INTEREST_SMPS_IS_ALLOWED() \
469 ((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK))
470
471/* Reserve 1024 bytes for extended board data */
472#define QCA988X_BOARD_DATA_SZ 7168
473#define QCA988X_BOARD_EXT_DATA_SZ 0
474
475#define QCA9887_BOARD_DATA_SZ 7168
476#define QCA9887_BOARD_EXT_DATA_SZ 0
477
478#define QCA6174_BOARD_DATA_SZ 8192
479#define QCA6174_BOARD_EXT_DATA_SZ 0
480
481#define QCA9377_BOARD_DATA_SZ QCA6174_BOARD_DATA_SZ
482#define QCA9377_BOARD_EXT_DATA_SZ 0
483
484#define QCA99X0_BOARD_DATA_SZ 12288
485#define QCA99X0_BOARD_EXT_DATA_SZ 0
486
487/* Dual band extended board data */
488#define QCA99X0_EXT_BOARD_DATA_SZ 2048
489#define EXT_BOARD_ADDRESS_OFFSET 0x3000
490
491#define QCA4019_BOARD_DATA_SZ 12064
492#define QCA4019_BOARD_EXT_DATA_SZ 0
493
494#endif /* __TARGADDRS_H__ */
1/* SPDX-License-Identifier: ISC */
2/*
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2016 Qualcomm Atheros, Inc.
5 */
6
7#ifndef __TARGADDRS_H__
8#define __TARGADDRS_H__
9
10#include "hw.h"
11
12/*
13 * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
14 * host_interest structure. It must match the address of the _host_interest
15 * symbol (see linker script).
16 *
17 * Host Interest is shared between Host and Target in order to coordinate
18 * between the two, and is intended to remain constant (with additions only
19 * at the end) across software releases.
20 *
21 * All addresses are available here so that it's possible to
22 * write a single binary that works with all Target Types.
23 * May be used in assembler code as well as C.
24 */
25#define QCA988X_HOST_INTEREST_ADDRESS 0x00400800
26#define HOST_INTEREST_MAX_SIZE 0x200
27
28/*
29 * These are items that the Host may need to access via BMI or via the
30 * Diagnostic Window. The position of items in this structure must remain
31 * constant across firmware revisions! Types for each item must be fixed
32 * size across target and host platforms. More items may be added at the end.
33 */
34struct host_interest {
35 /*
36 * Pointer to application-defined area, if any.
37 * Set by Target application during startup.
38 */
39 u32 hi_app_host_interest; /* 0x00 */
40
41 /* Pointer to register dump area, valid after Target crash. */
42 u32 hi_failure_state; /* 0x04 */
43
44 /* Pointer to debug logging header */
45 u32 hi_dbglog_hdr; /* 0x08 */
46
47 u32 hi_unused0c; /* 0x0c */
48
49 /*
50 * General-purpose flag bits, similar to SOC_OPTION_* flags.
51 * Can be used by application rather than by OS.
52 */
53 u32 hi_option_flag; /* 0x10 */
54
55 /*
56 * Boolean that determines whether or not to
57 * display messages on the serial port.
58 */
59 u32 hi_serial_enable; /* 0x14 */
60
61 /* Start address of DataSet index, if any */
62 u32 hi_dset_list_head; /* 0x18 */
63
64 /* Override Target application start address */
65 u32 hi_app_start; /* 0x1c */
66
67 /* Clock and voltage tuning */
68 u32 hi_skip_clock_init; /* 0x20 */
69 u32 hi_core_clock_setting; /* 0x24 */
70 u32 hi_cpu_clock_setting; /* 0x28 */
71 u32 hi_system_sleep_setting; /* 0x2c */
72 u32 hi_xtal_control_setting; /* 0x30 */
73 u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
74 u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
75 u32 hi_ref_voltage_trim_setting; /* 0x3c */
76 u32 hi_clock_info; /* 0x40 */
77
78 /* Host uses BE CPU or not */
79 u32 hi_be; /* 0x44 */
80
81 u32 hi_stack; /* normal stack */ /* 0x48 */
82 u32 hi_err_stack; /* error stack */ /* 0x4c */
83 u32 hi_desired_cpu_speed_hz; /* 0x50 */
84
85 /* Pointer to Board Data */
86 u32 hi_board_data; /* 0x54 */
87
88 /*
89 * Indication of Board Data state:
90 * 0: board data is not yet initialized.
91 * 1: board data is initialized; unknown size
92 * >1: number of bytes of initialized board data
93 */
94 u32 hi_board_data_initialized; /* 0x58 */
95
96 u32 hi_dset_ram_index_table; /* 0x5c */
97
98 u32 hi_desired_baud_rate; /* 0x60 */
99 u32 hi_dbglog_config; /* 0x64 */
100 u32 hi_end_ram_reserve_sz; /* 0x68 */
101 u32 hi_mbox_io_block_sz; /* 0x6c */
102
103 u32 hi_num_bpatch_streams; /* 0x70 -- unused */
104 u32 hi_mbox_isr_yield_limit; /* 0x74 */
105
106 u32 hi_refclk_hz; /* 0x78 */
107 u32 hi_ext_clk_detected; /* 0x7c */
108 u32 hi_dbg_uart_txpin; /* 0x80 */
109 u32 hi_dbg_uart_rxpin; /* 0x84 */
110 u32 hi_hci_uart_baud; /* 0x88 */
111 u32 hi_hci_uart_pin_assignments; /* 0x8C */
112
113 u32 hi_hci_uart_baud_scale_val; /* 0x90 */
114 u32 hi_hci_uart_baud_step_val; /* 0x94 */
115
116 u32 hi_allocram_start; /* 0x98 */
117 u32 hi_allocram_sz; /* 0x9c */
118 u32 hi_hci_bridge_flags; /* 0xa0 */
119 u32 hi_hci_uart_support_pins; /* 0xa4 */
120
121 u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
122
123 /*
124 * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
125 * [31:16]: wakeup timeout in ms
126 */
127 /* Pointer to extended board Data */
128 u32 hi_board_ext_data; /* 0xac */
129 u32 hi_board_ext_data_config; /* 0xb0 */
130 /*
131 * Bit [0] : valid
132 * Bit[31:16: size
133 */
134 /*
135 * hi_reset_flag is used to do some stuff when target reset.
136 * such as restore app_start after warm reset or
137 * preserve host Interest area, or preserve ROM data, literals etc.
138 */
139 u32 hi_reset_flag; /* 0xb4 */
140 /* indicate hi_reset_flag is valid */
141 u32 hi_reset_flag_valid; /* 0xb8 */
142 u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */
143 /* 0xbc - [31:0]: idle timeout in ms */
144 /* ACS flags */
145 u32 hi_acs_flags; /* 0xc0 */
146 u32 hi_console_flags; /* 0xc4 */
147 u32 hi_nvram_state; /* 0xc8 */
148 u32 hi_option_flag2; /* 0xcc */
149
150 /* If non-zero, override values sent to Host in WMI_READY event. */
151 u32 hi_sw_version_override; /* 0xd0 */
152 u32 hi_abi_version_override; /* 0xd4 */
153
154 /*
155 * Percentage of high priority RX traffic to total expected RX traffic
156 * applicable only to ar6004
157 */
158 u32 hi_hp_rx_traffic_ratio; /* 0xd8 */
159
160 /* test applications flags */
161 u32 hi_test_apps_related; /* 0xdc */
162 /* location of test script */
163 u32 hi_ota_testscript; /* 0xe0 */
164 /* location of CAL data */
165 u32 hi_cal_data; /* 0xe4 */
166
167 /* Number of packet log buffers */
168 u32 hi_pktlog_num_buffers; /* 0xe8 */
169
170 /* wow extension configuration */
171 u32 hi_wow_ext_config; /* 0xec */
172 u32 hi_pwr_save_flags; /* 0xf0 */
173
174 /* Spatial Multiplexing Power Save (SMPS) options */
175 u32 hi_smps_options; /* 0xf4 */
176
177 /* Interconnect-specific state */
178 u32 hi_interconnect_state; /* 0xf8 */
179
180 /* Coex configuration flags */
181 u32 hi_coex_config; /* 0xfc */
182
183 /* Early allocation support */
184 u32 hi_early_alloc; /* 0x100 */
185 /* FW swap field */
186 /*
187 * Bits of this 32bit word will be used to pass specific swap
188 * instruction to FW
189 */
190 /*
191 * Bit 0 -- AP Nart descriptor no swap. When this bit is set
192 * FW will not swap TX descriptor. Meaning packets are formed
193 * on the target processor.
194 */
195 /* Bit 1 - unused */
196 u32 hi_fw_swap; /* 0x104 */
197
198 /* global arenas pointer address, used by host driver debug */
199 u32 hi_dynamic_mem_arenas_addr; /* 0x108 */
200
201 /* allocated bytes of DRAM use by allocated */
202 u32 hi_dynamic_mem_allocated; /* 0x10C */
203
204 /* remaining bytes of DRAM */
205 u32 hi_dynamic_mem_remaining; /* 0x110 */
206
207 /* memory track count, configured by host */
208 u32 hi_dynamic_mem_track_max; /* 0x114 */
209
210 /* minidump buffer */
211 u32 hi_minidump; /* 0x118 */
212
213 /* bdata's sig and key addr */
214 u32 hi_bd_sig_key; /* 0x11c */
215} __packed;
216
217#define HI_ITEM(item) offsetof(struct host_interest, item)
218
219/* Bits defined in hi_option_flag */
220
221/* Enable timer workaround */
222#define HI_OPTION_TIMER_WAR 0x01
223/* Limit BMI command credits */
224#define HI_OPTION_BMI_CRED_LIMIT 0x02
225/* Relay Dot11 hdr to/from host */
226#define HI_OPTION_RELAY_DOT11_HDR 0x04
227/* MAC addr method 0-locally administred 1-globally unique addrs */
228#define HI_OPTION_MAC_ADDR_METHOD 0x08
229/* Firmware Bridging */
230#define HI_OPTION_FW_BRIDGE 0x10
231/* Enable CPU profiling */
232#define HI_OPTION_ENABLE_PROFILE 0x20
233/* Disable debug logging */
234#define HI_OPTION_DISABLE_DBGLOG 0x40
235/* Skip Era Tracking */
236#define HI_OPTION_SKIP_ERA_TRACKING 0x80
237/* Disable PAPRD (debug) */
238#define HI_OPTION_PAPRD_DISABLE 0x100
239#define HI_OPTION_NUM_DEV_LSB 0x200
240#define HI_OPTION_NUM_DEV_MSB 0x800
241#define HI_OPTION_DEV_MODE_LSB 0x1000
242#define HI_OPTION_DEV_MODE_MSB 0x8000000
243/* Disable LowFreq Timer Stabilization */
244#define HI_OPTION_NO_LFT_STBL 0x10000000
245/* Skip regulatory scan */
246#define HI_OPTION_SKIP_REG_SCAN 0x20000000
247/*
248 * Do regulatory scan during init before
249 * sending WMI ready event to host
250 */
251#define HI_OPTION_INIT_REG_SCAN 0x40000000
252
253/* REV6: Do not adjust memory map */
254#define HI_OPTION_SKIP_MEMMAP 0x80000000
255
256#define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3
257
258/* 2 bits of hi_option_flag are used to represent 3 modes */
259#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */
260#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
261#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */
262#define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */
263
264/* 2 bits of hi_option flag are usedto represent 4 submodes */
265#define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */
266#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */
267#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */
268#define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */
269
270/* Num dev Mask */
271#define HI_OPTION_NUM_DEV_MASK 0x7
272#define HI_OPTION_NUM_DEV_SHIFT 0x9
273
274/* firmware bridging */
275#define HI_OPTION_FW_BRIDGE_SHIFT 0x04
276
277/*
278 * Fw Mode/SubMode Mask
279 *-----------------------------------------------------------------------------
280 * SUB | SUB | SUB | SUB | | | |
281 *MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0]
282 * (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2)
283 *-----------------------------------------------------------------------------
284 */
285#define HI_OPTION_FW_MODE_BITS 0x2
286#define HI_OPTION_FW_MODE_MASK 0x3
287#define HI_OPTION_FW_MODE_SHIFT 0xC
288#define HI_OPTION_ALL_FW_MODE_MASK 0xFF
289
290#define HI_OPTION_FW_SUBMODE_BITS 0x2
291#define HI_OPTION_FW_SUBMODE_MASK 0x3
292#define HI_OPTION_FW_SUBMODE_SHIFT 0x14
293#define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00
294#define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8
295
296/* hi_option_flag2 options */
297#define HI_OPTION_OFFLOAD_AMSDU 0x01
298#define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */
299#define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature*/
300#define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */
301#define HI_OPTION_EARLY_CFG_DONE 0x10 /* Early configuration is complete */
302
303#define HI_OPTION_RF_KILL_SHIFT 0x2
304#define HI_OPTION_RF_KILL_MASK 0x1
305
306/* hi_reset_flag */
307/* preserve App Start address */
308#define HI_RESET_FLAG_PRESERVE_APP_START 0x01
309/* preserve host interest */
310#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02
311/* preserve ROM data */
312#define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04
313#define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08
314#define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10
315#define HI_RESET_FLAG_WARM_RESET 0x20
316
317/* define hi_fw_swap bits */
318#define HI_DESC_IN_FW_BIT 0x01
319
320/* indicate the reset flag is valid */
321#define HI_RESET_FLAG_IS_VALID 0x12345678
322
323/* ACS is enabled */
324#define HI_ACS_FLAGS_ENABLED (1 << 0)
325/* Use physical WWAN device */
326#define HI_ACS_FLAGS_USE_WWAN (1 << 1)
327/* Use test VAP */
328#define HI_ACS_FLAGS_TEST_VAP (1 << 2)
329/* SDIO/mailbox ACS flag definitions */
330#define HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET (1 << 0)
331#define HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET (1 << 1)
332#define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE (1 << 2)
333#define HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_FW_ACK (1 << 16)
334#define HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_FW_ACK (1 << 17)
335
336/*
337 * If both SDIO_CRASH_DUMP_ENHANCEMENT_HOST and SDIO_CRASH_DUMP_ENHANCEMENT_FW
338 * flags are set, then crashdump upload will be done using the BMI host/target
339 * communication channel.
340 */
341/* HOST to support using BMI dump FW memory when hit assert */
342#define HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST 0x400
343
344/* FW to support using BMI dump FW memory when hit assert */
345#define HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_FW 0x800
346
347/*
348 * CONSOLE FLAGS
349 *
350 * Bit Range Meaning
351 * --------- --------------------------------
352 * 2..0 UART ID (0 = Default)
353 * 3 Baud Select (0 = 9600, 1 = 115200)
354 * 30..4 Reserved
355 * 31 Enable Console
356 *
357 */
358
359#define HI_CONSOLE_FLAGS_ENABLE (1 << 31)
360#define HI_CONSOLE_FLAGS_UART_MASK (0x7)
361#define HI_CONSOLE_FLAGS_UART_SHIFT 0
362#define HI_CONSOLE_FLAGS_BAUD_SELECT (1 << 3)
363
364/* SM power save options */
365#define HI_SMPS_ALLOW_MASK (0x00000001)
366#define HI_SMPS_MODE_MASK (0x00000002)
367#define HI_SMPS_MODE_STATIC (0x00000000)
368#define HI_SMPS_MODE_DYNAMIC (0x00000002)
369#define HI_SMPS_DISABLE_AUTO_MODE (0x00000004)
370#define HI_SMPS_DATA_THRESH_MASK (0x000007f8)
371#define HI_SMPS_DATA_THRESH_SHIFT (3)
372#define HI_SMPS_RSSI_THRESH_MASK (0x0007f800)
373#define HI_SMPS_RSSI_THRESH_SHIFT (11)
374#define HI_SMPS_LOWPWR_CM_MASK (0x00380000)
375#define HI_SMPS_LOWPWR_CM_SHIFT (15)
376#define HI_SMPS_HIPWR_CM_MASK (0x03c00000)
377#define HI_SMPS_HIPWR_CM_SHIFT (19)
378
379/*
380 * WOW Extension configuration
381 *
382 * Bit Range Meaning
383 * --------- --------------------------------
384 * 8..0 Size of each WOW pattern (max 511)
385 * 15..9 Number of patterns per list (max 127)
386 * 17..16 Number of lists (max 4)
387 * 30..18 Reserved
388 * 31 Enabled
389 *
390 * set values (except enable) to zeros for default settings
391 */
392
393#define HI_WOW_EXT_ENABLED_MASK (1 << 31)
394#define HI_WOW_EXT_NUM_LIST_SHIFT 16
395#define HI_WOW_EXT_NUM_LIST_MASK (0x3 << HI_WOW_EXT_NUM_LIST_SHIFT)
396#define HI_WOW_EXT_NUM_PATTERNS_SHIFT 9
397#define HI_WOW_EXT_NUM_PATTERNS_MASK (0x7F << HI_WOW_EXT_NUM_PATTERNS_SHIFT)
398#define HI_WOW_EXT_PATTERN_SIZE_SHIFT 0
399#define HI_WOW_EXT_PATTERN_SIZE_MASK (0x1FF << HI_WOW_EXT_PATTERN_SIZE_SHIFT)
400
401#define HI_WOW_EXT_MAKE_CONFIG(num_lists, count, size) \
402 ((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & \
403 HI_WOW_EXT_NUM_LIST_MASK) | \
404 (((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & \
405 HI_WOW_EXT_NUM_PATTERNS_MASK) | \
406 (((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & \
407 HI_WOW_EXT_PATTERN_SIZE_MASK))
408
409#define HI_WOW_EXT_GET_NUM_LISTS(config) \
410 (((config) & HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT)
411#define HI_WOW_EXT_GET_NUM_PATTERNS(config) \
412 (((config) & HI_WOW_EXT_NUM_PATTERNS_MASK) >> \
413 HI_WOW_EXT_NUM_PATTERNS_SHIFT)
414#define HI_WOW_EXT_GET_PATTERN_SIZE(config) \
415 (((config) & HI_WOW_EXT_PATTERN_SIZE_MASK) >> \
416 HI_WOW_EXT_PATTERN_SIZE_SHIFT)
417
418/*
419 * Early allocation configuration
420 * Support RAM bank configuration before BMI done and this eases the memory
421 * allocation at very early stage
422 * Bit Range Meaning
423 * --------- ----------------------------------
424 * [0:3] number of bank assigned to be IRAM
425 * [4:15] reserved
426 * [16:31] magic number
427 *
428 * Note:
429 * 1. target firmware would check magic number and if it's a match, firmware
430 * would consider the bits[0:15] are valid and base on that to calculate
431 * the end of DRAM. Early allocation would be located at that area and
432 * may be reclaimed when necessary
433 * 2. if no magic number is found, early allocation would happen at "_end"
434 * symbol of ROM which is located before the app-data and might NOT be
435 * re-claimable. If this is adopted, link script should keep this in
436 * mind to avoid data corruption.
437 */
438#define HI_EARLY_ALLOC_MAGIC 0x6d8a
439#define HI_EARLY_ALLOC_MAGIC_MASK 0xffff0000
440#define HI_EARLY_ALLOC_MAGIC_SHIFT 16
441#define HI_EARLY_ALLOC_IRAM_BANKS_MASK 0x0000000f
442#define HI_EARLY_ALLOC_IRAM_BANKS_SHIFT 0
443
444#define HI_EARLY_ALLOC_VALID() \
445 ((((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_MAGIC_MASK) >> \
446 HI_EARLY_ALLOC_MAGIC_SHIFT) == (HI_EARLY_ALLOC_MAGIC))
447#define HI_EARLY_ALLOC_GET_IRAM_BANKS() \
448 (((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_IRAM_BANKS_MASK) \
449 >> HI_EARLY_ALLOC_IRAM_BANKS_SHIFT)
450
451/*power save flag bit definitions*/
452#define HI_PWR_SAVE_LPL_ENABLED 0x1
453/*b1-b3 reserved*/
454/*b4-b5 : dev0 LPL type : 0 - none
455 * 1- Reduce Pwr Search
456 * 2- Reduce Pwr Listen
457 */
458/*b6-b7 : dev1 LPL type and so on for Max 8 devices*/
459#define HI_PWR_SAVE_LPL_DEV0_LSB 4
460#define HI_PWR_SAVE_LPL_DEV_MASK 0x3
461/*power save related utility macros*/
462#define HI_LPL_ENABLED() \
463 ((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED))
464#define HI_DEV_LPL_TYPE_GET(_devix) \
465 (HOST_INTEREST->hi_pwr_save_flags & ((HI_PWR_SAVE_LPL_DEV_MASK) << \
466 (HI_PWR_SAVE_LPL_DEV0_LSB + (_devix) * 2)))
467
468#define HOST_INTEREST_SMPS_IS_ALLOWED() \
469 ((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK))
470
471/* Reserve 1024 bytes for extended board data */
472#define QCA988X_BOARD_DATA_SZ 7168
473#define QCA988X_BOARD_EXT_DATA_SZ 0
474
475#define QCA9887_BOARD_DATA_SZ 7168
476#define QCA9887_BOARD_EXT_DATA_SZ 0
477
478#define QCA6174_BOARD_DATA_SZ 8192
479#define QCA6174_BOARD_EXT_DATA_SZ 0
480
481#define QCA9377_BOARD_DATA_SZ QCA6174_BOARD_DATA_SZ
482#define QCA9377_BOARD_EXT_DATA_SZ 0
483
484#define QCA99X0_BOARD_DATA_SZ 12288
485#define QCA99X0_BOARD_EXT_DATA_SZ 0
486
487/* Dual band extended board data */
488#define QCA99X0_EXT_BOARD_DATA_SZ 2048
489#define EXT_BOARD_ADDRESS_OFFSET 0x3000
490
491#define QCA4019_BOARD_DATA_SZ 12064
492#define QCA4019_BOARD_EXT_DATA_SZ 0
493
494#define WCN3990_BOARD_DATA_SZ 26328
495#define WCN3990_BOARD_EXT_DATA_SZ 0
496
497#endif /* __TARGADDRS_H__ */