Loading...
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2017 Marvell
4 *
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
6 */
7
8#ifndef __SAFEXCEL_H__
9#define __SAFEXCEL_H__
10
11#include <crypto/aead.h>
12#include <crypto/algapi.h>
13#include <crypto/internal/hash.h>
14#include <crypto/sha1.h>
15#include <crypto/sha2.h>
16#include <crypto/sha3.h>
17#include <crypto/skcipher.h>
18#include <linux/types.h>
19
20#define EIP197_HIA_VERSION_BE 0xca35
21#define EIP197_HIA_VERSION_LE 0x35ca
22#define EIP97_VERSION_LE 0x9e61
23#define EIP196_VERSION_LE 0x3bc4
24#define EIP197_VERSION_LE 0x3ac5
25#define EIP96_VERSION_LE 0x9f60
26#define EIP201_VERSION_LE 0x36c9
27#define EIP206_VERSION_LE 0x31ce
28#define EIP207_VERSION_LE 0x30cf
29#define EIP197_REG_LO16(reg) (reg & 0xffff)
30#define EIP197_REG_HI16(reg) ((reg >> 16) & 0xffff)
31#define EIP197_VERSION_MASK(reg) ((reg >> 16) & 0xfff)
32#define EIP197_VERSION_SWAP(reg) (((reg & 0xf0) << 4) | \
33 ((reg >> 4) & 0xf0) | \
34 ((reg >> 12) & 0xf))
35
36/* EIP197 HIA OPTIONS ENCODING */
37#define EIP197_HIA_OPT_HAS_PE_ARB BIT(29)
38
39/* EIP206 OPTIONS ENCODING */
40#define EIP206_OPT_ICE_TYPE(n) ((n>>8)&3)
41#define EIP206_OPT_OCE_TYPE(n) ((n>>10)&3)
42
43/* EIP197 OPTIONS ENCODING */
44#define EIP197_OPT_HAS_TRC BIT(31)
45
46/* Static configuration */
47#define EIP197_DEFAULT_RING_SIZE 400
48#define EIP197_EMB_TOKENS 4 /* Pad CD to 16 dwords */
49#define EIP197_MAX_TOKENS 16
50#define EIP197_MAX_RINGS 4
51#define EIP197_FETCH_DEPTH 2
52#define EIP197_MAX_BATCH_SZ 64
53#define EIP197_MAX_RING_AIC 14
54
55#define EIP197_GFP_FLAGS(base) ((base).flags & CRYPTO_TFM_REQ_MAY_SLEEP ? \
56 GFP_KERNEL : GFP_ATOMIC)
57
58/* Custom on-stack requests (for invalidation) */
59#define EIP197_SKCIPHER_REQ_SIZE sizeof(struct skcipher_request) + \
60 sizeof(struct safexcel_cipher_req)
61#define EIP197_AHASH_REQ_SIZE sizeof(struct ahash_request) + \
62 sizeof(struct safexcel_ahash_req)
63#define EIP197_AEAD_REQ_SIZE sizeof(struct aead_request) + \
64 sizeof(struct safexcel_cipher_req)
65#define EIP197_REQUEST_ON_STACK(name, type, size) \
66 char __##name##_desc[size] CRYPTO_MINALIGN_ATTR; \
67 struct type##_request *name = (void *)__##name##_desc
68
69/* Xilinx dev board base offsets */
70#define EIP197_XLX_GPIO_BASE 0x200000
71#define EIP197_XLX_IRQ_BLOCK_ID_ADDR 0x2000
72#define EIP197_XLX_IRQ_BLOCK_ID_VALUE 0x1fc2
73#define EIP197_XLX_USER_INT_ENB_MSK 0x2004
74#define EIP197_XLX_USER_INT_ENB_SET 0x2008
75#define EIP197_XLX_USER_INT_ENB_CLEAR 0x200c
76#define EIP197_XLX_USER_INT_BLOCK 0x2040
77#define EIP197_XLX_USER_INT_PEND 0x2048
78#define EIP197_XLX_USER_VECT_LUT0_ADDR 0x2080
79#define EIP197_XLX_USER_VECT_LUT0_IDENT 0x03020100
80#define EIP197_XLX_USER_VECT_LUT1_ADDR 0x2084
81#define EIP197_XLX_USER_VECT_LUT1_IDENT 0x07060504
82#define EIP197_XLX_USER_VECT_LUT2_ADDR 0x2088
83#define EIP197_XLX_USER_VECT_LUT2_IDENT 0x0b0a0908
84#define EIP197_XLX_USER_VECT_LUT3_ADDR 0x208c
85#define EIP197_XLX_USER_VECT_LUT3_IDENT 0x0f0e0d0c
86
87/* Helper defines for probe function */
88#define EIP197_IRQ_NUMBER(i, is_pci) (i + is_pci)
89
90/* Register base offsets */
91#define EIP197_HIA_AIC(priv) ((priv)->base + (priv)->offsets.hia_aic)
92#define EIP197_HIA_AIC_G(priv) ((priv)->base + (priv)->offsets.hia_aic_g)
93#define EIP197_HIA_AIC_R(priv) ((priv)->base + (priv)->offsets.hia_aic_r)
94#define EIP197_HIA_AIC_xDR(priv) ((priv)->base + (priv)->offsets.hia_aic_xdr)
95#define EIP197_HIA_DFE(priv) ((priv)->base + (priv)->offsets.hia_dfe)
96#define EIP197_HIA_DFE_THR(priv) ((priv)->base + (priv)->offsets.hia_dfe_thr)
97#define EIP197_HIA_DSE(priv) ((priv)->base + (priv)->offsets.hia_dse)
98#define EIP197_HIA_DSE_THR(priv) ((priv)->base + (priv)->offsets.hia_dse_thr)
99#define EIP197_HIA_GEN_CFG(priv) ((priv)->base + (priv)->offsets.hia_gen_cfg)
100#define EIP197_PE(priv) ((priv)->base + (priv)->offsets.pe)
101#define EIP197_GLOBAL(priv) ((priv)->base + (priv)->offsets.global)
102
103/* EIP197 base offsets */
104#define EIP197_HIA_AIC_BASE 0x90000
105#define EIP197_HIA_AIC_G_BASE 0x90000
106#define EIP197_HIA_AIC_R_BASE 0x90800
107#define EIP197_HIA_AIC_xDR_BASE 0x80000
108#define EIP197_HIA_DFE_BASE 0x8c000
109#define EIP197_HIA_DFE_THR_BASE 0x8c040
110#define EIP197_HIA_DSE_BASE 0x8d000
111#define EIP197_HIA_DSE_THR_BASE 0x8d040
112#define EIP197_HIA_GEN_CFG_BASE 0xf0000
113#define EIP197_PE_BASE 0xa0000
114#define EIP197_GLOBAL_BASE 0xf0000
115
116/* EIP97 base offsets */
117#define EIP97_HIA_AIC_BASE 0x0
118#define EIP97_HIA_AIC_G_BASE 0x0
119#define EIP97_HIA_AIC_R_BASE 0x0
120#define EIP97_HIA_AIC_xDR_BASE 0x0
121#define EIP97_HIA_DFE_BASE 0xf000
122#define EIP97_HIA_DFE_THR_BASE 0xf200
123#define EIP97_HIA_DSE_BASE 0xf400
124#define EIP97_HIA_DSE_THR_BASE 0xf600
125#define EIP97_HIA_GEN_CFG_BASE 0x10000
126#define EIP97_PE_BASE 0x10000
127#define EIP97_GLOBAL_BASE 0x10000
128
129/* CDR/RDR register offsets */
130#define EIP197_HIA_xDR_OFF(priv, r) (EIP197_HIA_AIC_xDR(priv) + (r) * 0x1000)
131#define EIP197_HIA_CDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r))
132#define EIP197_HIA_RDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r) + 0x800)
133#define EIP197_HIA_xDR_RING_BASE_ADDR_LO 0x0000
134#define EIP197_HIA_xDR_RING_BASE_ADDR_HI 0x0004
135#define EIP197_HIA_xDR_RING_SIZE 0x0018
136#define EIP197_HIA_xDR_DESC_SIZE 0x001c
137#define EIP197_HIA_xDR_CFG 0x0020
138#define EIP197_HIA_xDR_DMA_CFG 0x0024
139#define EIP197_HIA_xDR_THRESH 0x0028
140#define EIP197_HIA_xDR_PREP_COUNT 0x002c
141#define EIP197_HIA_xDR_PROC_COUNT 0x0030
142#define EIP197_HIA_xDR_PREP_PNTR 0x0034
143#define EIP197_HIA_xDR_PROC_PNTR 0x0038
144#define EIP197_HIA_xDR_STAT 0x003c
145
146/* register offsets */
147#define EIP197_HIA_DFE_CFG(n) (0x0000 + (128 * (n)))
148#define EIP197_HIA_DFE_THR_CTRL(n) (0x0000 + (128 * (n)))
149#define EIP197_HIA_DFE_THR_STAT(n) (0x0004 + (128 * (n)))
150#define EIP197_HIA_DSE_CFG(n) (0x0000 + (128 * (n)))
151#define EIP197_HIA_DSE_THR_CTRL(n) (0x0000 + (128 * (n)))
152#define EIP197_HIA_DSE_THR_STAT(n) (0x0004 + (128 * (n)))
153#define EIP197_HIA_RA_PE_CTRL(n) (0x0010 + (8 * (n)))
154#define EIP197_HIA_RA_PE_STAT 0x0014
155#define EIP197_HIA_AIC_R_OFF(r) ((r) * 0x1000)
156#define EIP197_HIA_AIC_R_ENABLE_CTRL(r) (0xe008 - EIP197_HIA_AIC_R_OFF(r))
157#define EIP197_HIA_AIC_R_ENABLED_STAT(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r))
158#define EIP197_HIA_AIC_R_ACK(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r))
159#define EIP197_HIA_AIC_R_ENABLE_CLR(r) (0xe014 - EIP197_HIA_AIC_R_OFF(r))
160#define EIP197_HIA_AIC_R_VERSION(r) (0xe01c - EIP197_HIA_AIC_R_OFF(r))
161#define EIP197_HIA_AIC_G_ENABLE_CTRL 0xf808
162#define EIP197_HIA_AIC_G_ENABLED_STAT 0xf810
163#define EIP197_HIA_AIC_G_ACK 0xf810
164#define EIP197_HIA_MST_CTRL 0xfff4
165#define EIP197_HIA_OPTIONS 0xfff8
166#define EIP197_HIA_VERSION 0xfffc
167#define EIP197_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n)))
168#define EIP197_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n)))
169#define EIP197_PE_ICE_SCRATCH_RAM(n) (0x0800 + (0x2000 * (n)))
170#define EIP197_PE_ICE_PUE_CTRL(n) (0x0c80 + (0x2000 * (n)))
171#define EIP197_PE_ICE_PUTF_CTRL(n) (0x0d00 + (0x2000 * (n)))
172#define EIP197_PE_ICE_SCRATCH_CTRL(n) (0x0d04 + (0x2000 * (n)))
173#define EIP197_PE_ICE_FPP_CTRL(n) (0x0d80 + (0x2000 * (n)))
174#define EIP197_PE_ICE_PPTF_CTRL(n) (0x0e00 + (0x2000 * (n)))
175#define EIP197_PE_ICE_RAM_CTRL(n) (0x0ff0 + (0x2000 * (n)))
176#define EIP197_PE_ICE_VERSION(n) (0x0ffc + (0x2000 * (n)))
177#define EIP197_PE_EIP96_TOKEN_CTRL(n) (0x1000 + (0x2000 * (n)))
178#define EIP197_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n)))
179#define EIP197_PE_EIP96_CONTEXT_CTRL(n) (0x1008 + (0x2000 * (n)))
180#define EIP197_PE_EIP96_CONTEXT_STAT(n) (0x100c + (0x2000 * (n)))
181#define EIP197_PE_EIP96_TOKEN_CTRL2(n) (0x102c + (0x2000 * (n)))
182#define EIP197_PE_EIP96_FUNCTION2_EN(n) (0x1030 + (0x2000 * (n)))
183#define EIP197_PE_EIP96_OPTIONS(n) (0x13f8 + (0x2000 * (n)))
184#define EIP197_PE_EIP96_VERSION(n) (0x13fc + (0x2000 * (n)))
185#define EIP197_PE_OCE_VERSION(n) (0x1bfc + (0x2000 * (n)))
186#define EIP197_PE_OUT_DBUF_THRES(n) (0x1c00 + (0x2000 * (n)))
187#define EIP197_PE_OUT_TBUF_THRES(n) (0x1d00 + (0x2000 * (n)))
188#define EIP197_PE_PSE_VERSION(n) (0x1efc + (0x2000 * (n)))
189#define EIP197_PE_DEBUG(n) (0x1ff4 + (0x2000 * (n)))
190#define EIP197_PE_OPTIONS(n) (0x1ff8 + (0x2000 * (n)))
191#define EIP197_PE_VERSION(n) (0x1ffc + (0x2000 * (n)))
192#define EIP197_MST_CTRL 0xfff4
193#define EIP197_OPTIONS 0xfff8
194#define EIP197_VERSION 0xfffc
195
196/* EIP197-specific registers, no indirection */
197#define EIP197_CLASSIFICATION_RAMS 0xe0000
198#define EIP197_TRC_CTRL 0xf0800
199#define EIP197_TRC_LASTRES 0xf0804
200#define EIP197_TRC_REGINDEX 0xf0808
201#define EIP197_TRC_PARAMS 0xf0820
202#define EIP197_TRC_FREECHAIN 0xf0824
203#define EIP197_TRC_PARAMS2 0xf0828
204#define EIP197_TRC_ECCCTRL 0xf0830
205#define EIP197_TRC_ECCSTAT 0xf0834
206#define EIP197_TRC_ECCADMINSTAT 0xf0838
207#define EIP197_TRC_ECCDATASTAT 0xf083c
208#define EIP197_TRC_ECCDATA 0xf0840
209#define EIP197_STRC_CONFIG 0xf43f0
210#define EIP197_FLUE_CACHEBASE_LO(n) (0xf6000 + (32 * (n)))
211#define EIP197_FLUE_CACHEBASE_HI(n) (0xf6004 + (32 * (n)))
212#define EIP197_FLUE_CONFIG(n) (0xf6010 + (32 * (n)))
213#define EIP197_FLUE_OFFSETS 0xf6808
214#define EIP197_FLUE_ARC4_OFFSET 0xf680c
215#define EIP197_FLUE_IFC_LUT(n) (0xf6820 + (4 * (n)))
216#define EIP197_CS_RAM_CTRL 0xf7ff0
217
218/* EIP197_HIA_xDR_DESC_SIZE */
219#define EIP197_xDR_DESC_MODE_64BIT BIT(31)
220#define EIP197_CDR_DESC_MODE_ADCP BIT(30)
221
222/* EIP197_HIA_xDR_DMA_CFG */
223#define EIP197_HIA_xDR_WR_RES_BUF BIT(22)
224#define EIP197_HIA_xDR_WR_CTRL_BUF BIT(23)
225#define EIP197_HIA_xDR_WR_OWN_BUF BIT(24)
226#define EIP197_HIA_xDR_CFG_WR_CACHE(n) (((n) & 0x7) << 25)
227#define EIP197_HIA_xDR_CFG_RD_CACHE(n) (((n) & 0x7) << 29)
228
229/* EIP197_HIA_CDR_THRESH */
230#define EIP197_HIA_CDR_THRESH_PROC_PKT(n) (n)
231#define EIP197_HIA_CDR_THRESH_PROC_MODE BIT(22)
232#define EIP197_HIA_CDR_THRESH_PKT_MODE BIT(23)
233#define EIP197_HIA_CDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */
234
235/* EIP197_HIA_RDR_THRESH */
236#define EIP197_HIA_RDR_THRESH_PROC_PKT(n) (n)
237#define EIP197_HIA_RDR_THRESH_PKT_MODE BIT(23)
238#define EIP197_HIA_RDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */
239
240/* EIP197_HIA_xDR_PREP_COUNT */
241#define EIP197_xDR_PREP_CLR_COUNT BIT(31)
242
243/* EIP197_HIA_xDR_PROC_COUNT */
244#define EIP197_xDR_PROC_xD_PKT_OFFSET 24
245#define EIP197_xDR_PROC_xD_PKT_MASK GENMASK(6, 0)
246#define EIP197_xDR_PROC_xD_PKT(n) ((n) << 24)
247#define EIP197_xDR_PROC_CLR_COUNT BIT(31)
248
249/* EIP197_HIA_xDR_STAT */
250#define EIP197_xDR_DMA_ERR BIT(0)
251#define EIP197_xDR_PREP_CMD_THRES BIT(1)
252#define EIP197_xDR_ERR BIT(2)
253#define EIP197_xDR_THRESH BIT(4)
254#define EIP197_xDR_TIMEOUT BIT(5)
255
256#define EIP197_HIA_RA_PE_CTRL_RESET BIT(31)
257#define EIP197_HIA_RA_PE_CTRL_EN BIT(30)
258
259/* EIP197_HIA_OPTIONS */
260#define EIP197_N_RINGS_OFFSET 0
261#define EIP197_N_RINGS_MASK GENMASK(3, 0)
262#define EIP197_N_PES_OFFSET 4
263#define EIP197_N_PES_MASK GENMASK(4, 0)
264#define EIP97_N_PES_MASK GENMASK(2, 0)
265#define EIP197_HWDATAW_OFFSET 25
266#define EIP197_HWDATAW_MASK GENMASK(3, 0)
267#define EIP97_HWDATAW_MASK GENMASK(2, 0)
268#define EIP197_CFSIZE_OFFSET 9
269#define EIP197_CFSIZE_ADJUST 4
270#define EIP97_CFSIZE_OFFSET 8
271#define EIP197_CFSIZE_MASK GENMASK(2, 0)
272#define EIP97_CFSIZE_MASK GENMASK(3, 0)
273#define EIP197_RFSIZE_OFFSET 12
274#define EIP197_RFSIZE_ADJUST 4
275#define EIP97_RFSIZE_OFFSET 12
276#define EIP197_RFSIZE_MASK GENMASK(2, 0)
277#define EIP97_RFSIZE_MASK GENMASK(3, 0)
278
279/* EIP197_HIA_AIC_R_ENABLE_CTRL */
280#define EIP197_CDR_IRQ(n) BIT((n) * 2)
281#define EIP197_RDR_IRQ(n) BIT((n) * 2 + 1)
282
283/* EIP197_HIA_DFE/DSE_CFG */
284#define EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(n) ((n) << 0)
285#define EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(n) (((n) & 0x7) << 4)
286#define EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(n) ((n) << 8)
287#define EIP197_HIA_DSE_CFG_ALWAYS_BUFFERABLE GENMASK(15, 14)
288#define EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(n) ((n) << 16)
289#define EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(n) (((n) & 0x7) << 20)
290#define EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(n) ((n) << 24)
291#define EIP197_HIA_DFE_CFG_DIS_DEBUG GENMASK(31, 29)
292#define EIP197_HIA_DSE_CFG_EN_SINGLE_WR BIT(29)
293#define EIP197_HIA_DSE_CFG_DIS_DEBUG GENMASK(31, 30)
294
295/* EIP197_HIA_DFE/DSE_THR_CTRL */
296#define EIP197_DxE_THR_CTRL_EN BIT(30)
297#define EIP197_DxE_THR_CTRL_RESET_PE BIT(31)
298
299/* EIP197_PE_ICE_PUE/FPP_CTRL */
300#define EIP197_PE_ICE_UENG_START_OFFSET(n) ((n) << 16)
301#define EIP197_PE_ICE_UENG_INIT_ALIGN_MASK 0x7ff0
302#define EIP197_PE_ICE_UENG_DEBUG_RESET BIT(3)
303
304/* EIP197_HIA_AIC_G_ENABLED_STAT */
305#define EIP197_G_IRQ_DFE(n) BIT((n) << 1)
306#define EIP197_G_IRQ_DSE(n) BIT(((n) << 1) + 1)
307#define EIP197_G_IRQ_RING BIT(16)
308#define EIP197_G_IRQ_PE(n) BIT((n) + 20)
309
310/* EIP197_HIA_MST_CTRL */
311#define RD_CACHE_3BITS 0x5
312#define WR_CACHE_3BITS 0x3
313#define RD_CACHE_4BITS (RD_CACHE_3BITS << 1 | BIT(0))
314#define WR_CACHE_4BITS (WR_CACHE_3BITS << 1 | BIT(0))
315#define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0)
316#define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4)
317#define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20)
318#define EIP197_MST_CTRL_BYTE_SWAP BIT(24)
319#define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25)
320#define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24)
321
322/* EIP197_PE_IN_DBUF/TBUF_THRES */
323#define EIP197_PE_IN_xBUF_THRES_MIN(n) ((n) << 8)
324#define EIP197_PE_IN_xBUF_THRES_MAX(n) ((n) << 12)
325
326/* EIP197_PE_OUT_DBUF_THRES */
327#define EIP197_PE_OUT_DBUF_THRES_MIN(n) ((n) << 0)
328#define EIP197_PE_OUT_DBUF_THRES_MAX(n) ((n) << 4)
329
330/* EIP197_PE_ICE_SCRATCH_CTRL */
331#define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER BIT(2)
332#define EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN BIT(3)
333#define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS BIT(24)
334#define EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS BIT(25)
335
336/* EIP197_PE_ICE_SCRATCH_RAM */
337#define EIP197_NUM_OF_SCRATCH_BLOCKS 32
338
339/* EIP197_PE_ICE_PUE/FPP_CTRL */
340#define EIP197_PE_ICE_x_CTRL_SW_RESET BIT(0)
341#define EIP197_PE_ICE_x_CTRL_CLR_ECC_NON_CORR BIT(14)
342#define EIP197_PE_ICE_x_CTRL_CLR_ECC_CORR BIT(15)
343
344/* EIP197_PE_ICE_RAM_CTRL */
345#define EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN BIT(0)
346#define EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN BIT(1)
347
348/* EIP197_PE_EIP96_TOKEN_CTRL */
349#define EIP197_PE_EIP96_TOKEN_CTRL_CTX_UPDATES BIT(16)
350#define EIP197_PE_EIP96_TOKEN_CTRL_NO_TOKEN_WAIT BIT(17)
351#define EIP197_PE_EIP96_TOKEN_CTRL_ENABLE_TIMEOUT BIT(22)
352
353/* EIP197_PE_EIP96_FUNCTION_EN */
354#define EIP197_FUNCTION_ALL 0xffffffff
355
356/* EIP197_PE_EIP96_CONTEXT_CTRL */
357#define EIP197_CONTEXT_SIZE(n) (n)
358#define EIP197_ADDRESS_MODE BIT(8)
359#define EIP197_CONTROL_MODE BIT(9)
360
361/* EIP197_PE_EIP96_TOKEN_CTRL2 */
362#define EIP197_PE_EIP96_TOKEN_CTRL2_CTX_DONE BIT(3)
363
364/* EIP197_PE_DEBUG */
365#define EIP197_DEBUG_OCE_BYPASS BIT(1)
366
367/* EIP197_STRC_CONFIG */
368#define EIP197_STRC_CONFIG_INIT BIT(31)
369#define EIP197_STRC_CONFIG_LARGE_REC(s) (s<<8)
370#define EIP197_STRC_CONFIG_SMALL_REC(s) (s<<0)
371
372/* EIP197_FLUE_CONFIG */
373#define EIP197_FLUE_CONFIG_MAGIC 0xc7000004
374
375/* Context Control */
376struct safexcel_context_record {
377 __le32 control0;
378 __le32 control1;
379
380 __le32 data[40];
381} __packed;
382
383/* control0 */
384#define CONTEXT_CONTROL_TYPE_NULL_OUT 0x0
385#define CONTEXT_CONTROL_TYPE_NULL_IN 0x1
386#define CONTEXT_CONTROL_TYPE_HASH_OUT 0x2
387#define CONTEXT_CONTROL_TYPE_HASH_IN 0x3
388#define CONTEXT_CONTROL_TYPE_CRYPTO_OUT 0x4
389#define CONTEXT_CONTROL_TYPE_CRYPTO_IN 0x5
390#define CONTEXT_CONTROL_TYPE_ENCRYPT_HASH_OUT 0x6
391#define CONTEXT_CONTROL_TYPE_DECRYPT_HASH_IN 0x7
392#define CONTEXT_CONTROL_TYPE_HASH_ENCRYPT_OUT 0xe
393#define CONTEXT_CONTROL_TYPE_HASH_DECRYPT_IN 0xf
394#define CONTEXT_CONTROL_RESTART_HASH BIT(4)
395#define CONTEXT_CONTROL_NO_FINISH_HASH BIT(5)
396#define CONTEXT_CONTROL_SIZE(n) ((n) << 8)
397#define CONTEXT_CONTROL_KEY_EN BIT(16)
398#define CONTEXT_CONTROL_CRYPTO_ALG_DES (0x0 << 17)
399#define CONTEXT_CONTROL_CRYPTO_ALG_3DES (0x2 << 17)
400#define CONTEXT_CONTROL_CRYPTO_ALG_AES128 (0x5 << 17)
401#define CONTEXT_CONTROL_CRYPTO_ALG_AES192 (0x6 << 17)
402#define CONTEXT_CONTROL_CRYPTO_ALG_AES256 (0x7 << 17)
403#define CONTEXT_CONTROL_CRYPTO_ALG_CHACHA20 (0x8 << 17)
404#define CONTEXT_CONTROL_CRYPTO_ALG_SM4 (0xd << 17)
405#define CONTEXT_CONTROL_DIGEST_INITIAL (0x0 << 21)
406#define CONTEXT_CONTROL_DIGEST_PRECOMPUTED (0x1 << 21)
407#define CONTEXT_CONTROL_DIGEST_XCM (0x2 << 21)
408#define CONTEXT_CONTROL_DIGEST_HMAC (0x3 << 21)
409#define CONTEXT_CONTROL_CRYPTO_ALG_MD5 (0x0 << 23)
410#define CONTEXT_CONTROL_CRYPTO_ALG_CRC32 (0x0 << 23)
411#define CONTEXT_CONTROL_CRYPTO_ALG_SHA1 (0x2 << 23)
412#define CONTEXT_CONTROL_CRYPTO_ALG_SHA224 (0x4 << 23)
413#define CONTEXT_CONTROL_CRYPTO_ALG_SHA256 (0x3 << 23)
414#define CONTEXT_CONTROL_CRYPTO_ALG_SHA384 (0x6 << 23)
415#define CONTEXT_CONTROL_CRYPTO_ALG_SHA512 (0x5 << 23)
416#define CONTEXT_CONTROL_CRYPTO_ALG_GHASH (0x4 << 23)
417#define CONTEXT_CONTROL_CRYPTO_ALG_XCBC128 (0x1 << 23)
418#define CONTEXT_CONTROL_CRYPTO_ALG_XCBC192 (0x2 << 23)
419#define CONTEXT_CONTROL_CRYPTO_ALG_XCBC256 (0x3 << 23)
420#define CONTEXT_CONTROL_CRYPTO_ALG_SM3 (0x7 << 23)
421#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_256 (0xb << 23)
422#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_224 (0xc << 23)
423#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_512 (0xd << 23)
424#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_384 (0xe << 23)
425#define CONTEXT_CONTROL_CRYPTO_ALG_POLY1305 (0xf << 23)
426#define CONTEXT_CONTROL_INV_FR (0x5 << 24)
427#define CONTEXT_CONTROL_INV_TR (0x6 << 24)
428
429/* control1 */
430#define CONTEXT_CONTROL_CRYPTO_MODE_ECB (0 << 0)
431#define CONTEXT_CONTROL_CRYPTO_MODE_CBC (1 << 0)
432#define CONTEXT_CONTROL_CHACHA20_MODE_256_32 (2 << 0)
433#define CONTEXT_CONTROL_CRYPTO_MODE_OFB (4 << 0)
434#define CONTEXT_CONTROL_CRYPTO_MODE_CFB (5 << 0)
435#define CONTEXT_CONTROL_CRYPTO_MODE_CTR_LOAD (6 << 0)
436#define CONTEXT_CONTROL_CRYPTO_MODE_XTS (7 << 0)
437#define CONTEXT_CONTROL_CRYPTO_MODE_XCM ((6 << 0) | BIT(17))
438#define CONTEXT_CONTROL_CHACHA20_MODE_CALC_OTK (12 << 0)
439#define CONTEXT_CONTROL_IV0 BIT(5)
440#define CONTEXT_CONTROL_IV1 BIT(6)
441#define CONTEXT_CONTROL_IV2 BIT(7)
442#define CONTEXT_CONTROL_IV3 BIT(8)
443#define CONTEXT_CONTROL_DIGEST_CNT BIT(9)
444#define CONTEXT_CONTROL_COUNTER_MODE BIT(10)
445#define CONTEXT_CONTROL_CRYPTO_STORE BIT(12)
446#define CONTEXT_CONTROL_HASH_STORE BIT(19)
447
448#define EIP197_XCM_MODE_GCM 1
449#define EIP197_XCM_MODE_CCM 2
450
451#define EIP197_AEAD_TYPE_IPSEC_ESP 2
452#define EIP197_AEAD_TYPE_IPSEC_ESP_GMAC 3
453#define EIP197_AEAD_IPSEC_IV_SIZE 8
454#define EIP197_AEAD_IPSEC_NONCE_SIZE 4
455#define EIP197_AEAD_IPSEC_COUNTER_SIZE 4
456#define EIP197_AEAD_IPSEC_CCM_NONCE_SIZE 3
457
458/* The hash counter given to the engine in the context has a granularity of
459 * 64 bits.
460 */
461#define EIP197_COUNTER_BLOCK_SIZE 64
462
463/* EIP197_CS_RAM_CTRL */
464#define EIP197_TRC_ENABLE_0 BIT(4)
465#define EIP197_TRC_ENABLE_1 BIT(5)
466#define EIP197_TRC_ENABLE_2 BIT(6)
467#define EIP197_TRC_ENABLE_MASK GENMASK(6, 4)
468#define EIP197_CS_BANKSEL_MASK GENMASK(14, 12)
469#define EIP197_CS_BANKSEL_OFS 12
470
471/* EIP197_TRC_PARAMS */
472#define EIP197_TRC_PARAMS_SW_RESET BIT(0)
473#define EIP197_TRC_PARAMS_DATA_ACCESS BIT(2)
474#define EIP197_TRC_PARAMS_HTABLE_SZ(x) ((x) << 4)
475#define EIP197_TRC_PARAMS_BLK_TIMER_SPEED(x) ((x) << 10)
476#define EIP197_TRC_PARAMS_RC_SZ_LARGE(n) ((n) << 18)
477
478/* EIP197_TRC_FREECHAIN */
479#define EIP197_TRC_FREECHAIN_HEAD_PTR(p) (p)
480#define EIP197_TRC_FREECHAIN_TAIL_PTR(p) ((p) << 16)
481
482/* EIP197_TRC_PARAMS2 */
483#define EIP197_TRC_PARAMS2_HTABLE_PTR(p) (p)
484#define EIP197_TRC_PARAMS2_RC_SZ_SMALL(n) ((n) << 18)
485
486/* Cache helpers */
487#define EIP197_MIN_DSIZE 1024
488#define EIP197_MIN_ASIZE 8
489#define EIP197_CS_TRC_REC_WC 64
490#define EIP197_CS_RC_SIZE (4 * sizeof(u32))
491#define EIP197_CS_RC_NEXT(x) (x)
492#define EIP197_CS_RC_PREV(x) ((x) << 10)
493#define EIP197_RC_NULL 0x3ff
494
495/* Result data */
496struct result_data_desc {
497 u32 packet_length:17;
498 u32 error_code:15;
499
500 u32 bypass_length:4;
501 u32 e15:1;
502 u32 rsvd0:16;
503 u32 hash_bytes:1;
504 u32 hash_length:6;
505 u32 generic_bytes:1;
506 u32 checksum:1;
507 u32 next_header:1;
508 u32 length:1;
509
510 u16 application_id;
511 u16 rsvd1;
512
513 u32 rsvd2[5];
514} __packed;
515
516
517/* Basic Result Descriptor format */
518struct safexcel_result_desc {
519 u32 particle_size:17;
520 u8 rsvd0:3;
521 u8 descriptor_overflow:1;
522 u8 buffer_overflow:1;
523 u8 last_seg:1;
524 u8 first_seg:1;
525 u16 result_size:8;
526
527 u32 rsvd1;
528
529 u32 data_lo;
530 u32 data_hi;
531} __packed;
532
533/*
534 * The EIP(1)97 only needs to fetch the descriptor part of
535 * the result descriptor, not the result token part!
536 */
537#define EIP197_RD64_FETCH_SIZE (sizeof(struct safexcel_result_desc) /\
538 sizeof(u32))
539#define EIP197_RD64_RESULT_SIZE (sizeof(struct result_data_desc) /\
540 sizeof(u32))
541
542struct safexcel_token {
543 u32 packet_length:17;
544 u8 stat:2;
545 u16 instructions:9;
546 u8 opcode:4;
547} __packed;
548
549#define EIP197_TOKEN_HASH_RESULT_VERIFY BIT(16)
550
551#define EIP197_TOKEN_CTX_OFFSET(x) (x)
552#define EIP197_TOKEN_DIRECTION_EXTERNAL BIT(11)
553#define EIP197_TOKEN_EXEC_IF_SUCCESSFUL (0x1 << 12)
554
555#define EIP197_TOKEN_STAT_LAST_HASH BIT(0)
556#define EIP197_TOKEN_STAT_LAST_PACKET BIT(1)
557#define EIP197_TOKEN_OPCODE_DIRECTION 0x0
558#define EIP197_TOKEN_OPCODE_INSERT 0x2
559#define EIP197_TOKEN_OPCODE_NOOP EIP197_TOKEN_OPCODE_INSERT
560#define EIP197_TOKEN_OPCODE_RETRIEVE 0x4
561#define EIP197_TOKEN_OPCODE_INSERT_REMRES 0xa
562#define EIP197_TOKEN_OPCODE_VERIFY 0xd
563#define EIP197_TOKEN_OPCODE_CTX_ACCESS 0xe
564#define EIP197_TOKEN_OPCODE_BYPASS GENMASK(3, 0)
565
566static inline void eip197_noop_token(struct safexcel_token *token)
567{
568 token->opcode = EIP197_TOKEN_OPCODE_NOOP;
569 token->packet_length = BIT(2);
570 token->stat = 0;
571 token->instructions = 0;
572}
573
574/* Instructions */
575#define EIP197_TOKEN_INS_INSERT_HASH_DIGEST 0x1c
576#define EIP197_TOKEN_INS_ORIGIN_IV0 0x14
577#define EIP197_TOKEN_INS_ORIGIN_TOKEN 0x1b
578#define EIP197_TOKEN_INS_ORIGIN_LEN(x) ((x) << 5)
579#define EIP197_TOKEN_INS_TYPE_OUTPUT BIT(5)
580#define EIP197_TOKEN_INS_TYPE_HASH BIT(6)
581#define EIP197_TOKEN_INS_TYPE_CRYPTO BIT(7)
582#define EIP197_TOKEN_INS_LAST BIT(8)
583
584/* Processing Engine Control Data */
585struct safexcel_control_data_desc {
586 u32 packet_length:17;
587 u16 options:13;
588 u8 type:2;
589
590 u16 application_id;
591 u16 rsvd;
592
593 u32 context_lo;
594 u32 context_hi;
595
596 u32 control0;
597 u32 control1;
598
599 u32 token[EIP197_EMB_TOKENS];
600} __packed;
601
602#define EIP197_OPTION_MAGIC_VALUE BIT(0)
603#define EIP197_OPTION_64BIT_CTX BIT(1)
604#define EIP197_OPTION_RC_AUTO (0x2 << 3)
605#define EIP197_OPTION_CTX_CTRL_IN_CMD BIT(8)
606#define EIP197_OPTION_2_TOKEN_IV_CMD GENMASK(11, 10)
607#define EIP197_OPTION_4_TOKEN_IV_CMD GENMASK(11, 9)
608
609#define EIP197_TYPE_BCLA 0x0
610#define EIP197_TYPE_EXTENDED 0x3
611#define EIP197_CONTEXT_SMALL 0x2
612#define EIP197_CONTEXT_SIZE_MASK 0x3
613
614/* Basic Command Descriptor format */
615struct safexcel_command_desc {
616 u32 particle_size:17;
617 u8 rsvd0:5;
618 u8 last_seg:1;
619 u8 first_seg:1;
620 u8 additional_cdata_size:8;
621
622 u32 rsvd1;
623
624 u32 data_lo;
625 u32 data_hi;
626
627 u32 atok_lo;
628 u32 atok_hi;
629
630 struct safexcel_control_data_desc control_data;
631} __packed;
632
633#define EIP197_CD64_FETCH_SIZE (sizeof(struct safexcel_command_desc) /\
634 sizeof(u32))
635
636/*
637 * Internal structures & functions
638 */
639
640#define EIP197_FW_TERMINAL_NOPS 2
641#define EIP197_FW_START_POLLCNT 16
642#define EIP197_FW_PUE_READY 0x14
643#define EIP197_FW_FPP_READY 0x18
644
645enum eip197_fw {
646 FW_IFPP = 0,
647 FW_IPUE,
648 FW_NB
649};
650
651struct safexcel_desc_ring {
652 void *base;
653 void *shbase;
654 void *base_end;
655 void *shbase_end;
656 dma_addr_t base_dma;
657 dma_addr_t shbase_dma;
658
659 /* write and read pointers */
660 void *write;
661 void *shwrite;
662 void *read;
663
664 /* descriptor element offset */
665 unsigned int offset;
666 unsigned int shoffset;
667};
668
669enum safexcel_alg_type {
670 SAFEXCEL_ALG_TYPE_SKCIPHER,
671 SAFEXCEL_ALG_TYPE_AEAD,
672 SAFEXCEL_ALG_TYPE_AHASH,
673};
674
675struct safexcel_config {
676 u32 pes;
677 u32 rings;
678
679 u32 cd_size;
680 u32 cd_offset;
681 u32 cdsh_offset;
682
683 u32 rd_size;
684 u32 rd_offset;
685 u32 res_offset;
686};
687
688struct safexcel_work_data {
689 struct work_struct work;
690 struct safexcel_crypto_priv *priv;
691 int ring;
692};
693
694struct safexcel_ring {
695 spinlock_t lock;
696
697 struct workqueue_struct *workqueue;
698 struct safexcel_work_data work_data;
699
700 /* command/result rings */
701 struct safexcel_desc_ring cdr;
702 struct safexcel_desc_ring rdr;
703
704 /* result ring crypto API request */
705 struct crypto_async_request **rdr_req;
706
707 /* queue */
708 struct crypto_queue queue;
709 spinlock_t queue_lock;
710
711 /* Number of requests in the engine. */
712 int requests;
713
714 /* The ring is currently handling at least one request */
715 bool busy;
716
717 /* Store for current requests when bailing out of the dequeueing
718 * function when no enough resources are available.
719 */
720 struct crypto_async_request *req;
721 struct crypto_async_request *backlog;
722
723 /* irq of this ring */
724 int irq;
725};
726
727/* EIP integration context flags */
728enum safexcel_eip_version {
729 /* Platform (EIP integration context) specifier */
730 EIP97IES_MRVL,
731 EIP197B_MRVL,
732 EIP197D_MRVL,
733 EIP197_DEVBRD,
734 EIP197C_MXL,
735};
736
737struct safexcel_priv_data {
738 enum safexcel_eip_version version;
739 bool fw_little_endian;
740};
741
742/* Priority we use for advertising our algorithms */
743#define SAFEXCEL_CRA_PRIORITY 300
744
745/* SM3 digest result for zero length message */
746#define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \
747 "\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \
748 "\x22\xBE\xC8\xC7\x28\xFE\xFB\x74" \
749 "\x7E\xD0\x35\xEB\x50\x82\xAA\x2B"
750
751/* EIP algorithm presence flags */
752enum safexcel_eip_algorithms {
753 SAFEXCEL_ALG_BC0 = BIT(5),
754 SAFEXCEL_ALG_SM4 = BIT(6),
755 SAFEXCEL_ALG_SM3 = BIT(7),
756 SAFEXCEL_ALG_CHACHA20 = BIT(8),
757 SAFEXCEL_ALG_POLY1305 = BIT(9),
758 SAFEXCEL_SEQMASK_256 = BIT(10),
759 SAFEXCEL_SEQMASK_384 = BIT(11),
760 SAFEXCEL_ALG_AES = BIT(12),
761 SAFEXCEL_ALG_AES_XFB = BIT(13),
762 SAFEXCEL_ALG_DES = BIT(15),
763 SAFEXCEL_ALG_DES_XFB = BIT(16),
764 SAFEXCEL_ALG_ARC4 = BIT(18),
765 SAFEXCEL_ALG_AES_XTS = BIT(20),
766 SAFEXCEL_ALG_WIRELESS = BIT(21),
767 SAFEXCEL_ALG_MD5 = BIT(22),
768 SAFEXCEL_ALG_SHA1 = BIT(23),
769 SAFEXCEL_ALG_SHA2_256 = BIT(25),
770 SAFEXCEL_ALG_SHA2_512 = BIT(26),
771 SAFEXCEL_ALG_XCBC_MAC = BIT(27),
772 SAFEXCEL_ALG_CBC_MAC_ALL = BIT(29),
773 SAFEXCEL_ALG_GHASH = BIT(30),
774 SAFEXCEL_ALG_SHA3 = BIT(31),
775};
776
777struct safexcel_register_offsets {
778 u32 hia_aic;
779 u32 hia_aic_g;
780 u32 hia_aic_r;
781 u32 hia_aic_xdr;
782 u32 hia_dfe;
783 u32 hia_dfe_thr;
784 u32 hia_dse;
785 u32 hia_dse_thr;
786 u32 hia_gen_cfg;
787 u32 pe;
788 u32 global;
789};
790
791enum safexcel_flags {
792 EIP197_TRC_CACHE = BIT(0),
793 SAFEXCEL_HW_EIP197 = BIT(1),
794 EIP197_PE_ARB = BIT(2),
795 EIP197_ICE = BIT(3),
796 EIP197_SIMPLE_TRC = BIT(4),
797 EIP197_OCE = BIT(5),
798};
799
800struct safexcel_hwconfig {
801 enum safexcel_eip_algorithms algo_flags;
802 int hwver;
803 int hiaver;
804 int ppver;
805 int icever;
806 int pever;
807 int ocever;
808 int psever;
809 int hwdataw;
810 int hwcfsize;
811 int hwrfsize;
812 int hwnumpes;
813 int hwnumrings;
814 int hwnumraic;
815};
816
817struct safexcel_crypto_priv {
818 void __iomem *base;
819 struct device *dev;
820 struct clk *clk;
821 struct clk *reg_clk;
822 struct safexcel_config config;
823
824 struct safexcel_priv_data *data;
825 struct safexcel_register_offsets offsets;
826 struct safexcel_hwconfig hwconfig;
827 u32 flags;
828
829 /* context DMA pool */
830 struct dma_pool *context_pool;
831
832 atomic_t ring_used;
833
834 struct safexcel_ring *ring;
835};
836
837struct safexcel_context {
838 int (*send)(struct crypto_async_request *req, int ring,
839 int *commands, int *results);
840 int (*handle_result)(struct safexcel_crypto_priv *priv, int ring,
841 struct crypto_async_request *req, bool *complete,
842 int *ret);
843 struct safexcel_context_record *ctxr;
844 struct safexcel_crypto_priv *priv;
845 dma_addr_t ctxr_dma;
846
847 union {
848 __le32 le[SHA3_512_BLOCK_SIZE / 4];
849 __be32 be[SHA3_512_BLOCK_SIZE / 4];
850 u32 word[SHA3_512_BLOCK_SIZE / 4];
851 u8 byte[SHA3_512_BLOCK_SIZE];
852 } ipad, opad;
853
854 int ring;
855 bool needs_inv;
856 bool exit_inv;
857};
858
859#define HASH_CACHE_SIZE SHA512_BLOCK_SIZE
860
861struct safexcel_ahash_export_state {
862 u64 len;
863 u64 processed;
864
865 u32 digest;
866
867 u32 state[SHA512_DIGEST_SIZE / sizeof(u32)];
868 u8 cache[HASH_CACHE_SIZE];
869};
870
871/*
872 * Template structure to describe the algorithms in order to register them.
873 * It also has the purpose to contain our private structure and is actually
874 * the only way I know in this framework to avoid having global pointers...
875 */
876struct safexcel_alg_template {
877 struct safexcel_crypto_priv *priv;
878 enum safexcel_alg_type type;
879 enum safexcel_eip_algorithms algo_mask;
880 union {
881 struct skcipher_alg skcipher;
882 struct aead_alg aead;
883 struct ahash_alg ahash;
884 } alg;
885};
886
887void safexcel_dequeue(struct safexcel_crypto_priv *priv, int ring);
888int safexcel_rdesc_check_errors(struct safexcel_crypto_priv *priv,
889 void *rdp);
890void safexcel_complete(struct safexcel_crypto_priv *priv, int ring);
891int safexcel_invalidate_cache(struct crypto_async_request *async,
892 struct safexcel_crypto_priv *priv,
893 dma_addr_t ctxr_dma, int ring);
894int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv,
895 struct safexcel_desc_ring *cdr,
896 struct safexcel_desc_ring *rdr);
897int safexcel_select_ring(struct safexcel_crypto_priv *priv);
898void *safexcel_ring_next_rptr(struct safexcel_crypto_priv *priv,
899 struct safexcel_desc_ring *ring);
900void *safexcel_ring_first_rptr(struct safexcel_crypto_priv *priv, int ring);
901void safexcel_ring_rollback_wptr(struct safexcel_crypto_priv *priv,
902 struct safexcel_desc_ring *ring);
903struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *priv,
904 int ring_id,
905 bool first, bool last,
906 dma_addr_t data, u32 len,
907 u32 full_data_len,
908 dma_addr_t context,
909 struct safexcel_token **atoken);
910struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *priv,
911 int ring_id,
912 bool first, bool last,
913 dma_addr_t data, u32 len);
914int safexcel_ring_first_rdr_index(struct safexcel_crypto_priv *priv,
915 int ring);
916int safexcel_ring_rdr_rdesc_index(struct safexcel_crypto_priv *priv,
917 int ring,
918 struct safexcel_result_desc *rdesc);
919void safexcel_rdr_req_set(struct safexcel_crypto_priv *priv,
920 int ring,
921 struct safexcel_result_desc *rdesc,
922 struct crypto_async_request *req);
923inline struct crypto_async_request *
924safexcel_rdr_req_get(struct safexcel_crypto_priv *priv, int ring);
925int safexcel_hmac_setkey(struct safexcel_context *base, const u8 *key,
926 unsigned int keylen, const char *alg,
927 unsigned int state_sz);
928
929/* available algorithms */
930extern struct safexcel_alg_template safexcel_alg_ecb_des;
931extern struct safexcel_alg_template safexcel_alg_cbc_des;
932extern struct safexcel_alg_template safexcel_alg_ecb_des3_ede;
933extern struct safexcel_alg_template safexcel_alg_cbc_des3_ede;
934extern struct safexcel_alg_template safexcel_alg_ecb_aes;
935extern struct safexcel_alg_template safexcel_alg_cbc_aes;
936extern struct safexcel_alg_template safexcel_alg_ctr_aes;
937extern struct safexcel_alg_template safexcel_alg_md5;
938extern struct safexcel_alg_template safexcel_alg_sha1;
939extern struct safexcel_alg_template safexcel_alg_sha224;
940extern struct safexcel_alg_template safexcel_alg_sha256;
941extern struct safexcel_alg_template safexcel_alg_sha384;
942extern struct safexcel_alg_template safexcel_alg_sha512;
943extern struct safexcel_alg_template safexcel_alg_hmac_md5;
944extern struct safexcel_alg_template safexcel_alg_hmac_sha1;
945extern struct safexcel_alg_template safexcel_alg_hmac_sha224;
946extern struct safexcel_alg_template safexcel_alg_hmac_sha256;
947extern struct safexcel_alg_template safexcel_alg_hmac_sha384;
948extern struct safexcel_alg_template safexcel_alg_hmac_sha512;
949extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_aes;
950extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_aes;
951extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_aes;
952extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_aes;
953extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_aes;
954extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_des3_ede;
955extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_ctr_aes;
956extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_ctr_aes;
957extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_ctr_aes;
958extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_ctr_aes;
959extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_ctr_aes;
960extern struct safexcel_alg_template safexcel_alg_xts_aes;
961extern struct safexcel_alg_template safexcel_alg_gcm;
962extern struct safexcel_alg_template safexcel_alg_ccm;
963extern struct safexcel_alg_template safexcel_alg_crc32;
964extern struct safexcel_alg_template safexcel_alg_cbcmac;
965extern struct safexcel_alg_template safexcel_alg_xcbcmac;
966extern struct safexcel_alg_template safexcel_alg_cmac;
967extern struct safexcel_alg_template safexcel_alg_chacha20;
968extern struct safexcel_alg_template safexcel_alg_chachapoly;
969extern struct safexcel_alg_template safexcel_alg_chachapoly_esp;
970extern struct safexcel_alg_template safexcel_alg_sm3;
971extern struct safexcel_alg_template safexcel_alg_hmac_sm3;
972extern struct safexcel_alg_template safexcel_alg_ecb_sm4;
973extern struct safexcel_alg_template safexcel_alg_cbc_sm4;
974extern struct safexcel_alg_template safexcel_alg_ctr_sm4;
975extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_sm4;
976extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sm3_cbc_sm4;
977extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_ctr_sm4;
978extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sm3_ctr_sm4;
979extern struct safexcel_alg_template safexcel_alg_sha3_224;
980extern struct safexcel_alg_template safexcel_alg_sha3_256;
981extern struct safexcel_alg_template safexcel_alg_sha3_384;
982extern struct safexcel_alg_template safexcel_alg_sha3_512;
983extern struct safexcel_alg_template safexcel_alg_hmac_sha3_224;
984extern struct safexcel_alg_template safexcel_alg_hmac_sha3_256;
985extern struct safexcel_alg_template safexcel_alg_hmac_sha3_384;
986extern struct safexcel_alg_template safexcel_alg_hmac_sha3_512;
987extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_des;
988extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_des3_ede;
989extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_des3_ede;
990extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_des3_ede;
991extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_des3_ede;
992extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_des;
993extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_des;
994extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_des;
995extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_des;
996extern struct safexcel_alg_template safexcel_alg_rfc4106_gcm;
997extern struct safexcel_alg_template safexcel_alg_rfc4543_gcm;
998extern struct safexcel_alg_template safexcel_alg_rfc4309_ccm;
999
1000#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2017 Marvell
4 *
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
6 */
7
8#ifndef __SAFEXCEL_H__
9#define __SAFEXCEL_H__
10
11#include <crypto/aead.h>
12#include <crypto/algapi.h>
13#include <crypto/internal/hash.h>
14#include <crypto/sha1.h>
15#include <crypto/sha2.h>
16#include <crypto/sha3.h>
17#include <crypto/skcipher.h>
18#include <linux/types.h>
19
20#define EIP197_HIA_VERSION_BE 0xca35
21#define EIP197_HIA_VERSION_LE 0x35ca
22#define EIP97_VERSION_LE 0x9e61
23#define EIP196_VERSION_LE 0x3bc4
24#define EIP197_VERSION_LE 0x3ac5
25#define EIP96_VERSION_LE 0x9f60
26#define EIP201_VERSION_LE 0x36c9
27#define EIP206_VERSION_LE 0x31ce
28#define EIP207_VERSION_LE 0x30cf
29#define EIP197_REG_LO16(reg) (reg & 0xffff)
30#define EIP197_REG_HI16(reg) ((reg >> 16) & 0xffff)
31#define EIP197_VERSION_MASK(reg) ((reg >> 16) & 0xfff)
32#define EIP197_VERSION_SWAP(reg) (((reg & 0xf0) << 4) | \
33 ((reg >> 4) & 0xf0) | \
34 ((reg >> 12) & 0xf))
35
36/* EIP197 HIA OPTIONS ENCODING */
37#define EIP197_HIA_OPT_HAS_PE_ARB BIT(29)
38
39/* EIP206 OPTIONS ENCODING */
40#define EIP206_OPT_ICE_TYPE(n) ((n>>8)&3)
41#define EIP206_OPT_OCE_TYPE(n) ((n>>10)&3)
42
43/* EIP197 OPTIONS ENCODING */
44#define EIP197_OPT_HAS_TRC BIT(31)
45
46/* Static configuration */
47#define EIP197_DEFAULT_RING_SIZE 400
48#define EIP197_EMB_TOKENS 4 /* Pad CD to 16 dwords */
49#define EIP197_MAX_TOKENS 16
50#define EIP197_MAX_RINGS 4
51#define EIP197_FETCH_DEPTH 2
52#define EIP197_MAX_BATCH_SZ 64
53#define EIP197_MAX_RING_AIC 14
54
55#define EIP197_GFP_FLAGS(base) ((base).flags & CRYPTO_TFM_REQ_MAY_SLEEP ? \
56 GFP_KERNEL : GFP_ATOMIC)
57
58/* Custom on-stack requests (for invalidation) */
59#define EIP197_SKCIPHER_REQ_SIZE sizeof(struct skcipher_request) + \
60 sizeof(struct safexcel_cipher_req)
61#define EIP197_AHASH_REQ_SIZE sizeof(struct ahash_request) + \
62 sizeof(struct safexcel_ahash_req)
63#define EIP197_AEAD_REQ_SIZE sizeof(struct aead_request) + \
64 sizeof(struct safexcel_cipher_req)
65#define EIP197_REQUEST_ON_STACK(name, type, size) \
66 char __##name##_desc[size] CRYPTO_MINALIGN_ATTR; \
67 struct type##_request *name = (void *)__##name##_desc
68
69/* Xilinx dev board base offsets */
70#define EIP197_XLX_GPIO_BASE 0x200000
71#define EIP197_XLX_IRQ_BLOCK_ID_ADDR 0x2000
72#define EIP197_XLX_IRQ_BLOCK_ID_VALUE 0x1fc2
73#define EIP197_XLX_USER_INT_ENB_MSK 0x2004
74#define EIP197_XLX_USER_INT_ENB_SET 0x2008
75#define EIP197_XLX_USER_INT_ENB_CLEAR 0x200c
76#define EIP197_XLX_USER_INT_BLOCK 0x2040
77#define EIP197_XLX_USER_INT_PEND 0x2048
78#define EIP197_XLX_USER_VECT_LUT0_ADDR 0x2080
79#define EIP197_XLX_USER_VECT_LUT0_IDENT 0x03020100
80#define EIP197_XLX_USER_VECT_LUT1_ADDR 0x2084
81#define EIP197_XLX_USER_VECT_LUT1_IDENT 0x07060504
82#define EIP197_XLX_USER_VECT_LUT2_ADDR 0x2088
83#define EIP197_XLX_USER_VECT_LUT2_IDENT 0x0b0a0908
84#define EIP197_XLX_USER_VECT_LUT3_ADDR 0x208c
85#define EIP197_XLX_USER_VECT_LUT3_IDENT 0x0f0e0d0c
86
87/* Helper defines for probe function */
88#define EIP197_IRQ_NUMBER(i, is_pci) (i + is_pci)
89
90/* Register base offsets */
91#define EIP197_HIA_AIC(priv) ((priv)->base + (priv)->offsets.hia_aic)
92#define EIP197_HIA_AIC_G(priv) ((priv)->base + (priv)->offsets.hia_aic_g)
93#define EIP197_HIA_AIC_R(priv) ((priv)->base + (priv)->offsets.hia_aic_r)
94#define EIP197_HIA_AIC_xDR(priv) ((priv)->base + (priv)->offsets.hia_aic_xdr)
95#define EIP197_HIA_DFE(priv) ((priv)->base + (priv)->offsets.hia_dfe)
96#define EIP197_HIA_DFE_THR(priv) ((priv)->base + (priv)->offsets.hia_dfe_thr)
97#define EIP197_HIA_DSE(priv) ((priv)->base + (priv)->offsets.hia_dse)
98#define EIP197_HIA_DSE_THR(priv) ((priv)->base + (priv)->offsets.hia_dse_thr)
99#define EIP197_HIA_GEN_CFG(priv) ((priv)->base + (priv)->offsets.hia_gen_cfg)
100#define EIP197_PE(priv) ((priv)->base + (priv)->offsets.pe)
101#define EIP197_GLOBAL(priv) ((priv)->base + (priv)->offsets.global)
102
103/* EIP197 base offsets */
104#define EIP197_HIA_AIC_BASE 0x90000
105#define EIP197_HIA_AIC_G_BASE 0x90000
106#define EIP197_HIA_AIC_R_BASE 0x90800
107#define EIP197_HIA_AIC_xDR_BASE 0x80000
108#define EIP197_HIA_DFE_BASE 0x8c000
109#define EIP197_HIA_DFE_THR_BASE 0x8c040
110#define EIP197_HIA_DSE_BASE 0x8d000
111#define EIP197_HIA_DSE_THR_BASE 0x8d040
112#define EIP197_HIA_GEN_CFG_BASE 0xf0000
113#define EIP197_PE_BASE 0xa0000
114#define EIP197_GLOBAL_BASE 0xf0000
115
116/* EIP97 base offsets */
117#define EIP97_HIA_AIC_BASE 0x0
118#define EIP97_HIA_AIC_G_BASE 0x0
119#define EIP97_HIA_AIC_R_BASE 0x0
120#define EIP97_HIA_AIC_xDR_BASE 0x0
121#define EIP97_HIA_DFE_BASE 0xf000
122#define EIP97_HIA_DFE_THR_BASE 0xf200
123#define EIP97_HIA_DSE_BASE 0xf400
124#define EIP97_HIA_DSE_THR_BASE 0xf600
125#define EIP97_HIA_GEN_CFG_BASE 0x10000
126#define EIP97_PE_BASE 0x10000
127#define EIP97_GLOBAL_BASE 0x10000
128
129/* CDR/RDR register offsets */
130#define EIP197_HIA_xDR_OFF(priv, r) (EIP197_HIA_AIC_xDR(priv) + (r) * 0x1000)
131#define EIP197_HIA_CDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r))
132#define EIP197_HIA_RDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r) + 0x800)
133#define EIP197_HIA_xDR_RING_BASE_ADDR_LO 0x0000
134#define EIP197_HIA_xDR_RING_BASE_ADDR_HI 0x0004
135#define EIP197_HIA_xDR_RING_SIZE 0x0018
136#define EIP197_HIA_xDR_DESC_SIZE 0x001c
137#define EIP197_HIA_xDR_CFG 0x0020
138#define EIP197_HIA_xDR_DMA_CFG 0x0024
139#define EIP197_HIA_xDR_THRESH 0x0028
140#define EIP197_HIA_xDR_PREP_COUNT 0x002c
141#define EIP197_HIA_xDR_PROC_COUNT 0x0030
142#define EIP197_HIA_xDR_PREP_PNTR 0x0034
143#define EIP197_HIA_xDR_PROC_PNTR 0x0038
144#define EIP197_HIA_xDR_STAT 0x003c
145
146/* register offsets */
147#define EIP197_HIA_DFE_CFG(n) (0x0000 + (128 * (n)))
148#define EIP197_HIA_DFE_THR_CTRL(n) (0x0000 + (128 * (n)))
149#define EIP197_HIA_DFE_THR_STAT(n) (0x0004 + (128 * (n)))
150#define EIP197_HIA_DSE_CFG(n) (0x0000 + (128 * (n)))
151#define EIP197_HIA_DSE_THR_CTRL(n) (0x0000 + (128 * (n)))
152#define EIP197_HIA_DSE_THR_STAT(n) (0x0004 + (128 * (n)))
153#define EIP197_HIA_RA_PE_CTRL(n) (0x0010 + (8 * (n)))
154#define EIP197_HIA_RA_PE_STAT 0x0014
155#define EIP197_HIA_AIC_R_OFF(r) ((r) * 0x1000)
156#define EIP197_HIA_AIC_R_ENABLE_CTRL(r) (0xe008 - EIP197_HIA_AIC_R_OFF(r))
157#define EIP197_HIA_AIC_R_ENABLED_STAT(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r))
158#define EIP197_HIA_AIC_R_ACK(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r))
159#define EIP197_HIA_AIC_R_ENABLE_CLR(r) (0xe014 - EIP197_HIA_AIC_R_OFF(r))
160#define EIP197_HIA_AIC_R_VERSION(r) (0xe01c - EIP197_HIA_AIC_R_OFF(r))
161#define EIP197_HIA_AIC_G_ENABLE_CTRL 0xf808
162#define EIP197_HIA_AIC_G_ENABLED_STAT 0xf810
163#define EIP197_HIA_AIC_G_ACK 0xf810
164#define EIP197_HIA_MST_CTRL 0xfff4
165#define EIP197_HIA_OPTIONS 0xfff8
166#define EIP197_HIA_VERSION 0xfffc
167#define EIP197_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n)))
168#define EIP197_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n)))
169#define EIP197_PE_ICE_SCRATCH_RAM(n) (0x0800 + (0x2000 * (n)))
170#define EIP197_PE_ICE_PUE_CTRL(n) (0x0c80 + (0x2000 * (n)))
171#define EIP197_PE_ICE_PUTF_CTRL(n) (0x0d00 + (0x2000 * (n)))
172#define EIP197_PE_ICE_SCRATCH_CTRL(n) (0x0d04 + (0x2000 * (n)))
173#define EIP197_PE_ICE_FPP_CTRL(n) (0x0d80 + (0x2000 * (n)))
174#define EIP197_PE_ICE_PPTF_CTRL(n) (0x0e00 + (0x2000 * (n)))
175#define EIP197_PE_ICE_RAM_CTRL(n) (0x0ff0 + (0x2000 * (n)))
176#define EIP197_PE_ICE_VERSION(n) (0x0ffc + (0x2000 * (n)))
177#define EIP197_PE_EIP96_TOKEN_CTRL(n) (0x1000 + (0x2000 * (n)))
178#define EIP197_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n)))
179#define EIP197_PE_EIP96_CONTEXT_CTRL(n) (0x1008 + (0x2000 * (n)))
180#define EIP197_PE_EIP96_CONTEXT_STAT(n) (0x100c + (0x2000 * (n)))
181#define EIP197_PE_EIP96_TOKEN_CTRL2(n) (0x102c + (0x2000 * (n)))
182#define EIP197_PE_EIP96_FUNCTION2_EN(n) (0x1030 + (0x2000 * (n)))
183#define EIP197_PE_EIP96_OPTIONS(n) (0x13f8 + (0x2000 * (n)))
184#define EIP197_PE_EIP96_VERSION(n) (0x13fc + (0x2000 * (n)))
185#define EIP197_PE_OCE_VERSION(n) (0x1bfc + (0x2000 * (n)))
186#define EIP197_PE_OUT_DBUF_THRES(n) (0x1c00 + (0x2000 * (n)))
187#define EIP197_PE_OUT_TBUF_THRES(n) (0x1d00 + (0x2000 * (n)))
188#define EIP197_PE_PSE_VERSION(n) (0x1efc + (0x2000 * (n)))
189#define EIP197_PE_DEBUG(n) (0x1ff4 + (0x2000 * (n)))
190#define EIP197_PE_OPTIONS(n) (0x1ff8 + (0x2000 * (n)))
191#define EIP197_PE_VERSION(n) (0x1ffc + (0x2000 * (n)))
192#define EIP197_MST_CTRL 0xfff4
193#define EIP197_OPTIONS 0xfff8
194#define EIP197_VERSION 0xfffc
195
196/* EIP197-specific registers, no indirection */
197#define EIP197_CLASSIFICATION_RAMS 0xe0000
198#define EIP197_TRC_CTRL 0xf0800
199#define EIP197_TRC_LASTRES 0xf0804
200#define EIP197_TRC_REGINDEX 0xf0808
201#define EIP197_TRC_PARAMS 0xf0820
202#define EIP197_TRC_FREECHAIN 0xf0824
203#define EIP197_TRC_PARAMS2 0xf0828
204#define EIP197_TRC_ECCCTRL 0xf0830
205#define EIP197_TRC_ECCSTAT 0xf0834
206#define EIP197_TRC_ECCADMINSTAT 0xf0838
207#define EIP197_TRC_ECCDATASTAT 0xf083c
208#define EIP197_TRC_ECCDATA 0xf0840
209#define EIP197_STRC_CONFIG 0xf43f0
210#define EIP197_FLUE_CACHEBASE_LO(n) (0xf6000 + (32 * (n)))
211#define EIP197_FLUE_CACHEBASE_HI(n) (0xf6004 + (32 * (n)))
212#define EIP197_FLUE_CONFIG(n) (0xf6010 + (32 * (n)))
213#define EIP197_FLUE_OFFSETS 0xf6808
214#define EIP197_FLUE_ARC4_OFFSET 0xf680c
215#define EIP197_FLUE_IFC_LUT(n) (0xf6820 + (4 * (n)))
216#define EIP197_CS_RAM_CTRL 0xf7ff0
217
218/* EIP197_HIA_xDR_DESC_SIZE */
219#define EIP197_xDR_DESC_MODE_64BIT BIT(31)
220#define EIP197_CDR_DESC_MODE_ADCP BIT(30)
221
222/* EIP197_HIA_xDR_DMA_CFG */
223#define EIP197_HIA_xDR_WR_RES_BUF BIT(22)
224#define EIP197_HIA_xDR_WR_CTRL_BUF BIT(23)
225#define EIP197_HIA_xDR_WR_OWN_BUF BIT(24)
226#define EIP197_HIA_xDR_CFG_WR_CACHE(n) (((n) & 0x7) << 25)
227#define EIP197_HIA_xDR_CFG_RD_CACHE(n) (((n) & 0x7) << 29)
228
229/* EIP197_HIA_CDR_THRESH */
230#define EIP197_HIA_CDR_THRESH_PROC_PKT(n) (n)
231#define EIP197_HIA_CDR_THRESH_PROC_MODE BIT(22)
232#define EIP197_HIA_CDR_THRESH_PKT_MODE BIT(23)
233#define EIP197_HIA_CDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */
234
235/* EIP197_HIA_RDR_THRESH */
236#define EIP197_HIA_RDR_THRESH_PROC_PKT(n) (n)
237#define EIP197_HIA_RDR_THRESH_PKT_MODE BIT(23)
238#define EIP197_HIA_RDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */
239
240/* EIP197_HIA_xDR_PREP_COUNT */
241#define EIP197_xDR_PREP_CLR_COUNT BIT(31)
242
243/* EIP197_HIA_xDR_PROC_COUNT */
244#define EIP197_xDR_PROC_xD_PKT_OFFSET 24
245#define EIP197_xDR_PROC_xD_PKT_MASK GENMASK(6, 0)
246#define EIP197_xDR_PROC_xD_PKT(n) ((n) << 24)
247#define EIP197_xDR_PROC_CLR_COUNT BIT(31)
248
249/* EIP197_HIA_xDR_STAT */
250#define EIP197_xDR_DMA_ERR BIT(0)
251#define EIP197_xDR_PREP_CMD_THRES BIT(1)
252#define EIP197_xDR_ERR BIT(2)
253#define EIP197_xDR_THRESH BIT(4)
254#define EIP197_xDR_TIMEOUT BIT(5)
255
256#define EIP197_HIA_RA_PE_CTRL_RESET BIT(31)
257#define EIP197_HIA_RA_PE_CTRL_EN BIT(30)
258
259/* EIP197_HIA_OPTIONS */
260#define EIP197_N_RINGS_OFFSET 0
261#define EIP197_N_RINGS_MASK GENMASK(3, 0)
262#define EIP197_N_PES_OFFSET 4
263#define EIP197_N_PES_MASK GENMASK(4, 0)
264#define EIP97_N_PES_MASK GENMASK(2, 0)
265#define EIP197_HWDATAW_OFFSET 25
266#define EIP197_HWDATAW_MASK GENMASK(3, 0)
267#define EIP97_HWDATAW_MASK GENMASK(2, 0)
268#define EIP197_CFSIZE_OFFSET 9
269#define EIP197_CFSIZE_ADJUST 4
270#define EIP97_CFSIZE_OFFSET 8
271#define EIP197_CFSIZE_MASK GENMASK(2, 0)
272#define EIP97_CFSIZE_MASK GENMASK(3, 0)
273#define EIP197_RFSIZE_OFFSET 12
274#define EIP197_RFSIZE_ADJUST 4
275#define EIP97_RFSIZE_OFFSET 12
276#define EIP197_RFSIZE_MASK GENMASK(2, 0)
277#define EIP97_RFSIZE_MASK GENMASK(3, 0)
278
279/* EIP197_HIA_AIC_R_ENABLE_CTRL */
280#define EIP197_CDR_IRQ(n) BIT((n) * 2)
281#define EIP197_RDR_IRQ(n) BIT((n) * 2 + 1)
282
283/* EIP197_HIA_DFE/DSE_CFG */
284#define EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(n) ((n) << 0)
285#define EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(n) (((n) & 0x7) << 4)
286#define EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(n) ((n) << 8)
287#define EIP197_HIA_DSE_CFG_ALWAYS_BUFFERABLE GENMASK(15, 14)
288#define EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(n) ((n) << 16)
289#define EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(n) (((n) & 0x7) << 20)
290#define EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(n) ((n) << 24)
291#define EIP197_HIA_DFE_CFG_DIS_DEBUG GENMASK(31, 29)
292#define EIP197_HIA_DSE_CFG_EN_SINGLE_WR BIT(29)
293#define EIP197_HIA_DSE_CFG_DIS_DEBUG GENMASK(31, 30)
294
295/* EIP197_HIA_DFE/DSE_THR_CTRL */
296#define EIP197_DxE_THR_CTRL_EN BIT(30)
297#define EIP197_DxE_THR_CTRL_RESET_PE BIT(31)
298
299/* EIP197_PE_ICE_PUE/FPP_CTRL */
300#define EIP197_PE_ICE_UENG_START_OFFSET(n) ((n) << 16)
301#define EIP197_PE_ICE_UENG_INIT_ALIGN_MASK 0x7ff0
302#define EIP197_PE_ICE_UENG_DEBUG_RESET BIT(3)
303
304/* EIP197_HIA_AIC_G_ENABLED_STAT */
305#define EIP197_G_IRQ_DFE(n) BIT((n) << 1)
306#define EIP197_G_IRQ_DSE(n) BIT(((n) << 1) + 1)
307#define EIP197_G_IRQ_RING BIT(16)
308#define EIP197_G_IRQ_PE(n) BIT((n) + 20)
309
310/* EIP197_HIA_MST_CTRL */
311#define RD_CACHE_3BITS 0x5
312#define WR_CACHE_3BITS 0x3
313#define RD_CACHE_4BITS (RD_CACHE_3BITS << 1 | BIT(0))
314#define WR_CACHE_4BITS (WR_CACHE_3BITS << 1 | BIT(0))
315#define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0)
316#define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4)
317#define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20)
318#define EIP197_MST_CTRL_BYTE_SWAP BIT(24)
319#define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25)
320#define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24)
321
322/* EIP197_PE_IN_DBUF/TBUF_THRES */
323#define EIP197_PE_IN_xBUF_THRES_MIN(n) ((n) << 8)
324#define EIP197_PE_IN_xBUF_THRES_MAX(n) ((n) << 12)
325
326/* EIP197_PE_OUT_DBUF_THRES */
327#define EIP197_PE_OUT_DBUF_THRES_MIN(n) ((n) << 0)
328#define EIP197_PE_OUT_DBUF_THRES_MAX(n) ((n) << 4)
329
330/* EIP197_PE_ICE_SCRATCH_CTRL */
331#define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER BIT(2)
332#define EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN BIT(3)
333#define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS BIT(24)
334#define EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS BIT(25)
335
336/* EIP197_PE_ICE_SCRATCH_RAM */
337#define EIP197_NUM_OF_SCRATCH_BLOCKS 32
338
339/* EIP197_PE_ICE_PUE/FPP_CTRL */
340#define EIP197_PE_ICE_x_CTRL_SW_RESET BIT(0)
341#define EIP197_PE_ICE_x_CTRL_CLR_ECC_NON_CORR BIT(14)
342#define EIP197_PE_ICE_x_CTRL_CLR_ECC_CORR BIT(15)
343
344/* EIP197_PE_ICE_RAM_CTRL */
345#define EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN BIT(0)
346#define EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN BIT(1)
347
348/* EIP197_PE_EIP96_TOKEN_CTRL */
349#define EIP197_PE_EIP96_TOKEN_CTRL_CTX_UPDATES BIT(16)
350#define EIP197_PE_EIP96_TOKEN_CTRL_NO_TOKEN_WAIT BIT(17)
351#define EIP197_PE_EIP96_TOKEN_CTRL_ENABLE_TIMEOUT BIT(22)
352
353/* EIP197_PE_EIP96_FUNCTION_EN */
354#define EIP197_FUNCTION_ALL 0xffffffff
355
356/* EIP197_PE_EIP96_CONTEXT_CTRL */
357#define EIP197_CONTEXT_SIZE(n) (n)
358#define EIP197_ADDRESS_MODE BIT(8)
359#define EIP197_CONTROL_MODE BIT(9)
360
361/* EIP197_PE_EIP96_TOKEN_CTRL2 */
362#define EIP197_PE_EIP96_TOKEN_CTRL2_CTX_DONE BIT(3)
363
364/* EIP197_PE_DEBUG */
365#define EIP197_DEBUG_OCE_BYPASS BIT(1)
366
367/* EIP197_STRC_CONFIG */
368#define EIP197_STRC_CONFIG_INIT BIT(31)
369#define EIP197_STRC_CONFIG_LARGE_REC(s) (s<<8)
370#define EIP197_STRC_CONFIG_SMALL_REC(s) (s<<0)
371
372/* EIP197_FLUE_CONFIG */
373#define EIP197_FLUE_CONFIG_MAGIC 0xc7000004
374
375/* Context Control */
376struct safexcel_context_record {
377 __le32 control0;
378 __le32 control1;
379
380 __le32 data[40];
381} __packed;
382
383/* control0 */
384#define CONTEXT_CONTROL_TYPE_NULL_OUT 0x0
385#define CONTEXT_CONTROL_TYPE_NULL_IN 0x1
386#define CONTEXT_CONTROL_TYPE_HASH_OUT 0x2
387#define CONTEXT_CONTROL_TYPE_HASH_IN 0x3
388#define CONTEXT_CONTROL_TYPE_CRYPTO_OUT 0x4
389#define CONTEXT_CONTROL_TYPE_CRYPTO_IN 0x5
390#define CONTEXT_CONTROL_TYPE_ENCRYPT_HASH_OUT 0x6
391#define CONTEXT_CONTROL_TYPE_DECRYPT_HASH_IN 0x7
392#define CONTEXT_CONTROL_TYPE_HASH_ENCRYPT_OUT 0xe
393#define CONTEXT_CONTROL_TYPE_HASH_DECRYPT_IN 0xf
394#define CONTEXT_CONTROL_RESTART_HASH BIT(4)
395#define CONTEXT_CONTROL_NO_FINISH_HASH BIT(5)
396#define CONTEXT_CONTROL_SIZE(n) ((n) << 8)
397#define CONTEXT_CONTROL_KEY_EN BIT(16)
398#define CONTEXT_CONTROL_CRYPTO_ALG_DES (0x0 << 17)
399#define CONTEXT_CONTROL_CRYPTO_ALG_3DES (0x2 << 17)
400#define CONTEXT_CONTROL_CRYPTO_ALG_AES128 (0x5 << 17)
401#define CONTEXT_CONTROL_CRYPTO_ALG_AES192 (0x6 << 17)
402#define CONTEXT_CONTROL_CRYPTO_ALG_AES256 (0x7 << 17)
403#define CONTEXT_CONTROL_CRYPTO_ALG_CHACHA20 (0x8 << 17)
404#define CONTEXT_CONTROL_CRYPTO_ALG_SM4 (0xd << 17)
405#define CONTEXT_CONTROL_DIGEST_INITIAL (0x0 << 21)
406#define CONTEXT_CONTROL_DIGEST_PRECOMPUTED (0x1 << 21)
407#define CONTEXT_CONTROL_DIGEST_XCM (0x2 << 21)
408#define CONTEXT_CONTROL_DIGEST_HMAC (0x3 << 21)
409#define CONTEXT_CONTROL_CRYPTO_ALG_MD5 (0x0 << 23)
410#define CONTEXT_CONTROL_CRYPTO_ALG_CRC32 (0x0 << 23)
411#define CONTEXT_CONTROL_CRYPTO_ALG_SHA1 (0x2 << 23)
412#define CONTEXT_CONTROL_CRYPTO_ALG_SHA224 (0x4 << 23)
413#define CONTEXT_CONTROL_CRYPTO_ALG_SHA256 (0x3 << 23)
414#define CONTEXT_CONTROL_CRYPTO_ALG_SHA384 (0x6 << 23)
415#define CONTEXT_CONTROL_CRYPTO_ALG_SHA512 (0x5 << 23)
416#define CONTEXT_CONTROL_CRYPTO_ALG_GHASH (0x4 << 23)
417#define CONTEXT_CONTROL_CRYPTO_ALG_XCBC128 (0x1 << 23)
418#define CONTEXT_CONTROL_CRYPTO_ALG_XCBC192 (0x2 << 23)
419#define CONTEXT_CONTROL_CRYPTO_ALG_XCBC256 (0x3 << 23)
420#define CONTEXT_CONTROL_CRYPTO_ALG_SM3 (0x7 << 23)
421#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_256 (0xb << 23)
422#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_224 (0xc << 23)
423#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_512 (0xd << 23)
424#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_384 (0xe << 23)
425#define CONTEXT_CONTROL_CRYPTO_ALG_POLY1305 (0xf << 23)
426#define CONTEXT_CONTROL_INV_FR (0x5 << 24)
427#define CONTEXT_CONTROL_INV_TR (0x6 << 24)
428
429/* control1 */
430#define CONTEXT_CONTROL_CRYPTO_MODE_ECB (0 << 0)
431#define CONTEXT_CONTROL_CRYPTO_MODE_CBC (1 << 0)
432#define CONTEXT_CONTROL_CHACHA20_MODE_256_32 (2 << 0)
433#define CONTEXT_CONTROL_CRYPTO_MODE_OFB (4 << 0)
434#define CONTEXT_CONTROL_CRYPTO_MODE_CFB (5 << 0)
435#define CONTEXT_CONTROL_CRYPTO_MODE_CTR_LOAD (6 << 0)
436#define CONTEXT_CONTROL_CRYPTO_MODE_XTS (7 << 0)
437#define CONTEXT_CONTROL_CRYPTO_MODE_XCM ((6 << 0) | BIT(17))
438#define CONTEXT_CONTROL_CHACHA20_MODE_CALC_OTK (12 << 0)
439#define CONTEXT_CONTROL_IV0 BIT(5)
440#define CONTEXT_CONTROL_IV1 BIT(6)
441#define CONTEXT_CONTROL_IV2 BIT(7)
442#define CONTEXT_CONTROL_IV3 BIT(8)
443#define CONTEXT_CONTROL_DIGEST_CNT BIT(9)
444#define CONTEXT_CONTROL_COUNTER_MODE BIT(10)
445#define CONTEXT_CONTROL_CRYPTO_STORE BIT(12)
446#define CONTEXT_CONTROL_HASH_STORE BIT(19)
447
448#define EIP197_XCM_MODE_GCM 1
449#define EIP197_XCM_MODE_CCM 2
450
451#define EIP197_AEAD_TYPE_IPSEC_ESP 2
452#define EIP197_AEAD_TYPE_IPSEC_ESP_GMAC 3
453#define EIP197_AEAD_IPSEC_IV_SIZE 8
454#define EIP197_AEAD_IPSEC_NONCE_SIZE 4
455#define EIP197_AEAD_IPSEC_COUNTER_SIZE 4
456#define EIP197_AEAD_IPSEC_CCM_NONCE_SIZE 3
457
458/* The hash counter given to the engine in the context has a granularity of
459 * 64 bits.
460 */
461#define EIP197_COUNTER_BLOCK_SIZE 64
462
463/* EIP197_CS_RAM_CTRL */
464#define EIP197_TRC_ENABLE_0 BIT(4)
465#define EIP197_TRC_ENABLE_1 BIT(5)
466#define EIP197_TRC_ENABLE_2 BIT(6)
467#define EIP197_TRC_ENABLE_MASK GENMASK(6, 4)
468#define EIP197_CS_BANKSEL_MASK GENMASK(14, 12)
469#define EIP197_CS_BANKSEL_OFS 12
470
471/* EIP197_TRC_PARAMS */
472#define EIP197_TRC_PARAMS_SW_RESET BIT(0)
473#define EIP197_TRC_PARAMS_DATA_ACCESS BIT(2)
474#define EIP197_TRC_PARAMS_HTABLE_SZ(x) ((x) << 4)
475#define EIP197_TRC_PARAMS_BLK_TIMER_SPEED(x) ((x) << 10)
476#define EIP197_TRC_PARAMS_RC_SZ_LARGE(n) ((n) << 18)
477
478/* EIP197_TRC_FREECHAIN */
479#define EIP197_TRC_FREECHAIN_HEAD_PTR(p) (p)
480#define EIP197_TRC_FREECHAIN_TAIL_PTR(p) ((p) << 16)
481
482/* EIP197_TRC_PARAMS2 */
483#define EIP197_TRC_PARAMS2_HTABLE_PTR(p) (p)
484#define EIP197_TRC_PARAMS2_RC_SZ_SMALL(n) ((n) << 18)
485
486/* Cache helpers */
487#define EIP197_MIN_DSIZE 1024
488#define EIP197_MIN_ASIZE 8
489#define EIP197_CS_TRC_REC_WC 64
490#define EIP197_CS_RC_SIZE (4 * sizeof(u32))
491#define EIP197_CS_RC_NEXT(x) (x)
492#define EIP197_CS_RC_PREV(x) ((x) << 10)
493#define EIP197_RC_NULL 0x3ff
494
495/* Result data */
496struct result_data_desc {
497 u32 packet_length:17;
498 u32 error_code:15;
499
500 u32 bypass_length:4;
501 u32 e15:1;
502 u32 rsvd0:16;
503 u32 hash_bytes:1;
504 u32 hash_length:6;
505 u32 generic_bytes:1;
506 u32 checksum:1;
507 u32 next_header:1;
508 u32 length:1;
509
510 u16 application_id;
511 u16 rsvd1;
512
513 u32 rsvd2[5];
514} __packed;
515
516
517/* Basic Result Descriptor format */
518struct safexcel_result_desc {
519 u32 particle_size:17;
520 u8 rsvd0:3;
521 u8 descriptor_overflow:1;
522 u8 buffer_overflow:1;
523 u8 last_seg:1;
524 u8 first_seg:1;
525 u16 result_size:8;
526
527 u32 rsvd1;
528
529 u32 data_lo;
530 u32 data_hi;
531} __packed;
532
533/*
534 * The EIP(1)97 only needs to fetch the descriptor part of
535 * the result descriptor, not the result token part!
536 */
537#define EIP197_RD64_FETCH_SIZE (sizeof(struct safexcel_result_desc) /\
538 sizeof(u32))
539#define EIP197_RD64_RESULT_SIZE (sizeof(struct result_data_desc) /\
540 sizeof(u32))
541
542struct safexcel_token {
543 u32 packet_length:17;
544 u8 stat:2;
545 u16 instructions:9;
546 u8 opcode:4;
547} __packed;
548
549#define EIP197_TOKEN_HASH_RESULT_VERIFY BIT(16)
550
551#define EIP197_TOKEN_CTX_OFFSET(x) (x)
552#define EIP197_TOKEN_DIRECTION_EXTERNAL BIT(11)
553#define EIP197_TOKEN_EXEC_IF_SUCCESSFUL (0x1 << 12)
554
555#define EIP197_TOKEN_STAT_LAST_HASH BIT(0)
556#define EIP197_TOKEN_STAT_LAST_PACKET BIT(1)
557#define EIP197_TOKEN_OPCODE_DIRECTION 0x0
558#define EIP197_TOKEN_OPCODE_INSERT 0x2
559#define EIP197_TOKEN_OPCODE_NOOP EIP197_TOKEN_OPCODE_INSERT
560#define EIP197_TOKEN_OPCODE_RETRIEVE 0x4
561#define EIP197_TOKEN_OPCODE_INSERT_REMRES 0xa
562#define EIP197_TOKEN_OPCODE_VERIFY 0xd
563#define EIP197_TOKEN_OPCODE_CTX_ACCESS 0xe
564#define EIP197_TOKEN_OPCODE_BYPASS GENMASK(3, 0)
565
566static inline void eip197_noop_token(struct safexcel_token *token)
567{
568 token->opcode = EIP197_TOKEN_OPCODE_NOOP;
569 token->packet_length = BIT(2);
570 token->stat = 0;
571 token->instructions = 0;
572}
573
574/* Instructions */
575#define EIP197_TOKEN_INS_INSERT_HASH_DIGEST 0x1c
576#define EIP197_TOKEN_INS_ORIGIN_IV0 0x14
577#define EIP197_TOKEN_INS_ORIGIN_TOKEN 0x1b
578#define EIP197_TOKEN_INS_ORIGIN_LEN(x) ((x) << 5)
579#define EIP197_TOKEN_INS_TYPE_OUTPUT BIT(5)
580#define EIP197_TOKEN_INS_TYPE_HASH BIT(6)
581#define EIP197_TOKEN_INS_TYPE_CRYPTO BIT(7)
582#define EIP197_TOKEN_INS_LAST BIT(8)
583
584/* Processing Engine Control Data */
585struct safexcel_control_data_desc {
586 u32 packet_length:17;
587 u16 options:13;
588 u8 type:2;
589
590 u16 application_id;
591 u16 rsvd;
592
593 u32 context_lo;
594 u32 context_hi;
595
596 u32 control0;
597 u32 control1;
598
599 u32 token[EIP197_EMB_TOKENS];
600} __packed;
601
602#define EIP197_OPTION_MAGIC_VALUE BIT(0)
603#define EIP197_OPTION_64BIT_CTX BIT(1)
604#define EIP197_OPTION_RC_AUTO (0x2 << 3)
605#define EIP197_OPTION_CTX_CTRL_IN_CMD BIT(8)
606#define EIP197_OPTION_2_TOKEN_IV_CMD GENMASK(11, 10)
607#define EIP197_OPTION_4_TOKEN_IV_CMD GENMASK(11, 9)
608
609#define EIP197_TYPE_BCLA 0x0
610#define EIP197_TYPE_EXTENDED 0x3
611#define EIP197_CONTEXT_SMALL 0x2
612#define EIP197_CONTEXT_SIZE_MASK 0x3
613
614/* Basic Command Descriptor format */
615struct safexcel_command_desc {
616 u32 particle_size:17;
617 u8 rsvd0:5;
618 u8 last_seg:1;
619 u8 first_seg:1;
620 u8 additional_cdata_size:8;
621
622 u32 rsvd1;
623
624 u32 data_lo;
625 u32 data_hi;
626
627 u32 atok_lo;
628 u32 atok_hi;
629
630 struct safexcel_control_data_desc control_data;
631} __packed;
632
633#define EIP197_CD64_FETCH_SIZE (sizeof(struct safexcel_command_desc) /\
634 sizeof(u32))
635
636/*
637 * Internal structures & functions
638 */
639
640#define EIP197_FW_TERMINAL_NOPS 2
641#define EIP197_FW_START_POLLCNT 16
642#define EIP197_FW_PUE_READY 0x14
643#define EIP197_FW_FPP_READY 0x18
644
645enum eip197_fw {
646 FW_IFPP = 0,
647 FW_IPUE,
648 FW_NB
649};
650
651struct safexcel_desc_ring {
652 void *base;
653 void *shbase;
654 void *base_end;
655 void *shbase_end;
656 dma_addr_t base_dma;
657 dma_addr_t shbase_dma;
658
659 /* write and read pointers */
660 void *write;
661 void *shwrite;
662 void *read;
663
664 /* descriptor element offset */
665 unsigned int offset;
666 unsigned int shoffset;
667};
668
669enum safexcel_alg_type {
670 SAFEXCEL_ALG_TYPE_SKCIPHER,
671 SAFEXCEL_ALG_TYPE_AEAD,
672 SAFEXCEL_ALG_TYPE_AHASH,
673};
674
675struct safexcel_config {
676 u32 pes;
677 u32 rings;
678
679 u32 cd_size;
680 u32 cd_offset;
681 u32 cdsh_offset;
682
683 u32 rd_size;
684 u32 rd_offset;
685 u32 res_offset;
686};
687
688struct safexcel_work_data {
689 struct work_struct work;
690 struct safexcel_crypto_priv *priv;
691 int ring;
692};
693
694struct safexcel_ring {
695 spinlock_t lock;
696
697 struct workqueue_struct *workqueue;
698 struct safexcel_work_data work_data;
699
700 /* command/result rings */
701 struct safexcel_desc_ring cdr;
702 struct safexcel_desc_ring rdr;
703
704 /* result ring crypto API request */
705 struct crypto_async_request **rdr_req;
706
707 /* queue */
708 struct crypto_queue queue;
709 spinlock_t queue_lock;
710
711 /* Number of requests in the engine. */
712 int requests;
713
714 /* The ring is currently handling at least one request */
715 bool busy;
716
717 /* Store for current requests when bailing out of the dequeueing
718 * function when no enough resources are available.
719 */
720 struct crypto_async_request *req;
721 struct crypto_async_request *backlog;
722
723 /* irq of this ring */
724 int irq;
725};
726
727/* EIP integration context flags */
728enum safexcel_eip_version {
729 /* Platform (EIP integration context) specifier */
730 EIP97IES_MRVL,
731 EIP197B_MRVL,
732 EIP197D_MRVL,
733 EIP197_DEVBRD,
734 EIP197C_MXL,
735};
736
737struct safexcel_priv_data {
738 enum safexcel_eip_version version;
739 bool fw_little_endian;
740};
741
742/* Priority we use for advertising our algorithms */
743#define SAFEXCEL_CRA_PRIORITY 300
744
745/* SM3 digest result for zero length message */
746#define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \
747 "\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \
748 "\x22\xBE\xC8\xC7\x28\xFE\xFB\x74" \
749 "\x7E\xD0\x35\xEB\x50\x82\xAA\x2B"
750
751/* EIP algorithm presence flags */
752enum safexcel_eip_algorithms {
753 SAFEXCEL_ALG_BC0 = BIT(5),
754 SAFEXCEL_ALG_SM4 = BIT(6),
755 SAFEXCEL_ALG_SM3 = BIT(7),
756 SAFEXCEL_ALG_CHACHA20 = BIT(8),
757 SAFEXCEL_ALG_POLY1305 = BIT(9),
758 SAFEXCEL_SEQMASK_256 = BIT(10),
759 SAFEXCEL_SEQMASK_384 = BIT(11),
760 SAFEXCEL_ALG_AES = BIT(12),
761 SAFEXCEL_ALG_AES_XFB = BIT(13),
762 SAFEXCEL_ALG_DES = BIT(15),
763 SAFEXCEL_ALG_DES_XFB = BIT(16),
764 SAFEXCEL_ALG_ARC4 = BIT(18),
765 SAFEXCEL_ALG_AES_XTS = BIT(20),
766 SAFEXCEL_ALG_WIRELESS = BIT(21),
767 SAFEXCEL_ALG_MD5 = BIT(22),
768 SAFEXCEL_ALG_SHA1 = BIT(23),
769 SAFEXCEL_ALG_SHA2_256 = BIT(25),
770 SAFEXCEL_ALG_SHA2_512 = BIT(26),
771 SAFEXCEL_ALG_XCBC_MAC = BIT(27),
772 SAFEXCEL_ALG_CBC_MAC_ALL = BIT(29),
773 SAFEXCEL_ALG_GHASH = BIT(30),
774 SAFEXCEL_ALG_SHA3 = BIT(31),
775};
776
777struct safexcel_register_offsets {
778 u32 hia_aic;
779 u32 hia_aic_g;
780 u32 hia_aic_r;
781 u32 hia_aic_xdr;
782 u32 hia_dfe;
783 u32 hia_dfe_thr;
784 u32 hia_dse;
785 u32 hia_dse_thr;
786 u32 hia_gen_cfg;
787 u32 pe;
788 u32 global;
789};
790
791enum safexcel_flags {
792 EIP197_TRC_CACHE = BIT(0),
793 SAFEXCEL_HW_EIP197 = BIT(1),
794 EIP197_PE_ARB = BIT(2),
795 EIP197_ICE = BIT(3),
796 EIP197_SIMPLE_TRC = BIT(4),
797 EIP197_OCE = BIT(5),
798};
799
800struct safexcel_hwconfig {
801 enum safexcel_eip_algorithms algo_flags;
802 int hwver;
803 int hiaver;
804 int ppver;
805 int icever;
806 int pever;
807 int ocever;
808 int psever;
809 int hwdataw;
810 int hwcfsize;
811 int hwrfsize;
812 int hwnumpes;
813 int hwnumrings;
814 int hwnumraic;
815};
816
817struct safexcel_crypto_priv {
818 void __iomem *base;
819 struct device *dev;
820 struct clk *clk;
821 struct clk *reg_clk;
822 struct safexcel_config config;
823
824 struct safexcel_priv_data *data;
825 struct safexcel_register_offsets offsets;
826 struct safexcel_hwconfig hwconfig;
827 u32 flags;
828
829 /* context DMA pool */
830 struct dma_pool *context_pool;
831
832 atomic_t ring_used;
833
834 struct safexcel_ring *ring;
835};
836
837struct safexcel_context {
838 int (*send)(struct crypto_async_request *req, int ring,
839 int *commands, int *results);
840 int (*handle_result)(struct safexcel_crypto_priv *priv, int ring,
841 struct crypto_async_request *req, bool *complete,
842 int *ret);
843 struct safexcel_context_record *ctxr;
844 struct safexcel_crypto_priv *priv;
845 dma_addr_t ctxr_dma;
846
847 union {
848 __le32 le[SHA3_512_BLOCK_SIZE / 4];
849 __be32 be[SHA3_512_BLOCK_SIZE / 4];
850 u32 word[SHA3_512_BLOCK_SIZE / 4];
851 u8 byte[SHA3_512_BLOCK_SIZE];
852 } ipad, opad;
853
854 int ring;
855 bool needs_inv;
856 bool exit_inv;
857};
858
859#define HASH_CACHE_SIZE SHA512_BLOCK_SIZE
860
861struct safexcel_ahash_export_state {
862 u64 len;
863 u64 processed;
864
865 u32 digest;
866
867 u32 state[SHA512_DIGEST_SIZE / sizeof(u32)];
868 u8 cache[HASH_CACHE_SIZE];
869};
870
871/*
872 * Template structure to describe the algorithms in order to register them.
873 * It also has the purpose to contain our private structure and is actually
874 * the only way I know in this framework to avoid having global pointers...
875 */
876struct safexcel_alg_template {
877 struct safexcel_crypto_priv *priv;
878 enum safexcel_alg_type type;
879 enum safexcel_eip_algorithms algo_mask;
880 union {
881 struct skcipher_alg skcipher;
882 struct aead_alg aead;
883 struct ahash_alg ahash;
884 } alg;
885};
886
887void safexcel_dequeue(struct safexcel_crypto_priv *priv, int ring);
888int safexcel_rdesc_check_errors(struct safexcel_crypto_priv *priv,
889 void *rdp);
890void safexcel_complete(struct safexcel_crypto_priv *priv, int ring);
891int safexcel_invalidate_cache(struct crypto_async_request *async,
892 struct safexcel_crypto_priv *priv,
893 dma_addr_t ctxr_dma, int ring);
894int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv,
895 struct safexcel_desc_ring *cdr,
896 struct safexcel_desc_ring *rdr);
897int safexcel_select_ring(struct safexcel_crypto_priv *priv);
898void *safexcel_ring_next_rptr(struct safexcel_crypto_priv *priv,
899 struct safexcel_desc_ring *ring);
900void *safexcel_ring_first_rptr(struct safexcel_crypto_priv *priv, int ring);
901void safexcel_ring_rollback_wptr(struct safexcel_crypto_priv *priv,
902 struct safexcel_desc_ring *ring);
903struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *priv,
904 int ring_id,
905 bool first, bool last,
906 dma_addr_t data, u32 len,
907 u32 full_data_len,
908 dma_addr_t context,
909 struct safexcel_token **atoken);
910struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *priv,
911 int ring_id,
912 bool first, bool last,
913 dma_addr_t data, u32 len);
914int safexcel_ring_first_rdr_index(struct safexcel_crypto_priv *priv,
915 int ring);
916int safexcel_ring_rdr_rdesc_index(struct safexcel_crypto_priv *priv,
917 int ring,
918 struct safexcel_result_desc *rdesc);
919void safexcel_rdr_req_set(struct safexcel_crypto_priv *priv,
920 int ring,
921 struct safexcel_result_desc *rdesc,
922 struct crypto_async_request *req);
923inline struct crypto_async_request *
924safexcel_rdr_req_get(struct safexcel_crypto_priv *priv, int ring);
925int safexcel_hmac_setkey(struct safexcel_context *base, const u8 *key,
926 unsigned int keylen, const char *alg,
927 unsigned int state_sz);
928
929/* available algorithms */
930extern struct safexcel_alg_template safexcel_alg_ecb_des;
931extern struct safexcel_alg_template safexcel_alg_cbc_des;
932extern struct safexcel_alg_template safexcel_alg_ecb_des3_ede;
933extern struct safexcel_alg_template safexcel_alg_cbc_des3_ede;
934extern struct safexcel_alg_template safexcel_alg_ecb_aes;
935extern struct safexcel_alg_template safexcel_alg_cbc_aes;
936extern struct safexcel_alg_template safexcel_alg_ctr_aes;
937extern struct safexcel_alg_template safexcel_alg_md5;
938extern struct safexcel_alg_template safexcel_alg_sha1;
939extern struct safexcel_alg_template safexcel_alg_sha224;
940extern struct safexcel_alg_template safexcel_alg_sha256;
941extern struct safexcel_alg_template safexcel_alg_sha384;
942extern struct safexcel_alg_template safexcel_alg_sha512;
943extern struct safexcel_alg_template safexcel_alg_hmac_md5;
944extern struct safexcel_alg_template safexcel_alg_hmac_sha1;
945extern struct safexcel_alg_template safexcel_alg_hmac_sha224;
946extern struct safexcel_alg_template safexcel_alg_hmac_sha256;
947extern struct safexcel_alg_template safexcel_alg_hmac_sha384;
948extern struct safexcel_alg_template safexcel_alg_hmac_sha512;
949extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_aes;
950extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_aes;
951extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_aes;
952extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_aes;
953extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_aes;
954extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_des3_ede;
955extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_ctr_aes;
956extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_ctr_aes;
957extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_ctr_aes;
958extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_ctr_aes;
959extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_ctr_aes;
960extern struct safexcel_alg_template safexcel_alg_xts_aes;
961extern struct safexcel_alg_template safexcel_alg_gcm;
962extern struct safexcel_alg_template safexcel_alg_ccm;
963extern struct safexcel_alg_template safexcel_alg_crc32;
964extern struct safexcel_alg_template safexcel_alg_cbcmac;
965extern struct safexcel_alg_template safexcel_alg_xcbcmac;
966extern struct safexcel_alg_template safexcel_alg_cmac;
967extern struct safexcel_alg_template safexcel_alg_chacha20;
968extern struct safexcel_alg_template safexcel_alg_chachapoly;
969extern struct safexcel_alg_template safexcel_alg_chachapoly_esp;
970extern struct safexcel_alg_template safexcel_alg_sm3;
971extern struct safexcel_alg_template safexcel_alg_hmac_sm3;
972extern struct safexcel_alg_template safexcel_alg_ecb_sm4;
973extern struct safexcel_alg_template safexcel_alg_cbc_sm4;
974extern struct safexcel_alg_template safexcel_alg_ctr_sm4;
975extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_sm4;
976extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sm3_cbc_sm4;
977extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_ctr_sm4;
978extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sm3_ctr_sm4;
979extern struct safexcel_alg_template safexcel_alg_sha3_224;
980extern struct safexcel_alg_template safexcel_alg_sha3_256;
981extern struct safexcel_alg_template safexcel_alg_sha3_384;
982extern struct safexcel_alg_template safexcel_alg_sha3_512;
983extern struct safexcel_alg_template safexcel_alg_hmac_sha3_224;
984extern struct safexcel_alg_template safexcel_alg_hmac_sha3_256;
985extern struct safexcel_alg_template safexcel_alg_hmac_sha3_384;
986extern struct safexcel_alg_template safexcel_alg_hmac_sha3_512;
987extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_des;
988extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_des3_ede;
989extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_des3_ede;
990extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_des3_ede;
991extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_des3_ede;
992extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_des;
993extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_des;
994extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_des;
995extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_des;
996extern struct safexcel_alg_template safexcel_alg_rfc4106_gcm;
997extern struct safexcel_alg_template safexcel_alg_rfc4543_gcm;
998extern struct safexcel_alg_template safexcel_alg_rfc4309_ccm;
999
1000#endif