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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Western Digital Corporation or its affiliates.
4 *
5 * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
6 * CLINT MMIO timer device.
7 */
8
9#define pr_fmt(fmt) "clint: " fmt
10#include <linux/bitops.h>
11#include <linux/clocksource.h>
12#include <linux/clockchips.h>
13#include <linux/cpu.h>
14#include <linux/delay.h>
15#include <linux/module.h>
16#include <linux/of_address.h>
17#include <linux/sched_clock.h>
18#include <linux/io-64-nonatomic-lo-hi.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/irqchip/chained_irq.h>
22#include <linux/irqdomain.h>
23#include <linux/of_irq.h>
24#include <linux/smp.h>
25#include <linux/timex.h>
26
27#ifndef CONFIG_RISCV_M_MODE
28#include <asm/clint.h>
29#endif
30
31#define CLINT_IPI_OFF 0
32#define CLINT_TIMER_CMP_OFF 0x4000
33#define CLINT_TIMER_VAL_OFF 0xbff8
34
35/* CLINT manages IPI and Timer for RISC-V M-mode */
36static u32 __iomem *clint_ipi_base;
37static unsigned int clint_ipi_irq;
38static u64 __iomem *clint_timer_cmp;
39static u64 __iomem *clint_timer_val;
40static unsigned long clint_timer_freq;
41static unsigned int clint_timer_irq;
42
43#ifdef CONFIG_RISCV_M_MODE
44u64 __iomem *clint_time_val;
45EXPORT_SYMBOL(clint_time_val);
46#endif
47
48#ifdef CONFIG_SMP
49static void clint_send_ipi(unsigned int cpu)
50{
51 writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu));
52}
53
54static void clint_clear_ipi(void)
55{
56 writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id()));
57}
58
59static void clint_ipi_interrupt(struct irq_desc *desc)
60{
61 struct irq_chip *chip = irq_desc_get_chip(desc);
62
63 chained_irq_enter(chip, desc);
64
65 clint_clear_ipi();
66 ipi_mux_process();
67
68 chained_irq_exit(chip, desc);
69}
70#endif
71
72#ifdef CONFIG_64BIT
73#define clint_get_cycles() readq_relaxed(clint_timer_val)
74#else
75#define clint_get_cycles() readl_relaxed(clint_timer_val)
76#define clint_get_cycles_hi() readl_relaxed(((u32 *)clint_timer_val) + 1)
77#endif
78
79#ifdef CONFIG_64BIT
80static u64 notrace clint_get_cycles64(void)
81{
82 return clint_get_cycles();
83}
84#else /* CONFIG_64BIT */
85static u64 notrace clint_get_cycles64(void)
86{
87 u32 hi, lo;
88
89 do {
90 hi = clint_get_cycles_hi();
91 lo = clint_get_cycles();
92 } while (hi != clint_get_cycles_hi());
93
94 return ((u64)hi << 32) | lo;
95}
96#endif /* CONFIG_64BIT */
97
98static u64 clint_rdtime(struct clocksource *cs)
99{
100 return clint_get_cycles64();
101}
102
103static struct clocksource clint_clocksource = {
104 .name = "clint_clocksource",
105 .rating = 300,
106 .mask = CLOCKSOURCE_MASK(64),
107 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
108 .read = clint_rdtime,
109};
110
111static int clint_clock_next_event(unsigned long delta,
112 struct clock_event_device *ce)
113{
114 void __iomem *r = clint_timer_cmp +
115 cpuid_to_hartid_map(smp_processor_id());
116
117 csr_set(CSR_IE, IE_TIE);
118 writeq_relaxed(clint_get_cycles64() + delta, r);
119 return 0;
120}
121
122static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) = {
123 .name = "clint_clockevent",
124 .features = CLOCK_EVT_FEAT_ONESHOT,
125 .rating = 100,
126 .set_next_event = clint_clock_next_event,
127};
128
129static int clint_timer_starting_cpu(unsigned int cpu)
130{
131 struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu);
132
133 ce->cpumask = cpumask_of(cpu);
134 clockevents_config_and_register(ce, clint_timer_freq, 100, 0x7fffffff);
135
136 enable_percpu_irq(clint_timer_irq,
137 irq_get_trigger_type(clint_timer_irq));
138 enable_percpu_irq(clint_ipi_irq,
139 irq_get_trigger_type(clint_ipi_irq));
140 return 0;
141}
142
143static int clint_timer_dying_cpu(unsigned int cpu)
144{
145 disable_percpu_irq(clint_timer_irq);
146 /*
147 * Don't disable IPI when CPU goes offline because
148 * the masking/unmasking of virtual IPIs is done
149 * via generic IPI-Mux
150 */
151 return 0;
152}
153
154static irqreturn_t clint_timer_interrupt(int irq, void *dev_id)
155{
156 struct clock_event_device *evdev = this_cpu_ptr(&clint_clock_event);
157
158 csr_clear(CSR_IE, IE_TIE);
159 evdev->event_handler(evdev);
160
161 return IRQ_HANDLED;
162}
163
164static int __init clint_timer_init_dt(struct device_node *np)
165{
166 int rc;
167 u32 i, nr_irqs;
168 void __iomem *base;
169 struct of_phandle_args oirq;
170
171 /*
172 * Ensure that CLINT device interrupts are either RV_IRQ_TIMER or
173 * RV_IRQ_SOFT. If it's anything else then we ignore the device.
174 */
175 nr_irqs = of_irq_count(np);
176 for (i = 0; i < nr_irqs; i++) {
177 if (of_irq_parse_one(np, i, &oirq)) {
178 pr_err("%pOFP: failed to parse irq %d.\n", np, i);
179 continue;
180 }
181
182 if ((oirq.args_count != 1) ||
183 (oirq.args[0] != RV_IRQ_TIMER &&
184 oirq.args[0] != RV_IRQ_SOFT)) {
185 pr_err("%pOFP: invalid irq %d (hwirq %d)\n",
186 np, i, oirq.args[0]);
187 return -ENODEV;
188 }
189
190 /* Find parent irq domain and map ipi irq */
191 if (!clint_ipi_irq &&
192 oirq.args[0] == RV_IRQ_SOFT &&
193 irq_find_host(oirq.np))
194 clint_ipi_irq = irq_of_parse_and_map(np, i);
195
196 /* Find parent irq domain and map timer irq */
197 if (!clint_timer_irq &&
198 oirq.args[0] == RV_IRQ_TIMER &&
199 irq_find_host(oirq.np))
200 clint_timer_irq = irq_of_parse_and_map(np, i);
201 }
202
203 /* If CLINT ipi or timer irq not found then fail */
204 if (!clint_ipi_irq || !clint_timer_irq) {
205 pr_err("%pOFP: ipi/timer irq not found\n", np);
206 return -ENODEV;
207 }
208
209 base = of_iomap(np, 0);
210 if (!base) {
211 pr_err("%pOFP: could not map registers\n", np);
212 return -ENODEV;
213 }
214
215 clint_ipi_base = base + CLINT_IPI_OFF;
216 clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
217 clint_timer_val = base + CLINT_TIMER_VAL_OFF;
218 clint_timer_freq = riscv_timebase;
219
220#ifdef CONFIG_RISCV_M_MODE
221 /*
222 * Yes, that's an odd naming scheme. time_val is public, but hopefully
223 * will die in favor of something cleaner.
224 */
225 clint_time_val = clint_timer_val;
226#endif
227
228 pr_info("%pOFP: timer running at %ld Hz\n", np, clint_timer_freq);
229
230 rc = clocksource_register_hz(&clint_clocksource, clint_timer_freq);
231 if (rc) {
232 pr_err("%pOFP: clocksource register failed [%d]\n", np, rc);
233 goto fail_iounmap;
234 }
235
236 sched_clock_register(clint_get_cycles64, 64, clint_timer_freq);
237
238 rc = request_percpu_irq(clint_timer_irq, clint_timer_interrupt,
239 "clint-timer", &clint_clock_event);
240 if (rc) {
241 pr_err("registering percpu irq failed [%d]\n", rc);
242 goto fail_iounmap;
243 }
244
245#ifdef CONFIG_SMP
246 rc = ipi_mux_create(BITS_PER_BYTE, clint_send_ipi);
247 if (rc <= 0) {
248 pr_err("unable to create muxed IPIs\n");
249 rc = (rc < 0) ? rc : -ENODEV;
250 goto fail_free_irq;
251 }
252
253 irq_set_chained_handler(clint_ipi_irq, clint_ipi_interrupt);
254 riscv_ipi_set_virq_range(rc, BITS_PER_BYTE, true);
255 clint_clear_ipi();
256#endif
257
258 rc = cpuhp_setup_state(CPUHP_AP_CLINT_TIMER_STARTING,
259 "clockevents/clint/timer:starting",
260 clint_timer_starting_cpu,
261 clint_timer_dying_cpu);
262 if (rc) {
263 pr_err("%pOFP: cpuhp setup state failed [%d]\n", np, rc);
264 goto fail_free_irq;
265 }
266
267 return 0;
268
269fail_free_irq:
270 free_percpu_irq(clint_timer_irq, &clint_clock_event);
271fail_iounmap:
272 iounmap(base);
273 return rc;
274}
275
276TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt);
277TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Western Digital Corporation or its affiliates.
4 *
5 * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
6 * CLINT MMIO timer device.
7 */
8
9#define pr_fmt(fmt) "clint: " fmt
10#include <linux/bitops.h>
11#include <linux/clocksource.h>
12#include <linux/clockchips.h>
13#include <linux/cpu.h>
14#include <linux/delay.h>
15#include <linux/module.h>
16#include <linux/of_address.h>
17#include <linux/sched_clock.h>
18#include <linux/io-64-nonatomic-lo-hi.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/irqchip/chained_irq.h>
22#include <linux/irqdomain.h>
23#include <linux/of_irq.h>
24#include <linux/smp.h>
25#include <linux/timex.h>
26
27#ifndef CONFIG_RISCV_M_MODE
28#include <asm/clint.h>
29#endif
30
31#define CLINT_IPI_OFF 0
32#define CLINT_TIMER_CMP_OFF 0x4000
33#define CLINT_TIMER_VAL_OFF 0xbff8
34
35/* CLINT manages IPI and Timer for RISC-V M-mode */
36static u32 __iomem *clint_ipi_base;
37static unsigned int clint_ipi_irq;
38static u64 __iomem *clint_timer_cmp;
39static u64 __iomem *clint_timer_val;
40static unsigned long clint_timer_freq;
41static unsigned int clint_timer_irq;
42
43#ifdef CONFIG_RISCV_M_MODE
44u64 __iomem *clint_time_val;
45EXPORT_SYMBOL(clint_time_val);
46#endif
47
48#ifdef CONFIG_SMP
49static void clint_send_ipi(unsigned int cpu)
50{
51 writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu));
52}
53
54static void clint_clear_ipi(void)
55{
56 writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id()));
57}
58
59static void clint_ipi_interrupt(struct irq_desc *desc)
60{
61 struct irq_chip *chip = irq_desc_get_chip(desc);
62
63 chained_irq_enter(chip, desc);
64
65 clint_clear_ipi();
66 ipi_mux_process();
67
68 chained_irq_exit(chip, desc);
69}
70#endif
71
72#ifdef CONFIG_64BIT
73#define clint_get_cycles() readq_relaxed(clint_timer_val)
74#else
75#define clint_get_cycles() readl_relaxed(clint_timer_val)
76#define clint_get_cycles_hi() readl_relaxed(((u32 *)clint_timer_val) + 1)
77#endif
78
79#ifdef CONFIG_64BIT
80static u64 notrace clint_get_cycles64(void)
81{
82 return clint_get_cycles();
83}
84#else /* CONFIG_64BIT */
85static u64 notrace clint_get_cycles64(void)
86{
87 u32 hi, lo;
88
89 do {
90 hi = clint_get_cycles_hi();
91 lo = clint_get_cycles();
92 } while (hi != clint_get_cycles_hi());
93
94 return ((u64)hi << 32) | lo;
95}
96#endif /* CONFIG_64BIT */
97
98static u64 clint_rdtime(struct clocksource *cs)
99{
100 return clint_get_cycles64();
101}
102
103static struct clocksource clint_clocksource = {
104 .name = "clint_clocksource",
105 .rating = 300,
106 .mask = CLOCKSOURCE_MASK(64),
107 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
108 .read = clint_rdtime,
109};
110
111static int clint_clock_next_event(unsigned long delta,
112 struct clock_event_device *ce)
113{
114 void __iomem *r = clint_timer_cmp +
115 cpuid_to_hartid_map(smp_processor_id());
116
117 csr_set(CSR_IE, IE_TIE);
118 writeq_relaxed(clint_get_cycles64() + delta, r);
119 return 0;
120}
121
122static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) = {
123 .name = "clint_clockevent",
124 .features = CLOCK_EVT_FEAT_ONESHOT,
125 .rating = 100,
126 .set_next_event = clint_clock_next_event,
127};
128
129static int clint_timer_starting_cpu(unsigned int cpu)
130{
131 struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu);
132
133 ce->cpumask = cpumask_of(cpu);
134 clockevents_config_and_register(ce, clint_timer_freq, 100, ULONG_MAX);
135
136 enable_percpu_irq(clint_timer_irq,
137 irq_get_trigger_type(clint_timer_irq));
138 enable_percpu_irq(clint_ipi_irq,
139 irq_get_trigger_type(clint_ipi_irq));
140 return 0;
141}
142
143static int clint_timer_dying_cpu(unsigned int cpu)
144{
145 disable_percpu_irq(clint_timer_irq);
146 /*
147 * Don't disable IPI when CPU goes offline because
148 * the masking/unmasking of virtual IPIs is done
149 * via generic IPI-Mux
150 */
151 return 0;
152}
153
154static irqreturn_t clint_timer_interrupt(int irq, void *dev_id)
155{
156 struct clock_event_device *evdev = this_cpu_ptr(&clint_clock_event);
157
158 csr_clear(CSR_IE, IE_TIE);
159 evdev->event_handler(evdev);
160
161 return IRQ_HANDLED;
162}
163
164static int __init clint_timer_init_dt(struct device_node *np)
165{
166 int rc;
167 u32 i, nr_irqs;
168 void __iomem *base;
169 struct of_phandle_args oirq;
170
171 /*
172 * Ensure that CLINT device interrupts are either RV_IRQ_TIMER or
173 * RV_IRQ_SOFT. If it's anything else then we ignore the device.
174 */
175 nr_irqs = of_irq_count(np);
176 for (i = 0; i < nr_irqs; i++) {
177 if (of_irq_parse_one(np, i, &oirq)) {
178 pr_err("%pOFP: failed to parse irq %d.\n", np, i);
179 continue;
180 }
181
182 if ((oirq.args_count != 1) ||
183 (oirq.args[0] != RV_IRQ_TIMER &&
184 oirq.args[0] != RV_IRQ_SOFT)) {
185 pr_err("%pOFP: invalid irq %d (hwirq %d)\n",
186 np, i, oirq.args[0]);
187 return -ENODEV;
188 }
189
190 /* Find parent irq domain and map ipi irq */
191 if (!clint_ipi_irq &&
192 oirq.args[0] == RV_IRQ_SOFT &&
193 irq_find_host(oirq.np))
194 clint_ipi_irq = irq_of_parse_and_map(np, i);
195
196 /* Find parent irq domain and map timer irq */
197 if (!clint_timer_irq &&
198 oirq.args[0] == RV_IRQ_TIMER &&
199 irq_find_host(oirq.np))
200 clint_timer_irq = irq_of_parse_and_map(np, i);
201 }
202
203 /* If CLINT ipi or timer irq not found then fail */
204 if (!clint_ipi_irq || !clint_timer_irq) {
205 pr_err("%pOFP: ipi/timer irq not found\n", np);
206 return -ENODEV;
207 }
208
209 base = of_iomap(np, 0);
210 if (!base) {
211 pr_err("%pOFP: could not map registers\n", np);
212 return -ENODEV;
213 }
214
215 clint_ipi_base = base + CLINT_IPI_OFF;
216 clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
217 clint_timer_val = base + CLINT_TIMER_VAL_OFF;
218 clint_timer_freq = riscv_timebase;
219
220#ifdef CONFIG_RISCV_M_MODE
221 /*
222 * Yes, that's an odd naming scheme. time_val is public, but hopefully
223 * will die in favor of something cleaner.
224 */
225 clint_time_val = clint_timer_val;
226#endif
227
228 pr_info("%pOFP: timer running at %ld Hz\n", np, clint_timer_freq);
229
230 rc = clocksource_register_hz(&clint_clocksource, clint_timer_freq);
231 if (rc) {
232 pr_err("%pOFP: clocksource register failed [%d]\n", np, rc);
233 goto fail_iounmap;
234 }
235
236 sched_clock_register(clint_get_cycles64, 64, clint_timer_freq);
237
238 rc = request_percpu_irq(clint_timer_irq, clint_timer_interrupt,
239 "clint-timer", &clint_clock_event);
240 if (rc) {
241 pr_err("registering percpu irq failed [%d]\n", rc);
242 goto fail_iounmap;
243 }
244
245#ifdef CONFIG_SMP
246 rc = ipi_mux_create(BITS_PER_BYTE, clint_send_ipi);
247 if (rc <= 0) {
248 pr_err("unable to create muxed IPIs\n");
249 rc = (rc < 0) ? rc : -ENODEV;
250 goto fail_free_irq;
251 }
252
253 irq_set_chained_handler(clint_ipi_irq, clint_ipi_interrupt);
254 riscv_ipi_set_virq_range(rc, BITS_PER_BYTE, true);
255 clint_clear_ipi();
256#endif
257
258 rc = cpuhp_setup_state(CPUHP_AP_CLINT_TIMER_STARTING,
259 "clockevents/clint/timer:starting",
260 clint_timer_starting_cpu,
261 clint_timer_dying_cpu);
262 if (rc) {
263 pr_err("%pOFP: cpuhp setup state failed [%d]\n", np, rc);
264 goto fail_free_irq;
265 }
266
267 return 0;
268
269fail_free_irq:
270 free_percpu_irq(clint_timer_irq, &clint_clock_event);
271fail_iounmap:
272 iounmap(base);
273 return rc;
274}
275
276TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt);
277TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt);