Loading...
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2//
3// Copyright(c) 2023 Intel Corporation. All rights reserved.
4
5/*
6 * Hardware interface for audio DSP on LunarLake.
7 */
8
9#include <linux/firmware.h>
10#include <sound/hda_register.h>
11#include <sound/sof/ipc4/header.h>
12#include <trace/events/sof_intel.h>
13#include "../ipc4-priv.h"
14#include "../ops.h"
15#include "hda.h"
16#include "hda-ipc.h"
17#include "../sof-audio.h"
18#include "mtl.h"
19#include <sound/hda-mlink.h>
20
21/* LunarLake ops */
22struct snd_sof_dsp_ops sof_lnl_ops;
23EXPORT_SYMBOL_NS(sof_lnl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
24
25static const struct snd_sof_debugfs_map lnl_dsp_debugfs[] = {
26 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
27 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
28 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
29};
30
31/* this helps allows the DSP to setup DMIC/SSP */
32static int hdac_bus_offload_dmic_ssp(struct hdac_bus *bus)
33{
34 int ret;
35
36 ret = hdac_bus_eml_enable_offload(bus, true, AZX_REG_ML_LEPTR_ID_INTEL_SSP, true);
37 if (ret < 0)
38 return ret;
39
40 ret = hdac_bus_eml_enable_offload(bus, true, AZX_REG_ML_LEPTR_ID_INTEL_DMIC, true);
41 if (ret < 0)
42 return ret;
43
44 return 0;
45}
46
47static int lnl_hda_dsp_probe(struct snd_sof_dev *sdev)
48{
49 int ret;
50
51 ret = hda_dsp_probe(sdev);
52 if (ret < 0)
53 return ret;
54
55 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev));
56}
57
58static int lnl_hda_dsp_resume(struct snd_sof_dev *sdev)
59{
60 int ret;
61
62 ret = hda_dsp_resume(sdev);
63 if (ret < 0)
64 return ret;
65
66 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev));
67}
68
69static int lnl_hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
70{
71 int ret;
72
73 ret = hda_dsp_runtime_resume(sdev);
74 if (ret < 0)
75 return ret;
76
77 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev));
78}
79
80int sof_lnl_ops_init(struct snd_sof_dev *sdev)
81{
82 struct sof_ipc4_fw_data *ipc4_data;
83
84 /* common defaults */
85 memcpy(&sof_lnl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
86
87 /* probe */
88 sof_lnl_ops.probe = lnl_hda_dsp_probe;
89
90 /* shutdown */
91 sof_lnl_ops.shutdown = hda_dsp_shutdown;
92
93 /* doorbell */
94 sof_lnl_ops.irq_thread = mtl_ipc_irq_thread;
95
96 /* ipc */
97 sof_lnl_ops.send_msg = mtl_ipc_send_msg;
98 sof_lnl_ops.get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset;
99 sof_lnl_ops.get_window_offset = mtl_dsp_ipc_get_window_offset;
100
101 /* debug */
102 sof_lnl_ops.debug_map = lnl_dsp_debugfs;
103 sof_lnl_ops.debug_map_count = ARRAY_SIZE(lnl_dsp_debugfs);
104 sof_lnl_ops.dbg_dump = mtl_dsp_dump;
105 sof_lnl_ops.ipc_dump = mtl_ipc_dump;
106
107 /* pre/post fw run */
108 sof_lnl_ops.pre_fw_run = mtl_dsp_pre_fw_run;
109 sof_lnl_ops.post_fw_run = mtl_dsp_post_fw_run;
110
111 /* parse platform specific extended manifest */
112 sof_lnl_ops.parse_platform_ext_manifest = NULL;
113
114 /* dsp core get/put */
115 /* TODO: add core_get and core_put */
116
117 /* PM */
118 sof_lnl_ops.resume = lnl_hda_dsp_resume;
119 sof_lnl_ops.runtime_resume = lnl_hda_dsp_runtime_resume;
120
121 sof_lnl_ops.get_stream_position = mtl_dsp_get_stream_hda_link_position;
122
123 /* dsp core get/put */
124 sof_lnl_ops.core_get = mtl_dsp_core_get;
125 sof_lnl_ops.core_put = mtl_dsp_core_put;
126
127 sdev->private = kzalloc(sizeof(struct sof_ipc4_fw_data), GFP_KERNEL);
128 if (!sdev->private)
129 return -ENOMEM;
130
131 ipc4_data = sdev->private;
132 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
133
134 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;
135
136 ipc4_data->fw_context_save = true;
137
138 /* External library loading support */
139 ipc4_data->load_library = hda_dsp_ipc4_load_library;
140
141 /* set DAI ops */
142 hda_set_dai_drv_ops(sdev, &sof_lnl_ops);
143
144 sof_lnl_ops.set_power_state = hda_dsp_set_power_state_ipc4;
145
146 return 0;
147};
148EXPORT_SYMBOL_NS(sof_lnl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
149
150/* Check if an SDW IRQ occurred */
151static bool lnl_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
152{
153 struct hdac_bus *bus = sof_to_bus(sdev);
154
155 return hdac_bus_eml_check_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW);
156}
157
158static void lnl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
159{
160 struct hdac_bus *bus = sof_to_bus(sdev);
161
162 hdac_bus_eml_enable_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW, enable);
163}
164
165static int lnl_dsp_disable_interrupts(struct snd_sof_dev *sdev)
166{
167 lnl_enable_sdw_irq(sdev, false);
168 mtl_disable_ipc_interrupts(sdev);
169 return mtl_enable_interrupts(sdev, false);
170}
171
172const struct sof_intel_dsp_desc lnl_chip_info = {
173 .cores_num = 5,
174 .init_core_mask = BIT(0),
175 .host_managed_cores_mask = BIT(0),
176 .ipc_req = MTL_DSP_REG_HFIPCXIDR,
177 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY,
178 .ipc_ack = MTL_DSP_REG_HFIPCXIDA,
179 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
180 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
181 .rom_status_reg = MTL_DSP_ROM_STS,
182 .rom_init_timeout = 300,
183 .ssp_count = MTL_SSP_COUNT,
184 .d0i3_offset = MTL_HDA_VS_D0I3C,
185 .read_sdw_lcount = hda_sdw_check_lcount_ext,
186 .enable_sdw_irq = lnl_enable_sdw_irq,
187 .check_sdw_irq = lnl_dsp_check_sdw_irq,
188 .check_ipc_irq = mtl_dsp_check_ipc_irq,
189 .cl_init = mtl_dsp_cl_init,
190 .power_down_dsp = mtl_power_down_dsp,
191 .disable_interrupts = lnl_dsp_disable_interrupts,
192 .hw_ip_version = SOF_INTEL_ACE_2_0,
193};
194EXPORT_SYMBOL_NS(lnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2//
3// Copyright(c) 2023 Intel Corporation. All rights reserved.
4
5/*
6 * Hardware interface for audio DSP on LunarLake.
7 */
8
9#include <linux/firmware.h>
10#include <sound/hda_register.h>
11#include <sound/sof/ipc4/header.h>
12#include <trace/events/sof_intel.h>
13#include "../ipc4-priv.h"
14#include "../ops.h"
15#include "hda.h"
16#include "hda-ipc.h"
17#include "../sof-audio.h"
18#include "mtl.h"
19#include "lnl.h"
20#include <sound/hda-mlink.h>
21
22/* LunarLake ops */
23struct snd_sof_dsp_ops sof_lnl_ops;
24EXPORT_SYMBOL_NS(sof_lnl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
25
26static const struct snd_sof_debugfs_map lnl_dsp_debugfs[] = {
27 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
28 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
29 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
30};
31
32/* this helps allows the DSP to setup DMIC/SSP */
33static int hdac_bus_offload_dmic_ssp(struct hdac_bus *bus, bool enable)
34{
35 int ret;
36
37 ret = hdac_bus_eml_enable_offload(bus, true,
38 AZX_REG_ML_LEPTR_ID_INTEL_SSP, enable);
39 if (ret < 0)
40 return ret;
41
42 ret = hdac_bus_eml_enable_offload(bus, true,
43 AZX_REG_ML_LEPTR_ID_INTEL_DMIC, enable);
44 if (ret < 0)
45 return ret;
46
47 return 0;
48}
49
50static int lnl_hda_dsp_probe(struct snd_sof_dev *sdev)
51{
52 int ret;
53
54 ret = hda_dsp_probe(sdev);
55 if (ret < 0)
56 return ret;
57
58 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev), true);
59}
60
61static void lnl_hda_dsp_remove(struct snd_sof_dev *sdev)
62{
63 int ret;
64
65 ret = hdac_bus_offload_dmic_ssp(sof_to_bus(sdev), false);
66 if (ret < 0)
67 dev_warn(sdev->dev,
68 "Failed to disable offload for DMIC/SSP: %d\n", ret);
69
70 hda_dsp_remove(sdev);
71}
72
73static int lnl_hda_dsp_resume(struct snd_sof_dev *sdev)
74{
75 int ret;
76
77 ret = hda_dsp_resume(sdev);
78 if (ret < 0)
79 return ret;
80
81 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev), true);
82}
83
84static int lnl_hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
85{
86 int ret;
87
88 ret = hda_dsp_runtime_resume(sdev);
89 if (ret < 0)
90 return ret;
91
92 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev), true);
93}
94
95static int lnl_dsp_post_fw_run(struct snd_sof_dev *sdev)
96{
97 if (sdev->first_boot) {
98 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
99
100 /* Check if IMR boot is usable */
101 if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT))
102 hda->imrboot_supported = true;
103 }
104
105 return 0;
106}
107
108int sof_lnl_ops_init(struct snd_sof_dev *sdev)
109{
110 struct sof_ipc4_fw_data *ipc4_data;
111
112 /* common defaults */
113 memcpy(&sof_lnl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
114
115 /* probe/remove */
116 if (!sdev->dspless_mode_selected) {
117 sof_lnl_ops.probe = lnl_hda_dsp_probe;
118 sof_lnl_ops.remove = lnl_hda_dsp_remove;
119 }
120
121 /* shutdown */
122 sof_lnl_ops.shutdown = hda_dsp_shutdown;
123
124 /* doorbell */
125 sof_lnl_ops.irq_thread = mtl_ipc_irq_thread;
126
127 /* ipc */
128 sof_lnl_ops.send_msg = mtl_ipc_send_msg;
129 sof_lnl_ops.get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset;
130 sof_lnl_ops.get_window_offset = mtl_dsp_ipc_get_window_offset;
131
132 /* debug */
133 sof_lnl_ops.debug_map = lnl_dsp_debugfs;
134 sof_lnl_ops.debug_map_count = ARRAY_SIZE(lnl_dsp_debugfs);
135 sof_lnl_ops.dbg_dump = mtl_dsp_dump;
136 sof_lnl_ops.ipc_dump = mtl_ipc_dump;
137
138 /* pre/post fw run */
139 sof_lnl_ops.pre_fw_run = mtl_dsp_pre_fw_run;
140 sof_lnl_ops.post_fw_run = lnl_dsp_post_fw_run;
141
142 /* parse platform specific extended manifest */
143 sof_lnl_ops.parse_platform_ext_manifest = NULL;
144
145 /* dsp core get/put */
146 /* TODO: add core_get and core_put */
147
148 /* PM */
149 if (!sdev->dspless_mode_selected) {
150 sof_lnl_ops.resume = lnl_hda_dsp_resume;
151 sof_lnl_ops.runtime_resume = lnl_hda_dsp_runtime_resume;
152 }
153
154 /* dsp core get/put */
155 sof_lnl_ops.core_get = mtl_dsp_core_get;
156 sof_lnl_ops.core_put = mtl_dsp_core_put;
157
158 sdev->private = kzalloc(sizeof(struct sof_ipc4_fw_data), GFP_KERNEL);
159 if (!sdev->private)
160 return -ENOMEM;
161
162 ipc4_data = sdev->private;
163 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
164
165 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;
166
167 ipc4_data->fw_context_save = true;
168
169 /* External library loading support */
170 ipc4_data->load_library = hda_dsp_ipc4_load_library;
171
172 /* set DAI ops */
173 hda_set_dai_drv_ops(sdev, &sof_lnl_ops);
174
175 sof_lnl_ops.set_power_state = hda_dsp_set_power_state_ipc4;
176
177 return 0;
178};
179EXPORT_SYMBOL_NS(sof_lnl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
180
181/* Check if an SDW IRQ occurred */
182static bool lnl_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
183{
184 struct hdac_bus *bus = sof_to_bus(sdev);
185
186 return hdac_bus_eml_check_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW);
187}
188
189static void lnl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
190{
191 struct hdac_bus *bus = sof_to_bus(sdev);
192
193 hdac_bus_eml_enable_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW, enable);
194}
195
196static int lnl_dsp_disable_interrupts(struct snd_sof_dev *sdev)
197{
198 lnl_enable_sdw_irq(sdev, false);
199 mtl_disable_ipc_interrupts(sdev);
200 return mtl_enable_interrupts(sdev, false);
201}
202
203const struct sof_intel_dsp_desc lnl_chip_info = {
204 .cores_num = 5,
205 .init_core_mask = BIT(0),
206 .host_managed_cores_mask = BIT(0),
207 .ipc_req = MTL_DSP_REG_HFIPCXIDR,
208 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY,
209 .ipc_ack = MTL_DSP_REG_HFIPCXIDA,
210 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
211 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
212 .rom_status_reg = LNL_DSP_REG_HFDSC,
213 .rom_init_timeout = 300,
214 .ssp_count = MTL_SSP_COUNT,
215 .d0i3_offset = MTL_HDA_VS_D0I3C,
216 .read_sdw_lcount = hda_sdw_check_lcount_ext,
217 .enable_sdw_irq = lnl_enable_sdw_irq,
218 .check_sdw_irq = lnl_dsp_check_sdw_irq,
219 .check_ipc_irq = mtl_dsp_check_ipc_irq,
220 .cl_init = mtl_dsp_cl_init,
221 .power_down_dsp = mtl_power_down_dsp,
222 .disable_interrupts = lnl_dsp_disable_interrupts,
223 .hw_ip_version = SOF_INTEL_ACE_2_0,
224};
225EXPORT_SYMBOL_NS(lnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);