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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
4 *
5 *
6 * Name: mpi2_cnfg.h
7 * Title: MPI Configuration messages and pages
8 * Creation Date: November 10, 2006
9 *
10 * mpi2_cnfg.h Version: 02.00.47
11 *
12 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
13 * prefix are for use only on MPI v2.5 products, and must not be used
14 * with MPI v2.0 products. Unless otherwise noted, names beginning with
15 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
16 *
17 * Version History
18 * ---------------
19 *
20 * Date Version Description
21 * -------- -------- ------------------------------------------------------
22 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
23 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
24 * Added Manufacturing Page 11.
25 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
26 * define.
27 * 06-26-07 02.00.02 Adding generic structure for product-specific
28 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
29 * Rework of BIOS Page 2 configuration page.
30 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
31 * forms.
32 * Added configuration pages IOC Page 8 and Driver
33 * Persistent Mapping Page 0.
34 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
35 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
36 * RAID Physical Disk Pages 0 and 1, RAID Configuration
37 * Page 0).
38 * Added new value for AccessStatus field of SAS Device
39 * Page 0 (_SATA_NEEDS_INITIALIZATION).
40 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
41 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
42 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
43 * NVDATA.
44 * Modified IOC Page 7 to use masks and added field for
45 * SASBroadcastPrimitiveMasks.
46 * Added MPI2_CONFIG_PAGE_BIOS_4.
47 * Added MPI2_CONFIG_PAGE_LOG_0.
48 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
49 * Added SAS Device IDs.
50 * Updated Integrated RAID configuration pages including
51 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
52 * Page 0.
53 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
54 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
55 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
56 * Added missing MaxNumRoutedSasAddresses field to
57 * MPI2_CONFIG_PAGE_EXPANDER_0.
58 * Added SAS Port Page 0.
59 * Modified structure layout for
60 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
61 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
62 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
63 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
64 * to 0x000000FF.
65 * Added two new values for the Physical Disk Coercion Size
66 * bits in the Flags field of Manufacturing Page 4.
67 * Added product-specific Manufacturing pages 16 to 31.
68 * Modified Flags bits for controlling write cache on SATA
69 * drives in IO Unit Page 1.
70 * Added new bit to AdditionalControlFlags of SAS IO Unit
71 * Page 1 to control Invalid Topology Correction.
72 * Added additional defines for RAID Volume Page 0
73 * VolumeStatusFlags field.
74 * Modified meaning of RAID Volume Page 0 VolumeSettings
75 * define for auto-configure of hot-swap drives.
76 * Added SupportedPhysDisks field to RAID Volume Page 1 and
77 * added related defines.
78 * Added PhysDiskAttributes field (and related defines) to
79 * RAID Physical Disk Page 0.
80 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
81 * Added three new DiscoveryStatus bits for SAS IO Unit
82 * Page 0 and SAS Expander Page 0.
83 * Removed multiplexing information from SAS IO Unit pages.
84 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
85 * Removed Zone Address Resolved bit from PhyInfo and from
86 * Expander Page 0 Flags field.
87 * Added two new AccessStatus values to SAS Device Page 0
88 * for indicating routing problems. Added 3 reserved words
89 * to this page.
90 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
91 * Inserted missing reserved field into structure for IOC
92 * Page 6.
93 * Added more pending task bits to RAID Volume Page 0
94 * VolumeStatusFlags defines.
95 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
96 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
97 * and SAS Expander Page 0 to flag a downstream initiator
98 * when in simplified routing mode.
99 * Removed SATA Init Failure defines for DiscoveryStatus
100 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
101 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
102 * Added PortGroups, DmaGroup, and ControlGroup fields to
103 * SAS Device Page 0.
104 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
105 * Unit Page 6.
106 * Added expander reduced functionality data to SAS
107 * Expander Page 0.
108 * Added SAS PHY Page 2 and SAS PHY Page 3.
109 * 07-30-09 02.00.12 Added IO Unit Page 7.
110 * Added new device ids.
111 * Added SAS IO Unit Page 5.
112 * Added partial and slumber power management capable flags
113 * to SAS Device Page 0 Flags field.
114 * Added PhyInfo defines for power condition.
115 * Added Ethernet configuration pages.
116 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
117 * Added SAS PHY Page 4 structure and defines.
118 * 02-10-10 02.00.14 Modified the comments for the configuration page
119 * structures that contain an array of data. The host
120 * should use the "count" field in the page data (e.g. the
121 * NumPhys field) to determine the number of valid elements
122 * in the array.
123 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
124 * Added PowerManagementCapabilities to IO Unit Page 7.
125 * Added PortWidthModGroup field to
126 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
127 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
128 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
129 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
130 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
131 * define.
132 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
133 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
134 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing)
135 * defines.
136 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to
137 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
138 * the Pinout field.
139 * Added BoardTemperature and BoardTemperatureUnits fields
140 * to MPI2_CONFIG_PAGE_IO_UNIT_7.
141 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
142 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
143 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
144 * Added IO Unit Page 8, IO Unit Page 9,
145 * and IO Unit Page 10.
146 * Added SASNotifyPrimitiveMasks field to
147 * MPI2_CONFIG_PAGE_IOC_7.
148 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec).
149 * 05-25-11 02.00.20 Cleaned up a few comments.
150 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities
151 * for PCIe link as obsolete.
152 * Added SpinupFlags field containing a Disable Spin-up bit
153 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO
154 * Unit Page 4.
155 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT.
156 * Added UEFIVersion field to BIOS Page 1 and defined new
157 * BiosOptions bits.
158 * Incorporating additions for MPI v2.5.
159 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER.
160 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID.
161 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as
162 * obsolete for MPI v2.5 and later.
163 * Added some defines for 12G SAS speeds.
164 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK.
165 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to
166 * match the specification.
167 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for
168 * future use.
169 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for
170 * MPI2_CONFIG_PAGE_MAN_7.
171 * Added EnclosureLevel and ConnectorName fields to
172 * MPI2_CONFIG_PAGE_SAS_DEV_0.
173 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for
174 * MPI2_CONFIG_PAGE_SAS_DEV_0.
175 * Added EnclosureLevel field to
176 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
177 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for
178 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
179 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of
180 * MPI2_CONFIG_PAGE_BIOS_1.
181 * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and
182 * more defines for the BiosOptions field.
183 * 11-18-14 02.00.30 Updated copyright information.
184 * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG.
185 * Added AdapterOrderAux fields to BIOS Page 3.
186 * 03-16-15 02.00.31 Updated for MPI v2.6.
187 * Added Flags field to IO Unit Page 7.
188 * Added new SAS Phy Event codes
189 * 05-25-15 02.00.33 Added more defines for the BiosOptions field of
190 * MPI2_CONFIG_PAGE_BIOS_1.
191 * 08-25-15 02.00.34 Bumped Header Version.
192 * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4.
193 * 01-21-16 02.00.36 Added/modified MPI2_MFGPAGE_DEVID_SAS defines.
194 * Added Link field to PCIe Link Pages
195 * Added EnclosureLevel and ConnectorName to PCIe
196 * Device Page 0.
197 * Added define for PCIE IoUnit page 1 max rate shift.
198 * Added comment for reserved ExtPageTypes.
199 * Added SAS 4 22.5 gbs speed support.
200 * Added PCIe 4 16.0 GT/sec speec support.
201 * Removed AHCI support.
202 * Removed SOP support.
203 * Added NegotiatedLinkRate and NegotiatedPortWidth to
204 * PCIe device page 0.
205 * 04-10-16 02.00.37 Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines
206 * 07-01-16 02.00.38 Added Manufacturing page 7 Connector types.
207 * Changed declaration of ConnectorName in PCIe DevicePage0
208 * to match SAS DevicePage 0.
209 * Added SATADeviceWaitTime to IO Unit Page 11.
210 * Added MPI26_MFGPAGE_DEVID_SAS4008
211 * Added x16 PCIe width to IO Unit Page 7
212 * Added LINKFLAGS to control SRIS in PCIe IO Unit page 1
213 * phy data.
214 * Added InitStatus to PCIe IO Unit Page 1 header.
215 * 09-01-16 02.00.39 Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines.
216 * Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and
217 * MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats.
218 * 02-02-17 02.00.40 Added MPI2_MANPAGE7_SLOT_UNKNOWN.
219 * Added ChassisSlot field to SAS Enclosure Page 0.
220 * Added ChassisSlot Valid bit (bit 5) to the Flags field
221 * in SAS Enclosure Page 0.
222 * 06-13-17 02.00.41 Added MPI26_MFGPAGE_DEVID_SAS3816 and
223 * MPI26_MFGPAGE_DEVID_SAS3916 defines.
224 * Removed MPI26_MFGPAGE_DEVID_SAS4008 define.
225 * Added MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN define.
226 * Renamed PI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS to
227 * PI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN.
228 * Renamed MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS to
229 * MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK.
230 * 09-29-17 02.00.42 Added ControllerResetTO field to PCIe Device Page 2.
231 * Added NOIOB field to PCIe Device Page 2.
232 * Added MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN to
233 * the Capabilities field of PCIe Device Page 2.
234 * 07-22-18 02.00.43 Added defines for SAS3916 and SAS3816.
235 * Added WRiteCache defines to IO Unit Page 1.
236 * Added MaxEnclosureLevel to BIOS Page 1.
237 * Added OEMRD to SAS Enclosure Page 1.
238 * Added DMDReportPCIe to PCIe IO Unit Page 1.
239 * Added Flags field and flags for Retimers to
240 * PCIe Switch Page 1.
241 * 08-02-18 02.00.44 Added Slotx2, Slotx4 to ManPage 7.
242 * 08-15-18 02.00.45 Added ProductSpecific field at end of IOC Page 1
243 * 08-28-18 02.00.46 Added NVMs Write Cache flag to IOUnitPage1
244 * Added DMDReport Delay Time defines to
245 * PCIeIOUnitPage1
246 * --------------------------------------------------------------------------
247 * 08-02-18 02.00.44 Added Slotx2, Slotx4 to ManPage 7.
248 * 08-15-18 02.00.45 Added ProductSpecific field at end of IOC Page 1
249 * 08-28-18 02.00.46 Added NVMs Write Cache flag to IOUnitPage1
250 * Added DMDReport Delay Time defines to PCIeIOUnitPage1
251 * 12-17-18 02.00.47 Swap locations of Slotx2 and Slotx4 in ManPage 7.
252 * 08-01-19 02.00.49 Add MPI26_MANPAGE7_FLAG_X2_X4_SLOT_INFO_VALID
253 * Add MPI26_IOUNITPAGE1_NVME_WRCACHE_SHIFT
254 */
255
256#ifndef MPI2_CNFG_H
257#define MPI2_CNFG_H
258
259/*****************************************************************************
260* Configuration Page Header and defines
261*****************************************************************************/
262
263/*Config Page Header */
264typedef struct _MPI2_CONFIG_PAGE_HEADER {
265 U8 PageVersion; /*0x00 */
266 U8 PageLength; /*0x01 */
267 U8 PageNumber; /*0x02 */
268 U8 PageType; /*0x03 */
269} MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER,
270 Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t;
271
272typedef union _MPI2_CONFIG_PAGE_HEADER_UNION {
273 MPI2_CONFIG_PAGE_HEADER Struct;
274 U8 Bytes[4];
275 U16 Word16[2];
276 U32 Word32;
277} MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
278 Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion;
279
280/*Extended Config Page Header */
281typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER {
282 U8 PageVersion; /*0x00 */
283 U8 Reserved1; /*0x01 */
284 U8 PageNumber; /*0x02 */
285 U8 PageType; /*0x03 */
286 U16 ExtPageLength; /*0x04 */
287 U8 ExtPageType; /*0x06 */
288 U8 Reserved2; /*0x07 */
289} MPI2_CONFIG_EXTENDED_PAGE_HEADER,
290 *PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
291 Mpi2ConfigExtendedPageHeader_t,
292 *pMpi2ConfigExtendedPageHeader_t;
293
294typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION {
295 MPI2_CONFIG_PAGE_HEADER Struct;
296 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
297 U8 Bytes[8];
298 U16 Word16[4];
299 U32 Word32[2];
300} MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
301 *PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
302 Mpi2ConfigPageExtendedHeaderUnion,
303 *pMpi2ConfigPageExtendedHeaderUnion;
304
305
306/*PageType field values */
307#define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
308#define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
309#define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
310#define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
311
312#define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
313#define MPI2_CONFIG_PAGETYPE_IOC (0x01)
314#define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
315#define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
316#define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
317#define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
318#define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
319#define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
320
321#define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
322
323
324/*ExtPageType field values */
325#define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
326#define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
327#define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
328#define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
329#define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
330#define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
331#define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
332#define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
333#define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
334#define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
335#define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
336#define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT (0x1B)
337#define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH (0x1C)
338#define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE (0x1D)
339#define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK (0x1E)
340
341
342/*****************************************************************************
343* PageAddress defines
344*****************************************************************************/
345
346/*RAID Volume PageAddress format */
347#define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
348#define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
349#define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
350
351#define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
352
353
354/*RAID Physical Disk PageAddress format */
355#define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
356#define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
357#define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
358#define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
359
360#define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
361#define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
362
363
364/*SAS Expander PageAddress format */
365#define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
366#define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
367#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
368#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
369
370#define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
371#define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
372#define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
373
374
375/*SAS Device PageAddress format */
376#define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
377#define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
378#define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
379
380#define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
381
382
383/*SAS PHY PageAddress format */
384#define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
385#define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
386#define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
387
388#define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
389#define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
390
391
392/*SAS Port PageAddress format */
393#define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
394#define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
395#define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
396
397#define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
398
399
400/*SAS Enclosure PageAddress format */
401#define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
402#define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
403#define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
404
405#define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
406
407/*Enclosure PageAddress format */
408#define MPI26_ENCLOS_PGAD_FORM_MASK (0xF0000000)
409#define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
410#define MPI26_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
411
412#define MPI26_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
413
414/*RAID Configuration PageAddress format */
415#define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
416#define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
417#define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
418#define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
419
420#define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
421
422
423/*Driver Persistent Mapping PageAddress format */
424#define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
425#define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
426
427#define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
428#define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
429#define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
430
431
432/*Ethernet PageAddress format */
433#define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
434#define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
435
436#define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
437
438
439/*PCIe Switch PageAddress format */
440#define MPI26_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000)
441#define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
442#define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM (0x10000000)
443#define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL (0x20000000)
444
445#define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF)
446#define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000)
447#define MPI26_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16)
448
449
450/*PCIe Device PageAddress format */
451#define MPI26_PCIE_DEVICE_PGAD_FORM_MASK (0xF0000000)
452#define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
453#define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE (0x20000000)
454
455#define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
456
457/*PCIe Link PageAddress format */
458#define MPI26_PCIE_LINK_PGAD_FORM_MASK (0xF0000000)
459#define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000)
460#define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000)
461
462#define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK (0x000000FF)
463
464
465
466/****************************************************************************
467* Configuration messages
468****************************************************************************/
469
470/*Configuration Request Message */
471typedef struct _MPI2_CONFIG_REQUEST {
472 U8 Action; /*0x00 */
473 U8 SGLFlags; /*0x01 */
474 U8 ChainOffset; /*0x02 */
475 U8 Function; /*0x03 */
476 U16 ExtPageLength; /*0x04 */
477 U8 ExtPageType; /*0x06 */
478 U8 MsgFlags; /*0x07 */
479 U8 VP_ID; /*0x08 */
480 U8 VF_ID; /*0x09 */
481 U16 Reserved1; /*0x0A */
482 U8 Reserved2; /*0x0C */
483 U8 ProxyVF_ID; /*0x0D */
484 U16 Reserved4; /*0x0E */
485 U32 Reserved3; /*0x10 */
486 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */
487 U32 PageAddress; /*0x18 */
488 MPI2_SGE_IO_UNION PageBufferSGE; /*0x1C */
489} MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST,
490 Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t;
491
492/*values for the Action field */
493#define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
494#define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
495#define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
496#define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
497#define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
498#define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
499#define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
500#define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
501
502/*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
503
504
505/*Config Reply Message */
506typedef struct _MPI2_CONFIG_REPLY {
507 U8 Action; /*0x00 */
508 U8 SGLFlags; /*0x01 */
509 U8 MsgLength; /*0x02 */
510 U8 Function; /*0x03 */
511 U16 ExtPageLength; /*0x04 */
512 U8 ExtPageType; /*0x06 */
513 U8 MsgFlags; /*0x07 */
514 U8 VP_ID; /*0x08 */
515 U8 VF_ID; /*0x09 */
516 U16 Reserved1; /*0x0A */
517 U16 Reserved2; /*0x0C */
518 U16 IOCStatus; /*0x0E */
519 U32 IOCLogInfo; /*0x10 */
520 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */
521} MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY,
522 Mpi2ConfigReply_t, *pMpi2ConfigReply_t;
523
524
525
526/*****************************************************************************
527*
528* C o n f i g u r a t i o n P a g e s
529*
530*****************************************************************************/
531
532/****************************************************************************
533* Manufacturing Config pages
534****************************************************************************/
535
536#define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
537#define MPI2_MFGPAGE_VENDORID_ATTO (0x117C)
538
539/*MPI v2.0 SAS products */
540#define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
541#define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
542#define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
543#define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
544#define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
545#define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
546#define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
547
548#define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
549
550#define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
551#define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
552#define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
553#define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
554#define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
555#define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
556#define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
557#define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
558#define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
559#define MPI2_MFGPAGE_DEVID_SWITCH_MPI_EP (0x02B0)
560#define MPI2_MFGPAGE_DEVID_SWITCH_MPI_EP_1 (0x02B1)
561
562/*MPI v2.5 SAS products */
563#define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096)
564#define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097)
565#define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090)
566#define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091)
567#define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094)
568#define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095)
569
570/* MPI v2.6 SAS Products */
571#define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9)
572#define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4)
573#define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5)
574#define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6)
575#define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7)
576#define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8)
577#define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0)
578#define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1)
579#define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2)
580#define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3)
581
582#define MPI26_MFGPAGE_DEVID_SAS3516 (0x00AA)
583#define MPI26_MFGPAGE_DEVID_SAS3516_1 (0x00AB)
584#define MPI26_MFGPAGE_DEVID_SAS3416 (0x00AC)
585#define MPI26_MFGPAGE_DEVID_SAS3508 (0x00AD)
586#define MPI26_MFGPAGE_DEVID_SAS3508_1 (0x00AE)
587#define MPI26_MFGPAGE_DEVID_SAS3408 (0x00AF)
588#define MPI26_MFGPAGE_DEVID_SAS3716 (0x00D0)
589#define MPI26_MFGPAGE_DEVID_SAS3616 (0x00D1)
590#define MPI26_MFGPAGE_DEVID_SAS3708 (0x00D2)
591
592#define MPI26_MFGPAGE_DEVID_SEC_MASK_3916 (0x0003)
593#define MPI26_MFGPAGE_DEVID_INVALID0_3916 (0x00E0)
594#define MPI26_MFGPAGE_DEVID_CFG_SEC_3916 (0x00E1)
595#define MPI26_MFGPAGE_DEVID_HARD_SEC_3916 (0x00E2)
596#define MPI26_MFGPAGE_DEVID_INVALID1_3916 (0x00E3)
597
598#define MPI26_MFGPAGE_DEVID_SEC_MASK_3816 (0x0003)
599#define MPI26_MFGPAGE_DEVID_INVALID0_3816 (0x00E4)
600#define MPI26_MFGPAGE_DEVID_CFG_SEC_3816 (0x00E5)
601#define MPI26_MFGPAGE_DEVID_HARD_SEC_3816 (0x00E6)
602#define MPI26_MFGPAGE_DEVID_INVALID1_3816 (0x00E7)
603
604
605/*Manufacturing Page 0 */
606
607typedef struct _MPI2_CONFIG_PAGE_MAN_0 {
608 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
609 U8 ChipName[16]; /*0x04 */
610 U8 ChipRevision[8]; /*0x14 */
611 U8 BoardName[16]; /*0x1C */
612 U8 BoardAssembly[16]; /*0x2C */
613 U8 BoardTracerNumber[16]; /*0x3C */
614} MPI2_CONFIG_PAGE_MAN_0,
615 *PTR_MPI2_CONFIG_PAGE_MAN_0,
616 Mpi2ManufacturingPage0_t,
617 *pMpi2ManufacturingPage0_t;
618
619#define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
620
621
622/*Manufacturing Page 1 */
623
624typedef struct _MPI2_CONFIG_PAGE_MAN_1 {
625 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
626 U8 VPD[256]; /*0x04 */
627} MPI2_CONFIG_PAGE_MAN_1,
628 *PTR_MPI2_CONFIG_PAGE_MAN_1,
629 Mpi2ManufacturingPage1_t,
630 *pMpi2ManufacturingPage1_t;
631
632#define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
633
634
635typedef struct _MPI2_CHIP_REVISION_ID {
636 U16 DeviceID; /*0x00 */
637 U8 PCIRevisionID; /*0x02 */
638 U8 Reserved; /*0x03 */
639} MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID,
640 Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t;
641
642
643/*Manufacturing Page 2 */
644
645/*
646 *Host code (drivers, BIOS, utilities, etc.) should check Header.PageLength at
647 *runtime before using HwSettings[].
648 */
649
650typedef struct _MPI2_CONFIG_PAGE_MAN_2 {
651 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
652 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */
653 U32 HwSettings[]; /*0x08 */
654} MPI2_CONFIG_PAGE_MAN_2,
655 *PTR_MPI2_CONFIG_PAGE_MAN_2,
656 Mpi2ManufacturingPage2_t,
657 *pMpi2ManufacturingPage2_t;
658
659#define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
660
661
662/*Manufacturing Page 3 */
663
664/*
665 *Host code (drivers, BIOS, utilities, etc.) should check Header.PageLength at
666 *runtime before using Info[].
667 */
668
669typedef struct _MPI2_CONFIG_PAGE_MAN_3 {
670 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
671 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */
672 U32 Info[]; /*0x08 */
673} MPI2_CONFIG_PAGE_MAN_3,
674 *PTR_MPI2_CONFIG_PAGE_MAN_3,
675 Mpi2ManufacturingPage3_t,
676 *pMpi2ManufacturingPage3_t;
677
678#define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
679
680
681/*Manufacturing Page 4 */
682
683typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS {
684 U8 PowerSaveFlags; /*0x00 */
685 U8 InternalOperationsSleepTime; /*0x01 */
686 U8 InternalOperationsRunTime; /*0x02 */
687 U8 HostIdleTime; /*0x03 */
688} MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
689 *PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
690 Mpi2ManPage4PwrSaveSettings_t,
691 *pMpi2ManPage4PwrSaveSettings_t;
692
693/*defines for the PowerSaveFlags field */
694#define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
695#define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
696#define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
697#define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
698
699typedef struct _MPI2_CONFIG_PAGE_MAN_4 {
700 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
701 U32 Reserved1; /*0x04 */
702 U32 Flags; /*0x08 */
703 U8 InquirySize; /*0x0C */
704 U8 Reserved2; /*0x0D */
705 U16 Reserved3; /*0x0E */
706 U8 InquiryData[56]; /*0x10 */
707 U32 RAID0VolumeSettings; /*0x48 */
708 U32 RAID1EVolumeSettings; /*0x4C */
709 U32 RAID1VolumeSettings; /*0x50 */
710 U32 RAID10VolumeSettings; /*0x54 */
711 U32 Reserved4; /*0x58 */
712 U32 Reserved5; /*0x5C */
713 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /*0x60 */
714 U8 MaxOCEDisks; /*0x64 */
715 U8 ResyncRate; /*0x65 */
716 U16 DataScrubDuration; /*0x66 */
717 U8 MaxHotSpares; /*0x68 */
718 U8 MaxPhysDisksPerVol; /*0x69 */
719 U8 MaxPhysDisks; /*0x6A */
720 U8 MaxVolumes; /*0x6B */
721} MPI2_CONFIG_PAGE_MAN_4,
722 *PTR_MPI2_CONFIG_PAGE_MAN_4,
723 Mpi2ManufacturingPage4_t,
724 *pMpi2ManufacturingPage4_t;
725
726#define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
727
728/*Manufacturing Page 4 Flags field */
729#define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
730#define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
731
732#define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
733#define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
734#define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
735
736#define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
737#define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
738#define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
739#define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
740#define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
741
742#define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
743#define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
744#define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
745#define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
746
747#define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
748#define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
749#define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
750#define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
751#define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
752#define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
753#define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
754#define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
755
756
757/*Manufacturing Page 5 */
758
759/*
760 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
761 *for NumPhys at runtime before using Phy[].
762 */
763
764typedef struct _MPI2_MANUFACTURING5_ENTRY {
765 U64 WWID; /*0x00 */
766 U64 DeviceName; /*0x08 */
767} MPI2_MANUFACTURING5_ENTRY,
768 *PTR_MPI2_MANUFACTURING5_ENTRY,
769 Mpi2Manufacturing5Entry_t,
770 *pMpi2Manufacturing5Entry_t;
771
772typedef struct _MPI2_CONFIG_PAGE_MAN_5 {
773 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
774 U8 NumPhys; /*0x04 */
775 U8 Reserved1; /*0x05 */
776 U16 Reserved2; /*0x06 */
777 U32 Reserved3; /*0x08 */
778 U32 Reserved4; /*0x0C */
779 MPI2_MANUFACTURING5_ENTRY Phy[]; /*0x10 */
780} MPI2_CONFIG_PAGE_MAN_5,
781 *PTR_MPI2_CONFIG_PAGE_MAN_5,
782 Mpi2ManufacturingPage5_t,
783 *pMpi2ManufacturingPage5_t;
784
785#define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
786
787
788/*Manufacturing Page 6 */
789
790typedef struct _MPI2_CONFIG_PAGE_MAN_6 {
791 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
792 U32 ProductSpecificInfo;/*0x04 */
793} MPI2_CONFIG_PAGE_MAN_6,
794 *PTR_MPI2_CONFIG_PAGE_MAN_6,
795 Mpi2ManufacturingPage6_t,
796 *pMpi2ManufacturingPage6_t;
797
798#define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
799
800
801/*Manufacturing Page 7 */
802
803typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO {
804 U32 Pinout; /*0x00 */
805 U8 Connector[16]; /*0x04 */
806 U8 Location; /*0x14 */
807 U8 ReceptacleID; /*0x15 */
808 U16 Slot; /*0x16 */
809 U16 Slotx2; /*0x18 */
810 U16 Slotx4; /*0x1A */
811} MPI2_MANPAGE7_CONNECTOR_INFO,
812 *PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
813 Mpi2ManPage7ConnectorInfo_t,
814 *pMpi2ManPage7ConnectorInfo_t;
815
816/*defines for the Pinout field */
817#define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00)
818#define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8)
819
820#define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF)
821#define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00)
822#define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01)
823#define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02)
824#define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03)
825#define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04)
826#define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05)
827#define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06)
828#define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07)
829#define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08)
830#define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09)
831#define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A)
832#define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B)
833#define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C)
834#define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D)
835#define MPI2_MANPAGE7_PINOUT_SFF_8088_A (0x0E)
836#define MPI2_MANPAGE7_PINOUT_SFF_8643_16i (0x0F)
837#define MPI2_MANPAGE7_PINOUT_SFF_8654_4i (0x10)
838#define MPI2_MANPAGE7_PINOUT_SFF_8654_8i (0x11)
839#define MPI2_MANPAGE7_PINOUT_SFF_8611_4i (0x12)
840#define MPI2_MANPAGE7_PINOUT_SFF_8611_8i (0x13)
841
842/*defines for the Location field */
843#define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
844#define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
845#define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
846#define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
847#define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
848#define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
849#define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
850
851/*defines for the Slot field */
852#define MPI2_MANPAGE7_SLOT_UNKNOWN (0xFFFF)
853
854/*
855 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
856 *for NumPhys at runtime before using ConnectorInfo[].
857 */
858
859typedef struct _MPI2_CONFIG_PAGE_MAN_7 {
860 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
861 U32 Reserved1; /*0x04 */
862 U32 Reserved2; /*0x08 */
863 U32 Flags; /*0x0C */
864 U8 EnclosureName[16]; /*0x10 */
865 U8 NumPhys; /*0x20 */
866 U8 Reserved3; /*0x21 */
867 U16 Reserved4; /*0x22 */
868 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[]; /*0x24 */
869} MPI2_CONFIG_PAGE_MAN_7,
870 *PTR_MPI2_CONFIG_PAGE_MAN_7,
871 Mpi2ManufacturingPage7_t,
872 *pMpi2ManufacturingPage7_t;
873
874#define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
875
876/*defines for the Flags field */
877#define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008)
878#define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002)
879#define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
880
881#define MPI26_MANPAGE7_FLAG_CONN_LANE_USE_PINOUT (0x00000020)
882#define MPI26_MANPAGE7_FLAG_X2_X4_SLOT_INFO_VALID (0x00000010)
883
884/*
885 *Generic structure to use for product-specific manufacturing pages
886 *(currently Manufacturing Page 8 through Manufacturing Page 31).
887 */
888
889typedef struct _MPI2_CONFIG_PAGE_MAN_PS {
890 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
891 U32 ProductSpecificInfo;/*0x04 */
892} MPI2_CONFIG_PAGE_MAN_PS,
893 *PTR_MPI2_CONFIG_PAGE_MAN_PS,
894 Mpi2ManufacturingPagePS_t,
895 *pMpi2ManufacturingPagePS_t;
896
897#define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
898#define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
899#define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
900#define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
901#define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
902#define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
903#define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
904#define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
905#define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
906#define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
907#define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
908#define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
909#define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
910#define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
911#define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
912#define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
913#define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
914#define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
915#define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
916#define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
917#define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
918#define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
919#define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
920#define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
921
922
923/****************************************************************************
924* IO Unit Config Pages
925****************************************************************************/
926
927/*IO Unit Page 0 */
928
929typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 {
930 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
931 U64 UniqueValue; /*0x04 */
932 MPI2_VERSION_UNION NvdataVersionDefault; /*0x08 */
933 MPI2_VERSION_UNION NvdataVersionPersistent; /*0x0A */
934} MPI2_CONFIG_PAGE_IO_UNIT_0,
935 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
936 Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t;
937
938#define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
939
940
941/*IO Unit Page 1 */
942
943typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 {
944 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
945 U32 Flags; /*0x04 */
946} MPI2_CONFIG_PAGE_IO_UNIT_1,
947 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
948 Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t;
949
950#define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
951
952/* IO Unit Page 1 Flags defines */
953#define MPI26_IOUNITPAGE1_NVME_WRCACHE_MASK (0x00030000)
954#define MPI26_IOUNITPAGE1_NVME_WRCACHE_SHIFT (16)
955#define MPI26_IOUNITPAGE1_NVME_WRCACHE_NO_CHANGE (0x00000000)
956#define MPI26_IOUNITPAGE1_NVME_WRCACHE_ENABLE (0x00010000)
957#define MPI26_IOUNITPAGE1_NVME_WRCACHE_DISABLE (0x00020000)
958#define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000)
959#define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000)
960#define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000)
961#define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
962#define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
963#define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9)
964#define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
965#define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
966#define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
967#define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
968#define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
969#define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
970#define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
971
972
973/*IO Unit Page 3 */
974
975/*
976 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
977 *36 and check the value returned for GPIOCount at runtime.
978 */
979#ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
980#define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (36)
981#endif
982
983typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 {
984 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
985 U8 GPIOCount; /*0x04 */
986 U8 Reserved1; /*0x05 */
987 U16 Reserved2; /*0x06 */
988 U16
989 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */
990} MPI2_CONFIG_PAGE_IO_UNIT_3,
991 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
992 Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t;
993
994#define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
995
996/*defines for IO Unit Page 3 GPIOVal field */
997#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
998#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
999#define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
1000#define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
1001
1002
1003/*IO Unit Page 5 */
1004
1005/*
1006 *Upper layer code (drivers, utilities, etc.) should check the value returned
1007 *for NumDmaEngines at runtime before using DmaEngineCapabilities[].
1008 */
1009
1010typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
1011 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1012 U64
1013 RaidAcceleratorBufferBaseAddress; /*0x04 */
1014 U64
1015 RaidAcceleratorBufferSize; /*0x0C */
1016 U64
1017 RaidAcceleratorControlBaseAddress; /*0x14 */
1018 U8 RAControlSize; /*0x1C */
1019 U8 NumDmaEngines; /*0x1D */
1020 U8 RAMinControlSize; /*0x1E */
1021 U8 RAMaxControlSize; /*0x1F */
1022 U32 Reserved1; /*0x20 */
1023 U32 Reserved2; /*0x24 */
1024 U32 Reserved3; /*0x28 */
1025 U32
1026 DmaEngineCapabilities[]; /*0x2C */
1027} MPI2_CONFIG_PAGE_IO_UNIT_5,
1028 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
1029 Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t;
1030
1031#define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
1032
1033/*defines for IO Unit Page 5 DmaEngineCapabilities field */
1034#define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000)
1035#define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
1036
1037#define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
1038#define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
1039#define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
1040#define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
1041
1042
1043/*IO Unit Page 6 */
1044
1045typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
1046 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1047 U16 Flags; /*0x04 */
1048 U8 RAHostControlSize; /*0x06 */
1049 U8 Reserved0; /*0x07 */
1050 U64
1051 RaidAcceleratorHostControlBaseAddress; /*0x08 */
1052 U32 Reserved1; /*0x10 */
1053 U32 Reserved2; /*0x14 */
1054 U32 Reserved3; /*0x18 */
1055} MPI2_CONFIG_PAGE_IO_UNIT_6,
1056 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
1057 Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t;
1058
1059#define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
1060
1061/*defines for IO Unit Page 6 Flags field */
1062#define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
1063
1064
1065/*IO Unit Page 7 */
1066
1067typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
1068 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1069 U8 CurrentPowerMode; /*0x04 */
1070 U8 PreviousPowerMode; /*0x05 */
1071 U8 PCIeWidth; /*0x06 */
1072 U8 PCIeSpeed; /*0x07 */
1073 U32 ProcessorState; /*0x08 */
1074 U32
1075 PowerManagementCapabilities; /*0x0C */
1076 U16 IOCTemperature; /*0x10 */
1077 U8
1078 IOCTemperatureUnits; /*0x12 */
1079 U8 IOCSpeed; /*0x13 */
1080 U16 BoardTemperature; /*0x14 */
1081 U8
1082 BoardTemperatureUnits; /*0x16 */
1083 U8 Reserved3; /*0x17 */
1084 U32 BoardPowerRequirement; /*0x18 */
1085 U32 PCISlotPowerAllocation; /*0x1C */
1086/* reserved prior to MPI v2.6 */
1087 U8 Flags; /* 0x20 */
1088 U8 Reserved6; /* 0x21 */
1089 U16 Reserved7; /* 0x22 */
1090 U32 Reserved8; /* 0x24 */
1091} MPI2_CONFIG_PAGE_IO_UNIT_7,
1092 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
1093 Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t;
1094
1095#define MPI2_IOUNITPAGE7_PAGEVERSION (0x05)
1096
1097/*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */
1098#define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0)
1099#define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00)
1100#define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40)
1101#define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80)
1102#define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0)
1103
1104#define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07)
1105#define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00)
1106#define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01)
1107#define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04)
1108#define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05)
1109#define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06)
1110
1111
1112/*defines for IO Unit Page 7 PCIeWidth field */
1113#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
1114#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
1115#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
1116#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
1117#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16 (0x10)
1118
1119/*defines for IO Unit Page 7 PCIeSpeed field */
1120#define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
1121#define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
1122#define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
1123#define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS (0x03)
1124
1125/*defines for IO Unit Page 7 ProcessorState field */
1126#define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
1127#define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
1128
1129#define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
1130#define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
1131#define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
1132
1133/*defines for IO Unit Page 7 PowerManagementCapabilities field */
1134#define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000)
1135#define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000)
1136#define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000)
1137#define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000)
1138#define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000)
1139#define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000)
1140#define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000)
1141#define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000)
1142#define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000)
1143#define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400)
1144#define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200)
1145#define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100)
1146#define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040)
1147#define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020)
1148#define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010)
1149#define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008)
1150#define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004)
1151#define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002)
1152#define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001)
1153
1154/*obsolete names for the PowerManagementCapabilities bits (above) */
1155#define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
1156#define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
1157#define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
1158#define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /*obsolete */
1159#define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /*obsolete */
1160
1161
1162/*defines for IO Unit Page 7 IOCTemperatureUnits field */
1163#define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
1164#define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
1165#define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
1166
1167/*defines for IO Unit Page 7 IOCSpeed field */
1168#define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
1169#define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
1170#define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
1171#define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
1172
1173/*defines for IO Unit Page 7 BoardTemperatureUnits field */
1174#define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
1175#define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
1176#define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
1177
1178/* defines for IO Unit Page 7 Flags field */
1179#define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC (0x01)
1180
1181/*IO Unit Page 8 */
1182
1183#define MPI2_IOUNIT8_NUM_THRESHOLDS (4)
1184
1185typedef struct _MPI2_IOUNIT8_SENSOR {
1186 U16 Flags; /*0x00 */
1187 U16 Reserved1; /*0x02 */
1188 U16
1189 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */
1190 U32 Reserved2; /*0x0C */
1191 U32 Reserved3; /*0x10 */
1192 U32 Reserved4; /*0x14 */
1193} MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR,
1194 Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t;
1195
1196/*defines for IO Unit Page 8 Sensor Flags field */
1197#define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008)
1198#define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004)
1199#define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002)
1200#define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001)
1201
1202/*
1203 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
1204 *for NumSensors at runtime before using Sensor[].
1205 */
1206
1207typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 {
1208 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1209 U32 Reserved1; /*0x04 */
1210 U32 Reserved2; /*0x08 */
1211 U8 NumSensors; /*0x0C */
1212 U8 PollingInterval; /*0x0D */
1213 U16 Reserved3; /*0x0E */
1214 MPI2_IOUNIT8_SENSOR Sensor[]; /*0x10 */
1215} MPI2_CONFIG_PAGE_IO_UNIT_8,
1216 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
1217 Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t;
1218
1219#define MPI2_IOUNITPAGE8_PAGEVERSION (0x00)
1220
1221
1222/*IO Unit Page 9 */
1223
1224typedef struct _MPI2_IOUNIT9_SENSOR {
1225 U16 CurrentTemperature; /*0x00 */
1226 U16 Reserved1; /*0x02 */
1227 U8 Flags; /*0x04 */
1228 U8 Reserved2; /*0x05 */
1229 U16 Reserved3; /*0x06 */
1230 U32 Reserved4; /*0x08 */
1231 U32 Reserved5; /*0x0C */
1232} MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR,
1233 Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t;
1234
1235/*defines for IO Unit Page 9 Sensor Flags field */
1236#define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01)
1237
1238/*
1239 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
1240 *for NumSensors at runtime before using Sensor[].
1241 */
1242
1243typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 {
1244 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1245 U32 Reserved1; /*0x04 */
1246 U32 Reserved2; /*0x08 */
1247 U8 NumSensors; /*0x0C */
1248 U8 Reserved4; /*0x0D */
1249 U16 Reserved3; /*0x0E */
1250 MPI2_IOUNIT9_SENSOR Sensor[]; /*0x10 */
1251} MPI2_CONFIG_PAGE_IO_UNIT_9,
1252 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1253 Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t;
1254
1255#define MPI2_IOUNITPAGE9_PAGEVERSION (0x00)
1256
1257
1258/*IO Unit Page 10 */
1259
1260typedef struct _MPI2_IOUNIT10_FUNCTION {
1261 U8 CreditPercent; /*0x00 */
1262 U8 Reserved1; /*0x01 */
1263 U16 Reserved2; /*0x02 */
1264} MPI2_IOUNIT10_FUNCTION,
1265 *PTR_MPI2_IOUNIT10_FUNCTION,
1266 Mpi2IOUnit10Function_t,
1267 *pMpi2IOUnit10Function_t;
1268
1269/*
1270 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
1271 *for NumFunctions at runtime before using Function[].
1272 */
1273
1274typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 {
1275 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1276 U8 NumFunctions; /*0x04 */
1277 U8 Reserved1; /*0x05 */
1278 U16 Reserved2; /*0x06 */
1279 U32 Reserved3; /*0x08 */
1280 U32 Reserved4; /*0x0C */
1281 MPI2_IOUNIT10_FUNCTION Function[]; /*0x10 */
1282} MPI2_CONFIG_PAGE_IO_UNIT_10,
1283 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1284 Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t;
1285
1286#define MPI2_IOUNITPAGE10_PAGEVERSION (0x01)
1287
1288
1289/* IO Unit Page 11 (for MPI v2.6 and later) */
1290
1291typedef struct _MPI26_IOUNIT11_SPINUP_GROUP {
1292 U8 MaxTargetSpinup; /* 0x00 */
1293 U8 SpinupDelay; /* 0x01 */
1294 U8 SpinupFlags; /* 0x02 */
1295 U8 Reserved1; /* 0x03 */
1296} MPI26_IOUNIT11_SPINUP_GROUP,
1297 *PTR_MPI26_IOUNIT11_SPINUP_GROUP,
1298 Mpi26IOUnit11SpinupGroup_t,
1299 *pMpi26IOUnit11SpinupGroup_t;
1300
1301/* defines for IO Unit Page 11 SpinupFlags */
1302#define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01)
1303
1304
1305/*
1306 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1307 * four and check the value returned for NumPhys at runtime.
1308 */
1309#ifndef MPI26_IOUNITPAGE11_PHY_MAX
1310#define MPI26_IOUNITPAGE11_PHY_MAX (4)
1311#endif
1312
1313typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 {
1314 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1315 U32 Reserved1; /*0x04 */
1316 MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /*0x08 */
1317 U32 Reserved2; /*0x18 */
1318 U32 Reserved3; /*0x1C */
1319 U32 Reserved4; /*0x20 */
1320 U8 BootDeviceWaitTime; /*0x24 */
1321 U8 Reserved5; /*0x25 */
1322 U16 Reserved6; /*0x26 */
1323 U8 NumPhys; /*0x28 */
1324 U8 PEInitialSpinupDelay; /*0x29 */
1325 U8 PEReplyDelay; /*0x2A */
1326 U8 Flags; /*0x2B */
1327 U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/*0x2C */
1328} MPI26_CONFIG_PAGE_IO_UNIT_11,
1329 *PTR_MPI26_CONFIG_PAGE_IO_UNIT_11,
1330 Mpi26IOUnitPage11_t,
1331 *pMpi26IOUnitPage11_t;
1332
1333#define MPI26_IOUNITPAGE11_PAGEVERSION (0x00)
1334
1335/* defines for Flags field */
1336#define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01)
1337
1338/* defines for PHY field */
1339#define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03)
1340
1341
1342
1343
1344
1345
1346/****************************************************************************
1347* IOC Config Pages
1348****************************************************************************/
1349
1350/*IOC Page 0 */
1351
1352typedef struct _MPI2_CONFIG_PAGE_IOC_0 {
1353 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1354 U32 Reserved1; /*0x04 */
1355 U32 Reserved2; /*0x08 */
1356 U16 VendorID; /*0x0C */
1357 U16 DeviceID; /*0x0E */
1358 U8 RevisionID; /*0x10 */
1359 U8 Reserved3; /*0x11 */
1360 U16 Reserved4; /*0x12 */
1361 U32 ClassCode; /*0x14 */
1362 U16 SubsystemVendorID; /*0x18 */
1363 U16 SubsystemID; /*0x1A */
1364} MPI2_CONFIG_PAGE_IOC_0,
1365 *PTR_MPI2_CONFIG_PAGE_IOC_0,
1366 Mpi2IOCPage0_t, *pMpi2IOCPage0_t;
1367
1368#define MPI2_IOCPAGE0_PAGEVERSION (0x02)
1369
1370
1371/*IOC Page 1 */
1372
1373typedef struct _MPI2_CONFIG_PAGE_IOC_1 {
1374 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1375 U32 Flags; /*0x04 */
1376 U32 CoalescingTimeout; /*0x08 */
1377 U8 CoalescingDepth; /*0x0C */
1378 U8 PCISlotNum; /*0x0D */
1379 U8 PCIBusNum; /*0x0E */
1380 U8 PCIDomainSegment; /*0x0F */
1381 U32 Reserved1; /*0x10 */
1382 U32 ProductSpecific; /* 0x14 */
1383} MPI2_CONFIG_PAGE_IOC_1,
1384 *PTR_MPI2_CONFIG_PAGE_IOC_1,
1385 Mpi2IOCPage1_t, *pMpi2IOCPage1_t;
1386
1387#define MPI2_IOCPAGE1_PAGEVERSION (0x05)
1388
1389/*defines for IOC Page 1 Flags field */
1390#define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
1391
1392#define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
1393#define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
1394#define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
1395
1396/*IOC Page 6 */
1397
1398typedef struct _MPI2_CONFIG_PAGE_IOC_6 {
1399 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1400 U32
1401 CapabilitiesFlags; /*0x04 */
1402 U8 MaxDrivesRAID0; /*0x08 */
1403 U8 MaxDrivesRAID1; /*0x09 */
1404 U8
1405 MaxDrivesRAID1E; /*0x0A */
1406 U8
1407 MaxDrivesRAID10; /*0x0B */
1408 U8 MinDrivesRAID0; /*0x0C */
1409 U8 MinDrivesRAID1; /*0x0D */
1410 U8
1411 MinDrivesRAID1E; /*0x0E */
1412 U8
1413 MinDrivesRAID10; /*0x0F */
1414 U32 Reserved1; /*0x10 */
1415 U8
1416 MaxGlobalHotSpares; /*0x14 */
1417 U8 MaxPhysDisks; /*0x15 */
1418 U8 MaxVolumes; /*0x16 */
1419 U8 MaxConfigs; /*0x17 */
1420 U8 MaxOCEDisks; /*0x18 */
1421 U8 Reserved2; /*0x19 */
1422 U16 Reserved3; /*0x1A */
1423 U32
1424 SupportedStripeSizeMapRAID0; /*0x1C */
1425 U32
1426 SupportedStripeSizeMapRAID1E; /*0x20 */
1427 U32
1428 SupportedStripeSizeMapRAID10; /*0x24 */
1429 U32 Reserved4; /*0x28 */
1430 U32 Reserved5; /*0x2C */
1431 U16
1432 DefaultMetadataSize; /*0x30 */
1433 U16 Reserved6; /*0x32 */
1434 U16
1435 MaxBadBlockTableEntries; /*0x34 */
1436 U16 Reserved7; /*0x36 */
1437 U32
1438 IRNvsramVersion; /*0x38 */
1439} MPI2_CONFIG_PAGE_IOC_6,
1440 *PTR_MPI2_CONFIG_PAGE_IOC_6,
1441 Mpi2IOCPage6_t, *pMpi2IOCPage6_t;
1442
1443#define MPI2_IOCPAGE6_PAGEVERSION (0x05)
1444
1445/*defines for IOC Page 6 CapabilitiesFlags */
1446#define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020)
1447#define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
1448#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
1449#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
1450#define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
1451#define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1452
1453
1454/*IOC Page 7 */
1455
1456#define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
1457
1458typedef struct _MPI2_CONFIG_PAGE_IOC_7 {
1459 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1460 U32 Reserved1; /*0x04 */
1461 U32
1462 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */
1463 U16 SASBroadcastPrimitiveMasks; /*0x18 */
1464 U16 SASNotifyPrimitiveMasks; /*0x1A */
1465 U32 Reserved3; /*0x1C */
1466} MPI2_CONFIG_PAGE_IOC_7,
1467 *PTR_MPI2_CONFIG_PAGE_IOC_7,
1468 Mpi2IOCPage7_t, *pMpi2IOCPage7_t;
1469
1470#define MPI2_IOCPAGE7_PAGEVERSION (0x02)
1471
1472
1473/*IOC Page 8 */
1474
1475typedef struct _MPI2_CONFIG_PAGE_IOC_8 {
1476 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1477 U8 NumDevsPerEnclosure; /*0x04 */
1478 U8 Reserved1; /*0x05 */
1479 U16 Reserved2; /*0x06 */
1480 U16 MaxPersistentEntries; /*0x08 */
1481 U16 MaxNumPhysicalMappedIDs; /*0x0A */
1482 U16 Flags; /*0x0C */
1483 U16 Reserved3; /*0x0E */
1484 U16 IRVolumeMappingFlags; /*0x10 */
1485 U16 Reserved4; /*0x12 */
1486 U32 Reserved5; /*0x14 */
1487} MPI2_CONFIG_PAGE_IOC_8,
1488 *PTR_MPI2_CONFIG_PAGE_IOC_8,
1489 Mpi2IOCPage8_t, *pMpi2IOCPage8_t;
1490
1491#define MPI2_IOCPAGE8_PAGEVERSION (0x00)
1492
1493/*defines for IOC Page 8 Flags field */
1494#define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1495#define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1496
1497#define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1498#define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1499#define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1500
1501#define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1502#define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1503
1504/*defines for IOC Page 8 IRVolumeMappingFlags */
1505#define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1506#define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1507#define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1508
1509
1510/****************************************************************************
1511* BIOS Config Pages
1512****************************************************************************/
1513
1514/*BIOS Page 1 */
1515
1516typedef struct _MPI2_CONFIG_PAGE_BIOS_1 {
1517 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1518 U32 BiosOptions; /*0x04 */
1519 U32 IOCSettings; /*0x08 */
1520 U8 SSUTimeout; /*0x0C */
1521 U8 MaxEnclosureLevel; /*0x0D */
1522 U16 Reserved2; /*0x0E */
1523 U32 DeviceSettings; /*0x10 */
1524 U16 NumberOfDevices; /*0x14 */
1525 U16 UEFIVersion; /*0x16 */
1526 U16 IOTimeoutBlockDevicesNonRM; /*0x18 */
1527 U16 IOTimeoutSequential; /*0x1A */
1528 U16 IOTimeoutOther; /*0x1C */
1529 U16 IOTimeoutBlockDevicesRM; /*0x1E */
1530} MPI2_CONFIG_PAGE_BIOS_1,
1531 *PTR_MPI2_CONFIG_PAGE_BIOS_1,
1532 Mpi2BiosPage1_t, *pMpi2BiosPage1_t;
1533
1534#define MPI2_BIOSPAGE1_PAGEVERSION (0x07)
1535
1536/*values for BIOS Page 1 BiosOptions field */
1537#define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000)
1538#define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000)
1539
1540#define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800)
1541#define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000)
1542#define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800)
1543#define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000)
1544#define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800)
1545#define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000)
1546
1547#define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400)
1548
1549#define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300)
1550#define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000)
1551#define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100)
1552#define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200)
1553#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300)
1554
1555#define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0)
1556#define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000)
1557
1558#define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006)
1559#define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000)
1560#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002)
1561#define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004)
1562
1563#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1564
1565/*values for BIOS Page 1 IOCSettings field */
1566#define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1567#define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1568#define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1569
1570#define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1571#define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1572#define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1573#define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1574
1575#define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1576#define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1577#define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1578#define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1579#define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1580
1581#define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1582
1583/*values for BIOS Page 1 DeviceSettings field */
1584#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1585#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1586#define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1587#define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1588#define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1589
1590/*defines for BIOS Page 1 UEFIVersion field */
1591#define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00)
1592#define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8)
1593#define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF)
1594#define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0)
1595
1596
1597
1598/*BIOS Page 2 */
1599
1600typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER {
1601 U32 Reserved1; /*0x00 */
1602 U32 Reserved2; /*0x04 */
1603 U32 Reserved3; /*0x08 */
1604 U32 Reserved4; /*0x0C */
1605 U32 Reserved5; /*0x10 */
1606 U32 Reserved6; /*0x14 */
1607} MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1608 *PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1609 Mpi2BootDeviceAdapterOrder_t,
1610 *pMpi2BootDeviceAdapterOrder_t;
1611
1612typedef struct _MPI2_BOOT_DEVICE_SAS_WWID {
1613 U64 SASAddress; /*0x00 */
1614 U8 LUN[8]; /*0x08 */
1615 U32 Reserved1; /*0x10 */
1616 U32 Reserved2; /*0x14 */
1617} MPI2_BOOT_DEVICE_SAS_WWID,
1618 *PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1619 Mpi2BootDeviceSasWwid_t,
1620 *pMpi2BootDeviceSasWwid_t;
1621
1622typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT {
1623 U64 EnclosureLogicalID; /*0x00 */
1624 U32 Reserved1; /*0x08 */
1625 U32 Reserved2; /*0x0C */
1626 U16 SlotNumber; /*0x10 */
1627 U16 Reserved3; /*0x12 */
1628 U32 Reserved4; /*0x14 */
1629} MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1630 *PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1631 Mpi2BootDeviceEnclosureSlot_t,
1632 *pMpi2BootDeviceEnclosureSlot_t;
1633
1634typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME {
1635 U64 DeviceName; /*0x00 */
1636 U8 LUN[8]; /*0x08 */
1637 U32 Reserved1; /*0x10 */
1638 U32 Reserved2; /*0x14 */
1639} MPI2_BOOT_DEVICE_DEVICE_NAME,
1640 *PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1641 Mpi2BootDeviceDeviceName_t,
1642 *pMpi2BootDeviceDeviceName_t;
1643
1644typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE {
1645 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1646 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1647 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1648 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1649} MPI2_BIOSPAGE2_BOOT_DEVICE,
1650 *PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1651 Mpi2BiosPage2BootDevice_t,
1652 *pMpi2BiosPage2BootDevice_t;
1653
1654typedef struct _MPI2_CONFIG_PAGE_BIOS_2 {
1655 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1656 U32 Reserved1; /*0x04 */
1657 U32 Reserved2; /*0x08 */
1658 U32 Reserved3; /*0x0C */
1659 U32 Reserved4; /*0x10 */
1660 U32 Reserved5; /*0x14 */
1661 U32 Reserved6; /*0x18 */
1662 U8 ReqBootDeviceForm; /*0x1C */
1663 U8 Reserved7; /*0x1D */
1664 U16 Reserved8; /*0x1E */
1665 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /*0x20 */
1666 U8 ReqAltBootDeviceForm; /*0x38 */
1667 U8 Reserved9; /*0x39 */
1668 U16 Reserved10; /*0x3A */
1669 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /*0x3C */
1670 U8 CurrentBootDeviceForm; /*0x58 */
1671 U8 Reserved11; /*0x59 */
1672 U16 Reserved12; /*0x5A */
1673 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /*0x58 */
1674} MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2,
1675 Mpi2BiosPage2_t, *pMpi2BiosPage2_t;
1676
1677#define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1678
1679/*values for BIOS Page 2 BootDeviceForm fields */
1680#define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1681#define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1682#define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1683#define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1684#define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1685
1686
1687/*BIOS Page 3 */
1688
1689#define MPI2_BIOSPAGE3_NUM_ADAPTER (4)
1690
1691typedef struct _MPI2_ADAPTER_INFO {
1692 U8 PciBusNumber; /*0x00 */
1693 U8 PciDeviceAndFunctionNumber; /*0x01 */
1694 U16 AdapterFlags; /*0x02 */
1695} MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO,
1696 Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t;
1697
1698#define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1699#define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1700
1701typedef struct _MPI2_ADAPTER_ORDER_AUX {
1702 U64 WWID; /* 0x00 */
1703 U32 Reserved1; /* 0x08 */
1704 U32 Reserved2; /* 0x0C */
1705} MPI2_ADAPTER_ORDER_AUX, *PTR_MPI2_ADAPTER_ORDER_AUX,
1706 Mpi2AdapterOrderAux_t, *pMpi2AdapterOrderAux_t;
1707
1708
1709typedef struct _MPI2_CONFIG_PAGE_BIOS_3 {
1710 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1711 U32 GlobalFlags; /*0x04 */
1712 U32 BiosVersion; /*0x08 */
1713 MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER];
1714 U32 Reserved1; /*0x1C */
1715 MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER];
1716} MPI2_CONFIG_PAGE_BIOS_3,
1717 *PTR_MPI2_CONFIG_PAGE_BIOS_3,
1718 Mpi2BiosPage3_t, *pMpi2BiosPage3_t;
1719
1720#define MPI2_BIOSPAGE3_PAGEVERSION (0x01)
1721
1722/*values for BIOS Page 3 GlobalFlags */
1723#define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1724#define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1725#define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1726
1727#define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1728#define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1729#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1730#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1731
1732
1733/*BIOS Page 4 */
1734
1735/*
1736 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
1737 *for NumPhys at runtime before using Phy[].
1738 */
1739
1740typedef struct _MPI2_BIOS4_ENTRY {
1741 U64 ReassignmentWWID; /*0x00 */
1742 U64 ReassignmentDeviceName; /*0x08 */
1743} MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY,
1744 Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t;
1745
1746typedef struct _MPI2_CONFIG_PAGE_BIOS_4 {
1747 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1748 U8 NumPhys; /*0x04 */
1749 U8 Reserved1; /*0x05 */
1750 U16 Reserved2; /*0x06 */
1751 MPI2_BIOS4_ENTRY Phy[]; /*0x08 */
1752} MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4,
1753 Mpi2BiosPage4_t, *pMpi2BiosPage4_t;
1754
1755#define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1756
1757
1758/****************************************************************************
1759* RAID Volume Config Pages
1760****************************************************************************/
1761
1762/*RAID Volume Page 0 */
1763
1764typedef struct _MPI2_RAIDVOL0_PHYS_DISK {
1765 U8 RAIDSetNum; /*0x00 */
1766 U8 PhysDiskMap; /*0x01 */
1767 U8 PhysDiskNum; /*0x02 */
1768 U8 Reserved; /*0x03 */
1769} MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK,
1770 Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t;
1771
1772/*defines for the PhysDiskMap field */
1773#define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1774#define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1775
1776typedef struct _MPI2_RAIDVOL0_SETTINGS {
1777 U16 Settings; /*0x00 */
1778 U8 HotSparePool; /*0x01 */
1779 U8 Reserved; /*0x02 */
1780} MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS,
1781 Mpi2RaidVol0Settings_t,
1782 *pMpi2RaidVol0Settings_t;
1783
1784/*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1785#define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1786#define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1787#define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1788#define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1789#define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1790#define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1791#define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1792#define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1793
1794/*RAID Volume Page 0 VolumeSettings defines */
1795#define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1796#define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1797
1798#define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1799#define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1800#define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1801#define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1802
1803/*
1804 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
1805 *for NumPhysDisks at runtime before using PhysDisk[].
1806 */
1807
1808typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 {
1809 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1810 U16 DevHandle; /*0x04 */
1811 U8 VolumeState; /*0x06 */
1812 U8 VolumeType; /*0x07 */
1813 U32 VolumeStatusFlags; /*0x08 */
1814 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /*0x0C */
1815 U64 MaxLBA; /*0x10 */
1816 U32 StripeSize; /*0x18 */
1817 U16 BlockSize; /*0x1C */
1818 U16 Reserved1; /*0x1E */
1819 U8 SupportedPhysDisks;/*0x20 */
1820 U8 ResyncRate; /*0x21 */
1821 U16 DataScrubDuration; /*0x22 */
1822 U8 NumPhysDisks; /*0x24 */
1823 U8 Reserved2; /*0x25 */
1824 U8 Reserved3; /*0x26 */
1825 U8 InactiveStatus; /*0x27 */
1826 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[]; /*0x28 */
1827} MPI2_CONFIG_PAGE_RAID_VOL_0,
1828 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1829 Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t;
1830
1831#define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1832
1833/*values for RAID VolumeState */
1834#define MPI2_RAID_VOL_STATE_MISSING (0x00)
1835#define MPI2_RAID_VOL_STATE_FAILED (0x01)
1836#define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1837#define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1838#define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1839#define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1840
1841/*values for RAID VolumeType */
1842#define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1843#define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1844#define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1845#define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1846#define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1847
1848/*values for RAID Volume Page 0 VolumeStatusFlags field */
1849#define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1850#define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1851#define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1852#define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1853#define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1854#define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1855#define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1856#define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1857#define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1858#define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1859#define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
1860#define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1861#define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1862#define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1863#define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1864#define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1865#define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1866#define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1867#define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1868
1869/*values for RAID Volume Page 0 SupportedPhysDisks field */
1870#define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1871#define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1872#define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1873#define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1874
1875/*values for RAID Volume Page 0 InactiveStatus field */
1876#define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1877#define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1878#define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1879#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1880#define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1881#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1882#define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1883
1884
1885/*RAID Volume Page 1 */
1886
1887typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 {
1888 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1889 U16 DevHandle; /*0x04 */
1890 U16 Reserved0; /*0x06 */
1891 U8 GUID[24]; /*0x08 */
1892 U8 Name[16]; /*0x20 */
1893 U64 WWID; /*0x30 */
1894 U32 Reserved1; /*0x38 */
1895 U32 Reserved2; /*0x3C */
1896} MPI2_CONFIG_PAGE_RAID_VOL_1,
1897 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1898 Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t;
1899
1900#define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1901
1902
1903/****************************************************************************
1904* RAID Physical Disk Config Pages
1905****************************************************************************/
1906
1907/*RAID Physical Disk Page 0 */
1908
1909typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS {
1910 U16 Reserved1; /*0x00 */
1911 U8 HotSparePool; /*0x02 */
1912 U8 Reserved2; /*0x03 */
1913} MPI2_RAIDPHYSDISK0_SETTINGS,
1914 *PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1915 Mpi2RaidPhysDisk0Settings_t,
1916 *pMpi2RaidPhysDisk0Settings_t;
1917
1918/*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1919
1920typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA {
1921 U8 VendorID[8]; /*0x00 */
1922 U8 ProductID[16]; /*0x08 */
1923 U8 ProductRevLevel[4]; /*0x18 */
1924 U8 SerialNum[32]; /*0x1C */
1925} MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1926 *PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1927 Mpi2RaidPhysDisk0InquiryData_t,
1928 *pMpi2RaidPhysDisk0InquiryData_t;
1929
1930typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 {
1931 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1932 U16 DevHandle; /*0x04 */
1933 U8 Reserved1; /*0x06 */
1934 U8 PhysDiskNum; /*0x07 */
1935 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /*0x08 */
1936 U32 Reserved2; /*0x0C */
1937 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /*0x10 */
1938 U32 Reserved3; /*0x4C */
1939 U8 PhysDiskState; /*0x50 */
1940 U8 OfflineReason; /*0x51 */
1941 U8 IncompatibleReason; /*0x52 */
1942 U8 PhysDiskAttributes; /*0x53 */
1943 U32 PhysDiskStatusFlags;/*0x54 */
1944 U64 DeviceMaxLBA; /*0x58 */
1945 U64 HostMaxLBA; /*0x60 */
1946 U64 CoercedMaxLBA; /*0x68 */
1947 U16 BlockSize; /*0x70 */
1948 U16 Reserved5; /*0x72 */
1949 U32 Reserved6; /*0x74 */
1950} MPI2_CONFIG_PAGE_RD_PDISK_0,
1951 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1952 Mpi2RaidPhysDiskPage0_t,
1953 *pMpi2RaidPhysDiskPage0_t;
1954
1955#define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1956
1957/*PhysDiskState defines */
1958#define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1959#define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1960#define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1961#define MPI2_RAID_PD_STATE_ONLINE (0x03)
1962#define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1963#define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1964#define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1965#define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1966
1967/*OfflineReason defines */
1968#define MPI2_PHYSDISK0_ONLINE (0x00)
1969#define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1970#define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1971#define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1972#define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1973#define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1974#define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1975
1976/*IncompatibleReason defines */
1977#define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1978#define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1979#define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1980#define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1981#define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1982#define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1983#define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
1984#define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1985
1986/*PhysDiskAttributes defines */
1987#define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C)
1988#define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1989#define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1990
1991#define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
1992#define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1993#define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1994
1995/*PhysDiskStatusFlags defines */
1996#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1997#define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1998#define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1999#define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
2000#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
2001#define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
2002#define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
2003#define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
2004
2005
2006/*RAID Physical Disk Page 1 */
2007
2008/*
2009 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
2010 *for NumPhysDiskPaths at runtime before using PhysicalDiskPath[].
2011 */
2012
2013typedef struct _MPI2_RAIDPHYSDISK1_PATH {
2014 U16 DevHandle; /*0x00 */
2015 U16 Reserved1; /*0x02 */
2016 U64 WWID; /*0x04 */
2017 U64 OwnerWWID; /*0x0C */
2018 U8 OwnerIdentifier; /*0x14 */
2019 U8 Reserved2; /*0x15 */
2020 U16 Flags; /*0x16 */
2021} MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH,
2022 Mpi2RaidPhysDisk1Path_t,
2023 *pMpi2RaidPhysDisk1Path_t;
2024
2025/*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
2026#define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
2027#define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
2028#define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
2029
2030typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 {
2031 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
2032 U8 NumPhysDiskPaths; /*0x04 */
2033 U8 PhysDiskNum; /*0x05 */
2034 U16 Reserved1; /*0x06 */
2035 U32 Reserved2; /*0x08 */
2036 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[]; /*0x0C */
2037} MPI2_CONFIG_PAGE_RD_PDISK_1,
2038 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
2039 Mpi2RaidPhysDiskPage1_t,
2040 *pMpi2RaidPhysDiskPage1_t;
2041
2042#define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
2043
2044
2045/****************************************************************************
2046* values for fields used by several types of SAS Config Pages
2047****************************************************************************/
2048
2049/*values for NegotiatedLinkRates fields */
2050#define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
2051#define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
2052#define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
2053/*link rates used for Negotiated Physical and Logical Link Rate */
2054#define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
2055#define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
2056#define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
2057#define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
2058#define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
2059#define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
2060#define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
2061#define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
2062#define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
2063#define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
2064#define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B)
2065#define MPI26_SAS_NEG_LINK_RATE_22_5 (0x0C)
2066
2067
2068/*values for AttachedPhyInfo fields */
2069#define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
2070#define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
2071#define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
2072
2073#define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
2074#define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
2075#define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
2076#define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
2077#define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
2078#define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
2079#define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
2080#define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
2081#define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
2082#define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
2083
2084
2085/*values for PhyInfo fields */
2086#define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
2087
2088#define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
2089#define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27)
2090#define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
2091#define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
2092#define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
2093
2094#define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
2095#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
2096#define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
2097#define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
2098#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
2099#define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
2100
2101#define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
2102#define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
2103#define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
2104#define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
2105#define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
2106#define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
2107#define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
2108#define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
2109#define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
2110#define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
2111
2112#define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
2113#define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
2114#define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
2115#define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
2116
2117#define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
2118#define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
2119
2120#define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
2121#define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
2122#define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
2123#define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
2124
2125
2126/*values for SAS ProgrammedLinkRate fields */
2127#define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
2128#define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
2129#define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
2130#define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
2131#define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
2132#define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0)
2133#define MPI26_SAS_PRATE_MAX_RATE_22_5 (0xC0)
2134#define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
2135#define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
2136#define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
2137#define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
2138#define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
2139#define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B)
2140#define MPI26_SAS_PRATE_MIN_RATE_22_5 (0x0C)
2141
2142
2143/*values for SAS HwLinkRate fields */
2144#define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
2145#define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
2146#define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
2147#define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
2148#define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0)
2149#define MPI26_SAS_HWRATE_MAX_RATE_22_5 (0xC0)
2150#define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
2151#define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
2152#define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
2153#define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
2154#define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B)
2155#define MPI26_SAS_HWRATE_MIN_RATE_22_5 (0x0C)
2156
2157
2158
2159/****************************************************************************
2160* SAS IO Unit Config Pages
2161****************************************************************************/
2162
2163/*SAS IO Unit Page 0 */
2164
2165typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA {
2166 U8 Port; /*0x00 */
2167 U8 PortFlags; /*0x01 */
2168 U8 PhyFlags; /*0x02 */
2169 U8 NegotiatedLinkRate; /*0x03 */
2170 U32 ControllerPhyDeviceInfo;/*0x04 */
2171 U16 AttachedDevHandle; /*0x08 */
2172 U16 ControllerDevHandle; /*0x0A */
2173 U32 DiscoveryStatus; /*0x0C */
2174 U32 Reserved; /*0x10 */
2175} MPI2_SAS_IO_UNIT0_PHY_DATA,
2176 *PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
2177 Mpi2SasIOUnit0PhyData_t,
2178 *pMpi2SasIOUnit0PhyData_t;
2179
2180/*
2181 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
2182 *for NumPhys at runtime before using PhyData[].
2183 */
2184
2185typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 {
2186 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2187 U32 Reserved1;/*0x08 */
2188 U8 NumPhys; /*0x0C */
2189 U8 Reserved2;/*0x0D */
2190 U16 Reserved3;/*0x0E */
2191 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[];/*0x10 */
2192} MPI2_CONFIG_PAGE_SASIOUNIT_0,
2193 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
2194 Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t;
2195
2196#define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
2197
2198/*values for SAS IO Unit Page 0 PortFlags */
2199#define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
2200#define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
2201
2202/*values for SAS IO Unit Page 0 PhyFlags */
2203#define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40)
2204#define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20)
2205#define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
2206#define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
2207
2208/*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2209
2210/*see mpi2_sas.h for values for
2211 *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2212
2213/*values for SAS IO Unit Page 0 DiscoveryStatus */
2214#define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2215#define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2216#define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
2217#define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2218#define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2219#define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2220#define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2221#define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
2222#define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2223#define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
2224#define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
2225#define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
2226#define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
2227#define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
2228#define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
2229#define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2230#define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
2231#define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
2232#define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2233#define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
2234
2235
2236/*SAS IO Unit Page 1 */
2237
2238typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA {
2239 U8 Port; /*0x00 */
2240 U8 PortFlags; /*0x01 */
2241 U8 PhyFlags; /*0x02 */
2242 U8 MaxMinLinkRate; /*0x03 */
2243 U32 ControllerPhyDeviceInfo; /*0x04 */
2244 U16 MaxTargetPortConnectTime; /*0x08 */
2245 U16 Reserved1; /*0x0A */
2246} MPI2_SAS_IO_UNIT1_PHY_DATA,
2247 *PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
2248 Mpi2SasIOUnit1PhyData_t,
2249 *pMpi2SasIOUnit1PhyData_t;
2250
2251/*
2252 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
2253 *for NumPhys at runtime before using PhyData[].
2254 */
2255
2256typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 {
2257 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2258 U16
2259 ControlFlags; /*0x08 */
2260 U16
2261 SASNarrowMaxQueueDepth; /*0x0A */
2262 U16
2263 AdditionalControlFlags; /*0x0C */
2264 U16
2265 SASWideMaxQueueDepth; /*0x0E */
2266 U8
2267 NumPhys; /*0x10 */
2268 U8
2269 SATAMaxQDepth; /*0x11 */
2270 U8
2271 ReportDeviceMissingDelay; /*0x12 */
2272 U8
2273 IODeviceMissingDelay; /*0x13 */
2274 MPI2_SAS_IO_UNIT1_PHY_DATA
2275 PhyData[]; /*0x14 */
2276} MPI2_CONFIG_PAGE_SASIOUNIT_1,
2277 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
2278 Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t;
2279
2280#define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
2281
2282/*values for SAS IO Unit Page 1 ControlFlags */
2283#define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
2284#define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
2285#define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
2286#define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
2287
2288#define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
2289#define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
2290#define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
2291#define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
2292#define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
2293
2294#define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
2295#define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
2296#define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
2297#define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
2298#define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
2299#define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
2300#define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
2301#define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
2302
2303/*values for SAS IO Unit Page 1 AdditionalControlFlags */
2304#define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100)
2305#define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
2306#define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
2307#define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
2308#define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
2309#define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
2310#define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
2311#define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
2312#define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
2313
2314/*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2315#define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
2316#define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
2317
2318/*values for SAS IO Unit Page 1 PortFlags */
2319#define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2320
2321/*values for SAS IO Unit Page 1 PhyFlags */
2322#define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40)
2323#define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20)
2324#define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
2325#define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
2326
2327/*values for SAS IO Unit Page 1 MaxMinLinkRate */
2328#define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
2329#define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
2330#define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
2331#define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
2332#define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0)
2333#define MPI26_SASIOUNIT1_MAX_RATE_22_5 (0xC0)
2334#define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
2335#define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
2336#define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
2337#define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
2338#define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B)
2339#define MPI26_SASIOUNIT1_MIN_RATE_22_5 (0x0C)
2340
2341/*see mpi2_sas.h for values for
2342 *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2343
2344
2345/*SAS IO Unit Page 4 (for MPI v2.5 and earlier) */
2346
2347typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP {
2348 U8 MaxTargetSpinup; /*0x00 */
2349 U8 SpinupDelay; /*0x01 */
2350 U8 SpinupFlags; /*0x02 */
2351 U8 Reserved1; /*0x03 */
2352} MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2353 *PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2354 Mpi2SasIOUnit4SpinupGroup_t,
2355 *pMpi2SasIOUnit4SpinupGroup_t;
2356/*defines for SAS IO Unit Page 4 SpinupFlags */
2357#define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01)
2358
2359
2360/*
2361 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2362 *one and check the value returned for NumPhys at runtime.
2363 */
2364#ifndef MPI2_SAS_IOUNIT4_PHY_MAX
2365#define MPI2_SAS_IOUNIT4_PHY_MAX (4)
2366#endif
2367
2368typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 {
2369 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;/*0x00 */
2370 MPI2_SAS_IOUNIT4_SPINUP_GROUP
2371 SpinupGroupParameters[4]; /*0x08 */
2372 U32
2373 Reserved1; /*0x18 */
2374 U32
2375 Reserved2; /*0x1C */
2376 U32
2377 Reserved3; /*0x20 */
2378 U8
2379 BootDeviceWaitTime; /*0x24 */
2380 U8
2381 SATADeviceWaitTime; /*0x25 */
2382 U16
2383 Reserved5; /*0x26 */
2384 U8
2385 NumPhys; /*0x28 */
2386 U8
2387 PEInitialSpinupDelay; /*0x29 */
2388 U8
2389 PEReplyDelay; /*0x2A */
2390 U8
2391 Flags; /*0x2B */
2392 U8
2393 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /*0x2C */
2394} MPI2_CONFIG_PAGE_SASIOUNIT_4,
2395 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2396 Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t;
2397
2398#define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
2399
2400/*defines for Flags field */
2401#define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
2402
2403/*defines for PHY field */
2404#define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
2405
2406
2407/*SAS IO Unit Page 5 */
2408
2409typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
2410 U8 ControlFlags; /*0x00 */
2411 U8 PortWidthModGroup; /*0x01 */
2412 U16 InactivityTimerExponent; /*0x02 */
2413 U8 SATAPartialTimeout; /*0x04 */
2414 U8 Reserved2; /*0x05 */
2415 U8 SATASlumberTimeout; /*0x06 */
2416 U8 Reserved3; /*0x07 */
2417 U8 SASPartialTimeout; /*0x08 */
2418 U8 Reserved4; /*0x09 */
2419 U8 SASSlumberTimeout; /*0x0A */
2420 U8 Reserved5; /*0x0B */
2421} MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2422 *PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2423 Mpi2SasIOUnit5PhyPmSettings_t,
2424 *pMpi2SasIOUnit5PhyPmSettings_t;
2425
2426/*defines for ControlFlags field */
2427#define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
2428#define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
2429#define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
2430#define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
2431
2432/*defines for PortWidthModeGroup field */
2433#define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
2434
2435/*defines for InactivityTimerExponent field */
2436#define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
2437#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
2438#define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
2439#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
2440#define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
2441#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
2442#define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
2443#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
2444
2445#define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
2446#define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
2447#define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
2448#define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
2449#define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
2450#define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
2451#define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
2452#define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
2453
2454/*
2455 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
2456 *for NumPhys at runtime before using SASPhyPowerManagementSettings[].
2457 */
2458
2459typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
2460 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2461 U8 NumPhys; /*0x08 */
2462 U8 Reserved1;/*0x09 */
2463 U16 Reserved2;/*0x0A */
2464 U32 Reserved3;/*0x0C */
2465 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
2466 SASPhyPowerManagementSettings[]; /*0x10 */
2467} MPI2_CONFIG_PAGE_SASIOUNIT_5,
2468 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2469 Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t;
2470
2471#define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
2472
2473
2474/*SAS IO Unit Page 6 */
2475
2476typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
2477 U8 CurrentStatus; /*0x00 */
2478 U8 CurrentModulation; /*0x01 */
2479 U8 CurrentUtilization; /*0x02 */
2480 U8 Reserved1; /*0x03 */
2481 U32 Reserved2; /*0x04 */
2482} MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2483 *PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2484 Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2485 *pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2486
2487/*defines for CurrentStatus field */
2488#define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
2489#define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
2490#define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
2491#define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
2492#define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
2493#define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
2494#define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
2495#define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
2496
2497/*defines for CurrentModulation field */
2498#define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
2499#define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
2500#define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
2501#define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
2502
2503/*
2504 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
2505 *for NumGroups at runtime before using PortWidthModulationGroupStatus[].
2506 */
2507
2508typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
2509 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2510 U32 Reserved1; /*0x08 */
2511 U32 Reserved2; /*0x0C */
2512 U8 NumGroups; /*0x10 */
2513 U8 Reserved3; /*0x11 */
2514 U16 Reserved4; /*0x12 */
2515 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2516 PortWidthModulationGroupStatus[]; /*0x14 */
2517} MPI2_CONFIG_PAGE_SASIOUNIT_6,
2518 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2519 Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t;
2520
2521#define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
2522
2523
2524/*SAS IO Unit Page 7 */
2525
2526typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
2527 U8 Flags; /*0x00 */
2528 U8 Reserved1; /*0x01 */
2529 U16 Reserved2; /*0x02 */
2530 U8 Threshold75Pct; /*0x04 */
2531 U8 Threshold50Pct; /*0x05 */
2532 U8 Threshold25Pct; /*0x06 */
2533 U8 Reserved3; /*0x07 */
2534} MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2535 *PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2536 Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2537 *pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2538
2539/*defines for Flags field */
2540#define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
2541
2542
2543/*
2544 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
2545 *for NumGroups at runtime before using PortWidthModulationGroupSettings[].
2546 */
2547
2548typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
2549 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2550 U8 SamplingInterval; /*0x08 */
2551 U8 WindowLength; /*0x09 */
2552 U16 Reserved1; /*0x0A */
2553 U32 Reserved2; /*0x0C */
2554 U32 Reserved3; /*0x10 */
2555 U8 NumGroups; /*0x14 */
2556 U8 Reserved4; /*0x15 */
2557 U16 Reserved5; /*0x16 */
2558 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2559 PortWidthModulationGroupSettings[]; /*0x18 */
2560} MPI2_CONFIG_PAGE_SASIOUNIT_7,
2561 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2562 Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t;
2563
2564#define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
2565
2566
2567/*SAS IO Unit Page 8 */
2568
2569typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
2570 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2571 Header; /*0x00 */
2572 U32
2573 Reserved1; /*0x08 */
2574 U32
2575 PowerManagementCapabilities; /*0x0C */
2576 U8
2577 TxRxSleepStatus; /*0x10 */
2578 U8
2579 Reserved2; /*0x11 */
2580 U16
2581 Reserved3; /*0x12 */
2582} MPI2_CONFIG_PAGE_SASIOUNIT_8,
2583 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2584 Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t;
2585
2586#define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
2587
2588/*defines for PowerManagementCapabilities field */
2589#define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000)
2590#define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800)
2591#define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400)
2592#define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200)
2593#define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100)
2594#define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010)
2595#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008)
2596#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004)
2597#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002)
2598#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001)
2599
2600/*defines for TxRxSleepStatus field */
2601#define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00)
2602#define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01)
2603#define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02)
2604#define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03)
2605
2606
2607
2608/*SAS IO Unit Page 16 */
2609
2610typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 {
2611 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2612 Header; /*0x00 */
2613 U64
2614 TimeStamp; /*0x08 */
2615 U32
2616 Reserved1; /*0x10 */
2617 U32
2618 Reserved2; /*0x14 */
2619 U32
2620 FastPathPendedRequests; /*0x18 */
2621 U32
2622 FastPathUnPendedRequests; /*0x1C */
2623 U32
2624 FastPathHostRequestStarts; /*0x20 */
2625 U32
2626 FastPathFirmwareRequestStarts; /*0x24 */
2627 U32
2628 FastPathHostCompletions; /*0x28 */
2629 U32
2630 FastPathFirmwareCompletions; /*0x2C */
2631 U32
2632 NonFastPathRequestStarts; /*0x30 */
2633 U32
2634 NonFastPathHostCompletions; /*0x30 */
2635} MPI2_CONFIG_PAGE_SASIOUNIT16,
2636 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT16,
2637 Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t;
2638
2639#define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00)
2640
2641
2642/****************************************************************************
2643* SAS Expander Config Pages
2644****************************************************************************/
2645
2646/*SAS Expander Page 0 */
2647
2648typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 {
2649 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2650 Header; /*0x00 */
2651 U8
2652 PhysicalPort; /*0x08 */
2653 U8
2654 ReportGenLength; /*0x09 */
2655 U16
2656 EnclosureHandle; /*0x0A */
2657 U64
2658 SASAddress; /*0x0C */
2659 U32
2660 DiscoveryStatus; /*0x14 */
2661 U16
2662 DevHandle; /*0x18 */
2663 U16
2664 ParentDevHandle; /*0x1A */
2665 U16
2666 ExpanderChangeCount; /*0x1C */
2667 U16
2668 ExpanderRouteIndexes; /*0x1E */
2669 U8
2670 NumPhys; /*0x20 */
2671 U8
2672 SASLevel; /*0x21 */
2673 U16
2674 Flags; /*0x22 */
2675 U16
2676 STPBusInactivityTimeLimit; /*0x24 */
2677 U16
2678 STPMaxConnectTimeLimit; /*0x26 */
2679 U16
2680 STP_SMP_NexusLossTime; /*0x28 */
2681 U16
2682 MaxNumRoutedSasAddresses; /*0x2A */
2683 U64
2684 ActiveZoneManagerSASAddress;/*0x2C */
2685 U16
2686 ZoneLockInactivityLimit; /*0x34 */
2687 U16
2688 Reserved1; /*0x36 */
2689 U8
2690 TimeToReducedFunc; /*0x38 */
2691 U8
2692 InitialTimeToReducedFunc; /*0x39 */
2693 U8
2694 MaxReducedFuncTime; /*0x3A */
2695 U8
2696 Reserved2; /*0x3B */
2697} MPI2_CONFIG_PAGE_EXPANDER_0,
2698 *PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2699 Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t;
2700
2701#define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
2702
2703/*values for SAS Expander Page 0 DiscoveryStatus field */
2704#define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2705#define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2706#define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
2707#define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2708#define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2709#define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2710#define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2711#define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
2712#define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2713#define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2714#define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2715#define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2716#define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2717#define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2718#define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2719#define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2720#define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2721#define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2722#define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2723#define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2724
2725/*values for SAS Expander Page 0 Flags field */
2726#define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
2727#define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
2728#define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
2729#define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
2730#define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
2731#define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
2732#define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
2733#define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
2734#define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
2735#define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
2736#define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
2737
2738
2739/*SAS Expander Page 1 */
2740
2741typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 {
2742 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2743 Header; /*0x00 */
2744 U8
2745 PhysicalPort; /*0x08 */
2746 U8
2747 Reserved1; /*0x09 */
2748 U16
2749 Reserved2; /*0x0A */
2750 U8
2751 NumPhys; /*0x0C */
2752 U8
2753 Phy; /*0x0D */
2754 U16
2755 NumTableEntriesProgrammed; /*0x0E */
2756 U8
2757 ProgrammedLinkRate; /*0x10 */
2758 U8
2759 HwLinkRate; /*0x11 */
2760 U16
2761 AttachedDevHandle; /*0x12 */
2762 U32
2763 PhyInfo; /*0x14 */
2764 U32
2765 AttachedDeviceInfo; /*0x18 */
2766 U16
2767 ExpanderDevHandle; /*0x1C */
2768 U8
2769 ChangeCount; /*0x1E */
2770 U8
2771 NegotiatedLinkRate; /*0x1F */
2772 U8
2773 PhyIdentifier; /*0x20 */
2774 U8
2775 AttachedPhyIdentifier; /*0x21 */
2776 U8
2777 Reserved3; /*0x22 */
2778 U8
2779 DiscoveryInfo; /*0x23 */
2780 U32
2781 AttachedPhyInfo; /*0x24 */
2782 U8
2783 ZoneGroup; /*0x28 */
2784 U8
2785 SelfConfigStatus; /*0x29 */
2786 U16
2787 Reserved4; /*0x2A */
2788} MPI2_CONFIG_PAGE_EXPANDER_1,
2789 *PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2790 Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t;
2791
2792#define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2793
2794/*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2795
2796/*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2797
2798/*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2799
2800/*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines
2801 *used for the AttachedDeviceInfo field */
2802
2803/*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2804
2805/*values for SAS Expander Page 1 DiscoveryInfo field */
2806#define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2807#define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2808#define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2809
2810/*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2811
2812
2813/****************************************************************************
2814* SAS Device Config Pages
2815****************************************************************************/
2816
2817/*SAS Device Page 0 */
2818
2819typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 {
2820 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2821 Header; /*0x00 */
2822 U16
2823 Slot; /*0x08 */
2824 U16
2825 EnclosureHandle; /*0x0A */
2826 U64
2827 SASAddress; /*0x0C */
2828 U16
2829 ParentDevHandle; /*0x14 */
2830 U8
2831 PhyNum; /*0x16 */
2832 U8
2833 AccessStatus; /*0x17 */
2834 U16
2835 DevHandle; /*0x18 */
2836 U8
2837 AttachedPhyIdentifier; /*0x1A */
2838 U8
2839 ZoneGroup; /*0x1B */
2840 U32
2841 DeviceInfo; /*0x1C */
2842 U16
2843 Flags; /*0x20 */
2844 U8
2845 PhysicalPort; /*0x22 */
2846 U8
2847 MaxPortConnections; /*0x23 */
2848 U64
2849 DeviceName; /*0x24 */
2850 U8
2851 PortGroups; /*0x2C */
2852 U8
2853 DmaGroup; /*0x2D */
2854 U8
2855 ControlGroup; /*0x2E */
2856 U8
2857 EnclosureLevel; /*0x2F */
2858 U32
2859 ConnectorName[4]; /*0x30 */
2860 U32
2861 Reserved3; /*0x34 */
2862} MPI2_CONFIG_PAGE_SAS_DEV_0,
2863 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2864 Mpi2SasDevicePage0_t,
2865 *pMpi2SasDevicePage0_t;
2866
2867#define MPI2_SASDEVICE0_PAGEVERSION (0x09)
2868
2869/*values for SAS Device Page 0 AccessStatus field */
2870#define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2871#define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2872#define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2873#define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2874#define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2875#define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2876#define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2877#define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2878/*specific values for SATA Init failures */
2879#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2880#define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2881#define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2882#define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2883#define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2884#define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2885#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2886#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2887#define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2888#define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2889#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2890
2891/*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2892
2893/*values for SAS Device Page 0 Flags field */
2894#define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000)
2895#define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000)
2896#define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000)
2897#define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2898#define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
2899#define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2900#define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2901#define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2902#define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2903#define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2904#define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2905#define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2906#define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2907#define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004)
2908#define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002)
2909#define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2910
2911
2912/*SAS Device Page 1 */
2913
2914typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 {
2915 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2916 Header; /*0x00 */
2917 U32
2918 Reserved1; /*0x08 */
2919 U64
2920 SASAddress; /*0x0C */
2921 U32
2922 Reserved2; /*0x14 */
2923 U16
2924 DevHandle; /*0x18 */
2925 U16
2926 Reserved3; /*0x1A */
2927 U8
2928 InitialRegDeviceFIS[20];/*0x1C */
2929} MPI2_CONFIG_PAGE_SAS_DEV_1,
2930 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2931 Mpi2SasDevicePage1_t,
2932 *pMpi2SasDevicePage1_t;
2933
2934#define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2935
2936
2937/****************************************************************************
2938* SAS PHY Config Pages
2939****************************************************************************/
2940
2941/*SAS PHY Page 0 */
2942
2943typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 {
2944 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2945 Header; /*0x00 */
2946 U16
2947 OwnerDevHandle; /*0x08 */
2948 U16
2949 Reserved1; /*0x0A */
2950 U16
2951 AttachedDevHandle; /*0x0C */
2952 U8
2953 AttachedPhyIdentifier; /*0x0E */
2954 U8
2955 Reserved2; /*0x0F */
2956 U32
2957 AttachedPhyInfo; /*0x10 */
2958 U8
2959 ProgrammedLinkRate; /*0x14 */
2960 U8
2961 HwLinkRate; /*0x15 */
2962 U8
2963 ChangeCount; /*0x16 */
2964 U8
2965 Flags; /*0x17 */
2966 U32
2967 PhyInfo; /*0x18 */
2968 U8
2969 NegotiatedLinkRate; /*0x1C */
2970 U8
2971 Reserved3; /*0x1D */
2972 U16
2973 Reserved4; /*0x1E */
2974} MPI2_CONFIG_PAGE_SAS_PHY_0,
2975 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2976 Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t;
2977
2978#define MPI2_SASPHY0_PAGEVERSION (0x03)
2979
2980/*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2981
2982/*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2983
2984/*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2985
2986/*values for SAS PHY Page 0 Flags field */
2987#define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2988
2989/*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2990
2991/*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2992
2993
2994/*SAS PHY Page 1 */
2995
2996typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 {
2997 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2998 Header; /*0x00 */
2999 U32
3000 Reserved1; /*0x08 */
3001 U32
3002 InvalidDwordCount; /*0x0C */
3003 U32
3004 RunningDisparityErrorCount; /*0x10 */
3005 U32
3006 LossDwordSynchCount; /*0x14 */
3007 U32
3008 PhyResetProblemCount; /*0x18 */
3009} MPI2_CONFIG_PAGE_SAS_PHY_1,
3010 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
3011 Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t;
3012
3013#define MPI2_SASPHY1_PAGEVERSION (0x01)
3014
3015
3016/*SAS PHY Page 2 */
3017
3018typedef struct _MPI2_SASPHY2_PHY_EVENT {
3019 U8 PhyEventCode; /*0x00 */
3020 U8 Reserved1; /*0x01 */
3021 U16 Reserved2; /*0x02 */
3022 U32 PhyEventInfo; /*0x04 */
3023} MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT,
3024 Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t;
3025
3026/*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
3027
3028
3029/*
3030 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
3031 *for NumPhyEvents at runtime before using PhyEvent[].
3032 */
3033
3034typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
3035 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3036 Header; /*0x00 */
3037 U32
3038 Reserved1; /*0x08 */
3039 U8
3040 NumPhyEvents; /*0x0C */
3041 U8
3042 Reserved2; /*0x0D */
3043 U16
3044 Reserved3; /*0x0E */
3045 MPI2_SASPHY2_PHY_EVENT
3046 PhyEvent[]; /*0x10 */
3047} MPI2_CONFIG_PAGE_SAS_PHY_2,
3048 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
3049 Mpi2SasPhyPage2_t,
3050 *pMpi2SasPhyPage2_t;
3051
3052#define MPI2_SASPHY2_PAGEVERSION (0x00)
3053
3054
3055/*SAS PHY Page 3 */
3056
3057typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
3058 U8 PhyEventCode; /*0x00 */
3059 U8 Reserved1; /*0x01 */
3060 U16 Reserved2; /*0x02 */
3061 U8 CounterType; /*0x04 */
3062 U8 ThresholdWindow; /*0x05 */
3063 U8 TimeUnits; /*0x06 */
3064 U8 Reserved3; /*0x07 */
3065 U32 EventThreshold; /*0x08 */
3066 U16 ThresholdFlags; /*0x0C */
3067 U16 Reserved4; /*0x0E */
3068} MPI2_SASPHY3_PHY_EVENT_CONFIG,
3069 *PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
3070 Mpi2SasPhy3PhyEventConfig_t,
3071 *pMpi2SasPhy3PhyEventConfig_t;
3072
3073/*values for PhyEventCode field */
3074#define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
3075#define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
3076#define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
3077#define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
3078#define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
3079#define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
3080#define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
3081#define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
3082#define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
3083#define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
3084#define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
3085#define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
3086#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
3087#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
3088#define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
3089#define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
3090#define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
3091#define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
3092#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
3093#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
3094#define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
3095#define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
3096#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
3097#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
3098#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
3099#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
3100#define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
3101#define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
3102#define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
3103#define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
3104#define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
3105#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
3106#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
3107#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
3108#define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
3109#define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
3110#define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
3111
3112/*Following codes are product specific and in MPI v2.6 and later */
3113#define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3)
3114#define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4)
3115#define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5)
3116#define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6)
3117#define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7)
3118#define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8)
3119#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9)
3120#define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA)
3121#define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB)
3122#define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC)
3123
3124
3125/*values for the CounterType field */
3126#define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
3127#define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
3128#define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
3129
3130/*values for the TimeUnits field */
3131#define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
3132#define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
3133#define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
3134#define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
3135
3136/*values for the ThresholdFlags field */
3137#define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
3138#define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
3139
3140/*
3141 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
3142 *for NumPhyEvents at runtime before using PhyEventConfig[].
3143 */
3144
3145typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
3146 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3147 Header; /*0x00 */
3148 U32
3149 Reserved1; /*0x08 */
3150 U8
3151 NumPhyEvents; /*0x0C */
3152 U8
3153 Reserved2; /*0x0D */
3154 U16
3155 Reserved3; /*0x0E */
3156 MPI2_SASPHY3_PHY_EVENT_CONFIG
3157 PhyEventConfig[]; /*0x10 */
3158} MPI2_CONFIG_PAGE_SAS_PHY_3,
3159 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
3160 Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t;
3161
3162#define MPI2_SASPHY3_PAGEVERSION (0x00)
3163
3164
3165/*SAS PHY Page 4 */
3166
3167typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
3168 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3169 Header; /*0x00 */
3170 U16
3171 Reserved1; /*0x08 */
3172 U8
3173 Reserved2; /*0x0A */
3174 U8
3175 Flags; /*0x0B */
3176 U8
3177 InitialFrame[28]; /*0x0C */
3178} MPI2_CONFIG_PAGE_SAS_PHY_4,
3179 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
3180 Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t;
3181
3182#define MPI2_SASPHY4_PAGEVERSION (0x00)
3183
3184/*values for the Flags field */
3185#define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
3186#define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
3187
3188
3189
3190
3191/****************************************************************************
3192* SAS Port Config Pages
3193****************************************************************************/
3194
3195/*SAS Port Page 0 */
3196
3197typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 {
3198 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3199 Header; /*0x00 */
3200 U8
3201 PortNumber; /*0x08 */
3202 U8
3203 PhysicalPort; /*0x09 */
3204 U8
3205 PortWidth; /*0x0A */
3206 U8
3207 PhysicalPortWidth; /*0x0B */
3208 U8
3209 ZoneGroup; /*0x0C */
3210 U8
3211 Reserved1; /*0x0D */
3212 U16
3213 Reserved2; /*0x0E */
3214 U64
3215 SASAddress; /*0x10 */
3216 U32
3217 DeviceInfo; /*0x18 */
3218 U32
3219 Reserved3; /*0x1C */
3220 U32
3221 Reserved4; /*0x20 */
3222} MPI2_CONFIG_PAGE_SAS_PORT_0,
3223 *PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
3224 Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t;
3225
3226#define MPI2_SASPORT0_PAGEVERSION (0x00)
3227
3228/*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
3229
3230
3231/****************************************************************************
3232* SAS Enclosure Config Pages
3233****************************************************************************/
3234
3235/*SAS Enclosure Page 0 */
3236
3237typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 {
3238 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3239 U32 Reserved1; /*0x08 */
3240 U64 EnclosureLogicalID; /*0x0C */
3241 U16 Flags; /*0x14 */
3242 U16 EnclosureHandle; /*0x16 */
3243 U16 NumSlots; /*0x18 */
3244 U16 StartSlot; /*0x1A */
3245 U8 ChassisSlot; /*0x1C */
3246 U8 EnclosureLevel; /*0x1D */
3247 U16 SEPDevHandle; /*0x1E */
3248 U8 OEMRD; /*0x20 */
3249 U8 Reserved1a; /*0x21 */
3250 U16 Reserved2; /*0x22 */
3251 U32 Reserved3; /*0x24 */
3252} MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3253 *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3254 Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t,
3255 MPI26_CONFIG_PAGE_ENCLOSURE_0,
3256 *PTR_MPI26_CONFIG_PAGE_ENCLOSURE_0,
3257 Mpi26EnclosurePage0_t, *pMpi26EnclosurePage0_t;
3258
3259#define MPI2_SASENCLOSURE0_PAGEVERSION (0x04)
3260
3261/*values for SAS Enclosure Page 0 Flags field */
3262#define MPI26_SAS_ENCLS0_FLAGS_OEMRD_VALID (0x0080)
3263#define MPI26_SAS_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040)
3264#define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020)
3265#define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010)
3266#define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
3267#define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
3268#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
3269#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
3270#define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
3271#define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
3272#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
3273
3274#define MPI26_ENCLOSURE0_PAGEVERSION (0x04)
3275
3276/*Values for Enclosure Page 0 Flags field */
3277#define MPI26_ENCLS0_FLAGS_OEMRD_VALID (0x0080)
3278#define MPI26_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040)
3279#define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020)
3280#define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010)
3281#define MPI26_ENCLS0_FLAGS_MNG_MASK (0x000F)
3282#define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
3283#define MPI26_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
3284#define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
3285#define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
3286#define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
3287#define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
3288
3289/****************************************************************************
3290* Log Config Page
3291****************************************************************************/
3292
3293/*Log Page 0 */
3294
3295/*
3296 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
3297 *for NumLogEntries at runtime before using LogEntry[].
3298 */
3299
3300#define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
3301
3302typedef struct _MPI2_LOG_0_ENTRY {
3303 U64 TimeStamp; /*0x00 */
3304 U32 Reserved1; /*0x08 */
3305 U16 LogSequence; /*0x0C */
3306 U16 LogEntryQualifier; /*0x0E */
3307 U8 VP_ID; /*0x10 */
3308 U8 VF_ID; /*0x11 */
3309 U16 Reserved2; /*0x12 */
3310 U8
3311 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */
3312} MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY,
3313 Mpi2Log0Entry_t, *pMpi2Log0Entry_t;
3314
3315/*values for Log Page 0 LogEntry LogEntryQualifier field */
3316#define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
3317#define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
3318#define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
3319#define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
3320#define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
3321
3322typedef struct _MPI2_CONFIG_PAGE_LOG_0 {
3323 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3324 U32 Reserved1; /*0x08 */
3325 U32 Reserved2; /*0x0C */
3326 U16 NumLogEntries;/*0x10 */
3327 U16 Reserved3; /*0x12 */
3328 MPI2_LOG_0_ENTRY LogEntry[]; /*0x14 */
3329} MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0,
3330 Mpi2LogPage0_t, *pMpi2LogPage0_t;
3331
3332#define MPI2_LOG_0_PAGEVERSION (0x02)
3333
3334
3335/****************************************************************************
3336* RAID Config Page
3337****************************************************************************/
3338
3339/*RAID Page 0 */
3340
3341/*
3342 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
3343 *for NumElements at runtime before using ConfigElement[].
3344 */
3345
3346typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT {
3347 U16 ElementFlags; /*0x00 */
3348 U16 VolDevHandle; /*0x02 */
3349 U8 HotSparePool; /*0x04 */
3350 U8 PhysDiskNum; /*0x05 */
3351 U16 PhysDiskDevHandle; /*0x06 */
3352} MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3353 *PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3354 Mpi2RaidConfig0ConfigElement_t,
3355 *pMpi2RaidConfig0ConfigElement_t;
3356
3357/*values for the ElementFlags field */
3358#define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
3359#define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
3360#define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
3361#define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
3362#define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
3363
3364
3365typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 {
3366 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3367 U8 NumHotSpares; /*0x08 */
3368 U8 NumPhysDisks; /*0x09 */
3369 U8 NumVolumes; /*0x0A */
3370 U8 ConfigNum; /*0x0B */
3371 U32 Flags; /*0x0C */
3372 U8 ConfigGUID[24]; /*0x10 */
3373 U32 Reserved1; /*0x28 */
3374 U8 NumElements; /*0x2C */
3375 U8 Reserved2; /*0x2D */
3376 U16 Reserved3; /*0x2E */
3377 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[];/*0x30 */
3378} MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3379 *PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3380 Mpi2RaidConfigurationPage0_t,
3381 *pMpi2RaidConfigurationPage0_t;
3382
3383#define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
3384
3385/*values for RAID Configuration Page 0 Flags field */
3386#define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
3387
3388
3389/****************************************************************************
3390* Driver Persistent Mapping Config Pages
3391****************************************************************************/
3392
3393/*Driver Persistent Mapping Page 0 */
3394
3395typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY {
3396 U64 PhysicalIdentifier; /*0x00 */
3397 U16 MappingInformation; /*0x08 */
3398 U16 DeviceIndex; /*0x0A */
3399 U32 PhysicalBitsMapping; /*0x0C */
3400 U32 Reserved1; /*0x10 */
3401} MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3402 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3403 Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t;
3404
3405typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 {
3406 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3407 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /*0x08 */
3408} MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3409 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3410 Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t;
3411
3412#define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
3413
3414/*values for Driver Persistent Mapping Page 0 MappingInformation field */
3415#define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
3416#define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
3417#define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
3418
3419
3420/****************************************************************************
3421* Ethernet Config Pages
3422****************************************************************************/
3423
3424/*Ethernet Page 0 */
3425
3426/*IP address (union of IPv4 and IPv6) */
3427typedef union _MPI2_ETHERNET_IP_ADDR {
3428 U32 IPv4Addr;
3429 U32 IPv6Addr[4];
3430} MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR,
3431 Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t;
3432
3433#define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
3434
3435typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
3436 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3437 U8 NumInterfaces; /*0x08 */
3438 U8 Reserved0; /*0x09 */
3439 U16 Reserved1; /*0x0A */
3440 U32 Status; /*0x0C */
3441 U8 MediaState; /*0x10 */
3442 U8 Reserved2; /*0x11 */
3443 U16 Reserved3; /*0x12 */
3444 U8 MacAddress[6]; /*0x14 */
3445 U8 Reserved4; /*0x1A */
3446 U8 Reserved5; /*0x1B */
3447 MPI2_ETHERNET_IP_ADDR IpAddress; /*0x1C */
3448 MPI2_ETHERNET_IP_ADDR SubnetMask; /*0x2C */
3449 MPI2_ETHERNET_IP_ADDR GatewayIpAddress;/*0x3C */
3450 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /*0x4C */
3451 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /*0x5C */
3452 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /*0x6C */
3453 U8
3454 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3455} MPI2_CONFIG_PAGE_ETHERNET_0,
3456 *PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
3457 Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t;
3458
3459#define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
3460
3461/*values for Ethernet Page 0 Status field */
3462#define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
3463#define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
3464#define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
3465#define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
3466#define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
3467#define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
3468#define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
3469#define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
3470#define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
3471#define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
3472#define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
3473#define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
3474
3475/*values for Ethernet Page 0 MediaState field */
3476#define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
3477#define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
3478#define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
3479
3480#define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
3481#define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
3482#define MPI2_ETHPG0_MS_10MBIT (0x01)
3483#define MPI2_ETHPG0_MS_100MBIT (0x02)
3484#define MPI2_ETHPG0_MS_1GBIT (0x03)
3485
3486
3487/*Ethernet Page 1 */
3488
3489typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
3490 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3491 Header; /*0x00 */
3492 U32
3493 Reserved0; /*0x08 */
3494 U32
3495 Flags; /*0x0C */
3496 U8
3497 MediaState; /*0x10 */
3498 U8
3499 Reserved1; /*0x11 */
3500 U16
3501 Reserved2; /*0x12 */
3502 U8
3503 MacAddress[6]; /*0x14 */
3504 U8
3505 Reserved3; /*0x1A */
3506 U8
3507 Reserved4; /*0x1B */
3508 MPI2_ETHERNET_IP_ADDR
3509 StaticIpAddress; /*0x1C */
3510 MPI2_ETHERNET_IP_ADDR
3511 StaticSubnetMask; /*0x2C */
3512 MPI2_ETHERNET_IP_ADDR
3513 StaticGatewayIpAddress; /*0x3C */
3514 MPI2_ETHERNET_IP_ADDR
3515 StaticDNS1IpAddress; /*0x4C */
3516 MPI2_ETHERNET_IP_ADDR
3517 StaticDNS2IpAddress; /*0x5C */
3518 U32
3519 Reserved5; /*0x6C */
3520 U32
3521 Reserved6; /*0x70 */
3522 U32
3523 Reserved7; /*0x74 */
3524 U32
3525 Reserved8; /*0x78 */
3526 U8
3527 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3528} MPI2_CONFIG_PAGE_ETHERNET_1,
3529 *PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
3530 Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t;
3531
3532#define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
3533
3534/*values for Ethernet Page 1 Flags field */
3535#define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
3536#define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
3537#define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
3538#define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
3539#define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
3540#define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
3541#define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
3542#define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
3543#define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
3544
3545/*values for Ethernet Page 1 MediaState field */
3546#define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
3547#define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
3548#define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
3549
3550#define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
3551#define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
3552#define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
3553#define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
3554#define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
3555
3556
3557/****************************************************************************
3558* Extended Manufacturing Config Pages
3559****************************************************************************/
3560
3561/*
3562 *Generic structure to use for product-specific extended manufacturing pages
3563 *(currently Extended Manufacturing Page 40 through Extended Manufacturing
3564 *Page 60).
3565 */
3566
3567typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS {
3568 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3569 Header; /*0x00 */
3570 U32
3571 ProductSpecificInfo; /*0x08 */
3572} MPI2_CONFIG_PAGE_EXT_MAN_PS,
3573 *PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
3574 Mpi2ExtManufacturingPagePS_t,
3575 *pMpi2ExtManufacturingPagePS_t;
3576
3577/*PageVersion should be provided by product-specific code */
3578
3579
3580
3581/****************************************************************************
3582* values for fields used by several types of PCIe Config Pages
3583****************************************************************************/
3584
3585/*values for NegotiatedLinkRates fields */
3586#define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
3587/*link rates used for Negotiated Physical Link Rate */
3588#define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN (0x00)
3589#define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01)
3590#define MPI26_PCIE_NEG_LINK_RATE_2_5 (0x02)
3591#define MPI26_PCIE_NEG_LINK_RATE_5_0 (0x03)
3592#define MPI26_PCIE_NEG_LINK_RATE_8_0 (0x04)
3593#define MPI26_PCIE_NEG_LINK_RATE_16_0 (0x05)
3594
3595
3596/****************************************************************************
3597* PCIe IO Unit Config Pages (MPI v2.6 and later)
3598****************************************************************************/
3599
3600/*PCIe IO Unit Page 0 */
3601
3602typedef struct _MPI26_PCIE_IO_UNIT0_PHY_DATA {
3603 U8 Link; /*0x00 */
3604 U8 LinkFlags; /*0x01 */
3605 U8 PhyFlags; /*0x02 */
3606 U8 NegotiatedLinkRate; /*0x03 */
3607 U32 ControllerPhyDeviceInfo;/*0x04 */
3608 U16 AttachedDevHandle; /*0x08 */
3609 U16 ControllerDevHandle; /*0x0A */
3610 U32 EnumerationStatus; /*0x0C */
3611 U32 Reserved1; /*0x10 */
3612} MPI26_PCIE_IO_UNIT0_PHY_DATA,
3613 *PTR_MPI26_PCIE_IO_UNIT0_PHY_DATA,
3614 Mpi26PCIeIOUnit0PhyData_t, *pMpi26PCIeIOUnit0PhyData_t;
3615
3616/*
3617 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
3618 *for NumPhys at runtime before using PhyData[].
3619 */
3620
3621typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_0 {
3622 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3623 U32 Reserved1; /*0x08 */
3624 U8 NumPhys; /*0x0C */
3625 U8 InitStatus; /*0x0D */
3626 U16 Reserved3; /*0x0E */
3627 MPI26_PCIE_IO_UNIT0_PHY_DATA
3628 PhyData[]; /*0x10 */
3629} MPI26_CONFIG_PAGE_PIOUNIT_0,
3630 *PTR_MPI26_CONFIG_PAGE_PIOUNIT_0,
3631 Mpi26PCIeIOUnitPage0_t, *pMpi26PCIeIOUnitPage0_t;
3632
3633#define MPI26_PCIEIOUNITPAGE0_PAGEVERSION (0x00)
3634
3635/*values for PCIe IO Unit Page 0 LinkFlags */
3636#define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS (0x08)
3637
3638/*values for PCIe IO Unit Page 0 PhyFlags */
3639#define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
3640
3641/*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3642
3643/*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo
3644 *values
3645 */
3646
3647/*values for PCIe IO Unit Page 0 EnumerationStatus */
3648#define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000)
3649#define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED (0x20000000)
3650
3651
3652/*PCIe IO Unit Page 1 */
3653
3654typedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA {
3655 U8 Link; /*0x00 */
3656 U8 LinkFlags; /*0x01 */
3657 U8 PhyFlags; /*0x02 */
3658 U8 MaxMinLinkRate; /*0x03 */
3659 U32 ControllerPhyDeviceInfo; /*0x04 */
3660 U32 Reserved1; /*0x08 */
3661} MPI26_PCIE_IO_UNIT1_PHY_DATA,
3662 *PTR_MPI26_PCIE_IO_UNIT1_PHY_DATA,
3663 Mpi26PCIeIOUnit1PhyData_t, *pMpi26PCIeIOUnit1PhyData_t;
3664
3665/*values for LinkFlags */
3666#define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK (0x00)
3667#define MPI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN (0x01)
3668#define MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN (0x02)
3669
3670/*
3671 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
3672 *for NumPhys at runtime before using PhyData[].
3673 */
3674
3675typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 {
3676 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3677 U16 ControlFlags; /*0x08 */
3678 U16 Reserved; /*0x0A */
3679 U16 AdditionalControlFlags; /*0x0C */
3680 U16 NVMeMaxQueueDepth; /*0x0E */
3681 U8 NumPhys; /*0x10 */
3682 U8 DMDReportPCIe; /*0x11 */
3683 U16 Reserved2; /*0x12 */
3684 MPI26_PCIE_IO_UNIT1_PHY_DATA
3685 PhyData[]; /*0x14 */
3686} MPI26_CONFIG_PAGE_PIOUNIT_1,
3687 *PTR_MPI26_CONFIG_PAGE_PIOUNIT_1,
3688 Mpi26PCIeIOUnitPage1_t, *pMpi26PCIeIOUnitPage1_t;
3689
3690#define MPI26_PCIEIOUNITPAGE1_PAGEVERSION (0x00)
3691
3692/*values for PCIe IO Unit Page 1 PhyFlags */
3693#define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
3694#define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY (0x01)
3695
3696/*values for PCIe IO Unit Page 1 MaxMinLinkRate */
3697#define MPI26_PCIEIOUNIT1_MAX_RATE_MASK (0xF0)
3698#define MPI26_PCIEIOUNIT1_MAX_RATE_SHIFT (4)
3699#define MPI26_PCIEIOUNIT1_MAX_RATE_2_5 (0x20)
3700#define MPI26_PCIEIOUNIT1_MAX_RATE_5_0 (0x30)
3701#define MPI26_PCIEIOUNIT1_MAX_RATE_8_0 (0x40)
3702#define MPI26_PCIEIOUNIT1_MAX_RATE_16_0 (0x50)
3703
3704/*values for PCIe IO Unit Page 1 DMDReportPCIe */
3705#define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_MASK (0x80)
3706#define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_1_SEC (0x00)
3707#define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_16_SEC (0x80)
3708#define MPI26_PCIEIOUNIT1_DMDRPT_DELAY_TIME_MASK (0x7F)
3709
3710/*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo
3711 *values
3712 */
3713
3714
3715/****************************************************************************
3716* PCIe Switch Config Pages (MPI v2.6 and later)
3717****************************************************************************/
3718
3719/*PCIe Switch Page 0 */
3720
3721typedef struct _MPI26_CONFIG_PAGE_PSWITCH_0 {
3722 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3723 U8 PhysicalPort; /*0x08 */
3724 U8 Reserved1; /*0x09 */
3725 U16 Reserved2; /*0x0A */
3726 U16 DevHandle; /*0x0C */
3727 U16 ParentDevHandle; /*0x0E */
3728 U8 NumPorts; /*0x10 */
3729 U8 PCIeLevel; /*0x11 */
3730 U16 Reserved3; /*0x12 */
3731 U32 Reserved4; /*0x14 */
3732 U32 Reserved5; /*0x18 */
3733 U32 Reserved6; /*0x1C */
3734} MPI26_CONFIG_PAGE_PSWITCH_0, *PTR_MPI26_CONFIG_PAGE_PSWITCH_0,
3735 Mpi26PCIeSwitchPage0_t, *pMpi26PCIeSwitchPage0_t;
3736
3737#define MPI26_PCIESWITCH0_PAGEVERSION (0x00)
3738
3739
3740/*PCIe Switch Page 1 */
3741
3742typedef struct _MPI26_CONFIG_PAGE_PSWITCH_1 {
3743 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3744 U8 PhysicalPort; /*0x08 */
3745 U8 Reserved1; /*0x09 */
3746 U16 Reserved2; /*0x0A */
3747 U8 NumPorts; /*0x0C */
3748 U8 PortNum; /*0x0D */
3749 U16 AttachedDevHandle; /*0x0E */
3750 U16 SwitchDevHandle; /*0x10 */
3751 U8 NegotiatedPortWidth; /*0x12 */
3752 U8 NegotiatedLinkRate; /*0x13 */
3753 U32 Reserved4; /*0x14 */
3754 U32 Reserved5; /*0x18 */
3755} MPI26_CONFIG_PAGE_PSWITCH_1, *PTR_MPI26_CONFIG_PAGE_PSWITCH_1,
3756 Mpi26PCIeSwitchPage1_t, *pMpi26PCIeSwitchPage1_t;
3757
3758#define MPI26_PCIESWITCH1_PAGEVERSION (0x00)
3759
3760/*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3761
3762/* defines for the Flags field */
3763#define MPI26_PCIESWITCH1_2_RETIMER_PRESENCE (0x0002)
3764#define MPI26_PCIESWITCH1_RETIMER_PRESENCE (0x0001)
3765
3766/****************************************************************************
3767* PCIe Device Config Pages (MPI v2.6 and later)
3768****************************************************************************/
3769
3770/*PCIe Device Page 0 */
3771
3772typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0 {
3773 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3774 U16 Slot; /*0x08 */
3775 U16 EnclosureHandle; /*0x0A */
3776 U64 WWID; /*0x0C */
3777 U16 ParentDevHandle; /*0x14 */
3778 U8 PortNum; /*0x16 */
3779 U8 AccessStatus; /*0x17 */
3780 U16 DevHandle; /*0x18 */
3781 U8 PhysicalPort; /*0x1A */
3782 U8 Reserved1; /*0x1B */
3783 U32 DeviceInfo; /*0x1C */
3784 U32 Flags; /*0x20 */
3785 U8 SupportedLinkRates; /*0x24 */
3786 U8 MaxPortWidth; /*0x25 */
3787 U8 NegotiatedPortWidth; /*0x26 */
3788 U8 NegotiatedLinkRate; /*0x27 */
3789 U8 EnclosureLevel; /*0x28 */
3790 U8 Reserved2; /*0x29 */
3791 U16 Reserved3; /*0x2A */
3792 U8 ConnectorName[4]; /*0x2C */
3793 U32 Reserved4; /*0x30 */
3794 U32 Reserved5; /*0x34 */
3795} MPI26_CONFIG_PAGE_PCIEDEV_0, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_0,
3796 Mpi26PCIeDevicePage0_t, *pMpi26PCIeDevicePage0_t;
3797
3798#define MPI26_PCIEDEVICE0_PAGEVERSION (0x01)
3799
3800/*values for PCIe Device Page 0 AccessStatus field */
3801#define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS (0x00)
3802#define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION (0x04)
3803#define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED (0x02)
3804#define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED (0x07)
3805#define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED (0x08)
3806#define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE (0x09)
3807#define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED (0x0A)
3808#define MPI26_PCIEDEV0_ASTATUS_UNKNOWN (0x10)
3809
3810#define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT (0x30)
3811#define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x31)
3812#define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED (0x32)
3813#define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED (0x33)
3814#define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED (0x34)
3815#define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED (0x35)
3816#define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x36)
3817#define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT (0x37)
3818#define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS (0x38)
3819
3820#define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX (0x3F)
3821
3822/*see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo
3823 *field
3824 */
3825
3826/*values for PCIe Device Page 0 Flags field*/
3827#define MPI26_PCIEDEV0_FLAGS_2_RETIMER_PRESENCE (0x00020000)
3828#define MPI26_PCIEDEV0_FLAGS_RETIMER_PRESENCE (0x00010000)
3829#define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE (0x00008000)
3830#define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH (0x00004000)
3831#define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE (0x00002000)
3832#define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION (0x00000400)
3833#define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION (0x00000200)
3834#define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE (0x00000100)
3835#define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED (0x00000080)
3836#define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED (0x00000040)
3837#define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED (0x00000020)
3838#define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED (0x00000010)
3839#define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID (0x00000002)
3840#define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT (0x00000001)
3841
3842/* values for PCIe Device Page 0 SupportedLinkRates field */
3843#define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED (0x08)
3844#define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED (0x04)
3845#define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED (0x02)
3846#define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED (0x01)
3847
3848/*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3849
3850
3851/*PCIe Device Page 2 */
3852
3853typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2 {
3854 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3855 U16 DevHandle; /*0x08 */
3856 U8 ControllerResetTO; /* 0x0A */
3857 U8 Reserved1; /* 0x0B */
3858 U32 MaximumDataTransferSize; /*0x0C */
3859 U32 Capabilities; /*0x10 */
3860 U16 NOIOB; /* 0x14 */
3861 U16 ShutdownLatency; /* 0x16 */
3862 U16 VendorID; /* 0x18 */
3863 U16 DeviceID; /* 0x1A */
3864 U16 SubsystemVendorID; /* 0x1C */
3865 U16 SubsystemID; /* 0x1E */
3866 U8 RevisionID; /* 0x20 */
3867 U8 Reserved21[3]; /* 0x21 */
3868} MPI26_CONFIG_PAGE_PCIEDEV_2, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_2,
3869 Mpi26PCIeDevicePage2_t, *pMpi26PCIeDevicePage2_t;
3870
3871#define MPI26_PCIEDEVICE2_PAGEVERSION (0x01)
3872
3873/*defines for PCIe Device Page 2 Capabilities field */
3874#define MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN (0x00000008)
3875#define MPI26_PCIEDEV2_CAP_SGL_FORMAT (0x00000004)
3876#define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT (0x00000002)
3877#define MPI26_PCIEDEV2_CAP_SGL_SUPPORT (0x00000001)
3878
3879/* Defines for the NOIOB field */
3880#define MPI26_PCIEDEV2_NOIOB_UNSUPPORTED (0x0000)
3881
3882/****************************************************************************
3883* PCIe Link Config Pages (MPI v2.6 and later)
3884****************************************************************************/
3885
3886/*PCIe Link Page 1 */
3887
3888typedef struct _MPI26_CONFIG_PAGE_PCIELINK_1 {
3889 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3890 U8 Link; /*0x08 */
3891 U8 Reserved1; /*0x09 */
3892 U16 Reserved2; /*0x0A */
3893 U32 CorrectableErrorCount; /*0x0C */
3894 U16 NonFatalErrorCount; /*0x10 */
3895 U16 Reserved3; /*0x12 */
3896 U16 FatalErrorCount; /*0x14 */
3897 U16 Reserved4; /*0x16 */
3898} MPI26_CONFIG_PAGE_PCIELINK_1, *PTR_MPI26_CONFIG_PAGE_PCIELINK_1,
3899 Mpi26PcieLinkPage1_t, *pMpi26PcieLinkPage1_t;
3900
3901#define MPI26_PCIELINK1_PAGEVERSION (0x00)
3902
3903/*PCIe Link Page 2 */
3904
3905typedef struct _MPI26_PCIELINK2_LINK_EVENT {
3906 U8 LinkEventCode; /*0x00 */
3907 U8 Reserved1; /*0x01 */
3908 U16 Reserved2; /*0x02 */
3909 U32 LinkEventInfo; /*0x04 */
3910} MPI26_PCIELINK2_LINK_EVENT, *PTR_MPI26_PCIELINK2_LINK_EVENT,
3911 Mpi26PcieLink2LinkEvent_t, *pMpi26PcieLink2LinkEvent_t;
3912
3913/*use MPI26_PCIELINK3_EVTCODE_ for the LinkEventCode field */
3914
3915
3916/*
3917 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
3918 *for NumLinkEvents at runtime before using LinkEvent[].
3919 */
3920
3921typedef struct _MPI26_CONFIG_PAGE_PCIELINK_2 {
3922 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3923 U8 Link; /*0x08 */
3924 U8 Reserved1; /*0x09 */
3925 U16 Reserved2; /*0x0A */
3926 U8 NumLinkEvents; /*0x0C */
3927 U8 Reserved3; /*0x0D */
3928 U16 Reserved4; /*0x0E */
3929 MPI26_PCIELINK2_LINK_EVENT
3930 LinkEvent[]; /*0x10 */
3931} MPI26_CONFIG_PAGE_PCIELINK_2, *PTR_MPI26_CONFIG_PAGE_PCIELINK_2,
3932 Mpi26PcieLinkPage2_t, *pMpi26PcieLinkPage2_t;
3933
3934#define MPI26_PCIELINK2_PAGEVERSION (0x00)
3935
3936/*PCIe Link Page 3 */
3937
3938typedef struct _MPI26_PCIELINK3_LINK_EVENT_CONFIG {
3939 U8 LinkEventCode; /*0x00 */
3940 U8 Reserved1; /*0x01 */
3941 U16 Reserved2; /*0x02 */
3942 U8 CounterType; /*0x04 */
3943 U8 ThresholdWindow; /*0x05 */
3944 U8 TimeUnits; /*0x06 */
3945 U8 Reserved3; /*0x07 */
3946 U32 EventThreshold; /*0x08 */
3947 U16 ThresholdFlags; /*0x0C */
3948 U16 Reserved4; /*0x0E */
3949} MPI26_PCIELINK3_LINK_EVENT_CONFIG, *PTR_MPI26_PCIELINK3_LINK_EVENT_CONFIG,
3950 Mpi26PcieLink3LinkEventConfig_t, *pMpi26PcieLink3LinkEventConfig_t;
3951
3952/*values for LinkEventCode field */
3953#define MPI26_PCIELINK3_EVTCODE_NO_EVENT (0x00)
3954#define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED (0x01)
3955#define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED (0x02)
3956#define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED (0x03)
3957#define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED (0x04)
3958#define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED (0x05)
3959#define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED (0x06)
3960#define MPI26_PCIELINK3_EVTCODE_POISONED_TLP (0x07)
3961#define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP (0x08)
3962#define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP (0x09)
3963#define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE (0x0A)
3964#define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE (0x0B)
3965#define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE (0x0C)
3966#define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE (0x0D)
3967#define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE (0x0E)
3968#define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE (0x0F)
3969#define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR (0x10)
3970#define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR (0x11)
3971#define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR (0x12)
3972
3973/*values for the CounterType field */
3974#define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING (0x00)
3975#define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING (0x01)
3976#define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE (0x02)
3977
3978/*values for the TimeUnits field */
3979#define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS (0x00)
3980#define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS (0x01)
3981#define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND (0x02)
3982#define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS (0x03)
3983
3984/*values for the ThresholdFlags field */
3985#define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY (0x0001)
3986
3987/*
3988 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
3989 *for NumLinkEvents at runtime before using LinkEventConfig[].
3990 */
3991
3992typedef struct _MPI26_CONFIG_PAGE_PCIELINK_3 {
3993 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3994 U8 Link; /*0x08 */
3995 U8 Reserved1; /*0x09 */
3996 U16 Reserved2; /*0x0A */
3997 U8 NumLinkEvents; /*0x0C */
3998 U8 Reserved3; /*0x0D */
3999 U16 Reserved4; /*0x0E */
4000 MPI26_PCIELINK3_LINK_EVENT_CONFIG
4001 LinkEventConfig[]; /*0x10 */
4002} MPI26_CONFIG_PAGE_PCIELINK_3, *PTR_MPI26_CONFIG_PAGE_PCIELINK_3,
4003 Mpi26PcieLinkPage3_t, *pMpi26PcieLinkPage3_t;
4004
4005#define MPI26_PCIELINK3_PAGEVERSION (0x00)
4006
4007
4008#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
4 *
5 *
6 * Name: mpi2_cnfg.h
7 * Title: MPI Configuration messages and pages
8 * Creation Date: November 10, 2006
9 *
10 * mpi2_cnfg.h Version: 02.00.47
11 *
12 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
13 * prefix are for use only on MPI v2.5 products, and must not be used
14 * with MPI v2.0 products. Unless otherwise noted, names beginning with
15 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
16 *
17 * Version History
18 * ---------------
19 *
20 * Date Version Description
21 * -------- -------- ------------------------------------------------------
22 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
23 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
24 * Added Manufacturing Page 11.
25 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
26 * define.
27 * 06-26-07 02.00.02 Adding generic structure for product-specific
28 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
29 * Rework of BIOS Page 2 configuration page.
30 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
31 * forms.
32 * Added configuration pages IOC Page 8 and Driver
33 * Persistent Mapping Page 0.
34 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
35 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
36 * RAID Physical Disk Pages 0 and 1, RAID Configuration
37 * Page 0).
38 * Added new value for AccessStatus field of SAS Device
39 * Page 0 (_SATA_NEEDS_INITIALIZATION).
40 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
41 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
42 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
43 * NVDATA.
44 * Modified IOC Page 7 to use masks and added field for
45 * SASBroadcastPrimitiveMasks.
46 * Added MPI2_CONFIG_PAGE_BIOS_4.
47 * Added MPI2_CONFIG_PAGE_LOG_0.
48 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
49 * Added SAS Device IDs.
50 * Updated Integrated RAID configuration pages including
51 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
52 * Page 0.
53 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
54 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
55 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
56 * Added missing MaxNumRoutedSasAddresses field to
57 * MPI2_CONFIG_PAGE_EXPANDER_0.
58 * Added SAS Port Page 0.
59 * Modified structure layout for
60 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
61 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
62 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
63 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
64 * to 0x000000FF.
65 * Added two new values for the Physical Disk Coercion Size
66 * bits in the Flags field of Manufacturing Page 4.
67 * Added product-specific Manufacturing pages 16 to 31.
68 * Modified Flags bits for controlling write cache on SATA
69 * drives in IO Unit Page 1.
70 * Added new bit to AdditionalControlFlags of SAS IO Unit
71 * Page 1 to control Invalid Topology Correction.
72 * Added additional defines for RAID Volume Page 0
73 * VolumeStatusFlags field.
74 * Modified meaning of RAID Volume Page 0 VolumeSettings
75 * define for auto-configure of hot-swap drives.
76 * Added SupportedPhysDisks field to RAID Volume Page 1 and
77 * added related defines.
78 * Added PhysDiskAttributes field (and related defines) to
79 * RAID Physical Disk Page 0.
80 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
81 * Added three new DiscoveryStatus bits for SAS IO Unit
82 * Page 0 and SAS Expander Page 0.
83 * Removed multiplexing information from SAS IO Unit pages.
84 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
85 * Removed Zone Address Resolved bit from PhyInfo and from
86 * Expander Page 0 Flags field.
87 * Added two new AccessStatus values to SAS Device Page 0
88 * for indicating routing problems. Added 3 reserved words
89 * to this page.
90 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
91 * Inserted missing reserved field into structure for IOC
92 * Page 6.
93 * Added more pending task bits to RAID Volume Page 0
94 * VolumeStatusFlags defines.
95 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
96 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
97 * and SAS Expander Page 0 to flag a downstream initiator
98 * when in simplified routing mode.
99 * Removed SATA Init Failure defines for DiscoveryStatus
100 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
101 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
102 * Added PortGroups, DmaGroup, and ControlGroup fields to
103 * SAS Device Page 0.
104 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
105 * Unit Page 6.
106 * Added expander reduced functionality data to SAS
107 * Expander Page 0.
108 * Added SAS PHY Page 2 and SAS PHY Page 3.
109 * 07-30-09 02.00.12 Added IO Unit Page 7.
110 * Added new device ids.
111 * Added SAS IO Unit Page 5.
112 * Added partial and slumber power management capable flags
113 * to SAS Device Page 0 Flags field.
114 * Added PhyInfo defines for power condition.
115 * Added Ethernet configuration pages.
116 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
117 * Added SAS PHY Page 4 structure and defines.
118 * 02-10-10 02.00.14 Modified the comments for the configuration page
119 * structures that contain an array of data. The host
120 * should use the "count" field in the page data (e.g. the
121 * NumPhys field) to determine the number of valid elements
122 * in the array.
123 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
124 * Added PowerManagementCapabilities to IO Unit Page 7.
125 * Added PortWidthModGroup field to
126 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
127 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
128 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
129 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
130 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
131 * define.
132 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
133 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
134 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing)
135 * defines.
136 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to
137 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
138 * the Pinout field.
139 * Added BoardTemperature and BoardTemperatureUnits fields
140 * to MPI2_CONFIG_PAGE_IO_UNIT_7.
141 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
142 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
143 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
144 * Added IO Unit Page 8, IO Unit Page 9,
145 * and IO Unit Page 10.
146 * Added SASNotifyPrimitiveMasks field to
147 * MPI2_CONFIG_PAGE_IOC_7.
148 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec).
149 * 05-25-11 02.00.20 Cleaned up a few comments.
150 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities
151 * for PCIe link as obsolete.
152 * Added SpinupFlags field containing a Disable Spin-up bit
153 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO
154 * Unit Page 4.
155 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT.
156 * Added UEFIVersion field to BIOS Page 1 and defined new
157 * BiosOptions bits.
158 * Incorporating additions for MPI v2.5.
159 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER.
160 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID.
161 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as
162 * obsolete for MPI v2.5 and later.
163 * Added some defines for 12G SAS speeds.
164 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK.
165 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to
166 * match the specification.
167 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for
168 * future use.
169 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for
170 * MPI2_CONFIG_PAGE_MAN_7.
171 * Added EnclosureLevel and ConnectorName fields to
172 * MPI2_CONFIG_PAGE_SAS_DEV_0.
173 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for
174 * MPI2_CONFIG_PAGE_SAS_DEV_0.
175 * Added EnclosureLevel field to
176 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
177 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for
178 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
179 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of
180 * MPI2_CONFIG_PAGE_BIOS_1.
181 * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and
182 * more defines for the BiosOptions field.
183 * 11-18-14 02.00.30 Updated copyright information.
184 * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG.
185 * Added AdapterOrderAux fields to BIOS Page 3.
186 * 03-16-15 02.00.31 Updated for MPI v2.6.
187 * Added Flags field to IO Unit Page 7.
188 * Added new SAS Phy Event codes
189 * 05-25-15 02.00.33 Added more defines for the BiosOptions field of
190 * MPI2_CONFIG_PAGE_BIOS_1.
191 * 08-25-15 02.00.34 Bumped Header Version.
192 * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4.
193 * 01-21-16 02.00.36 Added/modified MPI2_MFGPAGE_DEVID_SAS defines.
194 * Added Link field to PCIe Link Pages
195 * Added EnclosureLevel and ConnectorName to PCIe
196 * Device Page 0.
197 * Added define for PCIE IoUnit page 1 max rate shift.
198 * Added comment for reserved ExtPageTypes.
199 * Added SAS 4 22.5 gbs speed support.
200 * Added PCIe 4 16.0 GT/sec speec support.
201 * Removed AHCI support.
202 * Removed SOP support.
203 * Added NegotiatedLinkRate and NegotiatedPortWidth to
204 * PCIe device page 0.
205 * 04-10-16 02.00.37 Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines
206 * 07-01-16 02.00.38 Added Manufacturing page 7 Connector types.
207 * Changed declaration of ConnectorName in PCIe DevicePage0
208 * to match SAS DevicePage 0.
209 * Added SATADeviceWaitTime to IO Unit Page 11.
210 * Added MPI26_MFGPAGE_DEVID_SAS4008
211 * Added x16 PCIe width to IO Unit Page 7
212 * Added LINKFLAGS to control SRIS in PCIe IO Unit page 1
213 * phy data.
214 * Added InitStatus to PCIe IO Unit Page 1 header.
215 * 09-01-16 02.00.39 Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines.
216 * Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and
217 * MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats.
218 * 02-02-17 02.00.40 Added MPI2_MANPAGE7_SLOT_UNKNOWN.
219 * Added ChassisSlot field to SAS Enclosure Page 0.
220 * Added ChassisSlot Valid bit (bit 5) to the Flags field
221 * in SAS Enclosure Page 0.
222 * 06-13-17 02.00.41 Added MPI26_MFGPAGE_DEVID_SAS3816 and
223 * MPI26_MFGPAGE_DEVID_SAS3916 defines.
224 * Removed MPI26_MFGPAGE_DEVID_SAS4008 define.
225 * Added MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN define.
226 * Renamed PI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS to
227 * PI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN.
228 * Renamed MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS to
229 * MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK.
230 * 09-29-17 02.00.42 Added ControllerResetTO field to PCIe Device Page 2.
231 * Added NOIOB field to PCIe Device Page 2.
232 * Added MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN to
233 * the Capabilities field of PCIe Device Page 2.
234 * 07-22-18 02.00.43 Added defines for SAS3916 and SAS3816.
235 * Added WRiteCache defines to IO Unit Page 1.
236 * Added MaxEnclosureLevel to BIOS Page 1.
237 * Added OEMRD to SAS Enclosure Page 1.
238 * Added DMDReportPCIe to PCIe IO Unit Page 1.
239 * Added Flags field and flags for Retimers to
240 * PCIe Switch Page 1.
241 * 08-02-18 02.00.44 Added Slotx2, Slotx4 to ManPage 7.
242 * 08-15-18 02.00.45 Added ProductSpecific field at end of IOC Page 1
243 * 08-28-18 02.00.46 Added NVMs Write Cache flag to IOUnitPage1
244 * Added DMDReport Delay Time defines to
245 * PCIeIOUnitPage1
246 * --------------------------------------------------------------------------
247 * 08-02-18 02.00.44 Added Slotx2, Slotx4 to ManPage 7.
248 * 08-15-18 02.00.45 Added ProductSpecific field at end of IOC Page 1
249 * 08-28-18 02.00.46 Added NVMs Write Cache flag to IOUnitPage1
250 * Added DMDReport Delay Time defines to PCIeIOUnitPage1
251 * 12-17-18 02.00.47 Swap locations of Slotx2 and Slotx4 in ManPage 7.
252 * 08-01-19 02.00.49 Add MPI26_MANPAGE7_FLAG_X2_X4_SLOT_INFO_VALID
253 * Add MPI26_IOUNITPAGE1_NVME_WRCACHE_SHIFT
254 */
255
256#ifndef MPI2_CNFG_H
257#define MPI2_CNFG_H
258
259/*****************************************************************************
260* Configuration Page Header and defines
261*****************************************************************************/
262
263/*Config Page Header */
264typedef struct _MPI2_CONFIG_PAGE_HEADER {
265 U8 PageVersion; /*0x00 */
266 U8 PageLength; /*0x01 */
267 U8 PageNumber; /*0x02 */
268 U8 PageType; /*0x03 */
269} MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER,
270 Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t;
271
272typedef union _MPI2_CONFIG_PAGE_HEADER_UNION {
273 MPI2_CONFIG_PAGE_HEADER Struct;
274 U8 Bytes[4];
275 U16 Word16[2];
276 U32 Word32;
277} MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
278 Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion;
279
280/*Extended Config Page Header */
281typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER {
282 U8 PageVersion; /*0x00 */
283 U8 Reserved1; /*0x01 */
284 U8 PageNumber; /*0x02 */
285 U8 PageType; /*0x03 */
286 U16 ExtPageLength; /*0x04 */
287 U8 ExtPageType; /*0x06 */
288 U8 Reserved2; /*0x07 */
289} MPI2_CONFIG_EXTENDED_PAGE_HEADER,
290 *PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
291 Mpi2ConfigExtendedPageHeader_t,
292 *pMpi2ConfigExtendedPageHeader_t;
293
294typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION {
295 MPI2_CONFIG_PAGE_HEADER Struct;
296 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
297 U8 Bytes[8];
298 U16 Word16[4];
299 U32 Word32[2];
300} MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
301 *PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
302 Mpi2ConfigPageExtendedHeaderUnion,
303 *pMpi2ConfigPageExtendedHeaderUnion;
304
305
306/*PageType field values */
307#define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
308#define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
309#define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
310#define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
311
312#define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
313#define MPI2_CONFIG_PAGETYPE_IOC (0x01)
314#define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
315#define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
316#define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
317#define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
318#define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
319#define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
320
321#define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
322
323
324/*ExtPageType field values */
325#define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
326#define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
327#define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
328#define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
329#define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
330#define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
331#define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
332#define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
333#define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
334#define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
335#define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
336#define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT (0x1B)
337#define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH (0x1C)
338#define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE (0x1D)
339#define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK (0x1E)
340
341
342/*****************************************************************************
343* PageAddress defines
344*****************************************************************************/
345
346/*RAID Volume PageAddress format */
347#define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
348#define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
349#define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
350
351#define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
352
353
354/*RAID Physical Disk PageAddress format */
355#define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
356#define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
357#define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
358#define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
359
360#define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
361#define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
362
363
364/*SAS Expander PageAddress format */
365#define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
366#define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
367#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
368#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
369
370#define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
371#define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
372#define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
373
374
375/*SAS Device PageAddress format */
376#define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
377#define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
378#define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
379
380#define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
381
382
383/*SAS PHY PageAddress format */
384#define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
385#define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
386#define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
387
388#define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
389#define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
390
391
392/*SAS Port PageAddress format */
393#define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
394#define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
395#define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
396
397#define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
398
399
400/*SAS Enclosure PageAddress format */
401#define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
402#define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
403#define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
404
405#define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
406
407/*Enclosure PageAddress format */
408#define MPI26_ENCLOS_PGAD_FORM_MASK (0xF0000000)
409#define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
410#define MPI26_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
411
412#define MPI26_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
413
414/*RAID Configuration PageAddress format */
415#define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
416#define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
417#define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
418#define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
419
420#define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
421
422
423/*Driver Persistent Mapping PageAddress format */
424#define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
425#define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
426
427#define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
428#define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
429#define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
430
431
432/*Ethernet PageAddress format */
433#define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
434#define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
435
436#define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
437
438
439/*PCIe Switch PageAddress format */
440#define MPI26_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000)
441#define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
442#define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM (0x10000000)
443#define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL (0x20000000)
444
445#define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF)
446#define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000)
447#define MPI26_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16)
448
449
450/*PCIe Device PageAddress format */
451#define MPI26_PCIE_DEVICE_PGAD_FORM_MASK (0xF0000000)
452#define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
453#define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE (0x20000000)
454
455#define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
456
457/*PCIe Link PageAddress format */
458#define MPI26_PCIE_LINK_PGAD_FORM_MASK (0xF0000000)
459#define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000)
460#define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000)
461
462#define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK (0x000000FF)
463
464
465
466/****************************************************************************
467* Configuration messages
468****************************************************************************/
469
470/*Configuration Request Message */
471typedef struct _MPI2_CONFIG_REQUEST {
472 U8 Action; /*0x00 */
473 U8 SGLFlags; /*0x01 */
474 U8 ChainOffset; /*0x02 */
475 U8 Function; /*0x03 */
476 U16 ExtPageLength; /*0x04 */
477 U8 ExtPageType; /*0x06 */
478 U8 MsgFlags; /*0x07 */
479 U8 VP_ID; /*0x08 */
480 U8 VF_ID; /*0x09 */
481 U16 Reserved1; /*0x0A */
482 U8 Reserved2; /*0x0C */
483 U8 ProxyVF_ID; /*0x0D */
484 U16 Reserved4; /*0x0E */
485 U32 Reserved3; /*0x10 */
486 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */
487 U32 PageAddress; /*0x18 */
488 MPI2_SGE_IO_UNION PageBufferSGE; /*0x1C */
489} MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST,
490 Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t;
491
492/*values for the Action field */
493#define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
494#define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
495#define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
496#define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
497#define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
498#define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
499#define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
500#define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
501
502/*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
503
504
505/*Config Reply Message */
506typedef struct _MPI2_CONFIG_REPLY {
507 U8 Action; /*0x00 */
508 U8 SGLFlags; /*0x01 */
509 U8 MsgLength; /*0x02 */
510 U8 Function; /*0x03 */
511 U16 ExtPageLength; /*0x04 */
512 U8 ExtPageType; /*0x06 */
513 U8 MsgFlags; /*0x07 */
514 U8 VP_ID; /*0x08 */
515 U8 VF_ID; /*0x09 */
516 U16 Reserved1; /*0x0A */
517 U16 Reserved2; /*0x0C */
518 U16 IOCStatus; /*0x0E */
519 U32 IOCLogInfo; /*0x10 */
520 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */
521} MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY,
522 Mpi2ConfigReply_t, *pMpi2ConfigReply_t;
523
524
525
526/*****************************************************************************
527*
528* C o n f i g u r a t i o n P a g e s
529*
530*****************************************************************************/
531
532/****************************************************************************
533* Manufacturing Config pages
534****************************************************************************/
535
536#define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
537#define MPI2_MFGPAGE_VENDORID_ATTO (0x117C)
538
539/*MPI v2.0 SAS products */
540#define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
541#define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
542#define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
543#define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
544#define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
545#define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
546#define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
547
548#define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
549
550#define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
551#define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
552#define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
553#define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
554#define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
555#define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
556#define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
557#define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
558#define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
559#define MPI2_MFGPAGE_DEVID_SWITCH_MPI_EP (0x02B0)
560#define MPI2_MFGPAGE_DEVID_SWITCH_MPI_EP_1 (0x02B1)
561
562/*MPI v2.5 SAS products */
563#define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096)
564#define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097)
565#define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090)
566#define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091)
567#define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094)
568#define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095)
569
570/* MPI v2.6 SAS Products */
571#define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9)
572#define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4)
573#define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5)
574#define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6)
575#define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7)
576#define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8)
577#define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0)
578#define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1)
579#define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2)
580#define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3)
581
582#define MPI26_MFGPAGE_DEVID_SAS3516 (0x00AA)
583#define MPI26_MFGPAGE_DEVID_SAS3516_1 (0x00AB)
584#define MPI26_MFGPAGE_DEVID_SAS3416 (0x00AC)
585#define MPI26_MFGPAGE_DEVID_SAS3508 (0x00AD)
586#define MPI26_MFGPAGE_DEVID_SAS3508_1 (0x00AE)
587#define MPI26_MFGPAGE_DEVID_SAS3408 (0x00AF)
588#define MPI26_MFGPAGE_DEVID_SAS3716 (0x00D0)
589#define MPI26_MFGPAGE_DEVID_SAS3616 (0x00D1)
590#define MPI26_MFGPAGE_DEVID_SAS3708 (0x00D2)
591
592#define MPI26_MFGPAGE_DEVID_SEC_MASK_3916 (0x0003)
593#define MPI26_MFGPAGE_DEVID_INVALID0_3916 (0x00E0)
594#define MPI26_MFGPAGE_DEVID_CFG_SEC_3916 (0x00E1)
595#define MPI26_MFGPAGE_DEVID_HARD_SEC_3916 (0x00E2)
596#define MPI26_MFGPAGE_DEVID_INVALID1_3916 (0x00E3)
597
598#define MPI26_MFGPAGE_DEVID_SEC_MASK_3816 (0x0003)
599#define MPI26_MFGPAGE_DEVID_INVALID0_3816 (0x00E4)
600#define MPI26_MFGPAGE_DEVID_CFG_SEC_3816 (0x00E5)
601#define MPI26_MFGPAGE_DEVID_HARD_SEC_3816 (0x00E6)
602#define MPI26_MFGPAGE_DEVID_INVALID1_3816 (0x00E7)
603
604
605/*Manufacturing Page 0 */
606
607typedef struct _MPI2_CONFIG_PAGE_MAN_0 {
608 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
609 U8 ChipName[16]; /*0x04 */
610 U8 ChipRevision[8]; /*0x14 */
611 U8 BoardName[16]; /*0x1C */
612 U8 BoardAssembly[16]; /*0x2C */
613 U8 BoardTracerNumber[16]; /*0x3C */
614} MPI2_CONFIG_PAGE_MAN_0,
615 *PTR_MPI2_CONFIG_PAGE_MAN_0,
616 Mpi2ManufacturingPage0_t,
617 *pMpi2ManufacturingPage0_t;
618
619#define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
620
621
622/*Manufacturing Page 1 */
623
624typedef struct _MPI2_CONFIG_PAGE_MAN_1 {
625 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
626 U8 VPD[256]; /*0x04 */
627} MPI2_CONFIG_PAGE_MAN_1,
628 *PTR_MPI2_CONFIG_PAGE_MAN_1,
629 Mpi2ManufacturingPage1_t,
630 *pMpi2ManufacturingPage1_t;
631
632#define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
633
634
635typedef struct _MPI2_CHIP_REVISION_ID {
636 U16 DeviceID; /*0x00 */
637 U8 PCIRevisionID; /*0x02 */
638 U8 Reserved; /*0x03 */
639} MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID,
640 Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t;
641
642
643/*Manufacturing Page 2 */
644
645/*
646 *Host code (drivers, BIOS, utilities, etc.) should check Header.PageLength at
647 *runtime before using HwSettings[].
648 */
649
650typedef struct _MPI2_CONFIG_PAGE_MAN_2 {
651 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
652 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */
653 U32 HwSettings[]; /*0x08 */
654} MPI2_CONFIG_PAGE_MAN_2,
655 *PTR_MPI2_CONFIG_PAGE_MAN_2,
656 Mpi2ManufacturingPage2_t,
657 *pMpi2ManufacturingPage2_t;
658
659#define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
660
661
662/*Manufacturing Page 3 */
663
664/*
665 *Host code (drivers, BIOS, utilities, etc.) should check Header.PageLength at
666 *runtime before using Info[].
667 */
668
669typedef struct _MPI2_CONFIG_PAGE_MAN_3 {
670 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
671 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */
672 U32 Info[]; /*0x08 */
673} MPI2_CONFIG_PAGE_MAN_3,
674 *PTR_MPI2_CONFIG_PAGE_MAN_3,
675 Mpi2ManufacturingPage3_t,
676 *pMpi2ManufacturingPage3_t;
677
678#define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
679
680
681/*Manufacturing Page 4 */
682
683typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS {
684 U8 PowerSaveFlags; /*0x00 */
685 U8 InternalOperationsSleepTime; /*0x01 */
686 U8 InternalOperationsRunTime; /*0x02 */
687 U8 HostIdleTime; /*0x03 */
688} MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
689 *PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
690 Mpi2ManPage4PwrSaveSettings_t,
691 *pMpi2ManPage4PwrSaveSettings_t;
692
693/*defines for the PowerSaveFlags field */
694#define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
695#define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
696#define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
697#define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
698
699typedef struct _MPI2_CONFIG_PAGE_MAN_4 {
700 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
701 U32 Reserved1; /*0x04 */
702 U32 Flags; /*0x08 */
703 U8 InquirySize; /*0x0C */
704 U8 Reserved2; /*0x0D */
705 U16 Reserved3; /*0x0E */
706 U8 InquiryData[56]; /*0x10 */
707 U32 RAID0VolumeSettings; /*0x48 */
708 U32 RAID1EVolumeSettings; /*0x4C */
709 U32 RAID1VolumeSettings; /*0x50 */
710 U32 RAID10VolumeSettings; /*0x54 */
711 U32 Reserved4; /*0x58 */
712 U32 Reserved5; /*0x5C */
713 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /*0x60 */
714 U8 MaxOCEDisks; /*0x64 */
715 U8 ResyncRate; /*0x65 */
716 U16 DataScrubDuration; /*0x66 */
717 U8 MaxHotSpares; /*0x68 */
718 U8 MaxPhysDisksPerVol; /*0x69 */
719 U8 MaxPhysDisks; /*0x6A */
720 U8 MaxVolumes; /*0x6B */
721} MPI2_CONFIG_PAGE_MAN_4,
722 *PTR_MPI2_CONFIG_PAGE_MAN_4,
723 Mpi2ManufacturingPage4_t,
724 *pMpi2ManufacturingPage4_t;
725
726#define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
727
728/*Manufacturing Page 4 Flags field */
729#define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
730#define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
731
732#define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
733#define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
734#define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
735
736#define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
737#define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
738#define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
739#define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
740#define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
741
742#define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
743#define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
744#define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
745#define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
746
747#define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
748#define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
749#define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
750#define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
751#define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
752#define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
753#define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
754#define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
755
756
757/*Manufacturing Page 5 */
758
759/*
760 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
761 *for NumPhys at runtime before using Phy[].
762 */
763
764typedef struct _MPI2_MANUFACTURING5_ENTRY {
765 U64 WWID; /*0x00 */
766 U64 DeviceName; /*0x08 */
767} MPI2_MANUFACTURING5_ENTRY,
768 *PTR_MPI2_MANUFACTURING5_ENTRY,
769 Mpi2Manufacturing5Entry_t,
770 *pMpi2Manufacturing5Entry_t;
771
772typedef struct _MPI2_CONFIG_PAGE_MAN_5 {
773 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
774 U8 NumPhys; /*0x04 */
775 U8 Reserved1; /*0x05 */
776 U16 Reserved2; /*0x06 */
777 U32 Reserved3; /*0x08 */
778 U32 Reserved4; /*0x0C */
779 MPI2_MANUFACTURING5_ENTRY Phy[]; /*0x10 */
780} MPI2_CONFIG_PAGE_MAN_5,
781 *PTR_MPI2_CONFIG_PAGE_MAN_5,
782 Mpi2ManufacturingPage5_t,
783 *pMpi2ManufacturingPage5_t;
784
785#define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
786
787
788/*Manufacturing Page 6 */
789
790typedef struct _MPI2_CONFIG_PAGE_MAN_6 {
791 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
792 U32 ProductSpecificInfo;/*0x04 */
793} MPI2_CONFIG_PAGE_MAN_6,
794 *PTR_MPI2_CONFIG_PAGE_MAN_6,
795 Mpi2ManufacturingPage6_t,
796 *pMpi2ManufacturingPage6_t;
797
798#define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
799
800
801/*Manufacturing Page 7 */
802
803typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO {
804 U32 Pinout; /*0x00 */
805 U8 Connector[16]; /*0x04 */
806 U8 Location; /*0x14 */
807 U8 ReceptacleID; /*0x15 */
808 U16 Slot; /*0x16 */
809 U16 Slotx2; /*0x18 */
810 U16 Slotx4; /*0x1A */
811} MPI2_MANPAGE7_CONNECTOR_INFO,
812 *PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
813 Mpi2ManPage7ConnectorInfo_t,
814 *pMpi2ManPage7ConnectorInfo_t;
815
816/*defines for the Pinout field */
817#define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00)
818#define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8)
819
820#define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF)
821#define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00)
822#define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01)
823#define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02)
824#define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03)
825#define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04)
826#define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05)
827#define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06)
828#define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07)
829#define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08)
830#define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09)
831#define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A)
832#define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B)
833#define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C)
834#define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D)
835#define MPI2_MANPAGE7_PINOUT_SFF_8088_A (0x0E)
836#define MPI2_MANPAGE7_PINOUT_SFF_8643_16i (0x0F)
837#define MPI2_MANPAGE7_PINOUT_SFF_8654_4i (0x10)
838#define MPI2_MANPAGE7_PINOUT_SFF_8654_8i (0x11)
839#define MPI2_MANPAGE7_PINOUT_SFF_8611_4i (0x12)
840#define MPI2_MANPAGE7_PINOUT_SFF_8611_8i (0x13)
841
842/*defines for the Location field */
843#define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
844#define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
845#define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
846#define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
847#define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
848#define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
849#define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
850
851/*defines for the Slot field */
852#define MPI2_MANPAGE7_SLOT_UNKNOWN (0xFFFF)
853
854/*
855 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
856 *for NumPhys at runtime before using ConnectorInfo[].
857 */
858
859typedef struct _MPI2_CONFIG_PAGE_MAN_7 {
860 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
861 U32 Reserved1; /*0x04 */
862 U32 Reserved2; /*0x08 */
863 U32 Flags; /*0x0C */
864 U8 EnclosureName[16]; /*0x10 */
865 U8 NumPhys; /*0x20 */
866 U8 Reserved3; /*0x21 */
867 U16 Reserved4; /*0x22 */
868 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[]; /*0x24 */
869} MPI2_CONFIG_PAGE_MAN_7,
870 *PTR_MPI2_CONFIG_PAGE_MAN_7,
871 Mpi2ManufacturingPage7_t,
872 *pMpi2ManufacturingPage7_t;
873
874#define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
875
876/*defines for the Flags field */
877#define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008)
878#define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002)
879#define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
880
881#define MPI26_MANPAGE7_FLAG_CONN_LANE_USE_PINOUT (0x00000020)
882#define MPI26_MANPAGE7_FLAG_X2_X4_SLOT_INFO_VALID (0x00000010)
883
884/*
885 *Generic structure to use for product-specific manufacturing pages
886 *(currently Manufacturing Page 8 through Manufacturing Page 31).
887 */
888
889typedef struct _MPI2_CONFIG_PAGE_MAN_PS {
890 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
891 U32 ProductSpecificInfo;/*0x04 */
892} MPI2_CONFIG_PAGE_MAN_PS,
893 *PTR_MPI2_CONFIG_PAGE_MAN_PS,
894 Mpi2ManufacturingPagePS_t,
895 *pMpi2ManufacturingPagePS_t;
896
897#define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
898#define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
899#define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
900#define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
901#define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
902#define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
903#define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
904#define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
905#define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
906#define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
907#define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
908#define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
909#define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
910#define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
911#define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
912#define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
913#define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
914#define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
915#define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
916#define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
917#define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
918#define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
919#define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
920#define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
921
922
923/****************************************************************************
924* IO Unit Config Pages
925****************************************************************************/
926
927/*IO Unit Page 0 */
928
929typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 {
930 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
931 U64 UniqueValue; /*0x04 */
932 MPI2_VERSION_UNION NvdataVersionDefault; /*0x08 */
933 MPI2_VERSION_UNION NvdataVersionPersistent; /*0x0A */
934} MPI2_CONFIG_PAGE_IO_UNIT_0,
935 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
936 Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t;
937
938#define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
939
940
941/*IO Unit Page 1 */
942
943typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 {
944 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
945 U32 Flags; /*0x04 */
946} MPI2_CONFIG_PAGE_IO_UNIT_1,
947 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
948 Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t;
949
950#define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
951
952/* IO Unit Page 1 Flags defines */
953#define MPI26_IOUNITPAGE1_NVME_WRCACHE_MASK (0x00030000)
954#define MPI26_IOUNITPAGE1_NVME_WRCACHE_SHIFT (16)
955#define MPI26_IOUNITPAGE1_NVME_WRCACHE_NO_CHANGE (0x00000000)
956#define MPI26_IOUNITPAGE1_NVME_WRCACHE_ENABLE (0x00010000)
957#define MPI26_IOUNITPAGE1_NVME_WRCACHE_DISABLE (0x00020000)
958#define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000)
959#define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000)
960#define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000)
961#define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
962#define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
963#define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9)
964#define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
965#define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
966#define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
967#define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
968#define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
969#define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
970#define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
971
972
973/*IO Unit Page 3 */
974
975/*
976 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
977 *36 and check the value returned for GPIOCount at runtime.
978 */
979#ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
980#define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (36)
981#endif
982
983typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 {
984 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
985 U8 GPIOCount; /*0x04 */
986 U8 Reserved1; /*0x05 */
987 U16 Reserved2; /*0x06 */
988 U16
989 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */
990} MPI2_CONFIG_PAGE_IO_UNIT_3,
991 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
992 Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t;
993
994#define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
995
996/*defines for IO Unit Page 3 GPIOVal field */
997#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
998#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
999#define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
1000#define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
1001
1002
1003/*IO Unit Page 5 */
1004
1005/*
1006 *Upper layer code (drivers, utilities, etc.) should check the value returned
1007 *for NumDmaEngines at runtime before using DmaEngineCapabilities[].
1008 */
1009
1010typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
1011 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1012 U64
1013 RaidAcceleratorBufferBaseAddress; /*0x04 */
1014 U64
1015 RaidAcceleratorBufferSize; /*0x0C */
1016 U64
1017 RaidAcceleratorControlBaseAddress; /*0x14 */
1018 U8 RAControlSize; /*0x1C */
1019 U8 NumDmaEngines; /*0x1D */
1020 U8 RAMinControlSize; /*0x1E */
1021 U8 RAMaxControlSize; /*0x1F */
1022 U32 Reserved1; /*0x20 */
1023 U32 Reserved2; /*0x24 */
1024 U32 Reserved3; /*0x28 */
1025 U32
1026 DmaEngineCapabilities[]; /*0x2C */
1027} MPI2_CONFIG_PAGE_IO_UNIT_5,
1028 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
1029 Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t;
1030
1031#define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
1032
1033/*defines for IO Unit Page 5 DmaEngineCapabilities field */
1034#define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000)
1035#define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
1036
1037#define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
1038#define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
1039#define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
1040#define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
1041
1042
1043/*IO Unit Page 6 */
1044
1045typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
1046 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1047 U16 Flags; /*0x04 */
1048 U8 RAHostControlSize; /*0x06 */
1049 U8 Reserved0; /*0x07 */
1050 U64
1051 RaidAcceleratorHostControlBaseAddress; /*0x08 */
1052 U32 Reserved1; /*0x10 */
1053 U32 Reserved2; /*0x14 */
1054 U32 Reserved3; /*0x18 */
1055} MPI2_CONFIG_PAGE_IO_UNIT_6,
1056 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
1057 Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t;
1058
1059#define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
1060
1061/*defines for IO Unit Page 6 Flags field */
1062#define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
1063
1064
1065/*IO Unit Page 7 */
1066
1067typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
1068 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1069 U8 CurrentPowerMode; /*0x04 */
1070 U8 PreviousPowerMode; /*0x05 */
1071 U8 PCIeWidth; /*0x06 */
1072 U8 PCIeSpeed; /*0x07 */
1073 U32 ProcessorState; /*0x08 */
1074 U32
1075 PowerManagementCapabilities; /*0x0C */
1076 U16 IOCTemperature; /*0x10 */
1077 U8
1078 IOCTemperatureUnits; /*0x12 */
1079 U8 IOCSpeed; /*0x13 */
1080 U16 BoardTemperature; /*0x14 */
1081 U8
1082 BoardTemperatureUnits; /*0x16 */
1083 U8 Reserved3; /*0x17 */
1084 U32 BoardPowerRequirement; /*0x18 */
1085 U32 PCISlotPowerAllocation; /*0x1C */
1086/* reserved prior to MPI v2.6 */
1087 U8 Flags; /* 0x20 */
1088 U8 Reserved6; /* 0x21 */
1089 U16 Reserved7; /* 0x22 */
1090 U32 Reserved8; /* 0x24 */
1091} MPI2_CONFIG_PAGE_IO_UNIT_7,
1092 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
1093 Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t;
1094
1095#define MPI2_IOUNITPAGE7_PAGEVERSION (0x05)
1096
1097/*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */
1098#define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0)
1099#define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00)
1100#define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40)
1101#define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80)
1102#define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0)
1103
1104#define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07)
1105#define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00)
1106#define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01)
1107#define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04)
1108#define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05)
1109#define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06)
1110
1111
1112/*defines for IO Unit Page 7 PCIeWidth field */
1113#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
1114#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
1115#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
1116#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
1117#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16 (0x10)
1118
1119/*defines for IO Unit Page 7 PCIeSpeed field */
1120#define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
1121#define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
1122#define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
1123#define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS (0x03)
1124
1125/*defines for IO Unit Page 7 ProcessorState field */
1126#define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
1127#define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
1128
1129#define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
1130#define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
1131#define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
1132
1133/*defines for IO Unit Page 7 PowerManagementCapabilities field */
1134#define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000)
1135#define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000)
1136#define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000)
1137#define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000)
1138#define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000)
1139#define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000)
1140#define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000)
1141#define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000)
1142#define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000)
1143#define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400)
1144#define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200)
1145#define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100)
1146#define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040)
1147#define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020)
1148#define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010)
1149#define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008)
1150#define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004)
1151#define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002)
1152#define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001)
1153
1154/*obsolete names for the PowerManagementCapabilities bits (above) */
1155#define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
1156#define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
1157#define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
1158#define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /*obsolete */
1159#define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /*obsolete */
1160
1161
1162/*defines for IO Unit Page 7 IOCTemperatureUnits field */
1163#define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
1164#define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
1165#define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
1166
1167/*defines for IO Unit Page 7 IOCSpeed field */
1168#define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
1169#define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
1170#define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
1171#define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
1172
1173/*defines for IO Unit Page 7 BoardTemperatureUnits field */
1174#define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
1175#define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
1176#define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
1177
1178/* defines for IO Unit Page 7 Flags field */
1179#define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC (0x01)
1180
1181/*IO Unit Page 8 */
1182
1183#define MPI2_IOUNIT8_NUM_THRESHOLDS (4)
1184
1185typedef struct _MPI2_IOUNIT8_SENSOR {
1186 U16 Flags; /*0x00 */
1187 U16 Reserved1; /*0x02 */
1188 U16
1189 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */
1190 U32 Reserved2; /*0x0C */
1191 U32 Reserved3; /*0x10 */
1192 U32 Reserved4; /*0x14 */
1193} MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR,
1194 Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t;
1195
1196/*defines for IO Unit Page 8 Sensor Flags field */
1197#define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008)
1198#define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004)
1199#define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002)
1200#define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001)
1201
1202/*
1203 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
1204 *for NumSensors at runtime before using Sensor[].
1205 */
1206
1207typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 {
1208 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1209 U32 Reserved1; /*0x04 */
1210 U32 Reserved2; /*0x08 */
1211 U8 NumSensors; /*0x0C */
1212 U8 PollingInterval; /*0x0D */
1213 U16 Reserved3; /*0x0E */
1214 MPI2_IOUNIT8_SENSOR Sensor[]; /*0x10 */
1215} MPI2_CONFIG_PAGE_IO_UNIT_8,
1216 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
1217 Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t;
1218
1219#define MPI2_IOUNITPAGE8_PAGEVERSION (0x00)
1220
1221
1222/*IO Unit Page 9 */
1223
1224typedef struct _MPI2_IOUNIT9_SENSOR {
1225 U16 CurrentTemperature; /*0x00 */
1226 U16 Reserved1; /*0x02 */
1227 U8 Flags; /*0x04 */
1228 U8 Reserved2; /*0x05 */
1229 U16 Reserved3; /*0x06 */
1230 U32 Reserved4; /*0x08 */
1231 U32 Reserved5; /*0x0C */
1232} MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR,
1233 Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t;
1234
1235/*defines for IO Unit Page 9 Sensor Flags field */
1236#define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01)
1237
1238/*
1239 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
1240 *for NumSensors at runtime before using Sensor[].
1241 */
1242
1243typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 {
1244 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1245 U32 Reserved1; /*0x04 */
1246 U32 Reserved2; /*0x08 */
1247 U8 NumSensors; /*0x0C */
1248 U8 Reserved4; /*0x0D */
1249 U16 Reserved3; /*0x0E */
1250 MPI2_IOUNIT9_SENSOR Sensor[]; /*0x10 */
1251} MPI2_CONFIG_PAGE_IO_UNIT_9,
1252 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1253 Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t;
1254
1255#define MPI2_IOUNITPAGE9_PAGEVERSION (0x00)
1256
1257
1258/*IO Unit Page 10 */
1259
1260typedef struct _MPI2_IOUNIT10_FUNCTION {
1261 U8 CreditPercent; /*0x00 */
1262 U8 Reserved1; /*0x01 */
1263 U16 Reserved2; /*0x02 */
1264} MPI2_IOUNIT10_FUNCTION,
1265 *PTR_MPI2_IOUNIT10_FUNCTION,
1266 Mpi2IOUnit10Function_t,
1267 *pMpi2IOUnit10Function_t;
1268
1269/*
1270 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
1271 *for NumFunctions at runtime before using Function[].
1272 */
1273
1274typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 {
1275 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1276 U8 NumFunctions; /*0x04 */
1277 U8 Reserved1; /*0x05 */
1278 U16 Reserved2; /*0x06 */
1279 U32 Reserved3; /*0x08 */
1280 U32 Reserved4; /*0x0C */
1281 MPI2_IOUNIT10_FUNCTION Function[]; /*0x10 */
1282} MPI2_CONFIG_PAGE_IO_UNIT_10,
1283 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1284 Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t;
1285
1286#define MPI2_IOUNITPAGE10_PAGEVERSION (0x01)
1287
1288
1289/* IO Unit Page 11 (for MPI v2.6 and later) */
1290
1291typedef struct _MPI26_IOUNIT11_SPINUP_GROUP {
1292 U8 MaxTargetSpinup; /* 0x00 */
1293 U8 SpinupDelay; /* 0x01 */
1294 U8 SpinupFlags; /* 0x02 */
1295 U8 Reserved1; /* 0x03 */
1296} MPI26_IOUNIT11_SPINUP_GROUP,
1297 *PTR_MPI26_IOUNIT11_SPINUP_GROUP,
1298 Mpi26IOUnit11SpinupGroup_t,
1299 *pMpi26IOUnit11SpinupGroup_t;
1300
1301/* defines for IO Unit Page 11 SpinupFlags */
1302#define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01)
1303
1304
1305/*
1306 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1307 * four and check the value returned for NumPhys at runtime.
1308 */
1309#ifndef MPI26_IOUNITPAGE11_PHY_MAX
1310#define MPI26_IOUNITPAGE11_PHY_MAX (4)
1311#endif
1312
1313typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 {
1314 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1315 U32 Reserved1; /*0x04 */
1316 MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /*0x08 */
1317 U32 Reserved2; /*0x18 */
1318 U32 Reserved3; /*0x1C */
1319 U32 Reserved4; /*0x20 */
1320 U8 BootDeviceWaitTime; /*0x24 */
1321 U8 Reserved5; /*0x25 */
1322 U16 Reserved6; /*0x26 */
1323 U8 NumPhys; /*0x28 */
1324 U8 PEInitialSpinupDelay; /*0x29 */
1325 U8 PEReplyDelay; /*0x2A */
1326 U8 Flags; /*0x2B */
1327 U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/*0x2C */
1328} MPI26_CONFIG_PAGE_IO_UNIT_11,
1329 *PTR_MPI26_CONFIG_PAGE_IO_UNIT_11,
1330 Mpi26IOUnitPage11_t,
1331 *pMpi26IOUnitPage11_t;
1332
1333#define MPI26_IOUNITPAGE11_PAGEVERSION (0x00)
1334
1335/* defines for Flags field */
1336#define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01)
1337
1338/* defines for PHY field */
1339#define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03)
1340
1341
1342
1343
1344
1345
1346/****************************************************************************
1347* IOC Config Pages
1348****************************************************************************/
1349
1350/*IOC Page 0 */
1351
1352typedef struct _MPI2_CONFIG_PAGE_IOC_0 {
1353 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1354 U32 Reserved1; /*0x04 */
1355 U32 Reserved2; /*0x08 */
1356 U16 VendorID; /*0x0C */
1357 U16 DeviceID; /*0x0E */
1358 U8 RevisionID; /*0x10 */
1359 U8 Reserved3; /*0x11 */
1360 U16 Reserved4; /*0x12 */
1361 U32 ClassCode; /*0x14 */
1362 U16 SubsystemVendorID; /*0x18 */
1363 U16 SubsystemID; /*0x1A */
1364} MPI2_CONFIG_PAGE_IOC_0,
1365 *PTR_MPI2_CONFIG_PAGE_IOC_0,
1366 Mpi2IOCPage0_t, *pMpi2IOCPage0_t;
1367
1368#define MPI2_IOCPAGE0_PAGEVERSION (0x02)
1369
1370
1371/*IOC Page 1 */
1372
1373typedef struct _MPI2_CONFIG_PAGE_IOC_1 {
1374 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1375 U32 Flags; /*0x04 */
1376 U32 CoalescingTimeout; /*0x08 */
1377 U8 CoalescingDepth; /*0x0C */
1378 U8 PCISlotNum; /*0x0D */
1379 U8 PCIBusNum; /*0x0E */
1380 U8 PCIDomainSegment; /*0x0F */
1381 U32 Reserved1; /*0x10 */
1382 U32 ProductSpecific; /* 0x14 */
1383} MPI2_CONFIG_PAGE_IOC_1,
1384 *PTR_MPI2_CONFIG_PAGE_IOC_1,
1385 Mpi2IOCPage1_t, *pMpi2IOCPage1_t;
1386
1387#define MPI2_IOCPAGE1_PAGEVERSION (0x05)
1388
1389/*defines for IOC Page 1 Flags field */
1390#define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
1391
1392#define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
1393#define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
1394#define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
1395
1396/*IOC Page 6 */
1397
1398typedef struct _MPI2_CONFIG_PAGE_IOC_6 {
1399 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1400 U32
1401 CapabilitiesFlags; /*0x04 */
1402 U8 MaxDrivesRAID0; /*0x08 */
1403 U8 MaxDrivesRAID1; /*0x09 */
1404 U8
1405 MaxDrivesRAID1E; /*0x0A */
1406 U8
1407 MaxDrivesRAID10; /*0x0B */
1408 U8 MinDrivesRAID0; /*0x0C */
1409 U8 MinDrivesRAID1; /*0x0D */
1410 U8
1411 MinDrivesRAID1E; /*0x0E */
1412 U8
1413 MinDrivesRAID10; /*0x0F */
1414 U32 Reserved1; /*0x10 */
1415 U8
1416 MaxGlobalHotSpares; /*0x14 */
1417 U8 MaxPhysDisks; /*0x15 */
1418 U8 MaxVolumes; /*0x16 */
1419 U8 MaxConfigs; /*0x17 */
1420 U8 MaxOCEDisks; /*0x18 */
1421 U8 Reserved2; /*0x19 */
1422 U16 Reserved3; /*0x1A */
1423 U32
1424 SupportedStripeSizeMapRAID0; /*0x1C */
1425 U32
1426 SupportedStripeSizeMapRAID1E; /*0x20 */
1427 U32
1428 SupportedStripeSizeMapRAID10; /*0x24 */
1429 U32 Reserved4; /*0x28 */
1430 U32 Reserved5; /*0x2C */
1431 U16
1432 DefaultMetadataSize; /*0x30 */
1433 U16 Reserved6; /*0x32 */
1434 U16
1435 MaxBadBlockTableEntries; /*0x34 */
1436 U16 Reserved7; /*0x36 */
1437 U32
1438 IRNvsramVersion; /*0x38 */
1439} MPI2_CONFIG_PAGE_IOC_6,
1440 *PTR_MPI2_CONFIG_PAGE_IOC_6,
1441 Mpi2IOCPage6_t, *pMpi2IOCPage6_t;
1442
1443#define MPI2_IOCPAGE6_PAGEVERSION (0x05)
1444
1445/*defines for IOC Page 6 CapabilitiesFlags */
1446#define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020)
1447#define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
1448#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
1449#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
1450#define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
1451#define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1452
1453
1454/*IOC Page 7 */
1455
1456#define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
1457
1458typedef struct _MPI2_CONFIG_PAGE_IOC_7 {
1459 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1460 U32 Reserved1; /*0x04 */
1461 U32
1462 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */
1463 U16 SASBroadcastPrimitiveMasks; /*0x18 */
1464 U16 SASNotifyPrimitiveMasks; /*0x1A */
1465 U32 Reserved3; /*0x1C */
1466} MPI2_CONFIG_PAGE_IOC_7,
1467 *PTR_MPI2_CONFIG_PAGE_IOC_7,
1468 Mpi2IOCPage7_t, *pMpi2IOCPage7_t;
1469
1470#define MPI2_IOCPAGE7_PAGEVERSION (0x02)
1471
1472
1473/*IOC Page 8 */
1474
1475typedef struct _MPI2_CONFIG_PAGE_IOC_8 {
1476 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1477 U8 NumDevsPerEnclosure; /*0x04 */
1478 U8 Reserved1; /*0x05 */
1479 U16 Reserved2; /*0x06 */
1480 U16 MaxPersistentEntries; /*0x08 */
1481 U16 MaxNumPhysicalMappedIDs; /*0x0A */
1482 U16 Flags; /*0x0C */
1483 U16 Reserved3; /*0x0E */
1484 U16 IRVolumeMappingFlags; /*0x10 */
1485 U16 Reserved4; /*0x12 */
1486 U32 Reserved5; /*0x14 */
1487} MPI2_CONFIG_PAGE_IOC_8,
1488 *PTR_MPI2_CONFIG_PAGE_IOC_8,
1489 Mpi2IOCPage8_t, *pMpi2IOCPage8_t;
1490
1491#define MPI2_IOCPAGE8_PAGEVERSION (0x00)
1492
1493/*defines for IOC Page 8 Flags field */
1494#define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1495#define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1496
1497#define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1498#define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1499#define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1500
1501#define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1502#define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1503
1504/*defines for IOC Page 8 IRVolumeMappingFlags */
1505#define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1506#define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1507#define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1508
1509
1510/****************************************************************************
1511* BIOS Config Pages
1512****************************************************************************/
1513
1514/*BIOS Page 1 */
1515
1516typedef struct _MPI2_CONFIG_PAGE_BIOS_1 {
1517 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1518 U32 BiosOptions; /*0x04 */
1519 U32 IOCSettings; /*0x08 */
1520 U8 SSUTimeout; /*0x0C */
1521 U8 MaxEnclosureLevel; /*0x0D */
1522 U16 Reserved2; /*0x0E */
1523 U32 DeviceSettings; /*0x10 */
1524 U16 NumberOfDevices; /*0x14 */
1525 U16 UEFIVersion; /*0x16 */
1526 U16 IOTimeoutBlockDevicesNonRM; /*0x18 */
1527 U16 IOTimeoutSequential; /*0x1A */
1528 U16 IOTimeoutOther; /*0x1C */
1529 U16 IOTimeoutBlockDevicesRM; /*0x1E */
1530} MPI2_CONFIG_PAGE_BIOS_1,
1531 *PTR_MPI2_CONFIG_PAGE_BIOS_1,
1532 Mpi2BiosPage1_t, *pMpi2BiosPage1_t;
1533
1534#define MPI2_BIOSPAGE1_PAGEVERSION (0x07)
1535
1536/*values for BIOS Page 1 BiosOptions field */
1537#define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000)
1538#define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000)
1539
1540#define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800)
1541#define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000)
1542#define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800)
1543#define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000)
1544#define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800)
1545#define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000)
1546
1547#define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400)
1548
1549#define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300)
1550#define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000)
1551#define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100)
1552#define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200)
1553#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300)
1554
1555#define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0)
1556#define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000)
1557
1558#define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006)
1559#define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000)
1560#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002)
1561#define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004)
1562
1563#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1564
1565/*values for BIOS Page 1 IOCSettings field */
1566#define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1567#define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1568#define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1569
1570#define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1571#define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1572#define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1573#define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1574
1575#define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1576#define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1577#define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1578#define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1579#define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1580
1581#define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1582
1583/*values for BIOS Page 1 DeviceSettings field */
1584#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1585#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1586#define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1587#define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1588#define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1589
1590/*defines for BIOS Page 1 UEFIVersion field */
1591#define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00)
1592#define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8)
1593#define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF)
1594#define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0)
1595
1596
1597
1598/*BIOS Page 2 */
1599
1600typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER {
1601 U32 Reserved1; /*0x00 */
1602 U32 Reserved2; /*0x04 */
1603 U32 Reserved3; /*0x08 */
1604 U32 Reserved4; /*0x0C */
1605 U32 Reserved5; /*0x10 */
1606 U32 Reserved6; /*0x14 */
1607} MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1608 *PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1609 Mpi2BootDeviceAdapterOrder_t,
1610 *pMpi2BootDeviceAdapterOrder_t;
1611
1612typedef struct _MPI2_BOOT_DEVICE_SAS_WWID {
1613 U64 SASAddress; /*0x00 */
1614 U8 LUN[8]; /*0x08 */
1615 U32 Reserved1; /*0x10 */
1616 U32 Reserved2; /*0x14 */
1617} MPI2_BOOT_DEVICE_SAS_WWID,
1618 *PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1619 Mpi2BootDeviceSasWwid_t,
1620 *pMpi2BootDeviceSasWwid_t;
1621
1622typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT {
1623 U64 EnclosureLogicalID; /*0x00 */
1624 U32 Reserved1; /*0x08 */
1625 U32 Reserved2; /*0x0C */
1626 U16 SlotNumber; /*0x10 */
1627 U16 Reserved3; /*0x12 */
1628 U32 Reserved4; /*0x14 */
1629} MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1630 *PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1631 Mpi2BootDeviceEnclosureSlot_t,
1632 *pMpi2BootDeviceEnclosureSlot_t;
1633
1634typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME {
1635 U64 DeviceName; /*0x00 */
1636 U8 LUN[8]; /*0x08 */
1637 U32 Reserved1; /*0x10 */
1638 U32 Reserved2; /*0x14 */
1639} MPI2_BOOT_DEVICE_DEVICE_NAME,
1640 *PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1641 Mpi2BootDeviceDeviceName_t,
1642 *pMpi2BootDeviceDeviceName_t;
1643
1644typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE {
1645 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1646 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1647 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1648 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1649} MPI2_BIOSPAGE2_BOOT_DEVICE,
1650 *PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1651 Mpi2BiosPage2BootDevice_t,
1652 *pMpi2BiosPage2BootDevice_t;
1653
1654typedef struct _MPI2_CONFIG_PAGE_BIOS_2 {
1655 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1656 U32 Reserved1; /*0x04 */
1657 U32 Reserved2; /*0x08 */
1658 U32 Reserved3; /*0x0C */
1659 U32 Reserved4; /*0x10 */
1660 U32 Reserved5; /*0x14 */
1661 U32 Reserved6; /*0x18 */
1662 U8 ReqBootDeviceForm; /*0x1C */
1663 U8 Reserved7; /*0x1D */
1664 U16 Reserved8; /*0x1E */
1665 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /*0x20 */
1666 U8 ReqAltBootDeviceForm; /*0x38 */
1667 U8 Reserved9; /*0x39 */
1668 U16 Reserved10; /*0x3A */
1669 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /*0x3C */
1670 U8 CurrentBootDeviceForm; /*0x58 */
1671 U8 Reserved11; /*0x59 */
1672 U16 Reserved12; /*0x5A */
1673 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /*0x58 */
1674} MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2,
1675 Mpi2BiosPage2_t, *pMpi2BiosPage2_t;
1676
1677#define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1678
1679/*values for BIOS Page 2 BootDeviceForm fields */
1680#define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1681#define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1682#define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1683#define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1684#define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1685
1686
1687/*BIOS Page 3 */
1688
1689#define MPI2_BIOSPAGE3_NUM_ADAPTER (4)
1690
1691typedef struct _MPI2_ADAPTER_INFO {
1692 U8 PciBusNumber; /*0x00 */
1693 U8 PciDeviceAndFunctionNumber; /*0x01 */
1694 U16 AdapterFlags; /*0x02 */
1695} MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO,
1696 Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t;
1697
1698#define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1699#define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1700
1701typedef struct _MPI2_ADAPTER_ORDER_AUX {
1702 U64 WWID; /* 0x00 */
1703 U32 Reserved1; /* 0x08 */
1704 U32 Reserved2; /* 0x0C */
1705} MPI2_ADAPTER_ORDER_AUX, *PTR_MPI2_ADAPTER_ORDER_AUX,
1706 Mpi2AdapterOrderAux_t, *pMpi2AdapterOrderAux_t;
1707
1708
1709typedef struct _MPI2_CONFIG_PAGE_BIOS_3 {
1710 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1711 U32 GlobalFlags; /*0x04 */
1712 U32 BiosVersion; /*0x08 */
1713 MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER];
1714 U32 Reserved1; /*0x1C */
1715 MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER];
1716} MPI2_CONFIG_PAGE_BIOS_3,
1717 *PTR_MPI2_CONFIG_PAGE_BIOS_3,
1718 Mpi2BiosPage3_t, *pMpi2BiosPage3_t;
1719
1720#define MPI2_BIOSPAGE3_PAGEVERSION (0x01)
1721
1722/*values for BIOS Page 3 GlobalFlags */
1723#define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1724#define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1725#define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1726
1727#define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1728#define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1729#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1730#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1731
1732
1733/*BIOS Page 4 */
1734
1735/*
1736 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
1737 *for NumPhys at runtime before using Phy[].
1738 */
1739
1740typedef struct _MPI2_BIOS4_ENTRY {
1741 U64 ReassignmentWWID; /*0x00 */
1742 U64 ReassignmentDeviceName; /*0x08 */
1743} MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY,
1744 Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t;
1745
1746typedef struct _MPI2_CONFIG_PAGE_BIOS_4 {
1747 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1748 U8 NumPhys; /*0x04 */
1749 U8 Reserved1; /*0x05 */
1750 U16 Reserved2; /*0x06 */
1751 MPI2_BIOS4_ENTRY Phy[]; /*0x08 */
1752} MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4,
1753 Mpi2BiosPage4_t, *pMpi2BiosPage4_t;
1754
1755#define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1756
1757
1758/****************************************************************************
1759* RAID Volume Config Pages
1760****************************************************************************/
1761
1762/*RAID Volume Page 0 */
1763
1764typedef struct _MPI2_RAIDVOL0_PHYS_DISK {
1765 U8 RAIDSetNum; /*0x00 */
1766 U8 PhysDiskMap; /*0x01 */
1767 U8 PhysDiskNum; /*0x02 */
1768 U8 Reserved; /*0x03 */
1769} MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK,
1770 Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t;
1771
1772/*defines for the PhysDiskMap field */
1773#define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1774#define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1775
1776typedef struct _MPI2_RAIDVOL0_SETTINGS {
1777 U16 Settings; /*0x00 */
1778 U8 HotSparePool; /*0x01 */
1779 U8 Reserved; /*0x02 */
1780} MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS,
1781 Mpi2RaidVol0Settings_t,
1782 *pMpi2RaidVol0Settings_t;
1783
1784/*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1785#define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1786#define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1787#define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1788#define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1789#define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1790#define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1791#define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1792#define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1793
1794/*RAID Volume Page 0 VolumeSettings defines */
1795#define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1796#define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1797
1798#define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1799#define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1800#define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1801#define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1802
1803/*
1804 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
1805 *for NumPhysDisks at runtime before using PhysDisk[].
1806 */
1807
1808typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 {
1809 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1810 U16 DevHandle; /*0x04 */
1811 U8 VolumeState; /*0x06 */
1812 U8 VolumeType; /*0x07 */
1813 U32 VolumeStatusFlags; /*0x08 */
1814 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /*0x0C */
1815 U64 MaxLBA; /*0x10 */
1816 U32 StripeSize; /*0x18 */
1817 U16 BlockSize; /*0x1C */
1818 U16 Reserved1; /*0x1E */
1819 U8 SupportedPhysDisks;/*0x20 */
1820 U8 ResyncRate; /*0x21 */
1821 U16 DataScrubDuration; /*0x22 */
1822 U8 NumPhysDisks; /*0x24 */
1823 U8 Reserved2; /*0x25 */
1824 U8 Reserved3; /*0x26 */
1825 U8 InactiveStatus; /*0x27 */
1826 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[]; /*0x28 */
1827} MPI2_CONFIG_PAGE_RAID_VOL_0,
1828 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1829 Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t;
1830
1831#define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1832
1833/*values for RAID VolumeState */
1834#define MPI2_RAID_VOL_STATE_MISSING (0x00)
1835#define MPI2_RAID_VOL_STATE_FAILED (0x01)
1836#define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1837#define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1838#define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1839#define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1840
1841/*values for RAID VolumeType */
1842#define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1843#define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1844#define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1845#define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1846#define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1847
1848/*values for RAID Volume Page 0 VolumeStatusFlags field */
1849#define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1850#define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1851#define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1852#define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1853#define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1854#define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1855#define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1856#define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1857#define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1858#define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1859#define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
1860#define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1861#define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1862#define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1863#define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1864#define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1865#define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1866#define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1867#define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1868
1869/*values for RAID Volume Page 0 SupportedPhysDisks field */
1870#define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1871#define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1872#define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1873#define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1874
1875/*values for RAID Volume Page 0 InactiveStatus field */
1876#define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1877#define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1878#define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1879#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1880#define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1881#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1882#define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1883
1884
1885/*RAID Volume Page 1 */
1886
1887typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 {
1888 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1889 U16 DevHandle; /*0x04 */
1890 U16 Reserved0; /*0x06 */
1891 U8 GUID[24]; /*0x08 */
1892 U8 Name[16]; /*0x20 */
1893 U64 WWID; /*0x30 */
1894 U32 Reserved1; /*0x38 */
1895 U32 Reserved2; /*0x3C */
1896} MPI2_CONFIG_PAGE_RAID_VOL_1,
1897 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1898 Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t;
1899
1900#define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1901
1902
1903/****************************************************************************
1904* RAID Physical Disk Config Pages
1905****************************************************************************/
1906
1907/*RAID Physical Disk Page 0 */
1908
1909typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS {
1910 U16 Reserved1; /*0x00 */
1911 U8 HotSparePool; /*0x02 */
1912 U8 Reserved2; /*0x03 */
1913} MPI2_RAIDPHYSDISK0_SETTINGS,
1914 *PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1915 Mpi2RaidPhysDisk0Settings_t,
1916 *pMpi2RaidPhysDisk0Settings_t;
1917
1918/*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1919
1920typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA {
1921 U8 VendorID[8]; /*0x00 */
1922 U8 ProductID[16]; /*0x08 */
1923 U8 ProductRevLevel[4]; /*0x18 */
1924 U8 SerialNum[32]; /*0x1C */
1925} MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1926 *PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1927 Mpi2RaidPhysDisk0InquiryData_t,
1928 *pMpi2RaidPhysDisk0InquiryData_t;
1929
1930typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 {
1931 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1932 U16 DevHandle; /*0x04 */
1933 U8 Reserved1; /*0x06 */
1934 U8 PhysDiskNum; /*0x07 */
1935 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /*0x08 */
1936 U32 Reserved2; /*0x0C */
1937 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /*0x10 */
1938 U32 Reserved3; /*0x4C */
1939 U8 PhysDiskState; /*0x50 */
1940 U8 OfflineReason; /*0x51 */
1941 U8 IncompatibleReason; /*0x52 */
1942 U8 PhysDiskAttributes; /*0x53 */
1943 U32 PhysDiskStatusFlags;/*0x54 */
1944 U64 DeviceMaxLBA; /*0x58 */
1945 U64 HostMaxLBA; /*0x60 */
1946 U64 CoercedMaxLBA; /*0x68 */
1947 U16 BlockSize; /*0x70 */
1948 U16 Reserved5; /*0x72 */
1949 U32 Reserved6; /*0x74 */
1950} MPI2_CONFIG_PAGE_RD_PDISK_0,
1951 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1952 Mpi2RaidPhysDiskPage0_t,
1953 *pMpi2RaidPhysDiskPage0_t;
1954
1955#define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1956
1957/*PhysDiskState defines */
1958#define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1959#define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1960#define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1961#define MPI2_RAID_PD_STATE_ONLINE (0x03)
1962#define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1963#define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1964#define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1965#define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1966
1967/*OfflineReason defines */
1968#define MPI2_PHYSDISK0_ONLINE (0x00)
1969#define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1970#define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1971#define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1972#define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1973#define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1974#define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1975
1976/*IncompatibleReason defines */
1977#define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1978#define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1979#define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1980#define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1981#define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1982#define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1983#define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
1984#define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1985
1986/*PhysDiskAttributes defines */
1987#define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C)
1988#define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1989#define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1990
1991#define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
1992#define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1993#define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1994
1995/*PhysDiskStatusFlags defines */
1996#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1997#define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1998#define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1999#define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
2000#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
2001#define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
2002#define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
2003#define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
2004
2005
2006/*RAID Physical Disk Page 1 */
2007
2008/*
2009 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
2010 *for NumPhysDiskPaths at runtime before using PhysicalDiskPath[].
2011 */
2012
2013typedef struct _MPI2_RAIDPHYSDISK1_PATH {
2014 U16 DevHandle; /*0x00 */
2015 U16 Reserved1; /*0x02 */
2016 U64 WWID; /*0x04 */
2017 U64 OwnerWWID; /*0x0C */
2018 U8 OwnerIdentifier; /*0x14 */
2019 U8 Reserved2; /*0x15 */
2020 U16 Flags; /*0x16 */
2021} MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH,
2022 Mpi2RaidPhysDisk1Path_t,
2023 *pMpi2RaidPhysDisk1Path_t;
2024
2025/*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
2026#define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
2027#define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
2028#define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
2029
2030typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 {
2031 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
2032 U8 NumPhysDiskPaths; /*0x04 */
2033 U8 PhysDiskNum; /*0x05 */
2034 U16 Reserved1; /*0x06 */
2035 U32 Reserved2; /*0x08 */
2036 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[]; /*0x0C */
2037} MPI2_CONFIG_PAGE_RD_PDISK_1,
2038 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
2039 Mpi2RaidPhysDiskPage1_t,
2040 *pMpi2RaidPhysDiskPage1_t;
2041
2042#define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
2043
2044
2045/****************************************************************************
2046* values for fields used by several types of SAS Config Pages
2047****************************************************************************/
2048
2049/*values for NegotiatedLinkRates fields */
2050#define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
2051#define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
2052#define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
2053/*link rates used for Negotiated Physical and Logical Link Rate */
2054#define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
2055#define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
2056#define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
2057#define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
2058#define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
2059#define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
2060#define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
2061#define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
2062#define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
2063#define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
2064#define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B)
2065#define MPI26_SAS_NEG_LINK_RATE_22_5 (0x0C)
2066
2067
2068/*values for AttachedPhyInfo fields */
2069#define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
2070#define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
2071#define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
2072
2073#define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
2074#define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
2075#define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
2076#define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
2077#define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
2078#define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
2079#define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
2080#define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
2081#define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
2082#define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
2083
2084
2085/*values for PhyInfo fields */
2086#define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
2087
2088#define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
2089#define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27)
2090#define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
2091#define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
2092#define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
2093
2094#define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
2095#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
2096#define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
2097#define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
2098#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
2099#define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
2100
2101#define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
2102#define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
2103#define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
2104#define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
2105#define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
2106#define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
2107#define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
2108#define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
2109#define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
2110#define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
2111
2112#define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
2113#define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
2114#define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
2115#define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
2116
2117#define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
2118#define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
2119
2120#define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
2121#define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
2122#define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
2123#define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
2124
2125
2126/*values for SAS ProgrammedLinkRate fields */
2127#define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
2128#define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
2129#define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
2130#define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
2131#define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
2132#define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0)
2133#define MPI26_SAS_PRATE_MAX_RATE_22_5 (0xC0)
2134#define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
2135#define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
2136#define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
2137#define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
2138#define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
2139#define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B)
2140#define MPI26_SAS_PRATE_MIN_RATE_22_5 (0x0C)
2141
2142
2143/*values for SAS HwLinkRate fields */
2144#define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
2145#define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
2146#define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
2147#define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
2148#define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0)
2149#define MPI26_SAS_HWRATE_MAX_RATE_22_5 (0xC0)
2150#define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
2151#define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
2152#define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
2153#define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
2154#define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B)
2155#define MPI26_SAS_HWRATE_MIN_RATE_22_5 (0x0C)
2156
2157
2158
2159/****************************************************************************
2160* SAS IO Unit Config Pages
2161****************************************************************************/
2162
2163/*SAS IO Unit Page 0 */
2164
2165typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA {
2166 U8 Port; /*0x00 */
2167 U8 PortFlags; /*0x01 */
2168 U8 PhyFlags; /*0x02 */
2169 U8 NegotiatedLinkRate; /*0x03 */
2170 U32 ControllerPhyDeviceInfo;/*0x04 */
2171 U16 AttachedDevHandle; /*0x08 */
2172 U16 ControllerDevHandle; /*0x0A */
2173 U32 DiscoveryStatus; /*0x0C */
2174 U32 Reserved; /*0x10 */
2175} MPI2_SAS_IO_UNIT0_PHY_DATA,
2176 *PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
2177 Mpi2SasIOUnit0PhyData_t,
2178 *pMpi2SasIOUnit0PhyData_t;
2179
2180/*
2181 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
2182 *for NumPhys at runtime before using PhyData[].
2183 */
2184
2185typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 {
2186 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2187 U32 Reserved1;/*0x08 */
2188 U8 NumPhys; /*0x0C */
2189 U8 Reserved2;/*0x0D */
2190 U16 Reserved3;/*0x0E */
2191 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[];/*0x10 */
2192} MPI2_CONFIG_PAGE_SASIOUNIT_0,
2193 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
2194 Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t;
2195
2196#define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
2197
2198/*values for SAS IO Unit Page 0 PortFlags */
2199#define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
2200#define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
2201
2202/*values for SAS IO Unit Page 0 PhyFlags */
2203#define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40)
2204#define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20)
2205#define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
2206#define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
2207
2208/*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2209
2210/*see mpi2_sas.h for values for
2211 *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2212
2213/*values for SAS IO Unit Page 0 DiscoveryStatus */
2214#define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2215#define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2216#define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
2217#define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2218#define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2219#define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2220#define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2221#define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
2222#define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2223#define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
2224#define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
2225#define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
2226#define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
2227#define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
2228#define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
2229#define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2230#define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
2231#define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
2232#define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2233#define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
2234
2235
2236/*SAS IO Unit Page 1 */
2237
2238typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA {
2239 U8 Port; /*0x00 */
2240 U8 PortFlags; /*0x01 */
2241 U8 PhyFlags; /*0x02 */
2242 U8 MaxMinLinkRate; /*0x03 */
2243 U32 ControllerPhyDeviceInfo; /*0x04 */
2244 U16 MaxTargetPortConnectTime; /*0x08 */
2245 U16 Reserved1; /*0x0A */
2246} MPI2_SAS_IO_UNIT1_PHY_DATA,
2247 *PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
2248 Mpi2SasIOUnit1PhyData_t,
2249 *pMpi2SasIOUnit1PhyData_t;
2250
2251/*
2252 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
2253 *for NumPhys at runtime before using PhyData[].
2254 */
2255
2256typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 {
2257 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2258 U16
2259 ControlFlags; /*0x08 */
2260 U16
2261 SASNarrowMaxQueueDepth; /*0x0A */
2262 U16
2263 AdditionalControlFlags; /*0x0C */
2264 U16
2265 SASWideMaxQueueDepth; /*0x0E */
2266 U8
2267 NumPhys; /*0x10 */
2268 U8
2269 SATAMaxQDepth; /*0x11 */
2270 U8
2271 ReportDeviceMissingDelay; /*0x12 */
2272 U8
2273 IODeviceMissingDelay; /*0x13 */
2274 MPI2_SAS_IO_UNIT1_PHY_DATA
2275 PhyData[]; /*0x14 */
2276} MPI2_CONFIG_PAGE_SASIOUNIT_1,
2277 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
2278 Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t;
2279
2280#define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
2281
2282/*values for SAS IO Unit Page 1 ControlFlags */
2283#define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
2284#define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
2285#define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
2286#define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
2287
2288#define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
2289#define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
2290#define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
2291#define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
2292#define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
2293
2294#define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
2295#define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
2296#define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
2297#define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
2298#define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
2299#define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
2300#define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
2301#define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
2302
2303/*values for SAS IO Unit Page 1 AdditionalControlFlags */
2304#define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100)
2305#define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
2306#define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
2307#define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
2308#define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
2309#define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
2310#define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
2311#define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
2312#define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
2313
2314/*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2315#define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
2316#define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
2317
2318/*values for SAS IO Unit Page 1 PortFlags */
2319#define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2320
2321/*values for SAS IO Unit Page 1 PhyFlags */
2322#define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40)
2323#define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20)
2324#define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
2325#define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
2326
2327/*values for SAS IO Unit Page 1 MaxMinLinkRate */
2328#define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
2329#define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
2330#define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
2331#define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
2332#define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0)
2333#define MPI26_SASIOUNIT1_MAX_RATE_22_5 (0xC0)
2334#define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
2335#define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
2336#define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
2337#define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
2338#define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B)
2339#define MPI26_SASIOUNIT1_MIN_RATE_22_5 (0x0C)
2340
2341/*see mpi2_sas.h for values for
2342 *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2343
2344
2345/*SAS IO Unit Page 4 (for MPI v2.5 and earlier) */
2346
2347typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP {
2348 U8 MaxTargetSpinup; /*0x00 */
2349 U8 SpinupDelay; /*0x01 */
2350 U8 SpinupFlags; /*0x02 */
2351 U8 Reserved1; /*0x03 */
2352} MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2353 *PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2354 Mpi2SasIOUnit4SpinupGroup_t,
2355 *pMpi2SasIOUnit4SpinupGroup_t;
2356/*defines for SAS IO Unit Page 4 SpinupFlags */
2357#define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01)
2358
2359
2360/*
2361 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2362 *one and check the value returned for NumPhys at runtime.
2363 */
2364#ifndef MPI2_SAS_IOUNIT4_PHY_MAX
2365#define MPI2_SAS_IOUNIT4_PHY_MAX (4)
2366#endif
2367
2368typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 {
2369 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;/*0x00 */
2370 MPI2_SAS_IOUNIT4_SPINUP_GROUP
2371 SpinupGroupParameters[4]; /*0x08 */
2372 U32
2373 Reserved1; /*0x18 */
2374 U32
2375 Reserved2; /*0x1C */
2376 U32
2377 Reserved3; /*0x20 */
2378 U8
2379 BootDeviceWaitTime; /*0x24 */
2380 U8
2381 SATADeviceWaitTime; /*0x25 */
2382 U16
2383 Reserved5; /*0x26 */
2384 U8
2385 NumPhys; /*0x28 */
2386 U8
2387 PEInitialSpinupDelay; /*0x29 */
2388 U8
2389 PEReplyDelay; /*0x2A */
2390 U8
2391 Flags; /*0x2B */
2392 U8
2393 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /*0x2C */
2394} MPI2_CONFIG_PAGE_SASIOUNIT_4,
2395 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2396 Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t;
2397
2398#define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
2399
2400/*defines for Flags field */
2401#define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
2402
2403/*defines for PHY field */
2404#define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
2405
2406
2407/*SAS IO Unit Page 5 */
2408
2409typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
2410 U8 ControlFlags; /*0x00 */
2411 U8 PortWidthModGroup; /*0x01 */
2412 U16 InactivityTimerExponent; /*0x02 */
2413 U8 SATAPartialTimeout; /*0x04 */
2414 U8 Reserved2; /*0x05 */
2415 U8 SATASlumberTimeout; /*0x06 */
2416 U8 Reserved3; /*0x07 */
2417 U8 SASPartialTimeout; /*0x08 */
2418 U8 Reserved4; /*0x09 */
2419 U8 SASSlumberTimeout; /*0x0A */
2420 U8 Reserved5; /*0x0B */
2421} MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2422 *PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2423 Mpi2SasIOUnit5PhyPmSettings_t,
2424 *pMpi2SasIOUnit5PhyPmSettings_t;
2425
2426/*defines for ControlFlags field */
2427#define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
2428#define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
2429#define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
2430#define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
2431
2432/*defines for PortWidthModeGroup field */
2433#define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
2434
2435/*defines for InactivityTimerExponent field */
2436#define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
2437#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
2438#define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
2439#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
2440#define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
2441#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
2442#define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
2443#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
2444
2445#define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
2446#define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
2447#define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
2448#define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
2449#define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
2450#define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
2451#define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
2452#define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
2453
2454/*
2455 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
2456 *for NumPhys at runtime before using SASPhyPowerManagementSettings[].
2457 */
2458
2459typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
2460 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2461 U8 NumPhys; /*0x08 */
2462 U8 Reserved1;/*0x09 */
2463 U16 Reserved2;/*0x0A */
2464 U32 Reserved3;/*0x0C */
2465 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
2466 SASPhyPowerManagementSettings[]; /*0x10 */
2467} MPI2_CONFIG_PAGE_SASIOUNIT_5,
2468 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2469 Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t;
2470
2471#define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
2472
2473
2474/*SAS IO Unit Page 6 */
2475
2476typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
2477 U8 CurrentStatus; /*0x00 */
2478 U8 CurrentModulation; /*0x01 */
2479 U8 CurrentUtilization; /*0x02 */
2480 U8 Reserved1; /*0x03 */
2481 U32 Reserved2; /*0x04 */
2482} MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2483 *PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2484 Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2485 *pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2486
2487/*defines for CurrentStatus field */
2488#define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
2489#define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
2490#define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
2491#define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
2492#define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
2493#define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
2494#define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
2495#define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
2496
2497/*defines for CurrentModulation field */
2498#define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
2499#define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
2500#define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
2501#define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
2502
2503/*
2504 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
2505 *for NumGroups at runtime before using PortWidthModulationGroupStatus[].
2506 */
2507
2508typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
2509 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2510 U32 Reserved1; /*0x08 */
2511 U32 Reserved2; /*0x0C */
2512 U8 NumGroups; /*0x10 */
2513 U8 Reserved3; /*0x11 */
2514 U16 Reserved4; /*0x12 */
2515 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2516 PortWidthModulationGroupStatus[]; /*0x14 */
2517} MPI2_CONFIG_PAGE_SASIOUNIT_6,
2518 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2519 Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t;
2520
2521#define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
2522
2523
2524/*SAS IO Unit Page 7 */
2525
2526typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
2527 U8 Flags; /*0x00 */
2528 U8 Reserved1; /*0x01 */
2529 U16 Reserved2; /*0x02 */
2530 U8 Threshold75Pct; /*0x04 */
2531 U8 Threshold50Pct; /*0x05 */
2532 U8 Threshold25Pct; /*0x06 */
2533 U8 Reserved3; /*0x07 */
2534} MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2535 *PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2536 Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2537 *pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2538
2539/*defines for Flags field */
2540#define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
2541
2542
2543/*
2544 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
2545 *for NumGroups at runtime before using PortWidthModulationGroupSettings[].
2546 */
2547
2548typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
2549 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2550 U8 SamplingInterval; /*0x08 */
2551 U8 WindowLength; /*0x09 */
2552 U16 Reserved1; /*0x0A */
2553 U32 Reserved2; /*0x0C */
2554 U32 Reserved3; /*0x10 */
2555 U8 NumGroups; /*0x14 */
2556 U8 Reserved4; /*0x15 */
2557 U16 Reserved5; /*0x16 */
2558 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2559 PortWidthModulationGroupSettings[]; /*0x18 */
2560} MPI2_CONFIG_PAGE_SASIOUNIT_7,
2561 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2562 Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t;
2563
2564#define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
2565
2566
2567/*SAS IO Unit Page 8 */
2568
2569typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
2570 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2571 Header; /*0x00 */
2572 U32
2573 Reserved1; /*0x08 */
2574 U32
2575 PowerManagementCapabilities; /*0x0C */
2576 U8
2577 TxRxSleepStatus; /*0x10 */
2578 U8
2579 Reserved2; /*0x11 */
2580 U16
2581 Reserved3; /*0x12 */
2582} MPI2_CONFIG_PAGE_SASIOUNIT_8,
2583 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2584 Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t;
2585
2586#define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
2587
2588/*defines for PowerManagementCapabilities field */
2589#define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000)
2590#define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800)
2591#define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400)
2592#define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200)
2593#define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100)
2594#define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010)
2595#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008)
2596#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004)
2597#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002)
2598#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001)
2599
2600/*defines for TxRxSleepStatus field */
2601#define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00)
2602#define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01)
2603#define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02)
2604#define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03)
2605
2606
2607
2608/*SAS IO Unit Page 16 */
2609
2610typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 {
2611 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2612 Header; /*0x00 */
2613 U64
2614 TimeStamp; /*0x08 */
2615 U32
2616 Reserved1; /*0x10 */
2617 U32
2618 Reserved2; /*0x14 */
2619 U32
2620 FastPathPendedRequests; /*0x18 */
2621 U32
2622 FastPathUnPendedRequests; /*0x1C */
2623 U32
2624 FastPathHostRequestStarts; /*0x20 */
2625 U32
2626 FastPathFirmwareRequestStarts; /*0x24 */
2627 U32
2628 FastPathHostCompletions; /*0x28 */
2629 U32
2630 FastPathFirmwareCompletions; /*0x2C */
2631 U32
2632 NonFastPathRequestStarts; /*0x30 */
2633 U32
2634 NonFastPathHostCompletions; /*0x30 */
2635} MPI2_CONFIG_PAGE_SASIOUNIT16,
2636 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT16,
2637 Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t;
2638
2639#define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00)
2640
2641
2642/****************************************************************************
2643* SAS Expander Config Pages
2644****************************************************************************/
2645
2646/*SAS Expander Page 0 */
2647
2648typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 {
2649 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2650 Header; /*0x00 */
2651 U8
2652 PhysicalPort; /*0x08 */
2653 U8
2654 ReportGenLength; /*0x09 */
2655 U16
2656 EnclosureHandle; /*0x0A */
2657 U64
2658 SASAddress; /*0x0C */
2659 U32
2660 DiscoveryStatus; /*0x14 */
2661 U16
2662 DevHandle; /*0x18 */
2663 U16
2664 ParentDevHandle; /*0x1A */
2665 U16
2666 ExpanderChangeCount; /*0x1C */
2667 U16
2668 ExpanderRouteIndexes; /*0x1E */
2669 U8
2670 NumPhys; /*0x20 */
2671 U8
2672 SASLevel; /*0x21 */
2673 U16
2674 Flags; /*0x22 */
2675 U16
2676 STPBusInactivityTimeLimit; /*0x24 */
2677 U16
2678 STPMaxConnectTimeLimit; /*0x26 */
2679 U16
2680 STP_SMP_NexusLossTime; /*0x28 */
2681 U16
2682 MaxNumRoutedSasAddresses; /*0x2A */
2683 U64
2684 ActiveZoneManagerSASAddress;/*0x2C */
2685 U16
2686 ZoneLockInactivityLimit; /*0x34 */
2687 U16
2688 Reserved1; /*0x36 */
2689 U8
2690 TimeToReducedFunc; /*0x38 */
2691 U8
2692 InitialTimeToReducedFunc; /*0x39 */
2693 U8
2694 MaxReducedFuncTime; /*0x3A */
2695 U8
2696 Reserved2; /*0x3B */
2697} MPI2_CONFIG_PAGE_EXPANDER_0,
2698 *PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2699 Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t;
2700
2701#define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
2702
2703/*values for SAS Expander Page 0 DiscoveryStatus field */
2704#define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2705#define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2706#define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
2707#define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2708#define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2709#define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2710#define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2711#define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
2712#define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2713#define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2714#define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2715#define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2716#define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2717#define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2718#define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2719#define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2720#define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2721#define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2722#define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2723#define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2724
2725/*values for SAS Expander Page 0 Flags field */
2726#define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
2727#define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
2728#define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
2729#define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
2730#define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
2731#define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
2732#define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
2733#define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
2734#define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
2735#define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
2736#define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
2737
2738
2739/*SAS Expander Page 1 */
2740
2741typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 {
2742 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2743 Header; /*0x00 */
2744 U8
2745 PhysicalPort; /*0x08 */
2746 U8
2747 Reserved1; /*0x09 */
2748 U16
2749 Reserved2; /*0x0A */
2750 U8
2751 NumPhys; /*0x0C */
2752 U8
2753 Phy; /*0x0D */
2754 U16
2755 NumTableEntriesProgrammed; /*0x0E */
2756 U8
2757 ProgrammedLinkRate; /*0x10 */
2758 U8
2759 HwLinkRate; /*0x11 */
2760 U16
2761 AttachedDevHandle; /*0x12 */
2762 U32
2763 PhyInfo; /*0x14 */
2764 U32
2765 AttachedDeviceInfo; /*0x18 */
2766 U16
2767 ExpanderDevHandle; /*0x1C */
2768 U8
2769 ChangeCount; /*0x1E */
2770 U8
2771 NegotiatedLinkRate; /*0x1F */
2772 U8
2773 PhyIdentifier; /*0x20 */
2774 U8
2775 AttachedPhyIdentifier; /*0x21 */
2776 U8
2777 Reserved3; /*0x22 */
2778 U8
2779 DiscoveryInfo; /*0x23 */
2780 U32
2781 AttachedPhyInfo; /*0x24 */
2782 U8
2783 ZoneGroup; /*0x28 */
2784 U8
2785 SelfConfigStatus; /*0x29 */
2786 U16
2787 Reserved4; /*0x2A */
2788} MPI2_CONFIG_PAGE_EXPANDER_1,
2789 *PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2790 Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t;
2791
2792#define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2793
2794/*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2795
2796/*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2797
2798/*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2799
2800/*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines
2801 *used for the AttachedDeviceInfo field */
2802
2803/*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2804
2805/*values for SAS Expander Page 1 DiscoveryInfo field */
2806#define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2807#define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2808#define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2809
2810/*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2811
2812
2813/****************************************************************************
2814* SAS Device Config Pages
2815****************************************************************************/
2816
2817/*SAS Device Page 0 */
2818
2819typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 {
2820 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2821 Header; /*0x00 */
2822 U16
2823 Slot; /*0x08 */
2824 U16
2825 EnclosureHandle; /*0x0A */
2826 U64
2827 SASAddress; /*0x0C */
2828 U16
2829 ParentDevHandle; /*0x14 */
2830 U8
2831 PhyNum; /*0x16 */
2832 U8
2833 AccessStatus; /*0x17 */
2834 U16
2835 DevHandle; /*0x18 */
2836 U8
2837 AttachedPhyIdentifier; /*0x1A */
2838 U8
2839 ZoneGroup; /*0x1B */
2840 U32
2841 DeviceInfo; /*0x1C */
2842 U16
2843 Flags; /*0x20 */
2844 U8
2845 PhysicalPort; /*0x22 */
2846 U8
2847 MaxPortConnections; /*0x23 */
2848 U64
2849 DeviceName; /*0x24 */
2850 U8
2851 PortGroups; /*0x2C */
2852 U8
2853 DmaGroup; /*0x2D */
2854 U8
2855 ControlGroup; /*0x2E */
2856 U8
2857 EnclosureLevel; /*0x2F */
2858 U32
2859 ConnectorName[4]; /*0x30 */
2860 U32
2861 Reserved3; /*0x34 */
2862} MPI2_CONFIG_PAGE_SAS_DEV_0,
2863 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2864 Mpi2SasDevicePage0_t,
2865 *pMpi2SasDevicePage0_t;
2866
2867#define MPI2_SASDEVICE0_PAGEVERSION (0x09)
2868
2869/*values for SAS Device Page 0 AccessStatus field */
2870#define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2871#define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2872#define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2873#define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2874#define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2875#define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2876#define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2877#define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2878/*specific values for SATA Init failures */
2879#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2880#define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2881#define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2882#define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2883#define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2884#define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2885#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2886#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2887#define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2888#define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2889#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2890
2891/*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2892
2893/*values for SAS Device Page 0 Flags field */
2894#define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000)
2895#define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000)
2896#define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000)
2897#define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2898#define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
2899#define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2900#define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2901#define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2902#define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2903#define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2904#define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2905#define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2906#define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2907#define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004)
2908#define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002)
2909#define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2910
2911
2912/*SAS Device Page 1 */
2913
2914typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 {
2915 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2916 Header; /*0x00 */
2917 U32
2918 Reserved1; /*0x08 */
2919 U64
2920 SASAddress; /*0x0C */
2921 U32
2922 Reserved2; /*0x14 */
2923 U16
2924 DevHandle; /*0x18 */
2925 U16
2926 Reserved3; /*0x1A */
2927 U8
2928 InitialRegDeviceFIS[20];/*0x1C */
2929} MPI2_CONFIG_PAGE_SAS_DEV_1,
2930 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2931 Mpi2SasDevicePage1_t,
2932 *pMpi2SasDevicePage1_t;
2933
2934#define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2935
2936
2937/****************************************************************************
2938* SAS PHY Config Pages
2939****************************************************************************/
2940
2941/*SAS PHY Page 0 */
2942
2943typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 {
2944 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2945 Header; /*0x00 */
2946 U16
2947 OwnerDevHandle; /*0x08 */
2948 U16
2949 Reserved1; /*0x0A */
2950 U16
2951 AttachedDevHandle; /*0x0C */
2952 U8
2953 AttachedPhyIdentifier; /*0x0E */
2954 U8
2955 Reserved2; /*0x0F */
2956 U32
2957 AttachedPhyInfo; /*0x10 */
2958 U8
2959 ProgrammedLinkRate; /*0x14 */
2960 U8
2961 HwLinkRate; /*0x15 */
2962 U8
2963 ChangeCount; /*0x16 */
2964 U8
2965 Flags; /*0x17 */
2966 U32
2967 PhyInfo; /*0x18 */
2968 U8
2969 NegotiatedLinkRate; /*0x1C */
2970 U8
2971 Reserved3; /*0x1D */
2972 U16
2973 Reserved4; /*0x1E */
2974} MPI2_CONFIG_PAGE_SAS_PHY_0,
2975 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2976 Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t;
2977
2978#define MPI2_SASPHY0_PAGEVERSION (0x03)
2979
2980/*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2981
2982/*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2983
2984/*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2985
2986/*values for SAS PHY Page 0 Flags field */
2987#define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2988
2989/*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2990
2991/*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2992
2993
2994/*SAS PHY Page 1 */
2995
2996typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 {
2997 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2998 Header; /*0x00 */
2999 U32
3000 Reserved1; /*0x08 */
3001 U32
3002 InvalidDwordCount; /*0x0C */
3003 U32
3004 RunningDisparityErrorCount; /*0x10 */
3005 U32
3006 LossDwordSynchCount; /*0x14 */
3007 U32
3008 PhyResetProblemCount; /*0x18 */
3009} MPI2_CONFIG_PAGE_SAS_PHY_1,
3010 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
3011 Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t;
3012
3013#define MPI2_SASPHY1_PAGEVERSION (0x01)
3014
3015
3016/*SAS PHY Page 2 */
3017
3018typedef struct _MPI2_SASPHY2_PHY_EVENT {
3019 U8 PhyEventCode; /*0x00 */
3020 U8 Reserved1; /*0x01 */
3021 U16 Reserved2; /*0x02 */
3022 U32 PhyEventInfo; /*0x04 */
3023} MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT,
3024 Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t;
3025
3026/*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
3027
3028
3029/*
3030 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
3031 *for NumPhyEvents at runtime before using PhyEvent[].
3032 */
3033
3034typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
3035 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3036 Header; /*0x00 */
3037 U32
3038 Reserved1; /*0x08 */
3039 U8
3040 NumPhyEvents; /*0x0C */
3041 U8
3042 Reserved2; /*0x0D */
3043 U16
3044 Reserved3; /*0x0E */
3045 MPI2_SASPHY2_PHY_EVENT
3046 PhyEvent[]; /*0x10 */
3047} MPI2_CONFIG_PAGE_SAS_PHY_2,
3048 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
3049 Mpi2SasPhyPage2_t,
3050 *pMpi2SasPhyPage2_t;
3051
3052#define MPI2_SASPHY2_PAGEVERSION (0x00)
3053
3054
3055/*SAS PHY Page 3 */
3056
3057typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
3058 U8 PhyEventCode; /*0x00 */
3059 U8 Reserved1; /*0x01 */
3060 U16 Reserved2; /*0x02 */
3061 U8 CounterType; /*0x04 */
3062 U8 ThresholdWindow; /*0x05 */
3063 U8 TimeUnits; /*0x06 */
3064 U8 Reserved3; /*0x07 */
3065 U32 EventThreshold; /*0x08 */
3066 U16 ThresholdFlags; /*0x0C */
3067 U16 Reserved4; /*0x0E */
3068} MPI2_SASPHY3_PHY_EVENT_CONFIG,
3069 *PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
3070 Mpi2SasPhy3PhyEventConfig_t,
3071 *pMpi2SasPhy3PhyEventConfig_t;
3072
3073/*values for PhyEventCode field */
3074#define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
3075#define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
3076#define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
3077#define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
3078#define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
3079#define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
3080#define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
3081#define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
3082#define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
3083#define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
3084#define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
3085#define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
3086#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
3087#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
3088#define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
3089#define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
3090#define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
3091#define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
3092#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
3093#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
3094#define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
3095#define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
3096#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
3097#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
3098#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
3099#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
3100#define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
3101#define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
3102#define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
3103#define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
3104#define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
3105#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
3106#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
3107#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
3108#define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
3109#define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
3110#define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
3111
3112/*Following codes are product specific and in MPI v2.6 and later */
3113#define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3)
3114#define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4)
3115#define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5)
3116#define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6)
3117#define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7)
3118#define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8)
3119#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9)
3120#define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA)
3121#define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB)
3122#define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC)
3123
3124
3125/*values for the CounterType field */
3126#define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
3127#define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
3128#define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
3129
3130/*values for the TimeUnits field */
3131#define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
3132#define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
3133#define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
3134#define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
3135
3136/*values for the ThresholdFlags field */
3137#define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
3138#define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
3139
3140/*
3141 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
3142 *for NumPhyEvents at runtime before using PhyEventConfig[].
3143 */
3144
3145typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
3146 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3147 Header; /*0x00 */
3148 U32
3149 Reserved1; /*0x08 */
3150 U8
3151 NumPhyEvents; /*0x0C */
3152 U8
3153 Reserved2; /*0x0D */
3154 U16
3155 Reserved3; /*0x0E */
3156 MPI2_SASPHY3_PHY_EVENT_CONFIG
3157 PhyEventConfig[]; /*0x10 */
3158} MPI2_CONFIG_PAGE_SAS_PHY_3,
3159 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
3160 Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t;
3161
3162#define MPI2_SASPHY3_PAGEVERSION (0x00)
3163
3164
3165/*SAS PHY Page 4 */
3166
3167typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
3168 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3169 Header; /*0x00 */
3170 U16
3171 Reserved1; /*0x08 */
3172 U8
3173 Reserved2; /*0x0A */
3174 U8
3175 Flags; /*0x0B */
3176 U8
3177 InitialFrame[28]; /*0x0C */
3178} MPI2_CONFIG_PAGE_SAS_PHY_4,
3179 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
3180 Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t;
3181
3182#define MPI2_SASPHY4_PAGEVERSION (0x00)
3183
3184/*values for the Flags field */
3185#define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
3186#define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
3187
3188
3189
3190
3191/****************************************************************************
3192* SAS Port Config Pages
3193****************************************************************************/
3194
3195/*SAS Port Page 0 */
3196
3197typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 {
3198 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3199 Header; /*0x00 */
3200 U8
3201 PortNumber; /*0x08 */
3202 U8
3203 PhysicalPort; /*0x09 */
3204 U8
3205 PortWidth; /*0x0A */
3206 U8
3207 PhysicalPortWidth; /*0x0B */
3208 U8
3209 ZoneGroup; /*0x0C */
3210 U8
3211 Reserved1; /*0x0D */
3212 U16
3213 Reserved2; /*0x0E */
3214 U64
3215 SASAddress; /*0x10 */
3216 U32
3217 DeviceInfo; /*0x18 */
3218 U32
3219 Reserved3; /*0x1C */
3220 U32
3221 Reserved4; /*0x20 */
3222} MPI2_CONFIG_PAGE_SAS_PORT_0,
3223 *PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
3224 Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t;
3225
3226#define MPI2_SASPORT0_PAGEVERSION (0x00)
3227
3228/*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
3229
3230
3231/****************************************************************************
3232* SAS Enclosure Config Pages
3233****************************************************************************/
3234
3235/*SAS Enclosure Page 0 */
3236
3237typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 {
3238 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3239 U32 Reserved1; /*0x08 */
3240 U64 EnclosureLogicalID; /*0x0C */
3241 U16 Flags; /*0x14 */
3242 U16 EnclosureHandle; /*0x16 */
3243 U16 NumSlots; /*0x18 */
3244 U16 StartSlot; /*0x1A */
3245 U8 ChassisSlot; /*0x1C */
3246 U8 EnclosureLevel; /*0x1D */
3247 U16 SEPDevHandle; /*0x1E */
3248 U8 OEMRD; /*0x20 */
3249 U8 Reserved1a; /*0x21 */
3250 U16 Reserved2; /*0x22 */
3251 U32 Reserved3; /*0x24 */
3252} MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3253 *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3254 Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t,
3255 MPI26_CONFIG_PAGE_ENCLOSURE_0,
3256 *PTR_MPI26_CONFIG_PAGE_ENCLOSURE_0,
3257 Mpi26EnclosurePage0_t, *pMpi26EnclosurePage0_t;
3258
3259#define MPI2_SASENCLOSURE0_PAGEVERSION (0x04)
3260
3261/*values for SAS Enclosure Page 0 Flags field */
3262#define MPI26_SAS_ENCLS0_FLAGS_OEMRD_VALID (0x0080)
3263#define MPI26_SAS_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040)
3264#define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020)
3265#define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010)
3266#define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
3267#define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
3268#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
3269#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
3270#define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
3271#define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
3272#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
3273
3274#define MPI26_ENCLOSURE0_PAGEVERSION (0x04)
3275
3276/*Values for Enclosure Page 0 Flags field */
3277#define MPI26_ENCLS0_FLAGS_OEMRD_VALID (0x0080)
3278#define MPI26_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040)
3279#define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020)
3280#define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010)
3281#define MPI26_ENCLS0_FLAGS_MNG_MASK (0x000F)
3282#define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
3283#define MPI26_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
3284#define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
3285#define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
3286#define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
3287#define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
3288
3289/****************************************************************************
3290* Log Config Page
3291****************************************************************************/
3292
3293/*Log Page 0 */
3294
3295/*
3296 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
3297 *for NumLogEntries at runtime before using LogEntry[].
3298 */
3299
3300#define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
3301
3302typedef struct _MPI2_LOG_0_ENTRY {
3303 U64 TimeStamp; /*0x00 */
3304 U32 Reserved1; /*0x08 */
3305 U16 LogSequence; /*0x0C */
3306 U16 LogEntryQualifier; /*0x0E */
3307 U8 VP_ID; /*0x10 */
3308 U8 VF_ID; /*0x11 */
3309 U16 Reserved2; /*0x12 */
3310 U8
3311 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */
3312} MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY,
3313 Mpi2Log0Entry_t, *pMpi2Log0Entry_t;
3314
3315/*values for Log Page 0 LogEntry LogEntryQualifier field */
3316#define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
3317#define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
3318#define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
3319#define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
3320#define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
3321
3322typedef struct _MPI2_CONFIG_PAGE_LOG_0 {
3323 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3324 U32 Reserved1; /*0x08 */
3325 U32 Reserved2; /*0x0C */
3326 U16 NumLogEntries;/*0x10 */
3327 U16 Reserved3; /*0x12 */
3328 MPI2_LOG_0_ENTRY LogEntry[]; /*0x14 */
3329} MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0,
3330 Mpi2LogPage0_t, *pMpi2LogPage0_t;
3331
3332#define MPI2_LOG_0_PAGEVERSION (0x02)
3333
3334
3335/****************************************************************************
3336* RAID Config Page
3337****************************************************************************/
3338
3339/*RAID Page 0 */
3340
3341/*
3342 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
3343 *for NumElements at runtime before using ConfigElement[].
3344 */
3345
3346typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT {
3347 U16 ElementFlags; /*0x00 */
3348 U16 VolDevHandle; /*0x02 */
3349 U8 HotSparePool; /*0x04 */
3350 U8 PhysDiskNum; /*0x05 */
3351 U16 PhysDiskDevHandle; /*0x06 */
3352} MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3353 *PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3354 Mpi2RaidConfig0ConfigElement_t,
3355 *pMpi2RaidConfig0ConfigElement_t;
3356
3357/*values for the ElementFlags field */
3358#define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
3359#define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
3360#define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
3361#define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
3362#define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
3363
3364
3365typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 {
3366 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3367 U8 NumHotSpares; /*0x08 */
3368 U8 NumPhysDisks; /*0x09 */
3369 U8 NumVolumes; /*0x0A */
3370 U8 ConfigNum; /*0x0B */
3371 U32 Flags; /*0x0C */
3372 U8 ConfigGUID[24]; /*0x10 */
3373 U32 Reserved1; /*0x28 */
3374 U8 NumElements; /*0x2C */
3375 U8 Reserved2; /*0x2D */
3376 U16 Reserved3; /*0x2E */
3377 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[];/*0x30 */
3378} MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3379 *PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3380 Mpi2RaidConfigurationPage0_t,
3381 *pMpi2RaidConfigurationPage0_t;
3382
3383#define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
3384
3385/*values for RAID Configuration Page 0 Flags field */
3386#define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
3387
3388
3389/****************************************************************************
3390* Driver Persistent Mapping Config Pages
3391****************************************************************************/
3392
3393/*Driver Persistent Mapping Page 0 */
3394
3395typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY {
3396 U64 PhysicalIdentifier; /*0x00 */
3397 U16 MappingInformation; /*0x08 */
3398 U16 DeviceIndex; /*0x0A */
3399 U32 PhysicalBitsMapping; /*0x0C */
3400 U32 Reserved1; /*0x10 */
3401} MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3402 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3403 Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t;
3404
3405typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 {
3406 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3407 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /*0x08 */
3408} MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3409 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3410 Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t;
3411
3412#define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
3413
3414/*values for Driver Persistent Mapping Page 0 MappingInformation field */
3415#define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
3416#define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
3417#define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
3418
3419
3420/****************************************************************************
3421* Ethernet Config Pages
3422****************************************************************************/
3423
3424/*Ethernet Page 0 */
3425
3426/*IP address (union of IPv4 and IPv6) */
3427typedef union _MPI2_ETHERNET_IP_ADDR {
3428 U32 IPv4Addr;
3429 U32 IPv6Addr[4];
3430} MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR,
3431 Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t;
3432
3433#define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
3434
3435typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
3436 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3437 U8 NumInterfaces; /*0x08 */
3438 U8 Reserved0; /*0x09 */
3439 U16 Reserved1; /*0x0A */
3440 U32 Status; /*0x0C */
3441 U8 MediaState; /*0x10 */
3442 U8 Reserved2; /*0x11 */
3443 U16 Reserved3; /*0x12 */
3444 U8 MacAddress[6]; /*0x14 */
3445 U8 Reserved4; /*0x1A */
3446 U8 Reserved5; /*0x1B */
3447 MPI2_ETHERNET_IP_ADDR IpAddress; /*0x1C */
3448 MPI2_ETHERNET_IP_ADDR SubnetMask; /*0x2C */
3449 MPI2_ETHERNET_IP_ADDR GatewayIpAddress;/*0x3C */
3450 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /*0x4C */
3451 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /*0x5C */
3452 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /*0x6C */
3453 U8
3454 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3455} MPI2_CONFIG_PAGE_ETHERNET_0,
3456 *PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
3457 Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t;
3458
3459#define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
3460
3461/*values for Ethernet Page 0 Status field */
3462#define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
3463#define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
3464#define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
3465#define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
3466#define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
3467#define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
3468#define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
3469#define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
3470#define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
3471#define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
3472#define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
3473#define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
3474
3475/*values for Ethernet Page 0 MediaState field */
3476#define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
3477#define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
3478#define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
3479
3480#define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
3481#define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
3482#define MPI2_ETHPG0_MS_10MBIT (0x01)
3483#define MPI2_ETHPG0_MS_100MBIT (0x02)
3484#define MPI2_ETHPG0_MS_1GBIT (0x03)
3485
3486
3487/*Ethernet Page 1 */
3488
3489typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
3490 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3491 Header; /*0x00 */
3492 U32
3493 Reserved0; /*0x08 */
3494 U32
3495 Flags; /*0x0C */
3496 U8
3497 MediaState; /*0x10 */
3498 U8
3499 Reserved1; /*0x11 */
3500 U16
3501 Reserved2; /*0x12 */
3502 U8
3503 MacAddress[6]; /*0x14 */
3504 U8
3505 Reserved3; /*0x1A */
3506 U8
3507 Reserved4; /*0x1B */
3508 MPI2_ETHERNET_IP_ADDR
3509 StaticIpAddress; /*0x1C */
3510 MPI2_ETHERNET_IP_ADDR
3511 StaticSubnetMask; /*0x2C */
3512 MPI2_ETHERNET_IP_ADDR
3513 StaticGatewayIpAddress; /*0x3C */
3514 MPI2_ETHERNET_IP_ADDR
3515 StaticDNS1IpAddress; /*0x4C */
3516 MPI2_ETHERNET_IP_ADDR
3517 StaticDNS2IpAddress; /*0x5C */
3518 U32
3519 Reserved5; /*0x6C */
3520 U32
3521 Reserved6; /*0x70 */
3522 U32
3523 Reserved7; /*0x74 */
3524 U32
3525 Reserved8; /*0x78 */
3526 U8
3527 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3528} MPI2_CONFIG_PAGE_ETHERNET_1,
3529 *PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
3530 Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t;
3531
3532#define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
3533
3534/*values for Ethernet Page 1 Flags field */
3535#define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
3536#define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
3537#define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
3538#define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
3539#define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
3540#define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
3541#define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
3542#define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
3543#define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
3544
3545/*values for Ethernet Page 1 MediaState field */
3546#define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
3547#define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
3548#define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
3549
3550#define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
3551#define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
3552#define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
3553#define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
3554#define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
3555
3556
3557/****************************************************************************
3558* Extended Manufacturing Config Pages
3559****************************************************************************/
3560
3561/*
3562 *Generic structure to use for product-specific extended manufacturing pages
3563 *(currently Extended Manufacturing Page 40 through Extended Manufacturing
3564 *Page 60).
3565 */
3566
3567typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS {
3568 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3569 Header; /*0x00 */
3570 U32
3571 ProductSpecificInfo; /*0x08 */
3572} MPI2_CONFIG_PAGE_EXT_MAN_PS,
3573 *PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
3574 Mpi2ExtManufacturingPagePS_t,
3575 *pMpi2ExtManufacturingPagePS_t;
3576
3577/*PageVersion should be provided by product-specific code */
3578
3579
3580
3581/****************************************************************************
3582* values for fields used by several types of PCIe Config Pages
3583****************************************************************************/
3584
3585/*values for NegotiatedLinkRates fields */
3586#define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
3587/*link rates used for Negotiated Physical Link Rate */
3588#define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN (0x00)
3589#define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01)
3590#define MPI26_PCIE_NEG_LINK_RATE_2_5 (0x02)
3591#define MPI26_PCIE_NEG_LINK_RATE_5_0 (0x03)
3592#define MPI26_PCIE_NEG_LINK_RATE_8_0 (0x04)
3593#define MPI26_PCIE_NEG_LINK_RATE_16_0 (0x05)
3594
3595
3596/****************************************************************************
3597* PCIe IO Unit Config Pages (MPI v2.6 and later)
3598****************************************************************************/
3599
3600/*PCIe IO Unit Page 0 */
3601
3602typedef struct _MPI26_PCIE_IO_UNIT0_PHY_DATA {
3603 U8 Link; /*0x00 */
3604 U8 LinkFlags; /*0x01 */
3605 U8 PhyFlags; /*0x02 */
3606 U8 NegotiatedLinkRate; /*0x03 */
3607 U32 ControllerPhyDeviceInfo;/*0x04 */
3608 U16 AttachedDevHandle; /*0x08 */
3609 U16 ControllerDevHandle; /*0x0A */
3610 U32 EnumerationStatus; /*0x0C */
3611 U32 Reserved1; /*0x10 */
3612} MPI26_PCIE_IO_UNIT0_PHY_DATA,
3613 *PTR_MPI26_PCIE_IO_UNIT0_PHY_DATA,
3614 Mpi26PCIeIOUnit0PhyData_t, *pMpi26PCIeIOUnit0PhyData_t;
3615
3616/*
3617 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
3618 *for NumPhys at runtime before using PhyData[].
3619 */
3620
3621typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_0 {
3622 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3623 U32 Reserved1; /*0x08 */
3624 U8 NumPhys; /*0x0C */
3625 U8 InitStatus; /*0x0D */
3626 U16 Reserved3; /*0x0E */
3627 MPI26_PCIE_IO_UNIT0_PHY_DATA
3628 PhyData[]; /*0x10 */
3629} MPI26_CONFIG_PAGE_PIOUNIT_0,
3630 *PTR_MPI26_CONFIG_PAGE_PIOUNIT_0,
3631 Mpi26PCIeIOUnitPage0_t, *pMpi26PCIeIOUnitPage0_t;
3632
3633#define MPI26_PCIEIOUNITPAGE0_PAGEVERSION (0x00)
3634
3635/*values for PCIe IO Unit Page 0 LinkFlags */
3636#define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS (0x08)
3637
3638/*values for PCIe IO Unit Page 0 PhyFlags */
3639#define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
3640
3641/*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3642
3643/*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo
3644 *values
3645 */
3646
3647/*values for PCIe IO Unit Page 0 EnumerationStatus */
3648#define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000)
3649#define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED (0x20000000)
3650
3651
3652/*PCIe IO Unit Page 1 */
3653
3654typedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA {
3655 U8 Link; /*0x00 */
3656 U8 LinkFlags; /*0x01 */
3657 U8 PhyFlags; /*0x02 */
3658 U8 MaxMinLinkRate; /*0x03 */
3659 U32 ControllerPhyDeviceInfo; /*0x04 */
3660 U32 Reserved1; /*0x08 */
3661} MPI26_PCIE_IO_UNIT1_PHY_DATA,
3662 *PTR_MPI26_PCIE_IO_UNIT1_PHY_DATA,
3663 Mpi26PCIeIOUnit1PhyData_t, *pMpi26PCIeIOUnit1PhyData_t;
3664
3665/*values for LinkFlags */
3666#define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK (0x00)
3667#define MPI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN (0x01)
3668#define MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN (0x02)
3669
3670/*
3671 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
3672 *for NumPhys at runtime before using PhyData[].
3673 */
3674
3675typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 {
3676 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3677 U16 ControlFlags; /*0x08 */
3678 U16 Reserved; /*0x0A */
3679 U16 AdditionalControlFlags; /*0x0C */
3680 U16 NVMeMaxQueueDepth; /*0x0E */
3681 U8 NumPhys; /*0x10 */
3682 U8 DMDReportPCIe; /*0x11 */
3683 U16 Reserved2; /*0x12 */
3684 MPI26_PCIE_IO_UNIT1_PHY_DATA
3685 PhyData[]; /*0x14 */
3686} MPI26_CONFIG_PAGE_PIOUNIT_1,
3687 *PTR_MPI26_CONFIG_PAGE_PIOUNIT_1,
3688 Mpi26PCIeIOUnitPage1_t, *pMpi26PCIeIOUnitPage1_t;
3689
3690#define MPI26_PCIEIOUNITPAGE1_PAGEVERSION (0x00)
3691
3692/*values for PCIe IO Unit Page 1 PhyFlags */
3693#define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
3694#define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY (0x01)
3695
3696/*values for PCIe IO Unit Page 1 MaxMinLinkRate */
3697#define MPI26_PCIEIOUNIT1_MAX_RATE_MASK (0xF0)
3698#define MPI26_PCIEIOUNIT1_MAX_RATE_SHIFT (4)
3699#define MPI26_PCIEIOUNIT1_MAX_RATE_2_5 (0x20)
3700#define MPI26_PCIEIOUNIT1_MAX_RATE_5_0 (0x30)
3701#define MPI26_PCIEIOUNIT1_MAX_RATE_8_0 (0x40)
3702#define MPI26_PCIEIOUNIT1_MAX_RATE_16_0 (0x50)
3703
3704/*values for PCIe IO Unit Page 1 DMDReportPCIe */
3705#define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_MASK (0x80)
3706#define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_1_SEC (0x00)
3707#define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_16_SEC (0x80)
3708#define MPI26_PCIEIOUNIT1_DMDRPT_DELAY_TIME_MASK (0x7F)
3709
3710/*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo
3711 *values
3712 */
3713
3714
3715/****************************************************************************
3716* PCIe Switch Config Pages (MPI v2.6 and later)
3717****************************************************************************/
3718
3719/*PCIe Switch Page 0 */
3720
3721typedef struct _MPI26_CONFIG_PAGE_PSWITCH_0 {
3722 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3723 U8 PhysicalPort; /*0x08 */
3724 U8 Reserved1; /*0x09 */
3725 U16 Reserved2; /*0x0A */
3726 U16 DevHandle; /*0x0C */
3727 U16 ParentDevHandle; /*0x0E */
3728 U8 NumPorts; /*0x10 */
3729 U8 PCIeLevel; /*0x11 */
3730 U16 Reserved3; /*0x12 */
3731 U32 Reserved4; /*0x14 */
3732 U32 Reserved5; /*0x18 */
3733 U32 Reserved6; /*0x1C */
3734} MPI26_CONFIG_PAGE_PSWITCH_0, *PTR_MPI26_CONFIG_PAGE_PSWITCH_0,
3735 Mpi26PCIeSwitchPage0_t, *pMpi26PCIeSwitchPage0_t;
3736
3737#define MPI26_PCIESWITCH0_PAGEVERSION (0x00)
3738
3739
3740/*PCIe Switch Page 1 */
3741
3742typedef struct _MPI26_CONFIG_PAGE_PSWITCH_1 {
3743 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3744 U8 PhysicalPort; /*0x08 */
3745 U8 Reserved1; /*0x09 */
3746 U16 Reserved2; /*0x0A */
3747 U8 NumPorts; /*0x0C */
3748 U8 PortNum; /*0x0D */
3749 U16 AttachedDevHandle; /*0x0E */
3750 U16 SwitchDevHandle; /*0x10 */
3751 U8 NegotiatedPortWidth; /*0x12 */
3752 U8 NegotiatedLinkRate; /*0x13 */
3753 U32 Reserved4; /*0x14 */
3754 U32 Reserved5; /*0x18 */
3755} MPI26_CONFIG_PAGE_PSWITCH_1, *PTR_MPI26_CONFIG_PAGE_PSWITCH_1,
3756 Mpi26PCIeSwitchPage1_t, *pMpi26PCIeSwitchPage1_t;
3757
3758#define MPI26_PCIESWITCH1_PAGEVERSION (0x00)
3759
3760/*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3761
3762/* defines for the Flags field */
3763#define MPI26_PCIESWITCH1_2_RETIMER_PRESENCE (0x0002)
3764#define MPI26_PCIESWITCH1_RETIMER_PRESENCE (0x0001)
3765
3766/****************************************************************************
3767* PCIe Device Config Pages (MPI v2.6 and later)
3768****************************************************************************/
3769
3770/*PCIe Device Page 0 */
3771
3772typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0 {
3773 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3774 U16 Slot; /*0x08 */
3775 U16 EnclosureHandle; /*0x0A */
3776 U64 WWID; /*0x0C */
3777 U16 ParentDevHandle; /*0x14 */
3778 U8 PortNum; /*0x16 */
3779 U8 AccessStatus; /*0x17 */
3780 U16 DevHandle; /*0x18 */
3781 U8 PhysicalPort; /*0x1A */
3782 U8 Reserved1; /*0x1B */
3783 U32 DeviceInfo; /*0x1C */
3784 U32 Flags; /*0x20 */
3785 U8 SupportedLinkRates; /*0x24 */
3786 U8 MaxPortWidth; /*0x25 */
3787 U8 NegotiatedPortWidth; /*0x26 */
3788 U8 NegotiatedLinkRate; /*0x27 */
3789 U8 EnclosureLevel; /*0x28 */
3790 U8 Reserved2; /*0x29 */
3791 U16 Reserved3; /*0x2A */
3792 U8 ConnectorName[4]; /*0x2C */
3793 U32 Reserved4; /*0x30 */
3794 U32 Reserved5; /*0x34 */
3795} MPI26_CONFIG_PAGE_PCIEDEV_0, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_0,
3796 Mpi26PCIeDevicePage0_t, *pMpi26PCIeDevicePage0_t;
3797
3798#define MPI26_PCIEDEVICE0_PAGEVERSION (0x01)
3799
3800/*values for PCIe Device Page 0 AccessStatus field */
3801#define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS (0x00)
3802#define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION (0x04)
3803#define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED (0x02)
3804#define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED (0x07)
3805#define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED (0x08)
3806#define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE (0x09)
3807#define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED (0x0A)
3808#define MPI26_PCIEDEV0_ASTATUS_UNKNOWN (0x10)
3809
3810#define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT (0x30)
3811#define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x31)
3812#define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED (0x32)
3813#define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED (0x33)
3814#define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED (0x34)
3815#define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED (0x35)
3816#define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x36)
3817#define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT (0x37)
3818#define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS (0x38)
3819
3820#define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX (0x3F)
3821
3822/*see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo
3823 *field
3824 */
3825
3826/*values for PCIe Device Page 0 Flags field*/
3827#define MPI26_PCIEDEV0_FLAGS_2_RETIMER_PRESENCE (0x00020000)
3828#define MPI26_PCIEDEV0_FLAGS_RETIMER_PRESENCE (0x00010000)
3829#define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE (0x00008000)
3830#define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH (0x00004000)
3831#define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE (0x00002000)
3832#define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION (0x00000400)
3833#define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION (0x00000200)
3834#define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE (0x00000100)
3835#define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED (0x00000080)
3836#define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED (0x00000040)
3837#define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED (0x00000020)
3838#define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED (0x00000010)
3839#define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID (0x00000002)
3840#define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT (0x00000001)
3841
3842/* values for PCIe Device Page 0 SupportedLinkRates field */
3843#define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED (0x08)
3844#define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED (0x04)
3845#define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED (0x02)
3846#define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED (0x01)
3847
3848/*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3849
3850
3851/*PCIe Device Page 2 */
3852
3853typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2 {
3854 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3855 U16 DevHandle; /*0x08 */
3856 U8 ControllerResetTO; /* 0x0A */
3857 U8 Reserved1; /* 0x0B */
3858 U32 MaximumDataTransferSize; /*0x0C */
3859 U32 Capabilities; /*0x10 */
3860 U16 NOIOB; /* 0x14 */
3861 U16 ShutdownLatency; /* 0x16 */
3862 U16 VendorID; /* 0x18 */
3863 U16 DeviceID; /* 0x1A */
3864 U16 SubsystemVendorID; /* 0x1C */
3865 U16 SubsystemID; /* 0x1E */
3866 U8 RevisionID; /* 0x20 */
3867 U8 Reserved21[3]; /* 0x21 */
3868} MPI26_CONFIG_PAGE_PCIEDEV_2, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_2,
3869 Mpi26PCIeDevicePage2_t, *pMpi26PCIeDevicePage2_t;
3870
3871#define MPI26_PCIEDEVICE2_PAGEVERSION (0x01)
3872
3873/*defines for PCIe Device Page 2 Capabilities field */
3874#define MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN (0x00000008)
3875#define MPI26_PCIEDEV2_CAP_SGL_FORMAT (0x00000004)
3876#define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT (0x00000002)
3877#define MPI26_PCIEDEV2_CAP_SGL_SUPPORT (0x00000001)
3878
3879/* Defines for the NOIOB field */
3880#define MPI26_PCIEDEV2_NOIOB_UNSUPPORTED (0x0000)
3881
3882/****************************************************************************
3883* PCIe Link Config Pages (MPI v2.6 and later)
3884****************************************************************************/
3885
3886/*PCIe Link Page 1 */
3887
3888typedef struct _MPI26_CONFIG_PAGE_PCIELINK_1 {
3889 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3890 U8 Link; /*0x08 */
3891 U8 Reserved1; /*0x09 */
3892 U16 Reserved2; /*0x0A */
3893 U32 CorrectableErrorCount; /*0x0C */
3894 U16 NonFatalErrorCount; /*0x10 */
3895 U16 Reserved3; /*0x12 */
3896 U16 FatalErrorCount; /*0x14 */
3897 U16 Reserved4; /*0x16 */
3898} MPI26_CONFIG_PAGE_PCIELINK_1, *PTR_MPI26_CONFIG_PAGE_PCIELINK_1,
3899 Mpi26PcieLinkPage1_t, *pMpi26PcieLinkPage1_t;
3900
3901#define MPI26_PCIELINK1_PAGEVERSION (0x00)
3902
3903/*PCIe Link Page 2 */
3904
3905typedef struct _MPI26_PCIELINK2_LINK_EVENT {
3906 U8 LinkEventCode; /*0x00 */
3907 U8 Reserved1; /*0x01 */
3908 U16 Reserved2; /*0x02 */
3909 U32 LinkEventInfo; /*0x04 */
3910} MPI26_PCIELINK2_LINK_EVENT, *PTR_MPI26_PCIELINK2_LINK_EVENT,
3911 Mpi26PcieLink2LinkEvent_t, *pMpi26PcieLink2LinkEvent_t;
3912
3913/*use MPI26_PCIELINK3_EVTCODE_ for the LinkEventCode field */
3914
3915
3916/*
3917 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
3918 *for NumLinkEvents at runtime before using LinkEvent[].
3919 */
3920
3921typedef struct _MPI26_CONFIG_PAGE_PCIELINK_2 {
3922 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3923 U8 Link; /*0x08 */
3924 U8 Reserved1; /*0x09 */
3925 U16 Reserved2; /*0x0A */
3926 U8 NumLinkEvents; /*0x0C */
3927 U8 Reserved3; /*0x0D */
3928 U16 Reserved4; /*0x0E */
3929 MPI26_PCIELINK2_LINK_EVENT
3930 LinkEvent[]; /*0x10 */
3931} MPI26_CONFIG_PAGE_PCIELINK_2, *PTR_MPI26_CONFIG_PAGE_PCIELINK_2,
3932 Mpi26PcieLinkPage2_t, *pMpi26PcieLinkPage2_t;
3933
3934#define MPI26_PCIELINK2_PAGEVERSION (0x00)
3935
3936/*PCIe Link Page 3 */
3937
3938typedef struct _MPI26_PCIELINK3_LINK_EVENT_CONFIG {
3939 U8 LinkEventCode; /*0x00 */
3940 U8 Reserved1; /*0x01 */
3941 U16 Reserved2; /*0x02 */
3942 U8 CounterType; /*0x04 */
3943 U8 ThresholdWindow; /*0x05 */
3944 U8 TimeUnits; /*0x06 */
3945 U8 Reserved3; /*0x07 */
3946 U32 EventThreshold; /*0x08 */
3947 U16 ThresholdFlags; /*0x0C */
3948 U16 Reserved4; /*0x0E */
3949} MPI26_PCIELINK3_LINK_EVENT_CONFIG, *PTR_MPI26_PCIELINK3_LINK_EVENT_CONFIG,
3950 Mpi26PcieLink3LinkEventConfig_t, *pMpi26PcieLink3LinkEventConfig_t;
3951
3952/*values for LinkEventCode field */
3953#define MPI26_PCIELINK3_EVTCODE_NO_EVENT (0x00)
3954#define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED (0x01)
3955#define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED (0x02)
3956#define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED (0x03)
3957#define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED (0x04)
3958#define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED (0x05)
3959#define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED (0x06)
3960#define MPI26_PCIELINK3_EVTCODE_POISONED_TLP (0x07)
3961#define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP (0x08)
3962#define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP (0x09)
3963#define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE (0x0A)
3964#define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE (0x0B)
3965#define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE (0x0C)
3966#define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE (0x0D)
3967#define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE (0x0E)
3968#define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE (0x0F)
3969#define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR (0x10)
3970#define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR (0x11)
3971#define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR (0x12)
3972
3973/*values for the CounterType field */
3974#define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING (0x00)
3975#define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING (0x01)
3976#define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE (0x02)
3977
3978/*values for the TimeUnits field */
3979#define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS (0x00)
3980#define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS (0x01)
3981#define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND (0x02)
3982#define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS (0x03)
3983
3984/*values for the ThresholdFlags field */
3985#define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY (0x0001)
3986
3987/*
3988 *Host code (drivers, BIOS, utilities, etc.) should check the value returned
3989 *for NumLinkEvents at runtime before using LinkEventConfig[].
3990 */
3991
3992typedef struct _MPI26_CONFIG_PAGE_PCIELINK_3 {
3993 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3994 U8 Link; /*0x08 */
3995 U8 Reserved1; /*0x09 */
3996 U16 Reserved2; /*0x0A */
3997 U8 NumLinkEvents; /*0x0C */
3998 U8 Reserved3; /*0x0D */
3999 U16 Reserved4; /*0x0E */
4000 MPI26_PCIELINK3_LINK_EVENT_CONFIG
4001 LinkEventConfig[]; /*0x10 */
4002} MPI26_CONFIG_PAGE_PCIELINK_3, *PTR_MPI26_CONFIG_PAGE_PCIELINK_3,
4003 Mpi26PcieLinkPage3_t, *pMpi26PcieLinkPage3_t;
4004
4005#define MPI26_PCIELINK3_PAGEVERSION (0x00)
4006
4007
4008#endif