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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
4 *
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
6 *
7 */
8#include <linux/clk.h>
9#include <linux/iopoll.h>
10#include <linux/of.h>
11#include <linux/module.h>
12#include <linux/pm_runtime.h>
13#include <linux/property.h>
14#include <linux/regmap.h>
15#include <linux/sys_soc.h>
16
17#include "cqhci.h"
18#include "sdhci-cqhci.h"
19#include "sdhci-pltfm.h"
20
21/* CTL_CFG Registers */
22#define CTL_CFG_2 0x14
23#define CTL_CFG_3 0x18
24
25#define SLOTTYPE_MASK GENMASK(31, 30)
26#define SLOTTYPE_EMBEDDED BIT(30)
27#define TUNINGFORSDR50_MASK BIT(13)
28
29/* PHY Registers */
30#define PHY_CTRL1 0x100
31#define PHY_CTRL2 0x104
32#define PHY_CTRL3 0x108
33#define PHY_CTRL4 0x10C
34#define PHY_CTRL5 0x110
35#define PHY_CTRL6 0x114
36#define PHY_STAT1 0x130
37#define PHY_STAT2 0x134
38
39#define IOMUX_ENABLE_SHIFT 31
40#define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
41#define OTAPDLYENA_SHIFT 20
42#define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
43#define OTAPDLYSEL_SHIFT 12
44#define OTAPDLYSEL_MASK GENMASK(15, 12)
45#define STRBSEL_SHIFT 24
46#define STRBSEL_4BIT_MASK GENMASK(27, 24)
47#define STRBSEL_8BIT_MASK GENMASK(31, 24)
48#define SEL50_SHIFT 8
49#define SEL50_MASK BIT(SEL50_SHIFT)
50#define SEL100_SHIFT 9
51#define SEL100_MASK BIT(SEL100_SHIFT)
52#define FREQSEL_SHIFT 8
53#define FREQSEL_MASK GENMASK(10, 8)
54#define CLKBUFSEL_SHIFT 0
55#define CLKBUFSEL_MASK GENMASK(2, 0)
56#define DLL_TRIM_ICP_SHIFT 4
57#define DLL_TRIM_ICP_MASK GENMASK(7, 4)
58#define DR_TY_SHIFT 20
59#define DR_TY_MASK GENMASK(22, 20)
60#define ENDLL_SHIFT 1
61#define ENDLL_MASK BIT(ENDLL_SHIFT)
62#define DLLRDY_SHIFT 0
63#define DLLRDY_MASK BIT(DLLRDY_SHIFT)
64#define PDB_SHIFT 0
65#define PDB_MASK BIT(PDB_SHIFT)
66#define CALDONE_SHIFT 1
67#define CALDONE_MASK BIT(CALDONE_SHIFT)
68#define RETRIM_SHIFT 17
69#define RETRIM_MASK BIT(RETRIM_SHIFT)
70#define SELDLYTXCLK_SHIFT 17
71#define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
72#define SELDLYRXCLK_SHIFT 16
73#define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
74#define ITAPDLYSEL_SHIFT 0
75#define ITAPDLYSEL_MASK GENMASK(4, 0)
76#define ITAPDLYENA_SHIFT 8
77#define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT)
78#define ITAPCHGWIN_SHIFT 9
79#define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT)
80
81#define DRIVER_STRENGTH_50_OHM 0x0
82#define DRIVER_STRENGTH_33_OHM 0x1
83#define DRIVER_STRENGTH_66_OHM 0x2
84#define DRIVER_STRENGTH_100_OHM 0x3
85#define DRIVER_STRENGTH_40_OHM 0x4
86
87#define CLOCK_TOO_SLOW_HZ 50000000
88#define SDHCI_AM654_AUTOSUSPEND_DELAY -1
89
90/* Command Queue Host Controller Interface Base address */
91#define SDHCI_AM654_CQE_BASE_ADDR 0x200
92
93static struct regmap_config sdhci_am654_regmap_config = {
94 .reg_bits = 32,
95 .val_bits = 32,
96 .reg_stride = 4,
97 .fast_io = true,
98};
99
100struct timing_data {
101 const char *otap_binding;
102 const char *itap_binding;
103 u32 capability;
104};
105
106static const struct timing_data td[] = {
107 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
108 "ti,itap-del-sel-legacy",
109 0},
110 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
111 "ti,itap-del-sel-mmc-hs",
112 MMC_CAP_MMC_HIGHSPEED},
113 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs",
114 "ti,itap-del-sel-sd-hs",
115 MMC_CAP_SD_HIGHSPEED},
116 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12",
117 "ti,itap-del-sel-sdr12",
118 MMC_CAP_UHS_SDR12},
119 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25",
120 "ti,itap-del-sel-sdr25",
121 MMC_CAP_UHS_SDR25},
122 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50",
123 NULL,
124 MMC_CAP_UHS_SDR50},
125 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
126 NULL,
127 MMC_CAP_UHS_SDR104},
128 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
129 NULL,
130 MMC_CAP_UHS_DDR50},
131 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
132 "ti,itap-del-sel-ddr52",
133 MMC_CAP_DDR},
134 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200",
135 NULL,
136 MMC_CAP2_HS200},
137 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400",
138 NULL,
139 MMC_CAP2_HS400},
140};
141
142struct sdhci_am654_data {
143 struct regmap *base;
144 int otap_del_sel[ARRAY_SIZE(td)];
145 int itap_del_sel[ARRAY_SIZE(td)];
146 int clkbuf_sel;
147 int trm_icp;
148 int drv_strength;
149 int strb_sel;
150 u32 flags;
151 u32 quirks;
152
153#define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0)
154};
155
156struct sdhci_am654_driver_data {
157 const struct sdhci_pltfm_data *pdata;
158 u32 flags;
159#define IOMUX_PRESENT (1 << 0)
160#define FREQSEL_2_BIT (1 << 1)
161#define STRBSEL_4_BIT (1 << 2)
162#define DLL_PRESENT (1 << 3)
163#define DLL_CALIB (1 << 4)
164};
165
166static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock)
167{
168 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
169 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
170 int sel50, sel100, freqsel;
171 u32 mask, val;
172 int ret;
173
174 /* Disable delay chain mode */
175 regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
176 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);
177
178 if (sdhci_am654->flags & FREQSEL_2_BIT) {
179 switch (clock) {
180 case 200000000:
181 sel50 = 0;
182 sel100 = 0;
183 break;
184 case 100000000:
185 sel50 = 0;
186 sel100 = 1;
187 break;
188 default:
189 sel50 = 1;
190 sel100 = 0;
191 }
192
193 /* Configure PHY DLL frequency */
194 mask = SEL50_MASK | SEL100_MASK;
195 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
196 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
197
198 } else {
199 switch (clock) {
200 case 200000000:
201 freqsel = 0x0;
202 break;
203 default:
204 freqsel = 0x4;
205 }
206
207 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK,
208 freqsel << FREQSEL_SHIFT);
209 }
210 /* Configure DLL TRIM */
211 mask = DLL_TRIM_ICP_MASK;
212 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
213
214 /* Configure DLL driver strength */
215 mask |= DR_TY_MASK;
216 val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
217 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
218
219 /* Enable DLL */
220 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
221 0x1 << ENDLL_SHIFT);
222 /*
223 * Poll for DLL ready. Use a one second timeout.
224 * Works in all experiments done so far
225 */
226 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val,
227 val & DLLRDY_MASK, 1000, 1000000);
228 if (ret) {
229 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
230 return;
231 }
232}
233
234static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654,
235 u32 itapdly)
236{
237 /* Set ITAPCHGWIN before writing to ITAPDLY */
238 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
239 1 << ITAPCHGWIN_SHIFT);
240 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,
241 itapdly << ITAPDLYSEL_SHIFT);
242 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
243}
244
245static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654,
246 unsigned char timing)
247{
248 u32 mask, val;
249
250 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
251
252 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;
253 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
254 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
255
256 sdhci_am654_write_itapdly(sdhci_am654,
257 sdhci_am654->itap_del_sel[timing]);
258}
259
260static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
261{
262 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
263 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
264 unsigned char timing = host->mmc->ios.timing;
265 u32 otap_del_sel;
266 u32 otap_del_ena;
267 u32 mask, val;
268
269 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
270
271 sdhci_set_clock(host, clock);
272
273 /* Setup DLL Output TAP delay */
274 otap_del_sel = sdhci_am654->otap_del_sel[timing];
275 otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0;
276
277 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
278 val = (otap_del_ena << OTAPDLYENA_SHIFT) |
279 (otap_del_sel << OTAPDLYSEL_SHIFT);
280
281 /* Write to STRBSEL for HS400 speed mode */
282 if (timing == MMC_TIMING_MMC_HS400) {
283 if (sdhci_am654->flags & STRBSEL_4_BIT)
284 mask |= STRBSEL_4BIT_MASK;
285 else
286 mask |= STRBSEL_8BIT_MASK;
287
288 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;
289 }
290
291 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
292
293 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ)
294 sdhci_am654_setup_dll(host, clock);
295 else
296 sdhci_am654_setup_delay_chain(sdhci_am654, timing);
297
298 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
299 sdhci_am654->clkbuf_sel);
300}
301
302static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
303 unsigned int clock)
304{
305 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
306 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
307 unsigned char timing = host->mmc->ios.timing;
308 u32 otap_del_sel;
309 u32 mask, val;
310
311 /* Setup DLL Output TAP delay */
312 otap_del_sel = sdhci_am654->otap_del_sel[timing];
313
314 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
315 val = (0x1 << OTAPDLYENA_SHIFT) |
316 (otap_del_sel << OTAPDLYSEL_SHIFT);
317 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
318
319 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
320 sdhci_am654->clkbuf_sel);
321
322 sdhci_set_clock(host, clock);
323}
324
325static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg)
326{
327 writeb(val, host->ioaddr + reg);
328 usleep_range(1000, 10000);
329 return readb(host->ioaddr + reg);
330}
331
332#define MAX_POWER_ON_TIMEOUT 1500000 /* us */
333static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
334{
335 unsigned char timing = host->mmc->ios.timing;
336 u8 pwr;
337 int ret;
338
339 if (reg == SDHCI_HOST_CONTROL) {
340 switch (timing) {
341 /*
342 * According to the data manual, HISPD bit
343 * should not be set in these speed modes.
344 */
345 case MMC_TIMING_SD_HS:
346 case MMC_TIMING_MMC_HS:
347 val &= ~SDHCI_CTRL_HISPD;
348 }
349 }
350
351 writeb(val, host->ioaddr + reg);
352 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) {
353 /*
354 * Power on will not happen until the card detect debounce
355 * timer expires. Wait at least 1.5 seconds for the power on
356 * bit to be set
357 */
358 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr,
359 pwr & SDHCI_POWER_ON, 0,
360 MAX_POWER_ON_TIMEOUT, false, host, val,
361 reg);
362 if (ret)
363 dev_info(mmc_dev(host->mmc), "Power on failed\n");
364 }
365}
366
367static void sdhci_am654_reset(struct sdhci_host *host, u8 mask)
368{
369 u8 ctrl;
370 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
371 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
372
373 sdhci_and_cqhci_reset(host, mask);
374
375 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) {
376 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
377 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
378 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
379 }
380}
381
382static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode)
383{
384 struct sdhci_host *host = mmc_priv(mmc);
385 int err = sdhci_execute_tuning(mmc, opcode);
386
387 if (err)
388 return err;
389 /*
390 * Tuning data remains in the buffer after tuning.
391 * Do a command and data reset to get rid of it
392 */
393 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
394
395 return 0;
396}
397
398static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask)
399{
400 int cmd_error = 0;
401 int data_error = 0;
402
403 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
404 return intmask;
405
406 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
407
408 return 0;
409}
410
411#define ITAP_MAX 32
412static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host,
413 u32 opcode)
414{
415 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
416 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
417 int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len;
418 u32 itap;
419
420 /* Enable ITAPDLY */
421 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
422 1 << ITAPDLYENA_SHIFT);
423
424 for (itap = 0; itap < ITAP_MAX; itap++) {
425 sdhci_am654_write_itapdly(sdhci_am654, itap);
426
427 cur_val = !mmc_send_tuning(host->mmc, opcode, NULL);
428 if (cur_val && !prev_val)
429 pass_window = itap;
430
431 if (!cur_val)
432 fail_len++;
433
434 prev_val = cur_val;
435 }
436 /*
437 * Having determined the length of the failing window and start of
438 * the passing window calculate the length of the passing window and
439 * set the final value halfway through it considering the range as a
440 * circular buffer
441 */
442 pass_len = ITAP_MAX - fail_len;
443 itap = (pass_window + (pass_len >> 1)) % ITAP_MAX;
444 sdhci_am654_write_itapdly(sdhci_am654, itap);
445
446 return 0;
447}
448
449static struct sdhci_ops sdhci_am654_ops = {
450 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
451 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
452 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
453 .set_uhs_signaling = sdhci_set_uhs_signaling,
454 .set_bus_width = sdhci_set_bus_width,
455 .set_power = sdhci_set_power_and_bus_voltage,
456 .set_clock = sdhci_am654_set_clock,
457 .write_b = sdhci_am654_write_b,
458 .irq = sdhci_am654_cqhci_irq,
459 .reset = sdhci_and_cqhci_reset,
460};
461
462static const struct sdhci_pltfm_data sdhci_am654_pdata = {
463 .ops = &sdhci_am654_ops,
464 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
465 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
466};
467
468static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = {
469 .pdata = &sdhci_am654_pdata,
470 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT |
471 DLL_CALIB,
472};
473
474static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
475 .pdata = &sdhci_am654_pdata,
476 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
477};
478
479static struct sdhci_ops sdhci_j721e_8bit_ops = {
480 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
481 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
482 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
483 .set_uhs_signaling = sdhci_set_uhs_signaling,
484 .set_bus_width = sdhci_set_bus_width,
485 .set_power = sdhci_set_power_and_bus_voltage,
486 .set_clock = sdhci_am654_set_clock,
487 .write_b = sdhci_am654_write_b,
488 .irq = sdhci_am654_cqhci_irq,
489 .reset = sdhci_and_cqhci_reset,
490};
491
492static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
493 .ops = &sdhci_j721e_8bit_ops,
494 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
495 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
496};
497
498static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
499 .pdata = &sdhci_j721e_8bit_pdata,
500 .flags = DLL_PRESENT | DLL_CALIB,
501};
502
503static struct sdhci_ops sdhci_j721e_4bit_ops = {
504 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
505 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
506 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
507 .set_uhs_signaling = sdhci_set_uhs_signaling,
508 .set_bus_width = sdhci_set_bus_width,
509 .set_power = sdhci_set_power_and_bus_voltage,
510 .set_clock = sdhci_j721e_4bit_set_clock,
511 .write_b = sdhci_am654_write_b,
512 .irq = sdhci_am654_cqhci_irq,
513 .reset = sdhci_am654_reset,
514};
515
516static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = {
517 .ops = &sdhci_j721e_4bit_ops,
518 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
519 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
520};
521
522static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = {
523 .pdata = &sdhci_j721e_4bit_pdata,
524 .flags = IOMUX_PRESENT,
525};
526
527static const struct soc_device_attribute sdhci_am654_devices[] = {
528 { .family = "AM65X",
529 .revision = "SR1.0",
530 .data = &sdhci_am654_sr1_drvdata
531 },
532 {/* sentinel */}
533};
534
535static void sdhci_am654_dumpregs(struct mmc_host *mmc)
536{
537 sdhci_dumpregs(mmc_priv(mmc));
538}
539
540static const struct cqhci_host_ops sdhci_am654_cqhci_ops = {
541 .enable = sdhci_cqe_enable,
542 .disable = sdhci_cqe_disable,
543 .dumpregs = sdhci_am654_dumpregs,
544};
545
546static int sdhci_am654_cqe_add_host(struct sdhci_host *host)
547{
548 struct cqhci_host *cq_host;
549
550 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host),
551 GFP_KERNEL);
552 if (!cq_host)
553 return -ENOMEM;
554
555 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR;
556 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
557 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
558 cq_host->ops = &sdhci_am654_cqhci_ops;
559
560 host->mmc->caps2 |= MMC_CAP2_CQE;
561
562 return cqhci_init(cq_host, host->mmc, 1);
563}
564
565static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
566 struct sdhci_am654_data *sdhci_am654)
567{
568 struct device *dev = mmc_dev(host->mmc);
569 int i;
570 int ret;
571
572 for (i = MMC_TIMING_LEGACY; i <= MMC_TIMING_MMC_HS400; i++) {
573
574 ret = device_property_read_u32(dev, td[i].otap_binding,
575 &sdhci_am654->otap_del_sel[i]);
576 if (ret) {
577 if (i == MMC_TIMING_LEGACY) {
578 dev_err(dev, "Couldn't find mandatory ti,otap-del-sel-legacy\n");
579 return ret;
580 }
581 dev_dbg(dev, "Couldn't find %s\n",
582 td[i].otap_binding);
583 /*
584 * Remove the corresponding capability
585 * if an otap-del-sel value is not found
586 */
587 if (i <= MMC_TIMING_MMC_DDR52)
588 host->mmc->caps &= ~td[i].capability;
589 else
590 host->mmc->caps2 &= ~td[i].capability;
591 }
592
593 if (td[i].itap_binding)
594 device_property_read_u32(dev, td[i].itap_binding,
595 &sdhci_am654->itap_del_sel[i]);
596 }
597
598 return 0;
599}
600
601static int sdhci_am654_init(struct sdhci_host *host)
602{
603 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
604 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
605 u32 ctl_cfg_2 = 0;
606 u32 mask;
607 u32 val;
608 int ret;
609
610 /* Reset OTAP to default value */
611 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
612 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
613
614 if (sdhci_am654->flags & DLL_CALIB) {
615 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
616 if (~val & CALDONE_MASK) {
617 /* Calibrate IO lines */
618 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
619 PDB_MASK, PDB_MASK);
620 ret = regmap_read_poll_timeout(sdhci_am654->base,
621 PHY_STAT1, val,
622 val & CALDONE_MASK,
623 1, 20);
624 if (ret)
625 return ret;
626 }
627 }
628
629 /* Enable pins by setting IO mux to 0 */
630 if (sdhci_am654->flags & IOMUX_PRESENT)
631 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
632 IOMUX_ENABLE_MASK, 0);
633
634 /* Set slot type based on SD or eMMC */
635 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
636 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
637
638 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
639 ctl_cfg_2);
640
641 /* Enable tuning for SDR50 */
642 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
643 TUNINGFORSDR50_MASK);
644
645 ret = sdhci_setup_host(host);
646 if (ret)
647 return ret;
648
649 ret = sdhci_am654_cqe_add_host(host);
650 if (ret)
651 goto err_cleanup_host;
652
653 ret = sdhci_am654_get_otap_delay(host, sdhci_am654);
654 if (ret)
655 goto err_cleanup_host;
656
657 ret = __sdhci_add_host(host);
658 if (ret)
659 goto err_cleanup_host;
660
661 return 0;
662
663err_cleanup_host:
664 sdhci_cleanup_host(host);
665 return ret;
666}
667
668static int sdhci_am654_get_of_property(struct platform_device *pdev,
669 struct sdhci_am654_data *sdhci_am654)
670{
671 struct device *dev = &pdev->dev;
672 int drv_strength;
673 int ret;
674
675 if (sdhci_am654->flags & DLL_PRESENT) {
676 ret = device_property_read_u32(dev, "ti,trm-icp",
677 &sdhci_am654->trm_icp);
678 if (ret)
679 return ret;
680
681 ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
682 &drv_strength);
683 if (ret)
684 return ret;
685
686 switch (drv_strength) {
687 case 50:
688 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
689 break;
690 case 33:
691 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
692 break;
693 case 66:
694 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
695 break;
696 case 100:
697 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
698 break;
699 case 40:
700 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
701 break;
702 default:
703 dev_err(dev, "Invalid driver strength\n");
704 return -EINVAL;
705 }
706 }
707
708 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
709 device_property_read_u32(dev, "ti,clkbuf-sel",
710 &sdhci_am654->clkbuf_sel);
711
712 if (device_property_read_bool(dev, "ti,fails-without-test-cd"))
713 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST;
714
715 sdhci_get_of_property(pdev);
716
717 return 0;
718}
719
720static const struct of_device_id sdhci_am654_of_match[] = {
721 {
722 .compatible = "ti,am654-sdhci-5.1",
723 .data = &sdhci_am654_drvdata,
724 },
725 {
726 .compatible = "ti,j721e-sdhci-8bit",
727 .data = &sdhci_j721e_8bit_drvdata,
728 },
729 {
730 .compatible = "ti,j721e-sdhci-4bit",
731 .data = &sdhci_j721e_4bit_drvdata,
732 },
733 {
734 .compatible = "ti,am64-sdhci-8bit",
735 .data = &sdhci_j721e_8bit_drvdata,
736 },
737 {
738 .compatible = "ti,am64-sdhci-4bit",
739 .data = &sdhci_j721e_4bit_drvdata,
740 },
741 {
742 .compatible = "ti,am62-sdhci",
743 .data = &sdhci_j721e_4bit_drvdata,
744 },
745 { /* sentinel */ }
746};
747MODULE_DEVICE_TABLE(of, sdhci_am654_of_match);
748
749static int sdhci_am654_probe(struct platform_device *pdev)
750{
751 const struct sdhci_am654_driver_data *drvdata;
752 const struct soc_device_attribute *soc;
753 struct sdhci_pltfm_host *pltfm_host;
754 struct sdhci_am654_data *sdhci_am654;
755 const struct of_device_id *match;
756 struct sdhci_host *host;
757 struct clk *clk_xin;
758 struct device *dev = &pdev->dev;
759 void __iomem *base;
760 int ret;
761
762 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);
763 drvdata = match->data;
764
765 /* Update drvdata based on SoC revision */
766 soc = soc_device_match(sdhci_am654_devices);
767 if (soc && soc->data)
768 drvdata = soc->data;
769
770 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
771 if (IS_ERR(host))
772 return PTR_ERR(host);
773
774 pltfm_host = sdhci_priv(host);
775 sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
776 sdhci_am654->flags = drvdata->flags;
777
778 clk_xin = devm_clk_get(dev, "clk_xin");
779 if (IS_ERR(clk_xin)) {
780 dev_err(dev, "clk_xin clock not found.\n");
781 ret = PTR_ERR(clk_xin);
782 goto err_pltfm_free;
783 }
784
785 pltfm_host->clk = clk_xin;
786
787 base = devm_platform_ioremap_resource(pdev, 1);
788 if (IS_ERR(base)) {
789 ret = PTR_ERR(base);
790 goto err_pltfm_free;
791 }
792
793 sdhci_am654->base = devm_regmap_init_mmio(dev, base,
794 &sdhci_am654_regmap_config);
795 if (IS_ERR(sdhci_am654->base)) {
796 dev_err(dev, "Failed to initialize regmap\n");
797 ret = PTR_ERR(sdhci_am654->base);
798 goto err_pltfm_free;
799 }
800
801 ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
802 if (ret)
803 goto err_pltfm_free;
804
805 ret = mmc_of_parse(host->mmc);
806 if (ret) {
807 dev_err_probe(dev, ret, "parsing dt failed\n");
808 goto err_pltfm_free;
809 }
810
811 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;
812
813 pm_runtime_get_noresume(dev);
814 ret = pm_runtime_set_active(dev);
815 if (ret)
816 goto pm_put;
817 pm_runtime_enable(dev);
818 ret = clk_prepare_enable(pltfm_host->clk);
819 if (ret)
820 goto pm_disable;
821
822 ret = sdhci_am654_init(host);
823 if (ret)
824 goto clk_disable;
825
826 /* Setting up autosuspend */
827 pm_runtime_set_autosuspend_delay(dev, SDHCI_AM654_AUTOSUSPEND_DELAY);
828 pm_runtime_use_autosuspend(dev);
829 pm_runtime_mark_last_busy(dev);
830 pm_runtime_put_autosuspend(dev);
831 return 0;
832
833clk_disable:
834 clk_disable_unprepare(pltfm_host->clk);
835pm_disable:
836 pm_runtime_disable(dev);
837pm_put:
838 pm_runtime_put_noidle(dev);
839err_pltfm_free:
840 sdhci_pltfm_free(pdev);
841 return ret;
842}
843
844static void sdhci_am654_remove(struct platform_device *pdev)
845{
846 struct sdhci_host *host = platform_get_drvdata(pdev);
847 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
848 struct device *dev = &pdev->dev;
849 int ret;
850
851 ret = pm_runtime_get_sync(dev);
852 if (ret < 0)
853 dev_err(dev, "pm_runtime_get_sync() Failed\n");
854
855 sdhci_remove_host(host, true);
856 clk_disable_unprepare(pltfm_host->clk);
857 pm_runtime_disable(dev);
858 pm_runtime_put_noidle(dev);
859 sdhci_pltfm_free(pdev);
860}
861
862#ifdef CONFIG_PM
863static int sdhci_am654_restore(struct sdhci_host *host)
864{
865 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
866 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
867 u32 ctl_cfg_2 = 0;
868 u32 val;
869 int ret;
870
871 if (sdhci_am654->flags & DLL_CALIB) {
872 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
873 if (~val & CALDONE_MASK) {
874 /* Calibrate IO lines */
875 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
876 PDB_MASK, PDB_MASK);
877 ret = regmap_read_poll_timeout(sdhci_am654->base,
878 PHY_STAT1, val,
879 val & CALDONE_MASK,
880 1, 20);
881 if (ret)
882 return ret;
883 }
884 }
885
886 /* Enable pins by setting IO mux to 0 */
887 if (sdhci_am654->flags & IOMUX_PRESENT)
888 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
889 IOMUX_ENABLE_MASK, 0);
890
891 /* Set slot type based on SD or eMMC */
892 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
893 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
894
895 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
896 ctl_cfg_2);
897
898 regmap_read(sdhci_am654->base, CTL_CFG_3, &val);
899 if (~val & TUNINGFORSDR50_MASK)
900 /* Enable tuning for SDR50 */
901 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
902 TUNINGFORSDR50_MASK);
903
904 return 0;
905}
906
907static int sdhci_am654_runtime_suspend(struct device *dev)
908{
909 struct sdhci_host *host = dev_get_drvdata(dev);
910 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
911 int ret;
912
913 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
914 mmc_retune_needed(host->mmc);
915
916 ret = cqhci_suspend(host->mmc);
917 if (ret)
918 return ret;
919
920 ret = sdhci_runtime_suspend_host(host);
921 if (ret)
922 return ret;
923
924 /* disable the clock */
925 clk_disable_unprepare(pltfm_host->clk);
926 return 0;
927}
928
929static int sdhci_am654_runtime_resume(struct device *dev)
930{
931 struct sdhci_host *host = dev_get_drvdata(dev);
932 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
933 int ret;
934
935 /* Enable the clock */
936 ret = clk_prepare_enable(pltfm_host->clk);
937 if (ret)
938 return ret;
939
940 ret = sdhci_am654_restore(host);
941 if (ret)
942 return ret;
943
944 ret = sdhci_runtime_resume_host(host, 0);
945 if (ret)
946 return ret;
947
948 ret = cqhci_resume(host->mmc);
949 if (ret)
950 return ret;
951
952 return 0;
953}
954#endif
955
956static const struct dev_pm_ops sdhci_am654_dev_pm_ops = {
957 SET_RUNTIME_PM_OPS(sdhci_am654_runtime_suspend,
958 sdhci_am654_runtime_resume, NULL)
959 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
960 pm_runtime_force_resume)
961};
962
963static struct platform_driver sdhci_am654_driver = {
964 .driver = {
965 .name = "sdhci-am654",
966 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
967 .pm = &sdhci_am654_dev_pm_ops,
968 .of_match_table = sdhci_am654_of_match,
969 },
970 .probe = sdhci_am654_probe,
971 .remove_new = sdhci_am654_remove,
972};
973
974module_platform_driver(sdhci_am654_driver);
975
976MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
977MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
978MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
4 *
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
6 *
7 */
8#include <linux/clk.h>
9#include <linux/iopoll.h>
10#include <linux/of.h>
11#include <linux/module.h>
12#include <linux/pm_runtime.h>
13#include <linux/property.h>
14#include <linux/regmap.h>
15#include <linux/sys_soc.h>
16
17#include "cqhci.h"
18#include "sdhci-cqhci.h"
19#include "sdhci-pltfm.h"
20
21/* CTL_CFG Registers */
22#define CTL_CFG_2 0x14
23#define CTL_CFG_3 0x18
24
25#define SLOTTYPE_MASK GENMASK(31, 30)
26#define SLOTTYPE_EMBEDDED BIT(30)
27#define TUNINGFORSDR50_MASK BIT(13)
28
29/* PHY Registers */
30#define PHY_CTRL1 0x100
31#define PHY_CTRL2 0x104
32#define PHY_CTRL3 0x108
33#define PHY_CTRL4 0x10C
34#define PHY_CTRL5 0x110
35#define PHY_CTRL6 0x114
36#define PHY_STAT1 0x130
37#define PHY_STAT2 0x134
38
39#define IOMUX_ENABLE_SHIFT 31
40#define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
41#define OTAPDLYENA_SHIFT 20
42#define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
43#define OTAPDLYSEL_SHIFT 12
44#define OTAPDLYSEL_MASK GENMASK(15, 12)
45#define STRBSEL_SHIFT 24
46#define STRBSEL_4BIT_MASK GENMASK(27, 24)
47#define STRBSEL_8BIT_MASK GENMASK(31, 24)
48#define SEL50_SHIFT 8
49#define SEL50_MASK BIT(SEL50_SHIFT)
50#define SEL100_SHIFT 9
51#define SEL100_MASK BIT(SEL100_SHIFT)
52#define FREQSEL_SHIFT 8
53#define FREQSEL_MASK GENMASK(10, 8)
54#define CLKBUFSEL_SHIFT 0
55#define CLKBUFSEL_MASK GENMASK(2, 0)
56#define DLL_TRIM_ICP_SHIFT 4
57#define DLL_TRIM_ICP_MASK GENMASK(7, 4)
58#define DR_TY_SHIFT 20
59#define DR_TY_MASK GENMASK(22, 20)
60#define ENDLL_SHIFT 1
61#define ENDLL_MASK BIT(ENDLL_SHIFT)
62#define DLLRDY_SHIFT 0
63#define DLLRDY_MASK BIT(DLLRDY_SHIFT)
64#define PDB_SHIFT 0
65#define PDB_MASK BIT(PDB_SHIFT)
66#define CALDONE_SHIFT 1
67#define CALDONE_MASK BIT(CALDONE_SHIFT)
68#define RETRIM_SHIFT 17
69#define RETRIM_MASK BIT(RETRIM_SHIFT)
70#define SELDLYTXCLK_SHIFT 17
71#define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
72#define SELDLYRXCLK_SHIFT 16
73#define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
74#define ITAPDLYSEL_SHIFT 0
75#define ITAPDLYSEL_MASK GENMASK(4, 0)
76#define ITAPDLYENA_SHIFT 8
77#define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT)
78#define ITAPCHGWIN_SHIFT 9
79#define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT)
80
81#define DRIVER_STRENGTH_50_OHM 0x0
82#define DRIVER_STRENGTH_33_OHM 0x1
83#define DRIVER_STRENGTH_66_OHM 0x2
84#define DRIVER_STRENGTH_100_OHM 0x3
85#define DRIVER_STRENGTH_40_OHM 0x4
86
87#define CLOCK_TOO_SLOW_HZ 50000000
88#define SDHCI_AM654_AUTOSUSPEND_DELAY -1
89
90/* Command Queue Host Controller Interface Base address */
91#define SDHCI_AM654_CQE_BASE_ADDR 0x200
92
93static struct regmap_config sdhci_am654_regmap_config = {
94 .reg_bits = 32,
95 .val_bits = 32,
96 .reg_stride = 4,
97 .fast_io = true,
98};
99
100struct timing_data {
101 const char *otap_binding;
102 const char *itap_binding;
103 u32 capability;
104};
105
106static const struct timing_data td[] = {
107 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
108 "ti,itap-del-sel-legacy",
109 0},
110 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
111 "ti,itap-del-sel-mmc-hs",
112 MMC_CAP_MMC_HIGHSPEED},
113 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs",
114 "ti,itap-del-sel-sd-hs",
115 MMC_CAP_SD_HIGHSPEED},
116 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12",
117 "ti,itap-del-sel-sdr12",
118 MMC_CAP_UHS_SDR12},
119 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25",
120 "ti,itap-del-sel-sdr25",
121 MMC_CAP_UHS_SDR25},
122 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50",
123 NULL,
124 MMC_CAP_UHS_SDR50},
125 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
126 NULL,
127 MMC_CAP_UHS_SDR104},
128 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
129 NULL,
130 MMC_CAP_UHS_DDR50},
131 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
132 "ti,itap-del-sel-ddr52",
133 MMC_CAP_DDR},
134 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200",
135 NULL,
136 MMC_CAP2_HS200},
137 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400",
138 NULL,
139 MMC_CAP2_HS400},
140};
141
142struct sdhci_am654_data {
143 struct regmap *base;
144 int otap_del_sel[ARRAY_SIZE(td)];
145 int itap_del_sel[ARRAY_SIZE(td)];
146 u32 itap_del_ena[ARRAY_SIZE(td)];
147 int clkbuf_sel;
148 int trm_icp;
149 int drv_strength;
150 int strb_sel;
151 u32 flags;
152 u32 quirks;
153 bool dll_enable;
154
155#define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0)
156};
157
158struct window {
159 u8 start;
160 u8 end;
161 u8 length;
162};
163
164struct sdhci_am654_driver_data {
165 const struct sdhci_pltfm_data *pdata;
166 u32 flags;
167#define IOMUX_PRESENT (1 << 0)
168#define FREQSEL_2_BIT (1 << 1)
169#define STRBSEL_4_BIT (1 << 2)
170#define DLL_PRESENT (1 << 3)
171#define DLL_CALIB (1 << 4)
172};
173
174static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock)
175{
176 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
177 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
178 int sel50, sel100, freqsel;
179 u32 mask, val;
180 int ret;
181
182 /* Disable delay chain mode */
183 regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
184 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);
185
186 if (sdhci_am654->flags & FREQSEL_2_BIT) {
187 switch (clock) {
188 case 200000000:
189 sel50 = 0;
190 sel100 = 0;
191 break;
192 case 100000000:
193 sel50 = 0;
194 sel100 = 1;
195 break;
196 default:
197 sel50 = 1;
198 sel100 = 0;
199 }
200
201 /* Configure PHY DLL frequency */
202 mask = SEL50_MASK | SEL100_MASK;
203 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
204 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
205
206 } else {
207 switch (clock) {
208 case 200000000:
209 freqsel = 0x0;
210 break;
211 default:
212 freqsel = 0x4;
213 }
214
215 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK,
216 freqsel << FREQSEL_SHIFT);
217 }
218 /* Configure DLL TRIM */
219 mask = DLL_TRIM_ICP_MASK;
220 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
221
222 /* Configure DLL driver strength */
223 mask |= DR_TY_MASK;
224 val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
225 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
226
227 /* Enable DLL */
228 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
229 0x1 << ENDLL_SHIFT);
230 /*
231 * Poll for DLL ready. Use a one second timeout.
232 * Works in all experiments done so far
233 */
234 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val,
235 val & DLLRDY_MASK, 1000, 1000000);
236 if (ret) {
237 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
238 return;
239 }
240}
241
242static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654,
243 u32 itapdly, u32 enable)
244{
245 /* Set ITAPCHGWIN before writing to ITAPDLY */
246 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
247 1 << ITAPCHGWIN_SHIFT);
248 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
249 enable << ITAPDLYENA_SHIFT);
250 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,
251 itapdly << ITAPDLYSEL_SHIFT);
252 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
253}
254
255static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654,
256 unsigned char timing)
257{
258 u32 mask, val;
259
260 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
261
262 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;
263 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
264 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
265
266 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing],
267 sdhci_am654->itap_del_ena[timing]);
268}
269
270static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
271{
272 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
273 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
274 unsigned char timing = host->mmc->ios.timing;
275 u32 otap_del_sel;
276 u32 mask, val;
277
278 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
279
280 sdhci_set_clock(host, clock);
281
282 /* Setup DLL Output TAP delay */
283 otap_del_sel = sdhci_am654->otap_del_sel[timing];
284
285 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
286 val = (0x1 << OTAPDLYENA_SHIFT) |
287 (otap_del_sel << OTAPDLYSEL_SHIFT);
288
289 /* Write to STRBSEL for HS400 speed mode */
290 if (timing == MMC_TIMING_MMC_HS400) {
291 if (sdhci_am654->flags & STRBSEL_4_BIT)
292 mask |= STRBSEL_4BIT_MASK;
293 else
294 mask |= STRBSEL_8BIT_MASK;
295
296 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;
297 }
298
299 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
300
301 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) {
302 sdhci_am654_setup_dll(host, clock);
303 sdhci_am654->dll_enable = true;
304
305 if (timing == MMC_TIMING_MMC_HS400) {
306 sdhci_am654->itap_del_ena[timing] = 0x1;
307 sdhci_am654->itap_del_sel[timing] = sdhci_am654->itap_del_sel[timing - 1];
308 }
309
310 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing],
311 sdhci_am654->itap_del_ena[timing]);
312 } else {
313 sdhci_am654_setup_delay_chain(sdhci_am654, timing);
314 sdhci_am654->dll_enable = false;
315 }
316
317 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
318 sdhci_am654->clkbuf_sel);
319}
320
321static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
322 unsigned int clock)
323{
324 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
325 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
326 unsigned char timing = host->mmc->ios.timing;
327 u32 otap_del_sel;
328 u32 itap_del_ena;
329 u32 itap_del_sel;
330 u32 mask, val;
331
332 /* Setup DLL Output TAP delay */
333 otap_del_sel = sdhci_am654->otap_del_sel[timing];
334
335 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
336 val = (0x1 << OTAPDLYENA_SHIFT) |
337 (otap_del_sel << OTAPDLYSEL_SHIFT);
338
339 /* Setup Input TAP delay */
340 itap_del_ena = sdhci_am654->itap_del_ena[timing];
341 itap_del_sel = sdhci_am654->itap_del_sel[timing];
342
343 mask |= ITAPDLYENA_MASK | ITAPDLYSEL_MASK;
344 val |= (itap_del_ena << ITAPDLYENA_SHIFT) |
345 (itap_del_sel << ITAPDLYSEL_SHIFT);
346
347 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
348 1 << ITAPCHGWIN_SHIFT);
349 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
350 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
351 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
352 sdhci_am654->clkbuf_sel);
353
354 sdhci_set_clock(host, clock);
355}
356
357static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg)
358{
359 writeb(val, host->ioaddr + reg);
360 usleep_range(1000, 10000);
361 return readb(host->ioaddr + reg);
362}
363
364#define MAX_POWER_ON_TIMEOUT 1500000 /* us */
365static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
366{
367 unsigned char timing = host->mmc->ios.timing;
368 u8 pwr;
369 int ret;
370
371 if (reg == SDHCI_HOST_CONTROL) {
372 switch (timing) {
373 /*
374 * According to the data manual, HISPD bit
375 * should not be set in these speed modes.
376 */
377 case MMC_TIMING_SD_HS:
378 case MMC_TIMING_MMC_HS:
379 val &= ~SDHCI_CTRL_HISPD;
380 }
381 }
382
383 writeb(val, host->ioaddr + reg);
384 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) {
385 /*
386 * Power on will not happen until the card detect debounce
387 * timer expires. Wait at least 1.5 seconds for the power on
388 * bit to be set
389 */
390 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr,
391 pwr & SDHCI_POWER_ON, 0,
392 MAX_POWER_ON_TIMEOUT, false, host, val,
393 reg);
394 if (ret)
395 dev_info(mmc_dev(host->mmc), "Power on failed\n");
396 }
397}
398
399static void sdhci_am654_reset(struct sdhci_host *host, u8 mask)
400{
401 u8 ctrl;
402 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
403 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
404
405 sdhci_and_cqhci_reset(host, mask);
406
407 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) {
408 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
409 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
410 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
411 }
412}
413
414static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode)
415{
416 struct sdhci_host *host = mmc_priv(mmc);
417 int err = sdhci_execute_tuning(mmc, opcode);
418
419 if (err)
420 return err;
421 /*
422 * Tuning data remains in the buffer after tuning.
423 * Do a command and data reset to get rid of it
424 */
425 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
426
427 return 0;
428}
429
430static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask)
431{
432 int cmd_error = 0;
433 int data_error = 0;
434
435 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
436 return intmask;
437
438 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
439
440 return 0;
441}
442
443#define ITAPDLY_LENGTH 32
444#define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1)
445
446static u32 sdhci_am654_calculate_itap(struct sdhci_host *host, struct window
447 *fail_window, u8 num_fails, bool circular_buffer)
448{
449 u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0;
450 u8 first_fail_start = 0, last_fail_end = 0;
451 struct device *dev = mmc_dev(host->mmc);
452 struct window pass_window = {0, 0, 0};
453 int prev_fail_end = -1;
454 u8 i;
455
456 if (!num_fails)
457 return ITAPDLY_LAST_INDEX >> 1;
458
459 if (fail_window->length == ITAPDLY_LENGTH) {
460 dev_err(dev, "No passing ITAPDLY, return 0\n");
461 return 0;
462 }
463
464 first_fail_start = fail_window->start;
465 last_fail_end = fail_window[num_fails - 1].end;
466
467 for (i = 0; i < num_fails; i++) {
468 start_fail = fail_window[i].start;
469 end_fail = fail_window[i].end;
470 pass_length = start_fail - (prev_fail_end + 1);
471
472 if (pass_length > pass_window.length) {
473 pass_window.start = prev_fail_end + 1;
474 pass_window.length = pass_length;
475 }
476 prev_fail_end = end_fail;
477 }
478
479 if (!circular_buffer)
480 pass_length = ITAPDLY_LAST_INDEX - last_fail_end;
481 else
482 pass_length = ITAPDLY_LAST_INDEX - last_fail_end + first_fail_start;
483
484 if (pass_length > pass_window.length) {
485 pass_window.start = last_fail_end + 1;
486 pass_window.length = pass_length;
487 }
488
489 if (!circular_buffer)
490 itap = pass_window.start + (pass_window.length >> 1);
491 else
492 itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH;
493
494 return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap;
495}
496
497static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host,
498 u32 opcode)
499{
500 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
501 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
502 unsigned char timing = host->mmc->ios.timing;
503 struct window fail_window[ITAPDLY_LENGTH];
504 u8 curr_pass, itap;
505 u8 fail_index = 0;
506 u8 prev_pass = 1;
507
508 memset(fail_window, 0, sizeof(fail_window));
509
510 /* Enable ITAPDLY */
511 sdhci_am654->itap_del_ena[timing] = 0x1;
512
513 for (itap = 0; itap < ITAPDLY_LENGTH; itap++) {
514 sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]);
515
516 curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL);
517
518 if (!curr_pass && prev_pass)
519 fail_window[fail_index].start = itap;
520
521 if (!curr_pass) {
522 fail_window[fail_index].end = itap;
523 fail_window[fail_index].length++;
524 }
525
526 if (curr_pass && !prev_pass)
527 fail_index++;
528
529 prev_pass = curr_pass;
530 }
531
532 if (fail_window[fail_index].length != 0)
533 fail_index++;
534
535 itap = sdhci_am654_calculate_itap(host, fail_window, fail_index,
536 sdhci_am654->dll_enable);
537
538 sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]);
539
540 /* Save ITAPDLY */
541 sdhci_am654->itap_del_sel[timing] = itap;
542
543 return 0;
544}
545
546static struct sdhci_ops sdhci_am654_ops = {
547 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
548 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
549 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
550 .set_uhs_signaling = sdhci_set_uhs_signaling,
551 .set_bus_width = sdhci_set_bus_width,
552 .set_power = sdhci_set_power_and_bus_voltage,
553 .set_clock = sdhci_am654_set_clock,
554 .write_b = sdhci_am654_write_b,
555 .irq = sdhci_am654_cqhci_irq,
556 .reset = sdhci_and_cqhci_reset,
557};
558
559static const struct sdhci_pltfm_data sdhci_am654_pdata = {
560 .ops = &sdhci_am654_ops,
561 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
562 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
563};
564
565static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = {
566 .pdata = &sdhci_am654_pdata,
567 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT |
568 DLL_CALIB,
569};
570
571static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
572 .pdata = &sdhci_am654_pdata,
573 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
574};
575
576static struct sdhci_ops sdhci_j721e_8bit_ops = {
577 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
578 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
579 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
580 .set_uhs_signaling = sdhci_set_uhs_signaling,
581 .set_bus_width = sdhci_set_bus_width,
582 .set_power = sdhci_set_power_and_bus_voltage,
583 .set_clock = sdhci_am654_set_clock,
584 .write_b = sdhci_am654_write_b,
585 .irq = sdhci_am654_cqhci_irq,
586 .reset = sdhci_and_cqhci_reset,
587};
588
589static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
590 .ops = &sdhci_j721e_8bit_ops,
591 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
592 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
593};
594
595static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
596 .pdata = &sdhci_j721e_8bit_pdata,
597 .flags = DLL_PRESENT | DLL_CALIB,
598};
599
600static struct sdhci_ops sdhci_j721e_4bit_ops = {
601 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
602 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
603 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
604 .set_uhs_signaling = sdhci_set_uhs_signaling,
605 .set_bus_width = sdhci_set_bus_width,
606 .set_power = sdhci_set_power_and_bus_voltage,
607 .set_clock = sdhci_j721e_4bit_set_clock,
608 .write_b = sdhci_am654_write_b,
609 .irq = sdhci_am654_cqhci_irq,
610 .reset = sdhci_am654_reset,
611};
612
613static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = {
614 .ops = &sdhci_j721e_4bit_ops,
615 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
616 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
617};
618
619static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = {
620 .pdata = &sdhci_j721e_4bit_pdata,
621 .flags = IOMUX_PRESENT,
622};
623
624static const struct soc_device_attribute sdhci_am654_devices[] = {
625 { .family = "AM65X",
626 .revision = "SR1.0",
627 .data = &sdhci_am654_sr1_drvdata
628 },
629 {/* sentinel */}
630};
631
632static void sdhci_am654_dumpregs(struct mmc_host *mmc)
633{
634 sdhci_dumpregs(mmc_priv(mmc));
635}
636
637static const struct cqhci_host_ops sdhci_am654_cqhci_ops = {
638 .enable = sdhci_cqe_enable,
639 .disable = sdhci_cqe_disable,
640 .dumpregs = sdhci_am654_dumpregs,
641};
642
643static int sdhci_am654_cqe_add_host(struct sdhci_host *host)
644{
645 struct cqhci_host *cq_host;
646
647 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host),
648 GFP_KERNEL);
649 if (!cq_host)
650 return -ENOMEM;
651
652 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR;
653 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
654 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
655 cq_host->ops = &sdhci_am654_cqhci_ops;
656
657 host->mmc->caps2 |= MMC_CAP2_CQE;
658
659 return cqhci_init(cq_host, host->mmc, 1);
660}
661
662static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
663 struct sdhci_am654_data *sdhci_am654)
664{
665 struct device *dev = mmc_dev(host->mmc);
666 int i;
667 int ret;
668
669 for (i = MMC_TIMING_LEGACY; i <= MMC_TIMING_MMC_HS400; i++) {
670
671 ret = device_property_read_u32(dev, td[i].otap_binding,
672 &sdhci_am654->otap_del_sel[i]);
673 if (ret) {
674 if (i == MMC_TIMING_LEGACY) {
675 dev_err(dev, "Couldn't find mandatory ti,otap-del-sel-legacy\n");
676 return ret;
677 }
678 dev_dbg(dev, "Couldn't find %s\n",
679 td[i].otap_binding);
680 /*
681 * Remove the corresponding capability
682 * if an otap-del-sel value is not found
683 */
684 if (i <= MMC_TIMING_MMC_DDR52)
685 host->mmc->caps &= ~td[i].capability;
686 else
687 host->mmc->caps2 &= ~td[i].capability;
688 }
689
690 if (td[i].itap_binding) {
691 ret = device_property_read_u32(dev, td[i].itap_binding,
692 &sdhci_am654->itap_del_sel[i]);
693 if (!ret)
694 sdhci_am654->itap_del_ena[i] = 0x1;
695 }
696 }
697
698 return 0;
699}
700
701static int sdhci_am654_init(struct sdhci_host *host)
702{
703 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
704 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
705 u32 ctl_cfg_2 = 0;
706 u32 mask;
707 u32 val;
708 int ret;
709
710 /* Reset OTAP to default value */
711 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
712 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
713
714 if (sdhci_am654->flags & DLL_CALIB) {
715 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
716 if (~val & CALDONE_MASK) {
717 /* Calibrate IO lines */
718 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
719 PDB_MASK, PDB_MASK);
720 ret = regmap_read_poll_timeout(sdhci_am654->base,
721 PHY_STAT1, val,
722 val & CALDONE_MASK,
723 1, 20);
724 if (ret)
725 return ret;
726 }
727 }
728
729 /* Enable pins by setting IO mux to 0 */
730 if (sdhci_am654->flags & IOMUX_PRESENT)
731 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
732 IOMUX_ENABLE_MASK, 0);
733
734 /* Set slot type based on SD or eMMC */
735 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
736 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
737
738 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
739 ctl_cfg_2);
740
741 /* Enable tuning for SDR50 */
742 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
743 TUNINGFORSDR50_MASK);
744
745 ret = sdhci_setup_host(host);
746 if (ret)
747 return ret;
748
749 ret = sdhci_am654_cqe_add_host(host);
750 if (ret)
751 goto err_cleanup_host;
752
753 ret = sdhci_am654_get_otap_delay(host, sdhci_am654);
754 if (ret)
755 goto err_cleanup_host;
756
757 ret = __sdhci_add_host(host);
758 if (ret)
759 goto err_cleanup_host;
760
761 return 0;
762
763err_cleanup_host:
764 sdhci_cleanup_host(host);
765 return ret;
766}
767
768static int sdhci_am654_get_of_property(struct platform_device *pdev,
769 struct sdhci_am654_data *sdhci_am654)
770{
771 struct device *dev = &pdev->dev;
772 int drv_strength;
773 int ret;
774
775 if (sdhci_am654->flags & DLL_PRESENT) {
776 ret = device_property_read_u32(dev, "ti,trm-icp",
777 &sdhci_am654->trm_icp);
778 if (ret)
779 return ret;
780
781 ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
782 &drv_strength);
783 if (ret)
784 return ret;
785
786 switch (drv_strength) {
787 case 50:
788 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
789 break;
790 case 33:
791 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
792 break;
793 case 66:
794 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
795 break;
796 case 100:
797 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
798 break;
799 case 40:
800 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
801 break;
802 default:
803 dev_err(dev, "Invalid driver strength\n");
804 return -EINVAL;
805 }
806 }
807
808 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
809 device_property_read_u32(dev, "ti,clkbuf-sel",
810 &sdhci_am654->clkbuf_sel);
811
812 if (device_property_read_bool(dev, "ti,fails-without-test-cd"))
813 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST;
814
815 sdhci_get_of_property(pdev);
816
817 return 0;
818}
819
820static const struct of_device_id sdhci_am654_of_match[] = {
821 {
822 .compatible = "ti,am654-sdhci-5.1",
823 .data = &sdhci_am654_drvdata,
824 },
825 {
826 .compatible = "ti,j721e-sdhci-8bit",
827 .data = &sdhci_j721e_8bit_drvdata,
828 },
829 {
830 .compatible = "ti,j721e-sdhci-4bit",
831 .data = &sdhci_j721e_4bit_drvdata,
832 },
833 {
834 .compatible = "ti,am64-sdhci-8bit",
835 .data = &sdhci_j721e_8bit_drvdata,
836 },
837 {
838 .compatible = "ti,am64-sdhci-4bit",
839 .data = &sdhci_j721e_4bit_drvdata,
840 },
841 {
842 .compatible = "ti,am62-sdhci",
843 .data = &sdhci_j721e_4bit_drvdata,
844 },
845 { /* sentinel */ }
846};
847MODULE_DEVICE_TABLE(of, sdhci_am654_of_match);
848
849static int sdhci_am654_probe(struct platform_device *pdev)
850{
851 const struct sdhci_am654_driver_data *drvdata;
852 const struct soc_device_attribute *soc;
853 struct sdhci_pltfm_host *pltfm_host;
854 struct sdhci_am654_data *sdhci_am654;
855 const struct of_device_id *match;
856 struct sdhci_host *host;
857 struct clk *clk_xin;
858 struct device *dev = &pdev->dev;
859 void __iomem *base;
860 int ret;
861
862 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);
863 drvdata = match->data;
864
865 /* Update drvdata based on SoC revision */
866 soc = soc_device_match(sdhci_am654_devices);
867 if (soc && soc->data)
868 drvdata = soc->data;
869
870 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
871 if (IS_ERR(host))
872 return PTR_ERR(host);
873
874 pltfm_host = sdhci_priv(host);
875 sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
876 sdhci_am654->flags = drvdata->flags;
877
878 clk_xin = devm_clk_get(dev, "clk_xin");
879 if (IS_ERR(clk_xin)) {
880 dev_err(dev, "clk_xin clock not found.\n");
881 ret = PTR_ERR(clk_xin);
882 goto err_pltfm_free;
883 }
884
885 pltfm_host->clk = clk_xin;
886
887 base = devm_platform_ioremap_resource(pdev, 1);
888 if (IS_ERR(base)) {
889 ret = PTR_ERR(base);
890 goto err_pltfm_free;
891 }
892
893 sdhci_am654->base = devm_regmap_init_mmio(dev, base,
894 &sdhci_am654_regmap_config);
895 if (IS_ERR(sdhci_am654->base)) {
896 dev_err(dev, "Failed to initialize regmap\n");
897 ret = PTR_ERR(sdhci_am654->base);
898 goto err_pltfm_free;
899 }
900
901 ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
902 if (ret)
903 goto err_pltfm_free;
904
905 ret = mmc_of_parse(host->mmc);
906 if (ret) {
907 dev_err_probe(dev, ret, "parsing dt failed\n");
908 goto err_pltfm_free;
909 }
910
911 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;
912
913 pm_runtime_get_noresume(dev);
914 ret = pm_runtime_set_active(dev);
915 if (ret)
916 goto pm_put;
917 pm_runtime_enable(dev);
918 ret = clk_prepare_enable(pltfm_host->clk);
919 if (ret)
920 goto pm_disable;
921
922 ret = sdhci_am654_init(host);
923 if (ret)
924 goto clk_disable;
925
926 /* Setting up autosuspend */
927 pm_runtime_set_autosuspend_delay(dev, SDHCI_AM654_AUTOSUSPEND_DELAY);
928 pm_runtime_use_autosuspend(dev);
929 pm_runtime_mark_last_busy(dev);
930 pm_runtime_put_autosuspend(dev);
931 return 0;
932
933clk_disable:
934 clk_disable_unprepare(pltfm_host->clk);
935pm_disable:
936 pm_runtime_disable(dev);
937pm_put:
938 pm_runtime_put_noidle(dev);
939err_pltfm_free:
940 sdhci_pltfm_free(pdev);
941 return ret;
942}
943
944static void sdhci_am654_remove(struct platform_device *pdev)
945{
946 struct sdhci_host *host = platform_get_drvdata(pdev);
947 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
948 struct device *dev = &pdev->dev;
949 int ret;
950
951 ret = pm_runtime_get_sync(dev);
952 if (ret < 0)
953 dev_err(dev, "pm_runtime_get_sync() Failed\n");
954
955 sdhci_remove_host(host, true);
956 clk_disable_unprepare(pltfm_host->clk);
957 pm_runtime_disable(dev);
958 pm_runtime_put_noidle(dev);
959 sdhci_pltfm_free(pdev);
960}
961
962#ifdef CONFIG_PM
963static int sdhci_am654_restore(struct sdhci_host *host)
964{
965 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
966 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
967 u32 ctl_cfg_2 = 0;
968 u32 val;
969 int ret;
970
971 if (sdhci_am654->flags & DLL_CALIB) {
972 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
973 if (~val & CALDONE_MASK) {
974 /* Calibrate IO lines */
975 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
976 PDB_MASK, PDB_MASK);
977 ret = regmap_read_poll_timeout(sdhci_am654->base,
978 PHY_STAT1, val,
979 val & CALDONE_MASK,
980 1, 20);
981 if (ret)
982 return ret;
983 }
984 }
985
986 /* Enable pins by setting IO mux to 0 */
987 if (sdhci_am654->flags & IOMUX_PRESENT)
988 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
989 IOMUX_ENABLE_MASK, 0);
990
991 /* Set slot type based on SD or eMMC */
992 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
993 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
994
995 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
996 ctl_cfg_2);
997
998 regmap_read(sdhci_am654->base, CTL_CFG_3, &val);
999 if (~val & TUNINGFORSDR50_MASK)
1000 /* Enable tuning for SDR50 */
1001 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
1002 TUNINGFORSDR50_MASK);
1003
1004 return 0;
1005}
1006
1007static int sdhci_am654_runtime_suspend(struct device *dev)
1008{
1009 struct sdhci_host *host = dev_get_drvdata(dev);
1010 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1011 int ret;
1012
1013 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1014 mmc_retune_needed(host->mmc);
1015
1016 ret = cqhci_suspend(host->mmc);
1017 if (ret)
1018 return ret;
1019
1020 ret = sdhci_runtime_suspend_host(host);
1021 if (ret)
1022 return ret;
1023
1024 /* disable the clock */
1025 clk_disable_unprepare(pltfm_host->clk);
1026 return 0;
1027}
1028
1029static int sdhci_am654_runtime_resume(struct device *dev)
1030{
1031 struct sdhci_host *host = dev_get_drvdata(dev);
1032 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1033 int ret;
1034
1035 /* Enable the clock */
1036 ret = clk_prepare_enable(pltfm_host->clk);
1037 if (ret)
1038 return ret;
1039
1040 ret = sdhci_am654_restore(host);
1041 if (ret)
1042 return ret;
1043
1044 ret = sdhci_runtime_resume_host(host, 0);
1045 if (ret)
1046 return ret;
1047
1048 ret = cqhci_resume(host->mmc);
1049 if (ret)
1050 return ret;
1051
1052 return 0;
1053}
1054#endif
1055
1056static const struct dev_pm_ops sdhci_am654_dev_pm_ops = {
1057 SET_RUNTIME_PM_OPS(sdhci_am654_runtime_suspend,
1058 sdhci_am654_runtime_resume, NULL)
1059 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1060 pm_runtime_force_resume)
1061};
1062
1063static struct platform_driver sdhci_am654_driver = {
1064 .driver = {
1065 .name = "sdhci-am654",
1066 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1067 .pm = &sdhci_am654_dev_pm_ops,
1068 .of_match_table = sdhci_am654_of_match,
1069 },
1070 .probe = sdhci_am654_probe,
1071 .remove_new = sdhci_am654_remove,
1072};
1073
1074module_platform_driver(sdhci_am654_driver);
1075
1076MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
1077MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
1078MODULE_LICENSE("GPL");