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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2022 Intel Corporation
4 */
5
6#include "xe_wa.h"
7
8#include <drm/drm_managed.h>
9#include <kunit/visibility.h>
10#include <linux/compiler_types.h>
11
12#include "generated/xe_wa_oob.h"
13#include "regs/xe_engine_regs.h"
14#include "regs/xe_gt_regs.h"
15#include "regs/xe_regs.h"
16#include "xe_device_types.h"
17#include "xe_force_wake.h"
18#include "xe_gt.h"
19#include "xe_hw_engine_types.h"
20#include "xe_mmio.h"
21#include "xe_platform_types.h"
22#include "xe_rtp.h"
23#include "xe_step.h"
24
25/**
26 * DOC: Hardware workarounds
27 *
28 * Hardware workarounds are register programming documented to be executed in
29 * the driver that fall outside of the normal programming sequences for a
30 * platform. There are some basic categories of workarounds, depending on
31 * how/when they are applied:
32 *
33 * - LRC workarounds: workarounds that touch registers that are
34 * saved/restored to/from the HW context image. The list is emitted (via Load
35 * Register Immediate commands) once when initializing the device and saved in
36 * the default context. That default context is then used on every context
37 * creation to have a "primed golden context", i.e. a context image that
38 * already contains the changes needed to all the registers.
39 *
40 * - Engine workarounds: the list of these WAs is applied whenever the specific
41 * engine is reset. It's also possible that a set of engine classes share a
42 * common power domain and they are reset together. This happens on some
43 * platforms with render and compute engines. In this case (at least) one of
44 * them need to keeep the workaround programming: the approach taken in the
45 * driver is to tie those workarounds to the first compute/render engine that
46 * is registered. When executing with GuC submission, engine resets are
47 * outside of kernel driver control, hence the list of registers involved in
48 * written once, on engine initialization, and then passed to GuC, that
49 * saves/restores their values before/after the reset takes place. See
50 * ``drivers/gpu/drm/xe/xe_guc_ads.c`` for reference.
51 *
52 * - GT workarounds: the list of these WAs is applied whenever these registers
53 * revert to their default values: on GPU reset, suspend/resume [1]_, etc.
54 *
55 * - Register whitelist: some workarounds need to be implemented in userspace,
56 * but need to touch privileged registers. The whitelist in the kernel
57 * instructs the hardware to allow the access to happen. From the kernel side,
58 * this is just a special case of a MMIO workaround (as we write the list of
59 * these to/be-whitelisted registers to some special HW registers).
60 *
61 * - Workaround batchbuffers: buffers that get executed automatically by the
62 * hardware on every HW context restore. These buffers are created and
63 * programmed in the default context so the hardware always go through those
64 * programming sequences when switching contexts. The support for workaround
65 * batchbuffers is enabled these hardware mechanisms:
66 *
67 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default
68 * context, pointing the hardware to jump to that location when that offset
69 * is reached in the context restore. Workaround batchbuffer in the driver
70 * currently uses this mechanism for all platforms.
71 *
72 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context,
73 * pointing the hardware to a buffer to continue executing after the
74 * engine registers are restored in a context restore sequence. This is
75 * currently not used in the driver.
76 *
77 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from
78 * a central place. Those are peppered around the rest of the code, as needed.
79 * Workarounds related to the display IP are the main example.
80 *
81 * .. [1] Technically, some registers are powercontext saved & restored, so they
82 * survive a suspend/resume. In practice, writing them again is not too
83 * costly and simplifies things, so it's the approach taken in the driver.
84 *
85 * .. note::
86 * Hardware workarounds in xe work the same way as in i915, with the
87 * difference of how they are maintained in the code. In xe it uses the
88 * xe_rtp infrastructure so the workarounds can be kept in tables, following
89 * a more declarative approach rather than procedural.
90 */
91
92#undef XE_REG_MCR
93#define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
94
95__diag_push();
96__diag_ignore_all("-Woverride-init", "Allow field overrides in table");
97
98static const struct xe_rtp_entry_sr gt_was[] = {
99 { XE_RTP_NAME("14011060649"),
100 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),
101 ENGINE_CLASS(VIDEO_DECODE),
102 FUNC(xe_rtp_match_even_instance)),
103 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
104 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
105 },
106 { XE_RTP_NAME("14011059788"),
107 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
108 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
109 },
110 { XE_RTP_NAME("14015795083"),
111 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)),
112 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
113 },
114
115 /* DG1 */
116
117 { XE_RTP_NAME("1409420604"),
118 XE_RTP_RULES(PLATFORM(DG1)),
119 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS))
120 },
121 { XE_RTP_NAME("1408615072"),
122 XE_RTP_RULES(PLATFORM(DG1)),
123 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS))
124 },
125
126 /* DG2 */
127
128 { XE_RTP_NAME("16010515920"),
129 XE_RTP_RULES(SUBPLATFORM(DG2, G10),
130 GRAPHICS_STEP(A0, B0),
131 ENGINE_CLASS(VIDEO_DECODE)),
132 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F18(0), ALNUNIT_CLKGATE_DIS)),
133 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
134 },
135 { XE_RTP_NAME("22010523718"),
136 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
137 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS))
138 },
139 { XE_RTP_NAME("14011006942"),
140 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
141 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
142 },
143 { XE_RTP_NAME("14012362059"),
144 XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
145 XE_RTP_ACTIONS(SET(XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB))
146 },
147 { XE_RTP_NAME("14012362059"),
148 XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0)),
149 XE_RTP_ACTIONS(SET(XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB))
150 },
151 { XE_RTP_NAME("14010948348"),
152 XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
153 XE_RTP_ACTIONS(SET(UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS))
154 },
155 { XE_RTP_NAME("14011037102"),
156 XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
157 XE_RTP_ACTIONS(SET(UNSLCGCTL9444, LTCDD_CLKGATE_DIS))
158 },
159 { XE_RTP_NAME("14011371254"),
160 XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
161 XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS))
162 },
163 { XE_RTP_NAME("14011431319"),
164 XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
165 XE_RTP_ACTIONS(SET(UNSLCGCTL9440,
166 GAMTLBOACS_CLKGATE_DIS |
167 GAMTLBVDBOX7_CLKGATE_DIS | GAMTLBVDBOX6_CLKGATE_DIS |
168 GAMTLBVDBOX5_CLKGATE_DIS | GAMTLBVDBOX4_CLKGATE_DIS |
169 GAMTLBVDBOX3_CLKGATE_DIS | GAMTLBVDBOX2_CLKGATE_DIS |
170 GAMTLBVDBOX1_CLKGATE_DIS | GAMTLBVDBOX0_CLKGATE_DIS |
171 GAMTLBKCR_CLKGATE_DIS | GAMTLBGUC_CLKGATE_DIS |
172 GAMTLBBLT_CLKGATE_DIS),
173 SET(UNSLCGCTL9444,
174 GAMTLBGFXA0_CLKGATE_DIS | GAMTLBGFXA1_CLKGATE_DIS |
175 GAMTLBCOMPA0_CLKGATE_DIS | GAMTLBCOMPA1_CLKGATE_DIS |
176 GAMTLBCOMPB0_CLKGATE_DIS | GAMTLBCOMPB1_CLKGATE_DIS |
177 GAMTLBCOMPC0_CLKGATE_DIS | GAMTLBCOMPC1_CLKGATE_DIS |
178 GAMTLBCOMPD0_CLKGATE_DIS | GAMTLBCOMPD1_CLKGATE_DIS |
179 GAMTLBMERT_CLKGATE_DIS |
180 GAMTLBVEBOX3_CLKGATE_DIS | GAMTLBVEBOX2_CLKGATE_DIS |
181 GAMTLBVEBOX1_CLKGATE_DIS | GAMTLBVEBOX0_CLKGATE_DIS))
182 },
183 { XE_RTP_NAME("14010569222"),
184 XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
185 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, GAMEDIA_CLKGATE_DIS))
186 },
187 { XE_RTP_NAME("14011028019"),
188 XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
189 XE_RTP_ACTIONS(SET(SSMCGCTL9530, RTFUNIT_CLKGATE_DIS))
190 },
191 { XE_RTP_NAME("14010680813"),
192 XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
193 XE_RTP_ACTIONS(SET(XEHP_GAMSTLB_CTRL,
194 CONTROL_BLOCK_CLKGATE_DIS |
195 EGRESS_BLOCK_CLKGATE_DIS |
196 TAG_BLOCK_CLKGATE_DIS))
197 },
198 { XE_RTP_NAME("14014830051"),
199 XE_RTP_RULES(PLATFORM(DG2)),
200 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN))
201 },
202 { XE_RTP_NAME("18018781329"),
203 XE_RTP_RULES(PLATFORM(DG2)),
204 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
205 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
206 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
207 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
208 },
209 { XE_RTP_NAME("1509235366"),
210 XE_RTP_RULES(PLATFORM(DG2)),
211 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL,
212 INVALIDATION_BROADCAST_MODE_DIS |
213 GLOBAL_INVALIDATION_MODE))
214 },
215 { XE_RTP_NAME("14010648519"),
216 XE_RTP_RULES(PLATFORM(DG2)),
217 XE_RTP_ACTIONS(SET(XEHP_L3NODEARBCFG, XEHP_LNESPARE))
218 },
219
220 /* PVC */
221
222 { XE_RTP_NAME("18018781329"),
223 XE_RTP_RULES(PLATFORM(PVC)),
224 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
225 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
226 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
227 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
228 },
229 { XE_RTP_NAME("16016694945"),
230 XE_RTP_RULES(PLATFORM(PVC)),
231 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC))
232 },
233
234 /* Xe_LPG */
235
236 { XE_RTP_NAME("14015795083"),
237 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)),
238 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
239 },
240 { XE_RTP_NAME("14018575942"),
241 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)),
242 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))
243 },
244 { XE_RTP_NAME("22016670082"),
245 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)),
246 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR))
247 },
248
249 /* Xe_LPM+ */
250
251 { XE_RTP_NAME("16021867713"),
252 XE_RTP_RULES(MEDIA_VERSION(1300),
253 ENGINE_CLASS(VIDEO_DECODE)),
254 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
255 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
256 },
257 { XE_RTP_NAME("22016670082"),
258 XE_RTP_RULES(MEDIA_VERSION(1300)),
259 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR))
260 },
261
262 /* Xe2_LPG */
263
264 { XE_RTP_NAME("16020975621"),
265 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),
266 XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, SBEUNIT_CLKGATE_DIS))
267 },
268 { XE_RTP_NAME("14018157293"),
269 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),
270 XE_RTP_ACTIONS(SET(XEHPC_L3CLOS_MASK(0), ~0),
271 SET(XEHPC_L3CLOS_MASK(1), ~0),
272 SET(XEHPC_L3CLOS_MASK(2), ~0),
273 SET(XEHPC_L3CLOS_MASK(3), ~0))
274 },
275
276 /* Xe2_LPM */
277
278 { XE_RTP_NAME("14017421178"),
279 XE_RTP_RULES(MEDIA_VERSION(2000),
280 ENGINE_CLASS(VIDEO_DECODE)),
281 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
282 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
283 },
284 { XE_RTP_NAME("16021867713"),
285 XE_RTP_RULES(MEDIA_VERSION(2000),
286 ENGINE_CLASS(VIDEO_DECODE)),
287 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
288 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
289 },
290 { XE_RTP_NAME("14019449301"),
291 XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)),
292 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
293 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
294 },
295
296 {}
297};
298
299static const struct xe_rtp_entry_sr engine_was[] = {
300 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
301 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
302 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE),
303 FF_TESSELATION_DOP_GATE_DISABLE))
304 },
305 { XE_RTP_NAME("1409804808"),
306 XE_RTP_RULES(GRAPHICS_VERSION(1200),
307 ENGINE_CLASS(RENDER),
308 IS_INTEGRATED),
309 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS))
310 },
311 { XE_RTP_NAME("14010229206, 1409085225"),
312 XE_RTP_RULES(GRAPHICS_VERSION(1200),
313 ENGINE_CLASS(RENDER),
314 IS_INTEGRATED),
315 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
316 },
317 { XE_RTP_NAME("1606931601"),
318 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
319 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ))
320 },
321 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"),
322 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)),
323 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE),
324 FF_DOP_CLOCK_GATE_DISABLE))
325 },
326 { XE_RTP_NAME("1406941453"),
327 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
328 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL))
329 },
330 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
331 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
332 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE),
333 FFSC_PERCTX_PREEMPT_CTRL))
334 },
335
336 /* TGL */
337
338 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
339 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),
340 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
341 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
342 RC_SEMA_IDLE_MSG_DISABLE))
343 },
344
345 /* RKL */
346
347 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
348 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),
349 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
350 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
351 RC_SEMA_IDLE_MSG_DISABLE))
352 },
353
354 /* ADL-P */
355
356 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
357 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)),
358 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
359 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
360 RC_SEMA_IDLE_MSG_DISABLE))
361 },
362
363 /* DG2 */
364
365 { XE_RTP_NAME("22013037850"),
366 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
367 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
368 DISABLE_128B_EVICTION_COMMAND_UDW))
369 },
370 { XE_RTP_NAME("22014226127"),
371 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
372 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
373 },
374 { XE_RTP_NAME("18017747507"),
375 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
376 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN,
377 POLYGON_TRIFAN_LINELOOP_DISABLE))
378 },
379 { XE_RTP_NAME("22012826095, 22013059131"),
380 XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(B0, C0),
381 FUNC(xe_rtp_match_first_render_or_compute)),
382 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
383 MAXREQS_PER_BANK,
384 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))
385 },
386 { XE_RTP_NAME("22012826095, 22013059131"),
387 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
388 FUNC(xe_rtp_match_first_render_or_compute)),
389 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
390 MAXREQS_PER_BANK,
391 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))
392 },
393 { XE_RTP_NAME("22013059131"),
394 XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(B0, C0),
395 FUNC(xe_rtp_match_first_render_or_compute)),
396 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
397 },
398 { XE_RTP_NAME("22013059131"),
399 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
400 FUNC(xe_rtp_match_first_render_or_compute)),
401 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
402 },
403 { XE_RTP_NAME("14010918519"),
404 XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0),
405 FUNC(xe_rtp_match_first_render_or_compute)),
406 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
407 FORCE_SLM_FENCE_SCOPE_TO_TILE |
408 FORCE_UGM_FENCE_SCOPE_TO_TILE,
409 /*
410 * Ignore read back as it always returns 0 in these
411 * steps
412 */
413 .read_mask = 0))
414 },
415 { XE_RTP_NAME("14015227452"),
416 XE_RTP_RULES(PLATFORM(DG2),
417 FUNC(xe_rtp_match_first_render_or_compute)),
418 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
419 },
420 { XE_RTP_NAME("16015675438"),
421 XE_RTP_RULES(PLATFORM(DG2),
422 FUNC(xe_rtp_match_first_render_or_compute)),
423 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2(RENDER_RING_BASE),
424 PERF_FIX_BALANCING_CFE_DISABLE))
425 },
426 { XE_RTP_NAME("18028616096"),
427 XE_RTP_RULES(PLATFORM(DG2),
428 FUNC(xe_rtp_match_first_render_or_compute)),
429 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
430 },
431 { XE_RTP_NAME("16011620976, 22015475538"),
432 XE_RTP_RULES(PLATFORM(DG2),
433 FUNC(xe_rtp_match_first_render_or_compute)),
434 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))
435 },
436 { XE_RTP_NAME("22012654132"),
437 XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, C0),
438 FUNC(xe_rtp_match_first_render_or_compute)),
439 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
440 /*
441 * Register can't be read back for verification on
442 * DG2 due to Wa_14012342262
443 */
444 .read_mask = 0))
445 },
446 { XE_RTP_NAME("22012654132"),
447 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
448 FUNC(xe_rtp_match_first_render_or_compute)),
449 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
450 /*
451 * Register can't be read back for verification on
452 * DG2 due to Wa_14012342262
453 */
454 .read_mask = 0))
455 },
456 { XE_RTP_NAME("1509727124"),
457 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
458 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB))
459 },
460 { XE_RTP_NAME("22012856258"),
461 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
462 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION))
463 },
464 { XE_RTP_NAME("14013392000"),
465 XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0),
466 ENGINE_CLASS(RENDER)),
467 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, ENABLE_LARGE_GRF_MODE))
468 },
469 { XE_RTP_NAME("14012419201"),
470 XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0),
471 ENGINE_CLASS(RENDER)),
472 XE_RTP_ACTIONS(SET(ROW_CHICKEN4,
473 DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX))
474 },
475 { XE_RTP_NAME("14012419201"),
476 XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0),
477 ENGINE_CLASS(RENDER)),
478 XE_RTP_ACTIONS(SET(ROW_CHICKEN4,
479 DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX))
480 },
481 { XE_RTP_NAME("1308578152"),
482 XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(B0, C0),
483 ENGINE_CLASS(RENDER),
484 FUNC(xe_rtp_match_first_gslice_fused_off)),
485 XE_RTP_ACTIONS(CLR(CS_DEBUG_MODE1(RENDER_RING_BASE),
486 REPLAY_MODE_GRANULARITY))
487 },
488 { XE_RTP_NAME("22010960976, 14013347512"),
489 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
490 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0,
491 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK))
492 },
493 { XE_RTP_NAME("1608949956, 14010198302"),
494 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
495 XE_RTP_ACTIONS(SET(ROW_CHICKEN,
496 MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE))
497 },
498 { XE_RTP_NAME("22010430635"),
499 XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0),
500 ENGINE_CLASS(RENDER)),
501 XE_RTP_ACTIONS(SET(ROW_CHICKEN4,
502 DISABLE_GRF_CLEAR))
503 },
504 { XE_RTP_NAME("14013202645"),
505 XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(B0, C0),
506 ENGINE_CLASS(RENDER)),
507 XE_RTP_ACTIONS(SET(RT_CTRL, DIS_NULL_QUERY))
508 },
509 { XE_RTP_NAME("14013202645"),
510 XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0),
511 ENGINE_CLASS(RENDER)),
512 XE_RTP_ACTIONS(SET(RT_CTRL, DIS_NULL_QUERY))
513 },
514 { XE_RTP_NAME("22012532006"),
515 XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, C0),
516 ENGINE_CLASS(RENDER)),
517 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,
518 DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA))
519 },
520 { XE_RTP_NAME("22012532006"),
521 XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0),
522 ENGINE_CLASS(RENDER)),
523 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,
524 DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA))
525 },
526 { XE_RTP_NAME("14015150844"),
527 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
528 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
529 XE_RTP_NOCHECK))
530 },
531
532 /* PVC */
533
534 { XE_RTP_NAME("22014226127"),
535 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
536 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
537 },
538 { XE_RTP_NAME("14015227452"),
539 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
540 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
541 },
542 { XE_RTP_NAME("16015675438"),
543 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
544 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2(RENDER_RING_BASE),
545 PERF_FIX_BALANCING_CFE_DISABLE))
546 },
547 { XE_RTP_NAME("14014999345"),
548 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE),
549 GRAPHICS_STEP(B0, C0)),
550 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC))
551 },
552
553 /* Xe_LPG */
554
555 { XE_RTP_NAME("14017856879"),
556 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271),
557 FUNC(xe_rtp_match_first_render_or_compute)),
558 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH))
559 },
560 { XE_RTP_NAME("14015150844"),
561 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271),
562 FUNC(xe_rtp_match_first_render_or_compute)),
563 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
564 XE_RTP_NOCHECK))
565 },
566
567 /* Xe2_LPG */
568
569 { XE_RTP_NAME("18032247524"),
570 XE_RTP_RULES(GRAPHICS_VERSION(2004),
571 FUNC(xe_rtp_match_first_render_or_compute)),
572 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
573 },
574 { XE_RTP_NAME("16018712365"),
575 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
576 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
577 },
578 { XE_RTP_NAME("14018957109"),
579 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
580 FUNC(xe_rtp_match_first_render_or_compute)),
581 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN5, DISABLE_SAMPLE_G_PERFORMANCE))
582 },
583 { XE_RTP_NAME("16021540221"),
584 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
585 FUNC(xe_rtp_match_first_render_or_compute)),
586 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
587 },
588 { XE_RTP_NAME("14019322943"),
589 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
590 FUNC(xe_rtp_match_first_render_or_compute)),
591 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE))
592 },
593 { XE_RTP_NAME("14018471104"),
594 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
595 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
596 },
597 { XE_RTP_NAME("16018737384"),
598 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
599 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
600 },
601 /*
602 * These two workarounds are the same, just applying to different
603 * engines. Although Wa_18032095049 (for the RCS) isn't required on
604 * all steppings, disabling these reports has no impact for our
605 * driver or the GuC, so we go ahead and treat it the same as
606 * Wa_16021639441 which does apply to all steppings.
607 */
608 { XE_RTP_NAME("18032095049, 16021639441"),
609 XE_RTP_RULES(GRAPHICS_VERSION(2004)),
610 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
611 GHWSP_CSB_REPORT_DIS |
612 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
613 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
614 },
615
616 {}
617};
618
619static const struct xe_rtp_entry_sr lrc_was[] = {
620 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"),
621 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
622 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3,
623 DISABLE_CPS_AWARE_COLOR_PIPE))
624 },
625 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),
626 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
627 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE),
628 PREEMPT_GPGPU_LEVEL_MASK,
629 PREEMPT_GPGPU_THREAD_GROUP_LEVEL))
630 },
631 { XE_RTP_NAME("1806527549"),
632 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
633 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE))
634 },
635 { XE_RTP_NAME("1606376872"),
636 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
637 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC))
638 },
639
640 /* DG1 */
641
642 { XE_RTP_NAME("1409044764"),
643 XE_RTP_RULES(PLATFORM(DG1)),
644 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3,
645 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN))
646 },
647 { XE_RTP_NAME("22010493298"),
648 XE_RTP_RULES(PLATFORM(DG1)),
649 XE_RTP_ACTIONS(SET(HIZ_CHICKEN,
650 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE))
651 },
652
653 /* DG2 */
654
655 { XE_RTP_NAME("16011186671"),
656 XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0)),
657 XE_RTP_ACTIONS(CLR(VFLSKPD, DIS_MULT_MISS_RD_SQUASH),
658 SET(VFLSKPD, DIS_OVER_FETCH_CACHE))
659 },
660 { XE_RTP_NAME("14010469329"),
661 XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
662 XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN3,
663 XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE))
664 },
665 { XE_RTP_NAME("14010698770, 22010613112, 22010465075"),
666 XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),
667 XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN3,
668 DISABLE_CPS_AWARE_COLOR_PIPE))
669 },
670 { XE_RTP_NAME("16013271637"),
671 XE_RTP_RULES(PLATFORM(DG2)),
672 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1,
673 MSC_MSAA_REODER_BUF_BYPASS_DISABLE))
674 },
675 { XE_RTP_NAME("14014947963"),
676 XE_RTP_RULES(PLATFORM(DG2)),
677 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION,
678 PREEMPTION_VERTEX_COUNT,
679 0x4000))
680 },
681 { XE_RTP_NAME("18018764978"),
682 XE_RTP_RULES(PLATFORM(DG2)),
683 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2,
684 SCOREBOARD_STALL_FLUSH_CONTROL))
685 },
686 { XE_RTP_NAME("18019271663"),
687 XE_RTP_RULES(PLATFORM(DG2)),
688 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
689 },
690 { XE_RTP_NAME("14019877138"),
691 XE_RTP_RULES(PLATFORM(DG2)),
692 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
693 },
694
695 /* PVC */
696
697 { XE_RTP_NAME("16017236439"),
698 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY),
699 FUNC(xe_rtp_match_even_instance)),
700 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0),
701 BCS_SWCTRL_DISABLE_256B,
702 XE_RTP_ACTION_FLAG(ENGINE_BASE))),
703 },
704
705 /* Xe_LPG */
706
707 { XE_RTP_NAME("18019271663"),
708 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)),
709 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
710 },
711
712 /* Xe2_LPG */
713
714 { XE_RTP_NAME("16020518922"),
715 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
716 ENGINE_CLASS(RENDER)),
717 XE_RTP_ACTIONS(SET(FF_MODE,
718 DIS_TE_AUTOSTRIP |
719 DIS_MESH_PARTIAL_AUTOSTRIP |
720 DIS_MESH_AUTOSTRIP),
721 SET(VFLSKPD,
722 DIS_PARTIAL_AUTOSTRIP |
723 DIS_AUTOSTRIP))
724 },
725 { XE_RTP_NAME("14019386621"),
726 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
727 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
728 },
729 { XE_RTP_NAME("14019877138"),
730 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
731 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
732 },
733 { XE_RTP_NAME("14020013138"),
734 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
735 ENGINE_CLASS(RENDER)),
736 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
737 },
738 { XE_RTP_NAME("14019988906"),
739 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
740 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
741 },
742
743 {}
744};
745
746static __maybe_unused const struct xe_rtp_entry oob_was[] = {
747#include <generated/xe_wa_oob.c>
748 {}
749};
750
751static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);
752
753__diag_pop();
754
755/**
756 * xe_wa_process_oob - process OOB workaround table
757 * @gt: GT instance to process workarounds for
758 *
759 * Process OOB workaround table for this platform, marking in @gt the
760 * workarounds that are active.
761 */
762void xe_wa_process_oob(struct xe_gt *gt)
763{
764 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
765
766 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob,
767 ARRAY_SIZE(oob_was));
768 xe_rtp_process(&ctx, oob_was);
769}
770
771/**
772 * xe_wa_process_gt - process GT workaround table
773 * @gt: GT instance to process workarounds for
774 *
775 * Process GT workaround table for this platform, saving in @gt all the
776 * workarounds that need to be applied at the GT level.
777 */
778void xe_wa_process_gt(struct xe_gt *gt)
779{
780 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
781
782 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt,
783 ARRAY_SIZE(gt_was));
784 xe_rtp_process_to_sr(&ctx, gt_was, >->reg_sr);
785}
786EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt);
787
788/**
789 * xe_wa_process_engine - process engine workaround table
790 * @hwe: engine instance to process workarounds for
791 *
792 * Process engine workaround table for this platform, saving in @hwe all the
793 * workarounds that need to be applied at the engine level that match this
794 * engine.
795 */
796void xe_wa_process_engine(struct xe_hw_engine *hwe)
797{
798 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
799
800 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine,
801 ARRAY_SIZE(engine_was));
802 xe_rtp_process_to_sr(&ctx, engine_was, &hwe->reg_sr);
803}
804
805/**
806 * xe_wa_process_lrc - process context workaround table
807 * @hwe: engine instance to process workarounds for
808 *
809 * Process context workaround table for this platform, saving in @hwe all the
810 * workarounds that need to be applied on context restore. These are workarounds
811 * touching registers that are part of the HW context image.
812 */
813void xe_wa_process_lrc(struct xe_hw_engine *hwe)
814{
815 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
816
817 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc,
818 ARRAY_SIZE(lrc_was));
819 xe_rtp_process_to_sr(&ctx, lrc_was, &hwe->reg_lrc);
820}
821
822/**
823 * xe_wa_init - initialize gt with workaround bookkeeping
824 * @gt: GT instance to initialize
825 *
826 * Returns 0 for success, negative error code otherwise.
827 */
828int xe_wa_init(struct xe_gt *gt)
829{
830 struct xe_device *xe = gt_to_xe(gt);
831 size_t n_oob, n_lrc, n_engine, n_gt, total;
832 unsigned long *p;
833
834 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was));
835 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was));
836 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was));
837 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was));
838 total = n_gt + n_engine + n_lrc + n_oob;
839
840 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
841 if (!p)
842 return -ENOMEM;
843
844 gt->wa_active.gt = p;
845 p += n_gt;
846 gt->wa_active.engine = p;
847 p += n_engine;
848 gt->wa_active.lrc = p;
849 p += n_lrc;
850 gt->wa_active.oob = p;
851
852 return 0;
853}
854
855void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p)
856{
857 size_t idx;
858
859 drm_printf(p, "GT Workarounds\n");
860 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was))
861 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name);
862
863 drm_printf(p, "\nEngine Workarounds\n");
864 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was))
865 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name);
866
867 drm_printf(p, "\nLRC Workarounds\n");
868 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was))
869 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name);
870
871 drm_printf(p, "\nOOB Workarounds\n");
872 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was))
873 if (oob_was[idx].name)
874 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);
875}
876
877/*
878 * Apply tile (non-GT, non-display) workarounds. Think very carefully before
879 * adding anything to this function; most workarounds should be implemented
880 * elsewhere. The programming here is primarily for sgunit/soc workarounds,
881 * which are relatively rare. Since the registers these workarounds target are
882 * outside the GT, they should only need to be applied once at device
883 * probe/resume; they will not lose their values on any kind of GT or engine
884 * reset.
885 *
886 * TODO: We may want to move this over to xe_rtp in the future once we have
887 * enough workarounds to justify the work.
888 */
889void xe_wa_apply_tile_workarounds(struct xe_tile *tile)
890{
891 struct xe_gt *mmio = tile->primary_gt;
892
893 if (XE_WA(mmio, 22010954014))
894 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
895}
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2022 Intel Corporation
4 */
5
6#include "xe_wa.h"
7
8#include <drm/drm_managed.h>
9#include <kunit/visibility.h>
10#include <linux/compiler_types.h>
11
12#include <generated/xe_wa_oob.h>
13
14#include "regs/xe_engine_regs.h"
15#include "regs/xe_gt_regs.h"
16#include "regs/xe_regs.h"
17#include "xe_device_types.h"
18#include "xe_force_wake.h"
19#include "xe_gt.h"
20#include "xe_hw_engine_types.h"
21#include "xe_mmio.h"
22#include "xe_platform_types.h"
23#include "xe_rtp.h"
24#include "xe_step.h"
25
26/**
27 * DOC: Hardware workarounds
28 *
29 * Hardware workarounds are register programming documented to be executed in
30 * the driver that fall outside of the normal programming sequences for a
31 * platform. There are some basic categories of workarounds, depending on
32 * how/when they are applied:
33 *
34 * - LRC workarounds: workarounds that touch registers that are
35 * saved/restored to/from the HW context image. The list is emitted (via Load
36 * Register Immediate commands) once when initializing the device and saved in
37 * the default context. That default context is then used on every context
38 * creation to have a "primed golden context", i.e. a context image that
39 * already contains the changes needed to all the registers.
40 *
41 * - Engine workarounds: the list of these WAs is applied whenever the specific
42 * engine is reset. It's also possible that a set of engine classes share a
43 * common power domain and they are reset together. This happens on some
44 * platforms with render and compute engines. In this case (at least) one of
45 * them need to keeep the workaround programming: the approach taken in the
46 * driver is to tie those workarounds to the first compute/render engine that
47 * is registered. When executing with GuC submission, engine resets are
48 * outside of kernel driver control, hence the list of registers involved in
49 * written once, on engine initialization, and then passed to GuC, that
50 * saves/restores their values before/after the reset takes place. See
51 * ``drivers/gpu/drm/xe/xe_guc_ads.c`` for reference.
52 *
53 * - GT workarounds: the list of these WAs is applied whenever these registers
54 * revert to their default values: on GPU reset, suspend/resume [1]_, etc.
55 *
56 * - Register whitelist: some workarounds need to be implemented in userspace,
57 * but need to touch privileged registers. The whitelist in the kernel
58 * instructs the hardware to allow the access to happen. From the kernel side,
59 * this is just a special case of a MMIO workaround (as we write the list of
60 * these to/be-whitelisted registers to some special HW registers).
61 *
62 * - Workaround batchbuffers: buffers that get executed automatically by the
63 * hardware on every HW context restore. These buffers are created and
64 * programmed in the default context so the hardware always go through those
65 * programming sequences when switching contexts. The support for workaround
66 * batchbuffers is enabled these hardware mechanisms:
67 *
68 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default
69 * context, pointing the hardware to jump to that location when that offset
70 * is reached in the context restore. Workaround batchbuffer in the driver
71 * currently uses this mechanism for all platforms.
72 *
73 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context,
74 * pointing the hardware to a buffer to continue executing after the
75 * engine registers are restored in a context restore sequence. This is
76 * currently not used in the driver.
77 *
78 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from
79 * a central place. Those are peppered around the rest of the code, as needed.
80 * Workarounds related to the display IP are the main example.
81 *
82 * .. [1] Technically, some registers are powercontext saved & restored, so they
83 * survive a suspend/resume. In practice, writing them again is not too
84 * costly and simplifies things, so it's the approach taken in the driver.
85 *
86 * .. note::
87 * Hardware workarounds in xe work the same way as in i915, with the
88 * difference of how they are maintained in the code. In xe it uses the
89 * xe_rtp infrastructure so the workarounds can be kept in tables, following
90 * a more declarative approach rather than procedural.
91 */
92
93#undef XE_REG_MCR
94#define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
95
96__diag_push();
97__diag_ignore_all("-Woverride-init", "Allow field overrides in table");
98
99static const struct xe_rtp_entry_sr gt_was[] = {
100 { XE_RTP_NAME("14011060649"),
101 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),
102 ENGINE_CLASS(VIDEO_DECODE),
103 FUNC(xe_rtp_match_even_instance)),
104 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
105 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
106 },
107 { XE_RTP_NAME("14011059788"),
108 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
109 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
110 },
111 { XE_RTP_NAME("14015795083"),
112 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)),
113 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
114 },
115
116 /* DG1 */
117
118 { XE_RTP_NAME("1409420604"),
119 XE_RTP_RULES(PLATFORM(DG1)),
120 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS))
121 },
122 { XE_RTP_NAME("1408615072"),
123 XE_RTP_RULES(PLATFORM(DG1)),
124 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS))
125 },
126
127 /* DG2 */
128
129 { XE_RTP_NAME("22010523718"),
130 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
131 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS))
132 },
133 { XE_RTP_NAME("14011006942"),
134 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
135 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
136 },
137 { XE_RTP_NAME("14014830051"),
138 XE_RTP_RULES(PLATFORM(DG2)),
139 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN))
140 },
141 { XE_RTP_NAME("18018781329"),
142 XE_RTP_RULES(PLATFORM(DG2)),
143 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
144 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
145 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
146 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
147 },
148 { XE_RTP_NAME("1509235366"),
149 XE_RTP_RULES(PLATFORM(DG2)),
150 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL,
151 INVALIDATION_BROADCAST_MODE_DIS |
152 GLOBAL_INVALIDATION_MODE))
153 },
154
155 /* PVC */
156
157 { XE_RTP_NAME("18018781329"),
158 XE_RTP_RULES(PLATFORM(PVC)),
159 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
160 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
161 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
162 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
163 },
164 { XE_RTP_NAME("16016694945"),
165 XE_RTP_RULES(PLATFORM(PVC)),
166 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC))
167 },
168
169 /* Xe_LPG */
170
171 { XE_RTP_NAME("14015795083"),
172 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)),
173 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
174 },
175 { XE_RTP_NAME("14018575942"),
176 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)),
177 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))
178 },
179 { XE_RTP_NAME("22016670082"),
180 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)),
181 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR))
182 },
183
184 /* Xe_LPM+ */
185
186 { XE_RTP_NAME("16021867713"),
187 XE_RTP_RULES(MEDIA_VERSION(1300),
188 ENGINE_CLASS(VIDEO_DECODE)),
189 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
190 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
191 },
192 { XE_RTP_NAME("22016670082"),
193 XE_RTP_RULES(MEDIA_VERSION(1300)),
194 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR))
195 },
196
197 /* Xe2_LPG */
198
199 { XE_RTP_NAME("16020975621"),
200 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),
201 XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, SBEUNIT_CLKGATE_DIS))
202 },
203 { XE_RTP_NAME("14018157293"),
204 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),
205 XE_RTP_ACTIONS(SET(XEHPC_L3CLOS_MASK(0), ~0),
206 SET(XEHPC_L3CLOS_MASK(1), ~0),
207 SET(XEHPC_L3CLOS_MASK(2), ~0),
208 SET(XEHPC_L3CLOS_MASK(3), ~0))
209 },
210
211 /* Xe2_LPM */
212
213 { XE_RTP_NAME("14017421178"),
214 XE_RTP_RULES(MEDIA_VERSION(2000),
215 ENGINE_CLASS(VIDEO_DECODE)),
216 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
217 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
218 },
219 { XE_RTP_NAME("16021867713"),
220 XE_RTP_RULES(MEDIA_VERSION(2000),
221 ENGINE_CLASS(VIDEO_DECODE)),
222 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
223 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
224 },
225 { XE_RTP_NAME("14019449301"),
226 XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)),
227 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
228 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
229 },
230
231 {}
232};
233
234static const struct xe_rtp_entry_sr engine_was[] = {
235 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
236 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
237 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE),
238 FF_TESSELATION_DOP_GATE_DISABLE))
239 },
240 { XE_RTP_NAME("1409804808"),
241 XE_RTP_RULES(GRAPHICS_VERSION(1200),
242 ENGINE_CLASS(RENDER),
243 IS_INTEGRATED),
244 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS))
245 },
246 { XE_RTP_NAME("14010229206, 1409085225"),
247 XE_RTP_RULES(GRAPHICS_VERSION(1200),
248 ENGINE_CLASS(RENDER),
249 IS_INTEGRATED),
250 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
251 },
252 { XE_RTP_NAME("1606931601"),
253 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
254 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ))
255 },
256 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"),
257 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)),
258 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE),
259 FF_DOP_CLOCK_GATE_DISABLE))
260 },
261 { XE_RTP_NAME("1406941453"),
262 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
263 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL))
264 },
265 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
266 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
267 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE),
268 FFSC_PERCTX_PREEMPT_CTRL))
269 },
270
271 /* TGL */
272
273 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
274 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),
275 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
276 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
277 RC_SEMA_IDLE_MSG_DISABLE))
278 },
279
280 /* RKL */
281
282 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
283 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),
284 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
285 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
286 RC_SEMA_IDLE_MSG_DISABLE))
287 },
288
289 /* ADL-P */
290
291 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
292 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)),
293 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
294 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
295 RC_SEMA_IDLE_MSG_DISABLE))
296 },
297
298 /* DG2 */
299
300 { XE_RTP_NAME("22013037850"),
301 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
302 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
303 DISABLE_128B_EVICTION_COMMAND_UDW))
304 },
305 { XE_RTP_NAME("22014226127"),
306 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
307 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
308 },
309 { XE_RTP_NAME("18017747507"),
310 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
311 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN,
312 POLYGON_TRIFAN_LINELOOP_DISABLE))
313 },
314 { XE_RTP_NAME("22012826095, 22013059131"),
315 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
316 FUNC(xe_rtp_match_first_render_or_compute)),
317 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
318 MAXREQS_PER_BANK,
319 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))
320 },
321 { XE_RTP_NAME("22013059131"),
322 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
323 FUNC(xe_rtp_match_first_render_or_compute)),
324 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
325 },
326 { XE_RTP_NAME("14015227452"),
327 XE_RTP_RULES(PLATFORM(DG2),
328 FUNC(xe_rtp_match_first_render_or_compute)),
329 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
330 },
331 { XE_RTP_NAME("16015675438"),
332 XE_RTP_RULES(PLATFORM(DG2),
333 FUNC(xe_rtp_match_first_render_or_compute)),
334 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2(RENDER_RING_BASE),
335 PERF_FIX_BALANCING_CFE_DISABLE))
336 },
337 { XE_RTP_NAME("18028616096"),
338 XE_RTP_RULES(PLATFORM(DG2),
339 FUNC(xe_rtp_match_first_render_or_compute)),
340 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
341 },
342 { XE_RTP_NAME("22015475538"),
343 XE_RTP_RULES(PLATFORM(DG2),
344 FUNC(xe_rtp_match_first_render_or_compute)),
345 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))
346 },
347 { XE_RTP_NAME("22012654132"),
348 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
349 FUNC(xe_rtp_match_first_render_or_compute)),
350 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
351 /*
352 * Register can't be read back for verification on
353 * DG2 due to Wa_14012342262
354 */
355 .read_mask = 0))
356 },
357 { XE_RTP_NAME("1509727124"),
358 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
359 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB))
360 },
361 { XE_RTP_NAME("22012856258"),
362 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
363 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION))
364 },
365 { XE_RTP_NAME("22010960976, 14013347512"),
366 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
367 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0,
368 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK))
369 },
370 { XE_RTP_NAME("14015150844"),
371 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
372 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
373 XE_RTP_NOCHECK))
374 },
375
376 /* PVC */
377
378 { XE_RTP_NAME("22014226127"),
379 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
380 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
381 },
382 { XE_RTP_NAME("14015227452"),
383 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
384 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
385 },
386 { XE_RTP_NAME("16015675438"),
387 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
388 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2(RENDER_RING_BASE),
389 PERF_FIX_BALANCING_CFE_DISABLE))
390 },
391 { XE_RTP_NAME("14014999345"),
392 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE),
393 GRAPHICS_STEP(B0, C0)),
394 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC))
395 },
396
397 /* Xe_LPG */
398
399 { XE_RTP_NAME("14017856879"),
400 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271),
401 FUNC(xe_rtp_match_first_render_or_compute)),
402 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH))
403 },
404 { XE_RTP_NAME("14015150844"),
405 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271),
406 FUNC(xe_rtp_match_first_render_or_compute)),
407 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
408 XE_RTP_NOCHECK))
409 },
410
411 /* Xe2_LPG */
412
413 { XE_RTP_NAME("18032247524"),
414 XE_RTP_RULES(GRAPHICS_VERSION(2004),
415 FUNC(xe_rtp_match_first_render_or_compute)),
416 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
417 },
418 { XE_RTP_NAME("16018712365"),
419 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
420 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
421 },
422 { XE_RTP_NAME("14018957109"),
423 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
424 FUNC(xe_rtp_match_first_render_or_compute)),
425 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN5, DISABLE_SAMPLE_G_PERFORMANCE))
426 },
427 { XE_RTP_NAME("16021540221"),
428 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
429 FUNC(xe_rtp_match_first_render_or_compute)),
430 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
431 },
432 { XE_RTP_NAME("14019322943"),
433 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
434 FUNC(xe_rtp_match_first_render_or_compute)),
435 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE))
436 },
437 { XE_RTP_NAME("14018471104"),
438 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
439 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
440 },
441 { XE_RTP_NAME("16018737384"),
442 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
443 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
444 },
445 /*
446 * These two workarounds are the same, just applying to different
447 * engines. Although Wa_18032095049 (for the RCS) isn't required on
448 * all steppings, disabling these reports has no impact for our
449 * driver or the GuC, so we go ahead and treat it the same as
450 * Wa_16021639441 which does apply to all steppings.
451 */
452 { XE_RTP_NAME("18032095049, 16021639441"),
453 XE_RTP_RULES(GRAPHICS_VERSION(2004)),
454 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
455 GHWSP_CSB_REPORT_DIS |
456 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
457 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
458 },
459 { XE_RTP_NAME("16018610683"),
460 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
461 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
462 },
463 {}
464};
465
466static const struct xe_rtp_entry_sr lrc_was[] = {
467 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"),
468 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
469 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3,
470 DISABLE_CPS_AWARE_COLOR_PIPE))
471 },
472 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),
473 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
474 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE),
475 PREEMPT_GPGPU_LEVEL_MASK,
476 PREEMPT_GPGPU_THREAD_GROUP_LEVEL))
477 },
478 { XE_RTP_NAME("1806527549"),
479 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
480 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE))
481 },
482 { XE_RTP_NAME("1606376872"),
483 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
484 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC))
485 },
486
487 /* DG1 */
488
489 { XE_RTP_NAME("1409044764"),
490 XE_RTP_RULES(PLATFORM(DG1)),
491 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3,
492 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN))
493 },
494 { XE_RTP_NAME("22010493298"),
495 XE_RTP_RULES(PLATFORM(DG1)),
496 XE_RTP_ACTIONS(SET(HIZ_CHICKEN,
497 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE))
498 },
499
500 /* DG2 */
501
502 { XE_RTP_NAME("16013271637"),
503 XE_RTP_RULES(PLATFORM(DG2)),
504 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1,
505 MSC_MSAA_REODER_BUF_BYPASS_DISABLE))
506 },
507 { XE_RTP_NAME("14014947963"),
508 XE_RTP_RULES(PLATFORM(DG2)),
509 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION,
510 PREEMPTION_VERTEX_COUNT,
511 0x4000))
512 },
513 { XE_RTP_NAME("18018764978"),
514 XE_RTP_RULES(PLATFORM(DG2)),
515 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2,
516 SCOREBOARD_STALL_FLUSH_CONTROL))
517 },
518 { XE_RTP_NAME("18019271663"),
519 XE_RTP_RULES(PLATFORM(DG2)),
520 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
521 },
522 { XE_RTP_NAME("14019877138"),
523 XE_RTP_RULES(PLATFORM(DG2)),
524 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
525 },
526
527 /* PVC */
528
529 { XE_RTP_NAME("16017236439"),
530 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY),
531 FUNC(xe_rtp_match_even_instance)),
532 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0),
533 BCS_SWCTRL_DISABLE_256B,
534 XE_RTP_ACTION_FLAG(ENGINE_BASE))),
535 },
536
537 /* Xe_LPG */
538
539 { XE_RTP_NAME("18019271663"),
540 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)),
541 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
542 },
543 { XE_RTP_NAME("14019877138"),
544 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), ENGINE_CLASS(RENDER)),
545 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
546 },
547
548 /* Xe2_LPG */
549
550 { XE_RTP_NAME("16020518922"),
551 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
552 ENGINE_CLASS(RENDER)),
553 XE_RTP_ACTIONS(SET(FF_MODE,
554 DIS_TE_AUTOSTRIP |
555 DIS_MESH_PARTIAL_AUTOSTRIP |
556 DIS_MESH_AUTOSTRIP),
557 SET(VFLSKPD,
558 DIS_PARTIAL_AUTOSTRIP |
559 DIS_AUTOSTRIP))
560 },
561 { XE_RTP_NAME("14019386621"),
562 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
563 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
564 },
565 { XE_RTP_NAME("14019877138"),
566 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
567 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
568 },
569 { XE_RTP_NAME("14020013138"),
570 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
571 ENGINE_CLASS(RENDER)),
572 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
573 },
574 { XE_RTP_NAME("14019988906"),
575 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
576 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
577 },
578 { XE_RTP_NAME("16020183090"),
579 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
580 ENGINE_CLASS(RENDER)),
581 XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT))
582 },
583
584 {}
585};
586
587static __maybe_unused const struct xe_rtp_entry oob_was[] = {
588#include <generated/xe_wa_oob.c>
589 {}
590};
591
592static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);
593
594__diag_pop();
595
596/**
597 * xe_wa_process_oob - process OOB workaround table
598 * @gt: GT instance to process workarounds for
599 *
600 * Process OOB workaround table for this platform, marking in @gt the
601 * workarounds that are active.
602 */
603void xe_wa_process_oob(struct xe_gt *gt)
604{
605 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
606
607 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob,
608 ARRAY_SIZE(oob_was));
609 xe_rtp_process(&ctx, oob_was);
610}
611
612/**
613 * xe_wa_process_gt - process GT workaround table
614 * @gt: GT instance to process workarounds for
615 *
616 * Process GT workaround table for this platform, saving in @gt all the
617 * workarounds that need to be applied at the GT level.
618 */
619void xe_wa_process_gt(struct xe_gt *gt)
620{
621 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
622
623 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt,
624 ARRAY_SIZE(gt_was));
625 xe_rtp_process_to_sr(&ctx, gt_was, >->reg_sr);
626}
627EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt);
628
629/**
630 * xe_wa_process_engine - process engine workaround table
631 * @hwe: engine instance to process workarounds for
632 *
633 * Process engine workaround table for this platform, saving in @hwe all the
634 * workarounds that need to be applied at the engine level that match this
635 * engine.
636 */
637void xe_wa_process_engine(struct xe_hw_engine *hwe)
638{
639 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
640
641 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine,
642 ARRAY_SIZE(engine_was));
643 xe_rtp_process_to_sr(&ctx, engine_was, &hwe->reg_sr);
644}
645
646/**
647 * xe_wa_process_lrc - process context workaround table
648 * @hwe: engine instance to process workarounds for
649 *
650 * Process context workaround table for this platform, saving in @hwe all the
651 * workarounds that need to be applied on context restore. These are workarounds
652 * touching registers that are part of the HW context image.
653 */
654void xe_wa_process_lrc(struct xe_hw_engine *hwe)
655{
656 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
657
658 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc,
659 ARRAY_SIZE(lrc_was));
660 xe_rtp_process_to_sr(&ctx, lrc_was, &hwe->reg_lrc);
661}
662
663/**
664 * xe_wa_init - initialize gt with workaround bookkeeping
665 * @gt: GT instance to initialize
666 *
667 * Returns 0 for success, negative error code otherwise.
668 */
669int xe_wa_init(struct xe_gt *gt)
670{
671 struct xe_device *xe = gt_to_xe(gt);
672 size_t n_oob, n_lrc, n_engine, n_gt, total;
673 unsigned long *p;
674
675 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was));
676 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was));
677 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was));
678 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was));
679 total = n_gt + n_engine + n_lrc + n_oob;
680
681 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
682 if (!p)
683 return -ENOMEM;
684
685 gt->wa_active.gt = p;
686 p += n_gt;
687 gt->wa_active.engine = p;
688 p += n_engine;
689 gt->wa_active.lrc = p;
690 p += n_lrc;
691 gt->wa_active.oob = p;
692
693 return 0;
694}
695
696void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p)
697{
698 size_t idx;
699
700 drm_printf(p, "GT Workarounds\n");
701 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was))
702 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name);
703
704 drm_printf(p, "\nEngine Workarounds\n");
705 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was))
706 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name);
707
708 drm_printf(p, "\nLRC Workarounds\n");
709 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was))
710 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name);
711
712 drm_printf(p, "\nOOB Workarounds\n");
713 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was))
714 if (oob_was[idx].name)
715 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);
716}
717
718/*
719 * Apply tile (non-GT, non-display) workarounds. Think very carefully before
720 * adding anything to this function; most workarounds should be implemented
721 * elsewhere. The programming here is primarily for sgunit/soc workarounds,
722 * which are relatively rare. Since the registers these workarounds target are
723 * outside the GT, they should only need to be applied once at device
724 * probe/resume; they will not lose their values on any kind of GT or engine
725 * reset.
726 *
727 * TODO: We may want to move this over to xe_rtp in the future once we have
728 * enough workarounds to justify the work.
729 */
730void xe_wa_apply_tile_workarounds(struct xe_tile *tile)
731{
732 struct xe_gt *mmio = tile->primary_gt;
733
734 if (XE_WA(mmio, 22010954014))
735 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
736}