1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
 4 *
 5 * Device Tree binding constants clock controllers of Samsung S3C2412.
 6 */
 7
 8#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H
 9#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H
10
11/*
12 * Let each exported clock get a unique index, which is used on DT-enabled
13 * platforms to lookup the clock from a clock specifier. These indices are
14 * therefore considered an ABI and so must not be changed. This implies
15 * that new clocks should be added either in free spaces between clock groups
16 * or at the end.
17 */
18
19/* Core clocks. */
20
21/* id 1 is reserved */
22#define MPLL			2
23#define UPLL			3
24#define MDIVCLK			4
25#define MSYSCLK			5
26#define USYSCLK			6
27#define HCLK			7
28#define PCLK			8
29#define ARMDIV			9
30#define ARMCLK			10
31
32
33/* Special clocks */
34#define SCLK_CAM		16
35#define SCLK_UART		17
36#define SCLK_I2S		18
37#define SCLK_USBD		19
38#define SCLK_USBH		20
39
40/* pclk-gates */
41#define PCLK_WDT		32
42#define PCLK_SPI		33
43#define PCLK_I2S		34
44#define PCLK_I2C		35
45#define PCLK_ADC		36
46#define PCLK_RTC		37
47#define PCLK_GPIO		38
48#define PCLK_UART2		39
49#define PCLK_UART1		40
50#define PCLK_UART0		41
51#define PCLK_SDI		42
52#define PCLK_PWM		43
53#define PCLK_USBD		44
54
55/* hclk-gates */
56#define HCLK_HALF		48
57#define HCLK_X2			49
58#define HCLK_SDRAM		50
59#define HCLK_USBH		51
60#define HCLK_LCD		52
61#define HCLK_NAND		53
62#define HCLK_DMA3		54
63#define HCLK_DMA2		55
64#define HCLK_DMA1		56
65#define HCLK_DMA0		57
66
67/* Total number of clocks. */
68#define NR_CLKS			(HCLK_DMA0 + 1)
69
70#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H */