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1// SPDX-License-Identifier: GPL-2.0
2/* linux/drivers/usb/gadget/s3c-hsudc.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com/
6 *
7 * S3C24XX USB 2.0 High-speed USB controller gadget driver
8 *
9 * The S3C24XX USB 2.0 high-speed USB controller supports upto 9 endpoints.
10 * Each endpoint can be configured as either in or out endpoint. Endpoints
11 * can be configured for Bulk or Interrupt transfer mode.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/spinlock.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
20#include <linux/delay.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23#include <linux/clk.h>
24#include <linux/err.h>
25#include <linux/usb/ch9.h>
26#include <linux/usb/gadget.h>
27#include <linux/usb/otg.h>
28#include <linux/prefetch.h>
29#include <linux/platform_data/s3c-hsudc.h>
30#include <linux/regulator/consumer.h>
31#include <linux/pm_runtime.h>
32
33#define S3C_HSUDC_REG(x) (x)
34
35/* Non-Indexed Registers */
36#define S3C_IR S3C_HSUDC_REG(0x00) /* Index Register */
37#define S3C_EIR S3C_HSUDC_REG(0x04) /* EP Intr Status */
38#define S3C_EIR_EP0 (1<<0)
39#define S3C_EIER S3C_HSUDC_REG(0x08) /* EP Intr Enable */
40#define S3C_FAR S3C_HSUDC_REG(0x0c) /* Gadget Address */
41#define S3C_FNR S3C_HSUDC_REG(0x10) /* Frame Number */
42#define S3C_EDR S3C_HSUDC_REG(0x14) /* EP Direction */
43#define S3C_TR S3C_HSUDC_REG(0x18) /* Test Register */
44#define S3C_SSR S3C_HSUDC_REG(0x1c) /* System Status */
45#define S3C_SSR_DTZIEN_EN (0xff8f)
46#define S3C_SSR_ERR (0xff80)
47#define S3C_SSR_VBUSON (1 << 8)
48#define S3C_SSR_HSP (1 << 4)
49#define S3C_SSR_SDE (1 << 3)
50#define S3C_SSR_RESUME (1 << 2)
51#define S3C_SSR_SUSPEND (1 << 1)
52#define S3C_SSR_RESET (1 << 0)
53#define S3C_SCR S3C_HSUDC_REG(0x20) /* System Control */
54#define S3C_SCR_DTZIEN_EN (1 << 14)
55#define S3C_SCR_RRD_EN (1 << 5)
56#define S3C_SCR_SUS_EN (1 << 1)
57#define S3C_SCR_RST_EN (1 << 0)
58#define S3C_EP0SR S3C_HSUDC_REG(0x24) /* EP0 Status */
59#define S3C_EP0SR_EP0_LWO (1 << 6)
60#define S3C_EP0SR_STALL (1 << 4)
61#define S3C_EP0SR_TX_SUCCESS (1 << 1)
62#define S3C_EP0SR_RX_SUCCESS (1 << 0)
63#define S3C_EP0CR S3C_HSUDC_REG(0x28) /* EP0 Control */
64#define S3C_BR(_x) S3C_HSUDC_REG(0x60 + (_x * 4))
65
66/* Indexed Registers */
67#define S3C_ESR S3C_HSUDC_REG(0x2c) /* EPn Status */
68#define S3C_ESR_FLUSH (1 << 6)
69#define S3C_ESR_STALL (1 << 5)
70#define S3C_ESR_LWO (1 << 4)
71#define S3C_ESR_PSIF_ONE (1 << 2)
72#define S3C_ESR_PSIF_TWO (2 << 2)
73#define S3C_ESR_TX_SUCCESS (1 << 1)
74#define S3C_ESR_RX_SUCCESS (1 << 0)
75#define S3C_ECR S3C_HSUDC_REG(0x30) /* EPn Control */
76#define S3C_ECR_DUEN (1 << 7)
77#define S3C_ECR_FLUSH (1 << 6)
78#define S3C_ECR_STALL (1 << 1)
79#define S3C_ECR_IEMS (1 << 0)
80#define S3C_BRCR S3C_HSUDC_REG(0x34) /* Read Count */
81#define S3C_BWCR S3C_HSUDC_REG(0x38) /* Write Count */
82#define S3C_MPR S3C_HSUDC_REG(0x3c) /* Max Pkt Size */
83
84#define WAIT_FOR_SETUP (0)
85#define DATA_STATE_XMIT (1)
86#define DATA_STATE_RECV (2)
87
88static const char * const s3c_hsudc_supply_names[] = {
89 "vdda", /* analog phy supply, 3.3V */
90 "vddi", /* digital phy supply, 1.2V */
91 "vddosc", /* oscillator supply, 1.8V - 3.3V */
92};
93
94/**
95 * struct s3c_hsudc_ep - Endpoint representation used by driver.
96 * @ep: USB gadget layer representation of device endpoint.
97 * @name: Endpoint name (as required by ep autoconfiguration).
98 * @dev: Reference to the device controller to which this EP belongs.
99 * @desc: Endpoint descriptor obtained from the gadget driver.
100 * @queue: Transfer request queue for the endpoint.
101 * @stopped: Maintains state of endpoint, set if EP is halted.
102 * @bEndpointAddress: EP address (including direction bit).
103 * @fifo: Base address of EP FIFO.
104 */
105struct s3c_hsudc_ep {
106 struct usb_ep ep;
107 char name[20];
108 struct s3c_hsudc *dev;
109 struct list_head queue;
110 u8 stopped;
111 u8 wedge;
112 u8 bEndpointAddress;
113 void __iomem *fifo;
114};
115
116/**
117 * struct s3c_hsudc_req - Driver encapsulation of USB gadget transfer request.
118 * @req: Reference to USB gadget transfer request.
119 * @queue: Used for inserting this request to the endpoint request queue.
120 */
121struct s3c_hsudc_req {
122 struct usb_request req;
123 struct list_head queue;
124};
125
126/**
127 * struct s3c_hsudc - Driver's abstraction of the device controller.
128 * @gadget: Instance of usb_gadget which is referenced by gadget driver.
129 * @driver: Reference to currently active gadget driver.
130 * @dev: The device reference used by probe function.
131 * @lock: Lock to synchronize the usage of Endpoints (EP's are indexed).
132 * @regs: Remapped base address of controller's register space.
133 * irq: IRQ number used by the controller.
134 * uclk: Reference to the controller clock.
135 * ep0state: Current state of EP0.
136 * ep: List of endpoints supported by the controller.
137 */
138struct s3c_hsudc {
139 struct usb_gadget gadget;
140 struct usb_gadget_driver *driver;
141 struct device *dev;
142 struct s3c24xx_hsudc_platdata *pd;
143 struct usb_phy *transceiver;
144 struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsudc_supply_names)];
145 spinlock_t lock;
146 void __iomem *regs;
147 int irq;
148 struct clk *uclk;
149 int ep0state;
150 struct s3c_hsudc_ep ep[];
151};
152
153#define ep_maxpacket(_ep) ((_ep)->ep.maxpacket)
154#define ep_is_in(_ep) ((_ep)->bEndpointAddress & USB_DIR_IN)
155#define ep_index(_ep) ((_ep)->bEndpointAddress & \
156 USB_ENDPOINT_NUMBER_MASK)
157
158static const char driver_name[] = "s3c-udc";
159static const char ep0name[] = "ep0-control";
160
161static inline struct s3c_hsudc_req *our_req(struct usb_request *req)
162{
163 return container_of(req, struct s3c_hsudc_req, req);
164}
165
166static inline struct s3c_hsudc_ep *our_ep(struct usb_ep *ep)
167{
168 return container_of(ep, struct s3c_hsudc_ep, ep);
169}
170
171static inline struct s3c_hsudc *to_hsudc(struct usb_gadget *gadget)
172{
173 return container_of(gadget, struct s3c_hsudc, gadget);
174}
175
176static inline void set_index(struct s3c_hsudc *hsudc, int ep_addr)
177{
178 ep_addr &= USB_ENDPOINT_NUMBER_MASK;
179 writel(ep_addr, hsudc->regs + S3C_IR);
180}
181
182static inline void __orr32(void __iomem *ptr, u32 val)
183{
184 writel(readl(ptr) | val, ptr);
185}
186
187/**
188 * s3c_hsudc_complete_request - Complete a transfer request.
189 * @hsep: Endpoint to which the request belongs.
190 * @hsreq: Transfer request to be completed.
191 * @status: Transfer completion status for the transfer request.
192 */
193static void s3c_hsudc_complete_request(struct s3c_hsudc_ep *hsep,
194 struct s3c_hsudc_req *hsreq, int status)
195{
196 unsigned int stopped = hsep->stopped;
197 struct s3c_hsudc *hsudc = hsep->dev;
198
199 list_del_init(&hsreq->queue);
200 hsreq->req.status = status;
201
202 if (!ep_index(hsep)) {
203 hsudc->ep0state = WAIT_FOR_SETUP;
204 hsep->bEndpointAddress &= ~USB_DIR_IN;
205 }
206
207 hsep->stopped = 1;
208 spin_unlock(&hsudc->lock);
209 usb_gadget_giveback_request(&hsep->ep, &hsreq->req);
210 spin_lock(&hsudc->lock);
211 hsep->stopped = stopped;
212}
213
214/**
215 * s3c_hsudc_nuke_ep - Terminate all requests queued for a endpoint.
216 * @hsep: Endpoint for which queued requests have to be terminated.
217 * @status: Transfer completion status for the transfer request.
218 */
219static void s3c_hsudc_nuke_ep(struct s3c_hsudc_ep *hsep, int status)
220{
221 struct s3c_hsudc_req *hsreq;
222
223 while (!list_empty(&hsep->queue)) {
224 hsreq = list_entry(hsep->queue.next,
225 struct s3c_hsudc_req, queue);
226 s3c_hsudc_complete_request(hsep, hsreq, status);
227 }
228}
229
230/**
231 * s3c_hsudc_stop_activity - Stop activity on all endpoints.
232 * @hsudc: Device controller for which EP activity is to be stopped.
233 *
234 * All the endpoints are stopped and any pending transfer requests if any on
235 * the endpoint are terminated.
236 */
237static void s3c_hsudc_stop_activity(struct s3c_hsudc *hsudc)
238{
239 struct s3c_hsudc_ep *hsep;
240 int epnum;
241
242 hsudc->gadget.speed = USB_SPEED_UNKNOWN;
243
244 for (epnum = 0; epnum < hsudc->pd->epnum; epnum++) {
245 hsep = &hsudc->ep[epnum];
246 hsep->stopped = 1;
247 s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
248 }
249}
250
251/**
252 * s3c_hsudc_read_setup_pkt - Read the received setup packet from EP0 fifo.
253 * @hsudc: Device controller from which setup packet is to be read.
254 * @buf: The buffer into which the setup packet is read.
255 *
256 * The setup packet received in the EP0 fifo is read and stored into a
257 * given buffer address.
258 */
259
260static void s3c_hsudc_read_setup_pkt(struct s3c_hsudc *hsudc, u16 *buf)
261{
262 int count;
263
264 count = readl(hsudc->regs + S3C_BRCR);
265 while (count--)
266 *buf++ = (u16)readl(hsudc->regs + S3C_BR(0));
267
268 writel(S3C_EP0SR_RX_SUCCESS, hsudc->regs + S3C_EP0SR);
269}
270
271/**
272 * s3c_hsudc_write_fifo - Write next chunk of transfer data to EP fifo.
273 * @hsep: Endpoint to which the data is to be written.
274 * @hsreq: Transfer request from which the next chunk of data is written.
275 *
276 * Write the next chunk of data from a transfer request to the endpoint FIFO.
277 * If the transfer request completes, 1 is returned, otherwise 0 is returned.
278 */
279static int s3c_hsudc_write_fifo(struct s3c_hsudc_ep *hsep,
280 struct s3c_hsudc_req *hsreq)
281{
282 u16 *buf;
283 u32 max = ep_maxpacket(hsep);
284 u32 count, length;
285 bool is_last;
286 void __iomem *fifo = hsep->fifo;
287
288 buf = hsreq->req.buf + hsreq->req.actual;
289 prefetch(buf);
290
291 length = hsreq->req.length - hsreq->req.actual;
292 length = min(length, max);
293 hsreq->req.actual += length;
294
295 writel(length, hsep->dev->regs + S3C_BWCR);
296 for (count = 0; count < length; count += 2)
297 writel(*buf++, fifo);
298
299 if (count != max) {
300 is_last = true;
301 } else {
302 if (hsreq->req.length != hsreq->req.actual || hsreq->req.zero)
303 is_last = false;
304 else
305 is_last = true;
306 }
307
308 if (is_last) {
309 s3c_hsudc_complete_request(hsep, hsreq, 0);
310 return 1;
311 }
312
313 return 0;
314}
315
316/**
317 * s3c_hsudc_read_fifo - Read the next chunk of data from EP fifo.
318 * @hsep: Endpoint from which the data is to be read.
319 * @hsreq: Transfer request to which the next chunk of data read is written.
320 *
321 * Read the next chunk of data from the endpoint FIFO and a write it to the
322 * transfer request buffer. If the transfer request completes, 1 is returned,
323 * otherwise 0 is returned.
324 */
325static int s3c_hsudc_read_fifo(struct s3c_hsudc_ep *hsep,
326 struct s3c_hsudc_req *hsreq)
327{
328 struct s3c_hsudc *hsudc = hsep->dev;
329 u32 csr, offset;
330 u16 *buf, word;
331 u32 buflen, rcnt, rlen;
332 void __iomem *fifo = hsep->fifo;
333 u32 is_short = 0;
334
335 offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
336 csr = readl(hsudc->regs + offset);
337 if (!(csr & S3C_ESR_RX_SUCCESS))
338 return -EINVAL;
339
340 buf = hsreq->req.buf + hsreq->req.actual;
341 prefetchw(buf);
342 buflen = hsreq->req.length - hsreq->req.actual;
343
344 rcnt = readl(hsudc->regs + S3C_BRCR);
345 rlen = (csr & S3C_ESR_LWO) ? (rcnt * 2 - 1) : (rcnt * 2);
346
347 hsreq->req.actual += min(rlen, buflen);
348 is_short = (rlen < hsep->ep.maxpacket);
349
350 while (rcnt-- != 0) {
351 word = (u16)readl(fifo);
352 if (buflen) {
353 *buf++ = word;
354 buflen--;
355 } else {
356 hsreq->req.status = -EOVERFLOW;
357 }
358 }
359
360 writel(S3C_ESR_RX_SUCCESS, hsudc->regs + offset);
361
362 if (is_short || hsreq->req.actual == hsreq->req.length) {
363 s3c_hsudc_complete_request(hsep, hsreq, 0);
364 return 1;
365 }
366
367 return 0;
368}
369
370/**
371 * s3c_hsudc_epin_intr - Handle in-endpoint interrupt.
372 * @hsudc - Device controller for which the interrupt is to be handled.
373 * @ep_idx - Endpoint number on which an interrupt is pending.
374 *
375 * Handles interrupt for a in-endpoint. The interrupts that are handled are
376 * stall and data transmit complete interrupt.
377 */
378static void s3c_hsudc_epin_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
379{
380 struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
381 struct s3c_hsudc_req *hsreq;
382 u32 csr;
383
384 csr = readl(hsudc->regs + S3C_ESR);
385 if (csr & S3C_ESR_STALL) {
386 writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
387 return;
388 }
389
390 if (csr & S3C_ESR_TX_SUCCESS) {
391 writel(S3C_ESR_TX_SUCCESS, hsudc->regs + S3C_ESR);
392 if (list_empty(&hsep->queue))
393 return;
394
395 hsreq = list_entry(hsep->queue.next,
396 struct s3c_hsudc_req, queue);
397 if ((s3c_hsudc_write_fifo(hsep, hsreq) == 0) &&
398 (csr & S3C_ESR_PSIF_TWO))
399 s3c_hsudc_write_fifo(hsep, hsreq);
400 }
401}
402
403/**
404 * s3c_hsudc_epout_intr - Handle out-endpoint interrupt.
405 * @hsudc - Device controller for which the interrupt is to be handled.
406 * @ep_idx - Endpoint number on which an interrupt is pending.
407 *
408 * Handles interrupt for a out-endpoint. The interrupts that are handled are
409 * stall, flush and data ready interrupt.
410 */
411static void s3c_hsudc_epout_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
412{
413 struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
414 struct s3c_hsudc_req *hsreq;
415 u32 csr;
416
417 csr = readl(hsudc->regs + S3C_ESR);
418 if (csr & S3C_ESR_STALL) {
419 writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
420 return;
421 }
422
423 if (csr & S3C_ESR_FLUSH) {
424 __orr32(hsudc->regs + S3C_ECR, S3C_ECR_FLUSH);
425 return;
426 }
427
428 if (csr & S3C_ESR_RX_SUCCESS) {
429 if (list_empty(&hsep->queue))
430 return;
431
432 hsreq = list_entry(hsep->queue.next,
433 struct s3c_hsudc_req, queue);
434 if (((s3c_hsudc_read_fifo(hsep, hsreq)) == 0) &&
435 (csr & S3C_ESR_PSIF_TWO))
436 s3c_hsudc_read_fifo(hsep, hsreq);
437 }
438}
439
440/** s3c_hsudc_set_halt - Set or clear a endpoint halt.
441 * @_ep: Endpoint on which halt has to be set or cleared.
442 * @value: 1 for setting halt on endpoint, 0 to clear halt.
443 *
444 * Set or clear endpoint halt. If halt is set, the endpoint is stopped.
445 * If halt is cleared, for in-endpoints, if there are any pending
446 * transfer requests, transfers are started.
447 */
448static int s3c_hsudc_set_halt(struct usb_ep *_ep, int value)
449{
450 struct s3c_hsudc_ep *hsep = our_ep(_ep);
451 struct s3c_hsudc *hsudc = hsep->dev;
452 struct s3c_hsudc_req *hsreq;
453 unsigned long irqflags;
454 u32 ecr;
455 u32 offset;
456
457 if (value && ep_is_in(hsep) && !list_empty(&hsep->queue))
458 return -EAGAIN;
459
460 spin_lock_irqsave(&hsudc->lock, irqflags);
461 set_index(hsudc, ep_index(hsep));
462 offset = (ep_index(hsep)) ? S3C_ECR : S3C_EP0CR;
463 ecr = readl(hsudc->regs + offset);
464
465 if (value) {
466 ecr |= S3C_ECR_STALL;
467 if (ep_index(hsep))
468 ecr |= S3C_ECR_FLUSH;
469 hsep->stopped = 1;
470 } else {
471 ecr &= ~S3C_ECR_STALL;
472 hsep->stopped = hsep->wedge = 0;
473 }
474 writel(ecr, hsudc->regs + offset);
475
476 if (ep_is_in(hsep) && !list_empty(&hsep->queue) && !value) {
477 hsreq = list_entry(hsep->queue.next,
478 struct s3c_hsudc_req, queue);
479 if (hsreq)
480 s3c_hsudc_write_fifo(hsep, hsreq);
481 }
482
483 spin_unlock_irqrestore(&hsudc->lock, irqflags);
484 return 0;
485}
486
487/** s3c_hsudc_set_wedge - Sets the halt feature with the clear requests ignored
488 * @_ep: Endpoint on which wedge has to be set.
489 *
490 * Sets the halt feature with the clear requests ignored.
491 */
492static int s3c_hsudc_set_wedge(struct usb_ep *_ep)
493{
494 struct s3c_hsudc_ep *hsep = our_ep(_ep);
495
496 if (!hsep)
497 return -EINVAL;
498
499 hsep->wedge = 1;
500 return usb_ep_set_halt(_ep);
501}
502
503/** s3c_hsudc_handle_reqfeat - Handle set feature or clear feature requests.
504 * @_ep: Device controller on which the set/clear feature needs to be handled.
505 * @ctrl: Control request as received on the endpoint 0.
506 *
507 * Handle set feature or clear feature control requests on the control endpoint.
508 */
509static int s3c_hsudc_handle_reqfeat(struct s3c_hsudc *hsudc,
510 struct usb_ctrlrequest *ctrl)
511{
512 struct s3c_hsudc_ep *hsep;
513 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
514 u8 ep_num = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
515
516 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
517 hsep = &hsudc->ep[ep_num];
518 switch (le16_to_cpu(ctrl->wValue)) {
519 case USB_ENDPOINT_HALT:
520 if (set || !hsep->wedge)
521 s3c_hsudc_set_halt(&hsep->ep, set);
522 return 0;
523 }
524 }
525
526 return -ENOENT;
527}
528
529/**
530 * s3c_hsudc_process_req_status - Handle get status control request.
531 * @hsudc: Device controller on which get status request has be handled.
532 * @ctrl: Control request as received on the endpoint 0.
533 *
534 * Handle get status control request received on control endpoint.
535 */
536static void s3c_hsudc_process_req_status(struct s3c_hsudc *hsudc,
537 struct usb_ctrlrequest *ctrl)
538{
539 struct s3c_hsudc_ep *hsep0 = &hsudc->ep[0];
540 struct s3c_hsudc_req hsreq;
541 struct s3c_hsudc_ep *hsep;
542 __le16 reply;
543 u8 epnum;
544
545 switch (ctrl->bRequestType & USB_RECIP_MASK) {
546 case USB_RECIP_DEVICE:
547 reply = cpu_to_le16(0);
548 break;
549
550 case USB_RECIP_INTERFACE:
551 reply = cpu_to_le16(0);
552 break;
553
554 case USB_RECIP_ENDPOINT:
555 epnum = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
556 hsep = &hsudc->ep[epnum];
557 reply = cpu_to_le16(hsep->stopped ? 1 : 0);
558 break;
559 }
560
561 INIT_LIST_HEAD(&hsreq.queue);
562 hsreq.req.length = 2;
563 hsreq.req.buf = &reply;
564 hsreq.req.actual = 0;
565 hsreq.req.complete = NULL;
566 s3c_hsudc_write_fifo(hsep0, &hsreq);
567}
568
569/**
570 * s3c_hsudc_process_setup - Process control request received on endpoint 0.
571 * @hsudc: Device controller on which control request has been received.
572 *
573 * Read the control request received on endpoint 0, decode it and handle
574 * the request.
575 */
576static void s3c_hsudc_process_setup(struct s3c_hsudc *hsudc)
577{
578 struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
579 struct usb_ctrlrequest ctrl = {0};
580 int ret;
581
582 s3c_hsudc_nuke_ep(hsep, -EPROTO);
583 s3c_hsudc_read_setup_pkt(hsudc, (u16 *)&ctrl);
584
585 if (ctrl.bRequestType & USB_DIR_IN) {
586 hsep->bEndpointAddress |= USB_DIR_IN;
587 hsudc->ep0state = DATA_STATE_XMIT;
588 } else {
589 hsep->bEndpointAddress &= ~USB_DIR_IN;
590 hsudc->ep0state = DATA_STATE_RECV;
591 }
592
593 switch (ctrl.bRequest) {
594 case USB_REQ_SET_ADDRESS:
595 if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
596 break;
597 hsudc->ep0state = WAIT_FOR_SETUP;
598 return;
599
600 case USB_REQ_GET_STATUS:
601 if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
602 break;
603 s3c_hsudc_process_req_status(hsudc, &ctrl);
604 return;
605
606 case USB_REQ_SET_FEATURE:
607 case USB_REQ_CLEAR_FEATURE:
608 if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
609 break;
610 s3c_hsudc_handle_reqfeat(hsudc, &ctrl);
611 hsudc->ep0state = WAIT_FOR_SETUP;
612 return;
613 }
614
615 if (hsudc->driver) {
616 spin_unlock(&hsudc->lock);
617 ret = hsudc->driver->setup(&hsudc->gadget, &ctrl);
618 spin_lock(&hsudc->lock);
619
620 if (ctrl.bRequest == USB_REQ_SET_CONFIGURATION) {
621 hsep->bEndpointAddress &= ~USB_DIR_IN;
622 hsudc->ep0state = WAIT_FOR_SETUP;
623 }
624
625 if (ret < 0) {
626 dev_err(hsudc->dev, "setup failed, returned %d\n",
627 ret);
628 s3c_hsudc_set_halt(&hsep->ep, 1);
629 hsudc->ep0state = WAIT_FOR_SETUP;
630 hsep->bEndpointAddress &= ~USB_DIR_IN;
631 }
632 }
633}
634
635/** s3c_hsudc_handle_ep0_intr - Handle endpoint 0 interrupt.
636 * @hsudc: Device controller on which endpoint 0 interrupt has occurred.
637 *
638 * Handle endpoint 0 interrupt when it occurs. EP0 interrupt could occur
639 * when a stall handshake is sent to host or data is sent/received on
640 * endpoint 0.
641 */
642static void s3c_hsudc_handle_ep0_intr(struct s3c_hsudc *hsudc)
643{
644 struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
645 struct s3c_hsudc_req *hsreq;
646 u32 csr = readl(hsudc->regs + S3C_EP0SR);
647 u32 ecr;
648
649 if (csr & S3C_EP0SR_STALL) {
650 ecr = readl(hsudc->regs + S3C_EP0CR);
651 ecr &= ~(S3C_ECR_STALL | S3C_ECR_FLUSH);
652 writel(ecr, hsudc->regs + S3C_EP0CR);
653
654 writel(S3C_EP0SR_STALL, hsudc->regs + S3C_EP0SR);
655 hsep->stopped = 0;
656
657 s3c_hsudc_nuke_ep(hsep, -ECONNABORTED);
658 hsudc->ep0state = WAIT_FOR_SETUP;
659 hsep->bEndpointAddress &= ~USB_DIR_IN;
660 return;
661 }
662
663 if (csr & S3C_EP0SR_TX_SUCCESS) {
664 writel(S3C_EP0SR_TX_SUCCESS, hsudc->regs + S3C_EP0SR);
665 if (ep_is_in(hsep)) {
666 if (list_empty(&hsep->queue))
667 return;
668
669 hsreq = list_entry(hsep->queue.next,
670 struct s3c_hsudc_req, queue);
671 s3c_hsudc_write_fifo(hsep, hsreq);
672 }
673 }
674
675 if (csr & S3C_EP0SR_RX_SUCCESS) {
676 if (hsudc->ep0state == WAIT_FOR_SETUP)
677 s3c_hsudc_process_setup(hsudc);
678 else {
679 if (!ep_is_in(hsep)) {
680 if (list_empty(&hsep->queue))
681 return;
682 hsreq = list_entry(hsep->queue.next,
683 struct s3c_hsudc_req, queue);
684 s3c_hsudc_read_fifo(hsep, hsreq);
685 }
686 }
687 }
688}
689
690/**
691 * s3c_hsudc_ep_enable - Enable a endpoint.
692 * @_ep: The endpoint to be enabled.
693 * @desc: Endpoint descriptor.
694 *
695 * Enables a endpoint when called from the gadget driver. Endpoint stall if
696 * any is cleared, transfer type is configured and endpoint interrupt is
697 * enabled.
698 */
699static int s3c_hsudc_ep_enable(struct usb_ep *_ep,
700 const struct usb_endpoint_descriptor *desc)
701{
702 struct s3c_hsudc_ep *hsep;
703 struct s3c_hsudc *hsudc;
704 unsigned long flags;
705 u32 ecr = 0;
706
707 hsep = our_ep(_ep);
708 if (!_ep || !desc || _ep->name == ep0name
709 || desc->bDescriptorType != USB_DT_ENDPOINT
710 || hsep->bEndpointAddress != desc->bEndpointAddress
711 || ep_maxpacket(hsep) < usb_endpoint_maxp(desc))
712 return -EINVAL;
713
714 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
715 && usb_endpoint_maxp(desc) != ep_maxpacket(hsep))
716 || !desc->wMaxPacketSize)
717 return -ERANGE;
718
719 hsudc = hsep->dev;
720 if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
721 return -ESHUTDOWN;
722
723 spin_lock_irqsave(&hsudc->lock, flags);
724
725 set_index(hsudc, hsep->bEndpointAddress);
726 ecr |= ((usb_endpoint_xfer_int(desc)) ? S3C_ECR_IEMS : S3C_ECR_DUEN);
727 writel(ecr, hsudc->regs + S3C_ECR);
728
729 hsep->stopped = hsep->wedge = 0;
730 hsep->ep.desc = desc;
731 hsep->ep.maxpacket = usb_endpoint_maxp(desc);
732
733 s3c_hsudc_set_halt(_ep, 0);
734 __set_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
735
736 spin_unlock_irqrestore(&hsudc->lock, flags);
737 return 0;
738}
739
740/**
741 * s3c_hsudc_ep_disable - Disable a endpoint.
742 * @_ep: The endpoint to be disabled.
743 * @desc: Endpoint descriptor.
744 *
745 * Disables a endpoint when called from the gadget driver.
746 */
747static int s3c_hsudc_ep_disable(struct usb_ep *_ep)
748{
749 struct s3c_hsudc_ep *hsep = our_ep(_ep);
750 struct s3c_hsudc *hsudc = hsep->dev;
751 unsigned long flags;
752
753 if (!_ep || !hsep->ep.desc)
754 return -EINVAL;
755
756 spin_lock_irqsave(&hsudc->lock, flags);
757
758 set_index(hsudc, hsep->bEndpointAddress);
759 __clear_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
760
761 s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
762
763 hsep->ep.desc = NULL;
764 hsep->stopped = 1;
765
766 spin_unlock_irqrestore(&hsudc->lock, flags);
767 return 0;
768}
769
770/**
771 * s3c_hsudc_alloc_request - Allocate a new request.
772 * @_ep: Endpoint for which request is allocated (not used).
773 * @gfp_flags: Flags used for the allocation.
774 *
775 * Allocates a single transfer request structure when called from gadget driver.
776 */
777static struct usb_request *s3c_hsudc_alloc_request(struct usb_ep *_ep,
778 gfp_t gfp_flags)
779{
780 struct s3c_hsudc_req *hsreq;
781
782 hsreq = kzalloc(sizeof(*hsreq), gfp_flags);
783 if (!hsreq)
784 return NULL;
785
786 INIT_LIST_HEAD(&hsreq->queue);
787 return &hsreq->req;
788}
789
790/**
791 * s3c_hsudc_free_request - Deallocate a request.
792 * @ep: Endpoint for which request is deallocated (not used).
793 * @_req: Request to be deallocated.
794 *
795 * Allocates a single transfer request structure when called from gadget driver.
796 */
797static void s3c_hsudc_free_request(struct usb_ep *ep, struct usb_request *_req)
798{
799 struct s3c_hsudc_req *hsreq;
800
801 hsreq = our_req(_req);
802 WARN_ON(!list_empty(&hsreq->queue));
803 kfree(hsreq);
804}
805
806/**
807 * s3c_hsudc_queue - Queue a transfer request for the endpoint.
808 * @_ep: Endpoint for which the request is queued.
809 * @_req: Request to be queued.
810 * @gfp_flags: Not used.
811 *
812 * Start or enqueue a request for a endpoint when called from gadget driver.
813 */
814static int s3c_hsudc_queue(struct usb_ep *_ep, struct usb_request *_req,
815 gfp_t gfp_flags)
816{
817 struct s3c_hsudc_req *hsreq;
818 struct s3c_hsudc_ep *hsep;
819 struct s3c_hsudc *hsudc;
820 unsigned long flags;
821 u32 offset;
822 u32 csr;
823
824 hsreq = our_req(_req);
825 if ((!_req || !_req->complete || !_req->buf ||
826 !list_empty(&hsreq->queue)))
827 return -EINVAL;
828
829 hsep = our_ep(_ep);
830 hsudc = hsep->dev;
831 if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
832 return -ESHUTDOWN;
833
834 spin_lock_irqsave(&hsudc->lock, flags);
835 set_index(hsudc, hsep->bEndpointAddress);
836
837 _req->status = -EINPROGRESS;
838 _req->actual = 0;
839
840 if (!ep_index(hsep) && _req->length == 0) {
841 hsudc->ep0state = WAIT_FOR_SETUP;
842 s3c_hsudc_complete_request(hsep, hsreq, 0);
843 spin_unlock_irqrestore(&hsudc->lock, flags);
844 return 0;
845 }
846
847 if (list_empty(&hsep->queue) && !hsep->stopped) {
848 offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
849 if (ep_is_in(hsep)) {
850 csr = readl(hsudc->regs + offset);
851 if (!(csr & S3C_ESR_TX_SUCCESS) &&
852 (s3c_hsudc_write_fifo(hsep, hsreq) == 1))
853 hsreq = NULL;
854 } else {
855 csr = readl(hsudc->regs + offset);
856 if ((csr & S3C_ESR_RX_SUCCESS)
857 && (s3c_hsudc_read_fifo(hsep, hsreq) == 1))
858 hsreq = NULL;
859 }
860 }
861
862 if (hsreq)
863 list_add_tail(&hsreq->queue, &hsep->queue);
864
865 spin_unlock_irqrestore(&hsudc->lock, flags);
866 return 0;
867}
868
869/**
870 * s3c_hsudc_dequeue - Dequeue a transfer request from an endpoint.
871 * @_ep: Endpoint from which the request is dequeued.
872 * @_req: Request to be dequeued.
873 *
874 * Dequeue a request from a endpoint when called from gadget driver.
875 */
876static int s3c_hsudc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
877{
878 struct s3c_hsudc_ep *hsep = our_ep(_ep);
879 struct s3c_hsudc *hsudc = hsep->dev;
880 struct s3c_hsudc_req *hsreq = NULL, *iter;
881 unsigned long flags;
882
883 hsep = our_ep(_ep);
884 if (!_ep || hsep->ep.name == ep0name)
885 return -EINVAL;
886
887 spin_lock_irqsave(&hsudc->lock, flags);
888
889 list_for_each_entry(iter, &hsep->queue, queue) {
890 if (&iter->req != _req)
891 continue;
892 hsreq = iter;
893 break;
894 }
895 if (!hsreq) {
896 spin_unlock_irqrestore(&hsudc->lock, flags);
897 return -EINVAL;
898 }
899
900 set_index(hsudc, hsep->bEndpointAddress);
901 s3c_hsudc_complete_request(hsep, hsreq, -ECONNRESET);
902
903 spin_unlock_irqrestore(&hsudc->lock, flags);
904 return 0;
905}
906
907static const struct usb_ep_ops s3c_hsudc_ep_ops = {
908 .enable = s3c_hsudc_ep_enable,
909 .disable = s3c_hsudc_ep_disable,
910 .alloc_request = s3c_hsudc_alloc_request,
911 .free_request = s3c_hsudc_free_request,
912 .queue = s3c_hsudc_queue,
913 .dequeue = s3c_hsudc_dequeue,
914 .set_halt = s3c_hsudc_set_halt,
915 .set_wedge = s3c_hsudc_set_wedge,
916};
917
918/**
919 * s3c_hsudc_initep - Initialize a endpoint to default state.
920 * @hsudc - Reference to the device controller.
921 * @hsep - Endpoint to be initialized.
922 * @epnum - Address to be assigned to the endpoint.
923 *
924 * Initialize a endpoint with default configuration.
925 */
926static void s3c_hsudc_initep(struct s3c_hsudc *hsudc,
927 struct s3c_hsudc_ep *hsep, int epnum)
928{
929 char *dir;
930
931 if ((epnum % 2) == 0) {
932 dir = "out";
933 } else {
934 dir = "in";
935 hsep->bEndpointAddress = USB_DIR_IN;
936 }
937
938 hsep->bEndpointAddress |= epnum;
939 if (epnum)
940 snprintf(hsep->name, sizeof(hsep->name), "ep%d%s", epnum, dir);
941 else
942 snprintf(hsep->name, sizeof(hsep->name), "%s", ep0name);
943
944 INIT_LIST_HEAD(&hsep->queue);
945 INIT_LIST_HEAD(&hsep->ep.ep_list);
946 if (epnum)
947 list_add_tail(&hsep->ep.ep_list, &hsudc->gadget.ep_list);
948
949 hsep->dev = hsudc;
950 hsep->ep.name = hsep->name;
951 usb_ep_set_maxpacket_limit(&hsep->ep, epnum ? 512 : 64);
952 hsep->ep.ops = &s3c_hsudc_ep_ops;
953 hsep->fifo = hsudc->regs + S3C_BR(epnum);
954 hsep->ep.desc = NULL;
955 hsep->stopped = 0;
956 hsep->wedge = 0;
957
958 if (epnum == 0) {
959 hsep->ep.caps.type_control = true;
960 hsep->ep.caps.dir_in = true;
961 hsep->ep.caps.dir_out = true;
962 } else {
963 hsep->ep.caps.type_iso = true;
964 hsep->ep.caps.type_bulk = true;
965 hsep->ep.caps.type_int = true;
966 }
967
968 if (epnum & 1)
969 hsep->ep.caps.dir_in = true;
970 else
971 hsep->ep.caps.dir_out = true;
972
973 set_index(hsudc, epnum);
974 writel(hsep->ep.maxpacket, hsudc->regs + S3C_MPR);
975}
976
977/**
978 * s3c_hsudc_setup_ep - Configure all endpoints to default state.
979 * @hsudc: Reference to device controller.
980 *
981 * Configures all endpoints to default state.
982 */
983static void s3c_hsudc_setup_ep(struct s3c_hsudc *hsudc)
984{
985 int epnum;
986
987 hsudc->ep0state = WAIT_FOR_SETUP;
988 INIT_LIST_HEAD(&hsudc->gadget.ep_list);
989 for (epnum = 0; epnum < hsudc->pd->epnum; epnum++)
990 s3c_hsudc_initep(hsudc, &hsudc->ep[epnum], epnum);
991}
992
993/**
994 * s3c_hsudc_reconfig - Reconfigure the device controller to default state.
995 * @hsudc: Reference to device controller.
996 *
997 * Reconfigures the device controller registers to a default state.
998 */
999static void s3c_hsudc_reconfig(struct s3c_hsudc *hsudc)
1000{
1001 writel(0xAA, hsudc->regs + S3C_EDR);
1002 writel(1, hsudc->regs + S3C_EIER);
1003 writel(0, hsudc->regs + S3C_TR);
1004 writel(S3C_SCR_DTZIEN_EN | S3C_SCR_RRD_EN | S3C_SCR_SUS_EN |
1005 S3C_SCR_RST_EN, hsudc->regs + S3C_SCR);
1006 writel(0, hsudc->regs + S3C_EP0CR);
1007
1008 s3c_hsudc_setup_ep(hsudc);
1009}
1010
1011/**
1012 * s3c_hsudc_irq - Interrupt handler for device controller.
1013 * @irq: Not used.
1014 * @_dev: Reference to the device controller.
1015 *
1016 * Interrupt handler for the device controller. This handler handles controller
1017 * interrupts and endpoint interrupts.
1018 */
1019static irqreturn_t s3c_hsudc_irq(int irq, void *_dev)
1020{
1021 struct s3c_hsudc *hsudc = _dev;
1022 struct s3c_hsudc_ep *hsep;
1023 u32 ep_intr;
1024 u32 sys_status;
1025 u32 ep_idx;
1026
1027 spin_lock(&hsudc->lock);
1028
1029 sys_status = readl(hsudc->regs + S3C_SSR);
1030 ep_intr = readl(hsudc->regs + S3C_EIR) & 0x3FF;
1031
1032 if (!ep_intr && !(sys_status & S3C_SSR_DTZIEN_EN)) {
1033 spin_unlock(&hsudc->lock);
1034 return IRQ_HANDLED;
1035 }
1036
1037 if (sys_status) {
1038 if (sys_status & S3C_SSR_VBUSON)
1039 writel(S3C_SSR_VBUSON, hsudc->regs + S3C_SSR);
1040
1041 if (sys_status & S3C_SSR_ERR)
1042 writel(S3C_SSR_ERR, hsudc->regs + S3C_SSR);
1043
1044 if (sys_status & S3C_SSR_SDE) {
1045 writel(S3C_SSR_SDE, hsudc->regs + S3C_SSR);
1046 hsudc->gadget.speed = (sys_status & S3C_SSR_HSP) ?
1047 USB_SPEED_HIGH : USB_SPEED_FULL;
1048 }
1049
1050 if (sys_status & S3C_SSR_SUSPEND) {
1051 writel(S3C_SSR_SUSPEND, hsudc->regs + S3C_SSR);
1052 if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
1053 && hsudc->driver && hsudc->driver->suspend)
1054 hsudc->driver->suspend(&hsudc->gadget);
1055 }
1056
1057 if (sys_status & S3C_SSR_RESUME) {
1058 writel(S3C_SSR_RESUME, hsudc->regs + S3C_SSR);
1059 if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
1060 && hsudc->driver && hsudc->driver->resume)
1061 hsudc->driver->resume(&hsudc->gadget);
1062 }
1063
1064 if (sys_status & S3C_SSR_RESET) {
1065 writel(S3C_SSR_RESET, hsudc->regs + S3C_SSR);
1066 for (ep_idx = 0; ep_idx < hsudc->pd->epnum; ep_idx++) {
1067 hsep = &hsudc->ep[ep_idx];
1068 hsep->stopped = 1;
1069 s3c_hsudc_nuke_ep(hsep, -ECONNRESET);
1070 }
1071 s3c_hsudc_reconfig(hsudc);
1072 hsudc->ep0state = WAIT_FOR_SETUP;
1073 }
1074 }
1075
1076 if (ep_intr & S3C_EIR_EP0) {
1077 writel(S3C_EIR_EP0, hsudc->regs + S3C_EIR);
1078 set_index(hsudc, 0);
1079 s3c_hsudc_handle_ep0_intr(hsudc);
1080 }
1081
1082 ep_intr >>= 1;
1083 ep_idx = 1;
1084 while (ep_intr) {
1085 if (ep_intr & 1) {
1086 hsep = &hsudc->ep[ep_idx];
1087 set_index(hsudc, ep_idx);
1088 writel(1 << ep_idx, hsudc->regs + S3C_EIR);
1089 if (ep_is_in(hsep))
1090 s3c_hsudc_epin_intr(hsudc, ep_idx);
1091 else
1092 s3c_hsudc_epout_intr(hsudc, ep_idx);
1093 }
1094 ep_intr >>= 1;
1095 ep_idx++;
1096 }
1097
1098 spin_unlock(&hsudc->lock);
1099 return IRQ_HANDLED;
1100}
1101
1102static int s3c_hsudc_start(struct usb_gadget *gadget,
1103 struct usb_gadget_driver *driver)
1104{
1105 struct s3c_hsudc *hsudc = to_hsudc(gadget);
1106 int ret;
1107
1108 if (!driver
1109 || driver->max_speed < USB_SPEED_FULL
1110 || !driver->setup)
1111 return -EINVAL;
1112
1113 if (!hsudc)
1114 return -ENODEV;
1115
1116 if (hsudc->driver)
1117 return -EBUSY;
1118
1119 hsudc->driver = driver;
1120
1121 ret = regulator_bulk_enable(ARRAY_SIZE(hsudc->supplies),
1122 hsudc->supplies);
1123 if (ret != 0) {
1124 dev_err(hsudc->dev, "failed to enable supplies: %d\n", ret);
1125 goto err_supplies;
1126 }
1127
1128 /* connect to bus through transceiver */
1129 if (!IS_ERR_OR_NULL(hsudc->transceiver)) {
1130 ret = otg_set_peripheral(hsudc->transceiver->otg,
1131 &hsudc->gadget);
1132 if (ret) {
1133 dev_err(hsudc->dev, "%s: can't bind to transceiver\n",
1134 hsudc->gadget.name);
1135 goto err_otg;
1136 }
1137 }
1138
1139 enable_irq(hsudc->irq);
1140 s3c_hsudc_reconfig(hsudc);
1141
1142 pm_runtime_get_sync(hsudc->dev);
1143
1144 if (hsudc->pd->phy_init)
1145 hsudc->pd->phy_init();
1146 if (hsudc->pd->gpio_init)
1147 hsudc->pd->gpio_init();
1148
1149 return 0;
1150err_otg:
1151 regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
1152err_supplies:
1153 hsudc->driver = NULL;
1154 return ret;
1155}
1156
1157static int s3c_hsudc_stop(struct usb_gadget *gadget)
1158{
1159 struct s3c_hsudc *hsudc = to_hsudc(gadget);
1160 unsigned long flags;
1161
1162 if (!hsudc)
1163 return -ENODEV;
1164
1165 spin_lock_irqsave(&hsudc->lock, flags);
1166 hsudc->gadget.speed = USB_SPEED_UNKNOWN;
1167 if (hsudc->pd->phy_uninit)
1168 hsudc->pd->phy_uninit();
1169
1170 pm_runtime_put(hsudc->dev);
1171
1172 if (hsudc->pd->gpio_uninit)
1173 hsudc->pd->gpio_uninit();
1174 s3c_hsudc_stop_activity(hsudc);
1175 spin_unlock_irqrestore(&hsudc->lock, flags);
1176
1177 if (!IS_ERR_OR_NULL(hsudc->transceiver))
1178 (void) otg_set_peripheral(hsudc->transceiver->otg, NULL);
1179
1180 disable_irq(hsudc->irq);
1181
1182 regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
1183 hsudc->driver = NULL;
1184
1185 return 0;
1186}
1187
1188static inline u32 s3c_hsudc_read_frameno(struct s3c_hsudc *hsudc)
1189{
1190 return readl(hsudc->regs + S3C_FNR) & 0x3FF;
1191}
1192
1193static int s3c_hsudc_gadget_getframe(struct usb_gadget *gadget)
1194{
1195 return s3c_hsudc_read_frameno(to_hsudc(gadget));
1196}
1197
1198static int s3c_hsudc_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1199{
1200 struct s3c_hsudc *hsudc = to_hsudc(gadget);
1201
1202 if (!hsudc)
1203 return -ENODEV;
1204
1205 if (!IS_ERR_OR_NULL(hsudc->transceiver))
1206 return usb_phy_set_power(hsudc->transceiver, mA);
1207
1208 return -EOPNOTSUPP;
1209}
1210
1211static const struct usb_gadget_ops s3c_hsudc_gadget_ops = {
1212 .get_frame = s3c_hsudc_gadget_getframe,
1213 .udc_start = s3c_hsudc_start,
1214 .udc_stop = s3c_hsudc_stop,
1215 .vbus_draw = s3c_hsudc_vbus_draw,
1216};
1217
1218static int s3c_hsudc_probe(struct platform_device *pdev)
1219{
1220 struct device *dev = &pdev->dev;
1221 struct s3c_hsudc *hsudc;
1222 struct s3c24xx_hsudc_platdata *pd = dev_get_platdata(&pdev->dev);
1223 int ret, i;
1224
1225 hsudc = devm_kzalloc(&pdev->dev, struct_size(hsudc, ep, pd->epnum),
1226 GFP_KERNEL);
1227 if (!hsudc)
1228 return -ENOMEM;
1229
1230 platform_set_drvdata(pdev, dev);
1231 hsudc->dev = dev;
1232 hsudc->pd = dev_get_platdata(&pdev->dev);
1233
1234 hsudc->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
1235
1236 for (i = 0; i < ARRAY_SIZE(hsudc->supplies); i++)
1237 hsudc->supplies[i].supply = s3c_hsudc_supply_names[i];
1238
1239 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsudc->supplies),
1240 hsudc->supplies);
1241 if (ret != 0) {
1242 if (ret != -EPROBE_DEFER)
1243 dev_err(dev, "failed to request supplies: %d\n", ret);
1244 goto err_supplies;
1245 }
1246
1247 hsudc->regs = devm_platform_ioremap_resource(pdev, 0);
1248 if (IS_ERR(hsudc->regs)) {
1249 ret = PTR_ERR(hsudc->regs);
1250 goto err_res;
1251 }
1252
1253 spin_lock_init(&hsudc->lock);
1254
1255 hsudc->gadget.max_speed = USB_SPEED_HIGH;
1256 hsudc->gadget.ops = &s3c_hsudc_gadget_ops;
1257 hsudc->gadget.name = dev_name(dev);
1258 hsudc->gadget.ep0 = &hsudc->ep[0].ep;
1259 hsudc->gadget.is_otg = 0;
1260 hsudc->gadget.is_a_peripheral = 0;
1261 hsudc->gadget.speed = USB_SPEED_UNKNOWN;
1262
1263 s3c_hsudc_setup_ep(hsudc);
1264
1265 ret = platform_get_irq(pdev, 0);
1266 if (ret < 0)
1267 goto err_res;
1268 hsudc->irq = ret;
1269
1270 ret = devm_request_irq(&pdev->dev, hsudc->irq, s3c_hsudc_irq, 0,
1271 driver_name, hsudc);
1272 if (ret < 0) {
1273 dev_err(dev, "irq request failed\n");
1274 goto err_res;
1275 }
1276
1277 hsudc->uclk = devm_clk_get(&pdev->dev, "usb-device");
1278 if (IS_ERR(hsudc->uclk)) {
1279 dev_err(dev, "failed to find usb-device clock source\n");
1280 ret = PTR_ERR(hsudc->uclk);
1281 goto err_res;
1282 }
1283 clk_enable(hsudc->uclk);
1284
1285 local_irq_disable();
1286
1287 disable_irq(hsudc->irq);
1288 local_irq_enable();
1289
1290 ret = usb_add_gadget_udc(&pdev->dev, &hsudc->gadget);
1291 if (ret)
1292 goto err_add_udc;
1293
1294 pm_runtime_enable(dev);
1295
1296 return 0;
1297err_add_udc:
1298 clk_disable(hsudc->uclk);
1299err_res:
1300 if (!IS_ERR_OR_NULL(hsudc->transceiver))
1301 usb_put_phy(hsudc->transceiver);
1302
1303err_supplies:
1304 return ret;
1305}
1306
1307static struct platform_driver s3c_hsudc_driver = {
1308 .driver = {
1309 .name = "s3c-hsudc",
1310 },
1311 .probe = s3c_hsudc_probe,
1312};
1313
1314module_platform_driver(s3c_hsudc_driver);
1315
1316MODULE_DESCRIPTION("Samsung S3C24XX USB high-speed controller driver");
1317MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
1318MODULE_LICENSE("GPL");
1319MODULE_ALIAS("platform:s3c-hsudc");