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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Freescale lpuart serial port driver
4 *
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
6 */
7
8#include <linux/bitfield.h>
9#include <linux/bits.h>
10#include <linux/clk.h>
11#include <linux/console.h>
12#include <linux/delay.h>
13#include <linux/dma-mapping.h>
14#include <linux/dmaengine.h>
15#include <linux/dmapool.h>
16#include <linux/io.h>
17#include <linux/iopoll.h>
18#include <linux/irq.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_dma.h>
22#include <linux/pinctrl/consumer.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/serial_core.h>
26#include <linux/slab.h>
27#include <linux/tty_flip.h>
28
29/* All registers are 8-bit width */
30#define UARTBDH 0x00
31#define UARTBDL 0x01
32#define UARTCR1 0x02
33#define UARTCR2 0x03
34#define UARTSR1 0x04
35#define UARTCR3 0x06
36#define UARTDR 0x07
37#define UARTCR4 0x0a
38#define UARTCR5 0x0b
39#define UARTMODEM 0x0d
40#define UARTPFIFO 0x10
41#define UARTCFIFO 0x11
42#define UARTSFIFO 0x12
43#define UARTTWFIFO 0x13
44#define UARTTCFIFO 0x14
45#define UARTRWFIFO 0x15
46
47#define UARTBDH_LBKDIE 0x80
48#define UARTBDH_RXEDGIE 0x40
49#define UARTBDH_SBR_MASK 0x1f
50
51#define UARTCR1_LOOPS 0x80
52#define UARTCR1_RSRC 0x20
53#define UARTCR1_M 0x10
54#define UARTCR1_WAKE 0x08
55#define UARTCR1_ILT 0x04
56#define UARTCR1_PE 0x02
57#define UARTCR1_PT 0x01
58
59#define UARTCR2_TIE 0x80
60#define UARTCR2_TCIE 0x40
61#define UARTCR2_RIE 0x20
62#define UARTCR2_ILIE 0x10
63#define UARTCR2_TE 0x08
64#define UARTCR2_RE 0x04
65#define UARTCR2_RWU 0x02
66#define UARTCR2_SBK 0x01
67
68#define UARTSR1_TDRE 0x80
69#define UARTSR1_TC 0x40
70#define UARTSR1_RDRF 0x20
71#define UARTSR1_IDLE 0x10
72#define UARTSR1_OR 0x08
73#define UARTSR1_NF 0x04
74#define UARTSR1_FE 0x02
75#define UARTSR1_PE 0x01
76
77#define UARTCR3_R8 0x80
78#define UARTCR3_T8 0x40
79#define UARTCR3_TXDIR 0x20
80#define UARTCR3_TXINV 0x10
81#define UARTCR3_ORIE 0x08
82#define UARTCR3_NEIE 0x04
83#define UARTCR3_FEIE 0x02
84#define UARTCR3_PEIE 0x01
85
86#define UARTCR4_MAEN1 0x80
87#define UARTCR4_MAEN2 0x40
88#define UARTCR4_M10 0x20
89#define UARTCR4_BRFA_MASK 0x1f
90#define UARTCR4_BRFA_OFF 0
91
92#define UARTCR5_TDMAS 0x80
93#define UARTCR5_RDMAS 0x20
94
95#define UARTMODEM_RXRTSE 0x08
96#define UARTMODEM_TXRTSPOL 0x04
97#define UARTMODEM_TXRTSE 0x02
98#define UARTMODEM_TXCTSE 0x01
99
100#define UARTPFIFO_TXFE 0x80
101#define UARTPFIFO_FIFOSIZE_MASK 0x7
102#define UARTPFIFO_TXSIZE_OFF 4
103#define UARTPFIFO_RXFE 0x08
104#define UARTPFIFO_RXSIZE_OFF 0
105
106#define UARTCFIFO_TXFLUSH 0x80
107#define UARTCFIFO_RXFLUSH 0x40
108#define UARTCFIFO_RXOFE 0x04
109#define UARTCFIFO_TXOFE 0x02
110#define UARTCFIFO_RXUFE 0x01
111
112#define UARTSFIFO_TXEMPT 0x80
113#define UARTSFIFO_RXEMPT 0x40
114#define UARTSFIFO_RXOF 0x04
115#define UARTSFIFO_TXOF 0x02
116#define UARTSFIFO_RXUF 0x01
117
118/* 32-bit global registers only for i.MX7ULP/i.MX8x
119 * Used to reset all internal logic and registers, except the Global Register.
120 */
121#define UART_GLOBAL 0x8
122
123/* 32-bit register definition */
124#define UARTBAUD 0x00
125#define UARTSTAT 0x04
126#define UARTCTRL 0x08
127#define UARTDATA 0x0C
128#define UARTMATCH 0x10
129#define UARTMODIR 0x14
130#define UARTFIFO 0x18
131#define UARTWATER 0x1c
132
133#define UARTBAUD_MAEN1 0x80000000
134#define UARTBAUD_MAEN2 0x40000000
135#define UARTBAUD_M10 0x20000000
136#define UARTBAUD_TDMAE 0x00800000
137#define UARTBAUD_RDMAE 0x00200000
138#define UARTBAUD_MATCFG 0x00400000
139#define UARTBAUD_BOTHEDGE 0x00020000
140#define UARTBAUD_RESYNCDIS 0x00010000
141#define UARTBAUD_LBKDIE 0x00008000
142#define UARTBAUD_RXEDGIE 0x00004000
143#define UARTBAUD_SBNS 0x00002000
144#define UARTBAUD_SBR 0x00000000
145#define UARTBAUD_SBR_MASK 0x1fff
146#define UARTBAUD_OSR_MASK 0x1f
147#define UARTBAUD_OSR_SHIFT 24
148
149#define UARTSTAT_LBKDIF 0x80000000
150#define UARTSTAT_RXEDGIF 0x40000000
151#define UARTSTAT_MSBF 0x20000000
152#define UARTSTAT_RXINV 0x10000000
153#define UARTSTAT_RWUID 0x08000000
154#define UARTSTAT_BRK13 0x04000000
155#define UARTSTAT_LBKDE 0x02000000
156#define UARTSTAT_RAF 0x01000000
157#define UARTSTAT_TDRE 0x00800000
158#define UARTSTAT_TC 0x00400000
159#define UARTSTAT_RDRF 0x00200000
160#define UARTSTAT_IDLE 0x00100000
161#define UARTSTAT_OR 0x00080000
162#define UARTSTAT_NF 0x00040000
163#define UARTSTAT_FE 0x00020000
164#define UARTSTAT_PE 0x00010000
165#define UARTSTAT_MA1F 0x00008000
166#define UARTSTAT_M21F 0x00004000
167
168#define UARTCTRL_R8T9 0x80000000
169#define UARTCTRL_R9T8 0x40000000
170#define UARTCTRL_TXDIR 0x20000000
171#define UARTCTRL_TXINV 0x10000000
172#define UARTCTRL_ORIE 0x08000000
173#define UARTCTRL_NEIE 0x04000000
174#define UARTCTRL_FEIE 0x02000000
175#define UARTCTRL_PEIE 0x01000000
176#define UARTCTRL_TIE 0x00800000
177#define UARTCTRL_TCIE 0x00400000
178#define UARTCTRL_RIE 0x00200000
179#define UARTCTRL_ILIE 0x00100000
180#define UARTCTRL_TE 0x00080000
181#define UARTCTRL_RE 0x00040000
182#define UARTCTRL_RWU 0x00020000
183#define UARTCTRL_SBK 0x00010000
184#define UARTCTRL_MA1IE 0x00008000
185#define UARTCTRL_MA2IE 0x00004000
186#define UARTCTRL_IDLECFG GENMASK(10, 8)
187#define UARTCTRL_LOOPS 0x00000080
188#define UARTCTRL_DOZEEN 0x00000040
189#define UARTCTRL_RSRC 0x00000020
190#define UARTCTRL_M 0x00000010
191#define UARTCTRL_WAKE 0x00000008
192#define UARTCTRL_ILT 0x00000004
193#define UARTCTRL_PE 0x00000002
194#define UARTCTRL_PT 0x00000001
195
196#define UARTDATA_NOISY 0x00008000
197#define UARTDATA_PARITYE 0x00004000
198#define UARTDATA_FRETSC 0x00002000
199#define UARTDATA_RXEMPT 0x00001000
200#define UARTDATA_IDLINE 0x00000800
201#define UARTDATA_MASK 0x3ff
202
203#define UARTMODIR_IREN 0x00020000
204#define UARTMODIR_RTSWATER GENMASK(10, 8)
205#define UARTMODIR_TXCTSSRC 0x00000020
206#define UARTMODIR_TXCTSC 0x00000010
207#define UARTMODIR_RXRTSE 0x00000008
208#define UARTMODIR_TXRTSPOL 0x00000004
209#define UARTMODIR_TXRTSE 0x00000002
210#define UARTMODIR_TXCTSE 0x00000001
211
212#define UARTFIFO_TXEMPT 0x00800000
213#define UARTFIFO_RXEMPT 0x00400000
214#define UARTFIFO_TXOF 0x00020000
215#define UARTFIFO_RXUF 0x00010000
216#define UARTFIFO_TXFLUSH 0x00008000
217#define UARTFIFO_RXFLUSH 0x00004000
218#define UARTFIFO_RXIDEN GENMASK(12, 10)
219#define UARTFIFO_TXOFE 0x00000200
220#define UARTFIFO_RXUFE 0x00000100
221#define UARTFIFO_TXFE 0x00000080
222#define UARTFIFO_FIFOSIZE_MASK 0x7
223#define UARTFIFO_TXSIZE_OFF 4
224#define UARTFIFO_RXFE 0x00000008
225#define UARTFIFO_RXSIZE_OFF 0
226#define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0))
227
228#define UARTWATER_COUNT_MASK 0xff
229#define UARTWATER_TXCNT_OFF 8
230#define UARTWATER_RXCNT_OFF 24
231#define UARTWATER_WATER_MASK 0xff
232#define UARTWATER_TXWATER_OFF 0
233#define UARTWATER_RXWATER_OFF 16
234
235#define UART_GLOBAL_RST 0x2
236#define GLOBAL_RST_MIN_US 20
237#define GLOBAL_RST_MAX_US 40
238
239/* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
240#define DMA_RX_TIMEOUT (10)
241#define DMA_RX_IDLE_CHARS 8
242#define UART_AUTOSUSPEND_TIMEOUT 3000
243
244#define DRIVER_NAME "fsl-lpuart"
245#define DEV_NAME "ttyLP"
246#define UART_NR 8
247
248/* IMX lpuart has four extra unused regs located at the beginning */
249#define IMX_REG_OFF 0x10
250
251enum lpuart_type {
252 VF610_LPUART,
253 LS1021A_LPUART,
254 LS1028A_LPUART,
255 IMX7ULP_LPUART,
256 IMX8ULP_LPUART,
257 IMX8QXP_LPUART,
258 IMXRT1050_LPUART,
259};
260
261struct lpuart_port {
262 struct uart_port port;
263 enum lpuart_type devtype;
264 struct clk *ipg_clk;
265 struct clk *baud_clk;
266 unsigned int txfifo_size;
267 unsigned int rxfifo_size;
268
269 u8 rx_watermark;
270 bool lpuart_dma_tx_use;
271 bool lpuart_dma_rx_use;
272 struct dma_chan *dma_tx_chan;
273 struct dma_chan *dma_rx_chan;
274 struct dma_async_tx_descriptor *dma_tx_desc;
275 struct dma_async_tx_descriptor *dma_rx_desc;
276 dma_cookie_t dma_tx_cookie;
277 dma_cookie_t dma_rx_cookie;
278 unsigned int dma_tx_bytes;
279 unsigned int dma_rx_bytes;
280 bool dma_tx_in_progress;
281 unsigned int dma_rx_timeout;
282 struct timer_list lpuart_timer;
283 struct scatterlist rx_sgl, tx_sgl[2];
284 struct circ_buf rx_ring;
285 int rx_dma_rng_buf_len;
286 int last_residue;
287 unsigned int dma_tx_nents;
288 wait_queue_head_t dma_wait;
289 bool is_cs7; /* Set to true when character size is 7 */
290 /* and the parity is enabled */
291 bool dma_idle_int;
292};
293
294struct lpuart_soc_data {
295 enum lpuart_type devtype;
296 char iotype;
297 u8 reg_off;
298 u8 rx_watermark;
299};
300
301static const struct lpuart_soc_data vf_data = {
302 .devtype = VF610_LPUART,
303 .iotype = UPIO_MEM,
304 .rx_watermark = 1,
305};
306
307static const struct lpuart_soc_data ls1021a_data = {
308 .devtype = LS1021A_LPUART,
309 .iotype = UPIO_MEM32BE,
310 .rx_watermark = 1,
311};
312
313static const struct lpuart_soc_data ls1028a_data = {
314 .devtype = LS1028A_LPUART,
315 .iotype = UPIO_MEM32,
316 .rx_watermark = 0,
317};
318
319static struct lpuart_soc_data imx7ulp_data = {
320 .devtype = IMX7ULP_LPUART,
321 .iotype = UPIO_MEM32,
322 .reg_off = IMX_REG_OFF,
323 .rx_watermark = 1,
324};
325
326static struct lpuart_soc_data imx8ulp_data = {
327 .devtype = IMX8ULP_LPUART,
328 .iotype = UPIO_MEM32,
329 .reg_off = IMX_REG_OFF,
330 .rx_watermark = 3,
331};
332
333static struct lpuart_soc_data imx8qxp_data = {
334 .devtype = IMX8QXP_LPUART,
335 .iotype = UPIO_MEM32,
336 .reg_off = IMX_REG_OFF,
337 .rx_watermark = 7, /* A lower watermark is ideal for low baud rates. */
338};
339static struct lpuart_soc_data imxrt1050_data = {
340 .devtype = IMXRT1050_LPUART,
341 .iotype = UPIO_MEM32,
342 .reg_off = IMX_REG_OFF,
343 .rx_watermark = 1,
344};
345
346static const struct of_device_id lpuart_dt_ids[] = {
347 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
348 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
349 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, },
350 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
351 { .compatible = "fsl,imx8ulp-lpuart", .data = &imx8ulp_data, },
352 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, },
353 { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data},
354 { /* sentinel */ }
355};
356MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
357
358/* Forward declare this for the dma callbacks*/
359static void lpuart_dma_tx_complete(void *arg);
360
361static inline bool is_layerscape_lpuart(struct lpuart_port *sport)
362{
363 return (sport->devtype == LS1021A_LPUART ||
364 sport->devtype == LS1028A_LPUART);
365}
366
367static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport)
368{
369 return sport->devtype == IMX7ULP_LPUART;
370}
371
372static inline bool is_imx8ulp_lpuart(struct lpuart_port *sport)
373{
374 return sport->devtype == IMX8ULP_LPUART;
375}
376
377static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
378{
379 return sport->devtype == IMX8QXP_LPUART;
380}
381
382static inline u32 lpuart32_read(struct uart_port *port, u32 off)
383{
384 switch (port->iotype) {
385 case UPIO_MEM32:
386 return readl(port->membase + off);
387 case UPIO_MEM32BE:
388 return ioread32be(port->membase + off);
389 default:
390 return 0;
391 }
392}
393
394static inline void lpuart32_write(struct uart_port *port, u32 val,
395 u32 off)
396{
397 switch (port->iotype) {
398 case UPIO_MEM32:
399 writel(val, port->membase + off);
400 break;
401 case UPIO_MEM32BE:
402 iowrite32be(val, port->membase + off);
403 break;
404 }
405}
406
407static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
408{
409 int ret = 0;
410
411 if (is_en) {
412 ret = clk_prepare_enable(sport->ipg_clk);
413 if (ret)
414 return ret;
415
416 ret = clk_prepare_enable(sport->baud_clk);
417 if (ret) {
418 clk_disable_unprepare(sport->ipg_clk);
419 return ret;
420 }
421 } else {
422 clk_disable_unprepare(sport->baud_clk);
423 clk_disable_unprepare(sport->ipg_clk);
424 }
425
426 return 0;
427}
428
429static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
430{
431 if (is_imx8qxp_lpuart(sport))
432 return clk_get_rate(sport->baud_clk);
433
434 return clk_get_rate(sport->ipg_clk);
435}
436
437#define lpuart_enable_clks(x) __lpuart_enable_clks(x, true)
438#define lpuart_disable_clks(x) __lpuart_enable_clks(x, false)
439
440static void lpuart_stop_tx(struct uart_port *port)
441{
442 unsigned char temp;
443
444 temp = readb(port->membase + UARTCR2);
445 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
446 writeb(temp, port->membase + UARTCR2);
447}
448
449static void lpuart32_stop_tx(struct uart_port *port)
450{
451 unsigned long temp;
452
453 temp = lpuart32_read(port, UARTCTRL);
454 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
455 lpuart32_write(port, temp, UARTCTRL);
456}
457
458static void lpuart_stop_rx(struct uart_port *port)
459{
460 unsigned char temp;
461
462 temp = readb(port->membase + UARTCR2);
463 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
464}
465
466static void lpuart32_stop_rx(struct uart_port *port)
467{
468 unsigned long temp;
469
470 temp = lpuart32_read(port, UARTCTRL);
471 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
472}
473
474static void lpuart_dma_tx(struct lpuart_port *sport)
475{
476 struct circ_buf *xmit = &sport->port.state->xmit;
477 struct scatterlist *sgl = sport->tx_sgl;
478 struct device *dev = sport->port.dev;
479 struct dma_chan *chan = sport->dma_tx_chan;
480 int ret;
481
482 if (sport->dma_tx_in_progress)
483 return;
484
485 sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
486
487 if (xmit->tail < xmit->head || xmit->head == 0) {
488 sport->dma_tx_nents = 1;
489 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
490 } else {
491 sport->dma_tx_nents = 2;
492 sg_init_table(sgl, 2);
493 sg_set_buf(sgl, xmit->buf + xmit->tail,
494 UART_XMIT_SIZE - xmit->tail);
495 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
496 }
497
498 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,
499 DMA_TO_DEVICE);
500 if (!ret) {
501 dev_err(dev, "DMA mapping error for TX.\n");
502 return;
503 }
504
505 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,
506 ret, DMA_MEM_TO_DEV,
507 DMA_PREP_INTERRUPT);
508 if (!sport->dma_tx_desc) {
509 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
510 DMA_TO_DEVICE);
511 dev_err(dev, "Cannot prepare TX slave DMA!\n");
512 return;
513 }
514
515 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
516 sport->dma_tx_desc->callback_param = sport;
517 sport->dma_tx_in_progress = true;
518 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
519 dma_async_issue_pending(chan);
520}
521
522static bool lpuart_stopped_or_empty(struct uart_port *port)
523{
524 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port);
525}
526
527static void lpuart_dma_tx_complete(void *arg)
528{
529 struct lpuart_port *sport = arg;
530 struct scatterlist *sgl = &sport->tx_sgl[0];
531 struct circ_buf *xmit = &sport->port.state->xmit;
532 struct dma_chan *chan = sport->dma_tx_chan;
533 unsigned long flags;
534
535 uart_port_lock_irqsave(&sport->port, &flags);
536 if (!sport->dma_tx_in_progress) {
537 uart_port_unlock_irqrestore(&sport->port, flags);
538 return;
539 }
540
541 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
542 DMA_TO_DEVICE);
543
544 uart_xmit_advance(&sport->port, sport->dma_tx_bytes);
545 sport->dma_tx_in_progress = false;
546 uart_port_unlock_irqrestore(&sport->port, flags);
547
548 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
549 uart_write_wakeup(&sport->port);
550
551 if (waitqueue_active(&sport->dma_wait)) {
552 wake_up(&sport->dma_wait);
553 return;
554 }
555
556 uart_port_lock_irqsave(&sport->port, &flags);
557
558 if (!lpuart_stopped_or_empty(&sport->port))
559 lpuart_dma_tx(sport);
560
561 uart_port_unlock_irqrestore(&sport->port, flags);
562}
563
564static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
565{
566 switch (sport->port.iotype) {
567 case UPIO_MEM32:
568 return sport->port.mapbase + UARTDATA;
569 case UPIO_MEM32BE:
570 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
571 }
572 return sport->port.mapbase + UARTDR;
573}
574
575static int lpuart_dma_tx_request(struct uart_port *port)
576{
577 struct lpuart_port *sport = container_of(port,
578 struct lpuart_port, port);
579 struct dma_slave_config dma_tx_sconfig = {};
580 int ret;
581
582 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
583 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
584 dma_tx_sconfig.dst_maxburst = 1;
585 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
586 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
587
588 if (ret) {
589 dev_err(sport->port.dev,
590 "DMA slave config failed, err = %d\n", ret);
591 return ret;
592 }
593
594 return 0;
595}
596
597static bool lpuart_is_32(struct lpuart_port *sport)
598{
599 return sport->port.iotype == UPIO_MEM32 ||
600 sport->port.iotype == UPIO_MEM32BE;
601}
602
603static void lpuart_flush_buffer(struct uart_port *port)
604{
605 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
606 struct dma_chan *chan = sport->dma_tx_chan;
607 u32 val;
608
609 if (sport->lpuart_dma_tx_use) {
610 if (sport->dma_tx_in_progress) {
611 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],
612 sport->dma_tx_nents, DMA_TO_DEVICE);
613 sport->dma_tx_in_progress = false;
614 }
615 dmaengine_terminate_async(chan);
616 }
617
618 if (lpuart_is_32(sport)) {
619 val = lpuart32_read(&sport->port, UARTFIFO);
620 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
621 lpuart32_write(&sport->port, val, UARTFIFO);
622 } else {
623 val = readb(sport->port.membase + UARTCFIFO);
624 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
625 writeb(val, sport->port.membase + UARTCFIFO);
626 }
627}
628
629static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
630 u8 bit)
631{
632 while (!(readb(port->membase + offset) & bit))
633 cpu_relax();
634}
635
636static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
637 u32 bit)
638{
639 while (!(lpuart32_read(port, offset) & bit))
640 cpu_relax();
641}
642
643#if defined(CONFIG_CONSOLE_POLL)
644
645static int lpuart_poll_init(struct uart_port *port)
646{
647 struct lpuart_port *sport = container_of(port,
648 struct lpuart_port, port);
649 unsigned long flags;
650 unsigned char temp;
651
652 sport->port.fifosize = 0;
653
654 uart_port_lock_irqsave(&sport->port, &flags);
655 /* Disable Rx & Tx */
656 writeb(0, sport->port.membase + UARTCR2);
657
658 temp = readb(sport->port.membase + UARTPFIFO);
659 /* Enable Rx and Tx FIFO */
660 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
661 sport->port.membase + UARTPFIFO);
662
663 /* flush Tx and Rx FIFO */
664 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
665 sport->port.membase + UARTCFIFO);
666
667 /* explicitly clear RDRF */
668 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
669 readb(sport->port.membase + UARTDR);
670 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
671 }
672
673 writeb(0, sport->port.membase + UARTTWFIFO);
674 writeb(1, sport->port.membase + UARTRWFIFO);
675
676 /* Enable Rx and Tx */
677 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
678 uart_port_unlock_irqrestore(&sport->port, flags);
679
680 return 0;
681}
682
683static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
684{
685 /* drain */
686 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
687 writeb(c, port->membase + UARTDR);
688}
689
690static int lpuart_poll_get_char(struct uart_port *port)
691{
692 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
693 return NO_POLL_CHAR;
694
695 return readb(port->membase + UARTDR);
696}
697
698static int lpuart32_poll_init(struct uart_port *port)
699{
700 unsigned long flags;
701 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
702 u32 temp;
703
704 sport->port.fifosize = 0;
705
706 uart_port_lock_irqsave(&sport->port, &flags);
707
708 /* Disable Rx & Tx */
709 lpuart32_write(&sport->port, 0, UARTCTRL);
710
711 temp = lpuart32_read(&sport->port, UARTFIFO);
712
713 /* Enable Rx and Tx FIFO */
714 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
715
716 /* flush Tx and Rx FIFO */
717 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
718
719 /* explicitly clear RDRF */
720 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
721 lpuart32_read(&sport->port, UARTDATA);
722 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
723 }
724
725 /* Enable Rx and Tx */
726 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
727 uart_port_unlock_irqrestore(&sport->port, flags);
728
729 return 0;
730}
731
732static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
733{
734 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
735 lpuart32_write(port, c, UARTDATA);
736}
737
738static int lpuart32_poll_get_char(struct uart_port *port)
739{
740 if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF))
741 return NO_POLL_CHAR;
742
743 return lpuart32_read(port, UARTDATA);
744}
745#endif
746
747static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
748{
749 struct uart_port *port = &sport->port;
750 u8 ch;
751
752 uart_port_tx(port, ch,
753 readb(port->membase + UARTTCFIFO) < sport->txfifo_size,
754 writeb(ch, port->membase + UARTDR));
755}
756
757static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
758{
759 struct circ_buf *xmit = &sport->port.state->xmit;
760 unsigned long txcnt;
761
762 if (sport->port.x_char) {
763 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
764 sport->port.icount.tx++;
765 sport->port.x_char = 0;
766 return;
767 }
768
769 if (lpuart_stopped_or_empty(&sport->port)) {
770 lpuart32_stop_tx(&sport->port);
771 return;
772 }
773
774 txcnt = lpuart32_read(&sport->port, UARTWATER);
775 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
776 txcnt &= UARTWATER_COUNT_MASK;
777 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
778 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
779 uart_xmit_advance(&sport->port, 1);
780 txcnt = lpuart32_read(&sport->port, UARTWATER);
781 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
782 txcnt &= UARTWATER_COUNT_MASK;
783 }
784
785 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
786 uart_write_wakeup(&sport->port);
787
788 if (uart_circ_empty(xmit))
789 lpuart32_stop_tx(&sport->port);
790}
791
792static void lpuart_start_tx(struct uart_port *port)
793{
794 struct lpuart_port *sport = container_of(port,
795 struct lpuart_port, port);
796 unsigned char temp;
797
798 temp = readb(port->membase + UARTCR2);
799 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
800
801 if (sport->lpuart_dma_tx_use) {
802 if (!lpuart_stopped_or_empty(port))
803 lpuart_dma_tx(sport);
804 } else {
805 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
806 lpuart_transmit_buffer(sport);
807 }
808}
809
810static void lpuart32_start_tx(struct uart_port *port)
811{
812 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
813 unsigned long temp;
814
815 if (sport->lpuart_dma_tx_use) {
816 if (!lpuart_stopped_or_empty(port))
817 lpuart_dma_tx(sport);
818 } else {
819 temp = lpuart32_read(port, UARTCTRL);
820 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
821
822 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
823 lpuart32_transmit_buffer(sport);
824 }
825}
826
827static void
828lpuart_uart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
829{
830 switch (state) {
831 case UART_PM_STATE_OFF:
832 pm_runtime_mark_last_busy(port->dev);
833 pm_runtime_put_autosuspend(port->dev);
834 break;
835 default:
836 pm_runtime_get_sync(port->dev);
837 break;
838 }
839}
840
841/* return TIOCSER_TEMT when transmitter is not busy */
842static unsigned int lpuart_tx_empty(struct uart_port *port)
843{
844 struct lpuart_port *sport = container_of(port,
845 struct lpuart_port, port);
846 unsigned char sr1 = readb(port->membase + UARTSR1);
847 unsigned char sfifo = readb(port->membase + UARTSFIFO);
848
849 if (sport->dma_tx_in_progress)
850 return 0;
851
852 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
853 return TIOCSER_TEMT;
854
855 return 0;
856}
857
858static unsigned int lpuart32_tx_empty(struct uart_port *port)
859{
860 struct lpuart_port *sport = container_of(port,
861 struct lpuart_port, port);
862 unsigned long stat = lpuart32_read(port, UARTSTAT);
863 unsigned long sfifo = lpuart32_read(port, UARTFIFO);
864 unsigned long ctrl = lpuart32_read(port, UARTCTRL);
865
866 if (sport->dma_tx_in_progress)
867 return 0;
868
869 /*
870 * LPUART Transmission Complete Flag may never be set while queuing a break
871 * character, so avoid checking for transmission complete when UARTCTRL_SBK
872 * is asserted.
873 */
874 if ((stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) || ctrl & UARTCTRL_SBK)
875 return TIOCSER_TEMT;
876
877 return 0;
878}
879
880static void lpuart_txint(struct lpuart_port *sport)
881{
882 uart_port_lock(&sport->port);
883 lpuart_transmit_buffer(sport);
884 uart_port_unlock(&sport->port);
885}
886
887static void lpuart_rxint(struct lpuart_port *sport)
888{
889 unsigned int flg, ignored = 0, overrun = 0;
890 struct tty_port *port = &sport->port.state->port;
891 unsigned char rx, sr;
892
893 uart_port_lock(&sport->port);
894
895 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
896 flg = TTY_NORMAL;
897 sport->port.icount.rx++;
898 /*
899 * to clear the FE, OR, NF, FE, PE flags,
900 * read SR1 then read DR
901 */
902 sr = readb(sport->port.membase + UARTSR1);
903 rx = readb(sport->port.membase + UARTDR);
904
905 if (uart_prepare_sysrq_char(&sport->port, rx))
906 continue;
907
908 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
909 if (sr & UARTSR1_PE)
910 sport->port.icount.parity++;
911 else if (sr & UARTSR1_FE)
912 sport->port.icount.frame++;
913
914 if (sr & UARTSR1_OR)
915 overrun++;
916
917 if (sr & sport->port.ignore_status_mask) {
918 if (++ignored > 100)
919 goto out;
920 continue;
921 }
922
923 sr &= sport->port.read_status_mask;
924
925 if (sr & UARTSR1_PE)
926 flg = TTY_PARITY;
927 else if (sr & UARTSR1_FE)
928 flg = TTY_FRAME;
929
930 if (sr & UARTSR1_OR)
931 flg = TTY_OVERRUN;
932
933 sport->port.sysrq = 0;
934 }
935
936 if (tty_insert_flip_char(port, rx, flg) == 0)
937 sport->port.icount.buf_overrun++;
938 }
939
940out:
941 if (overrun) {
942 sport->port.icount.overrun += overrun;
943
944 /*
945 * Overruns cause FIFO pointers to become missaligned.
946 * Flushing the receive FIFO reinitializes the pointers.
947 */
948 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
949 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
950 }
951
952 uart_unlock_and_check_sysrq(&sport->port);
953
954 tty_flip_buffer_push(port);
955}
956
957static void lpuart32_txint(struct lpuart_port *sport)
958{
959 uart_port_lock(&sport->port);
960 lpuart32_transmit_buffer(sport);
961 uart_port_unlock(&sport->port);
962}
963
964static void lpuart32_rxint(struct lpuart_port *sport)
965{
966 unsigned int flg, ignored = 0;
967 struct tty_port *port = &sport->port.state->port;
968 unsigned long rx, sr;
969 bool is_break;
970
971 uart_port_lock(&sport->port);
972
973 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
974 flg = TTY_NORMAL;
975 sport->port.icount.rx++;
976 /*
977 * to clear the FE, OR, NF, FE, PE flags,
978 * read STAT then read DATA reg
979 */
980 sr = lpuart32_read(&sport->port, UARTSTAT);
981 rx = lpuart32_read(&sport->port, UARTDATA);
982 rx &= UARTDATA_MASK;
983
984 /*
985 * The LPUART can't distinguish between a break and a framing error,
986 * thus we assume it is a break if the received data is zero.
987 */
988 is_break = (sr & UARTSTAT_FE) && !rx;
989
990 if (is_break && uart_handle_break(&sport->port))
991 continue;
992
993 if (uart_prepare_sysrq_char(&sport->port, rx))
994 continue;
995
996 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
997 if (sr & UARTSTAT_PE) {
998 sport->port.icount.parity++;
999 } else if (sr & UARTSTAT_FE) {
1000 if (is_break)
1001 sport->port.icount.brk++;
1002 else
1003 sport->port.icount.frame++;
1004 }
1005
1006 if (sr & UARTSTAT_OR)
1007 sport->port.icount.overrun++;
1008
1009 if (sr & sport->port.ignore_status_mask) {
1010 if (++ignored > 100)
1011 goto out;
1012 continue;
1013 }
1014
1015 sr &= sport->port.read_status_mask;
1016
1017 if (sr & UARTSTAT_PE) {
1018 flg = TTY_PARITY;
1019 } else if (sr & UARTSTAT_FE) {
1020 if (is_break)
1021 flg = TTY_BREAK;
1022 else
1023 flg = TTY_FRAME;
1024 }
1025
1026 if (sr & UARTSTAT_OR)
1027 flg = TTY_OVERRUN;
1028 }
1029
1030 if (sport->is_cs7)
1031 rx &= 0x7F;
1032
1033 if (tty_insert_flip_char(port, rx, flg) == 0)
1034 sport->port.icount.buf_overrun++;
1035 }
1036
1037out:
1038 uart_unlock_and_check_sysrq(&sport->port);
1039
1040 tty_flip_buffer_push(port);
1041}
1042
1043static irqreturn_t lpuart_int(int irq, void *dev_id)
1044{
1045 struct lpuart_port *sport = dev_id;
1046 unsigned char sts;
1047
1048 sts = readb(sport->port.membase + UARTSR1);
1049
1050 /* SysRq, using dma, check for linebreak by framing err. */
1051 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) {
1052 readb(sport->port.membase + UARTDR);
1053 uart_handle_break(&sport->port);
1054 /* linebreak produces some garbage, removing it */
1055 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
1056 return IRQ_HANDLED;
1057 }
1058
1059 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
1060 lpuart_rxint(sport);
1061
1062 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
1063 lpuart_txint(sport);
1064
1065 return IRQ_HANDLED;
1066}
1067
1068static inline void lpuart_handle_sysrq_chars(struct uart_port *port,
1069 unsigned char *p, int count)
1070{
1071 while (count--) {
1072 if (*p && uart_handle_sysrq_char(port, *p))
1073 return;
1074 p++;
1075 }
1076}
1077
1078static void lpuart_handle_sysrq(struct lpuart_port *sport)
1079{
1080 struct circ_buf *ring = &sport->rx_ring;
1081 int count;
1082
1083 if (ring->head < ring->tail) {
1084 count = sport->rx_sgl.length - ring->tail;
1085 lpuart_handle_sysrq_chars(&sport->port,
1086 ring->buf + ring->tail, count);
1087 ring->tail = 0;
1088 }
1089
1090 if (ring->head > ring->tail) {
1091 count = ring->head - ring->tail;
1092 lpuart_handle_sysrq_chars(&sport->port,
1093 ring->buf + ring->tail, count);
1094 ring->tail = ring->head;
1095 }
1096}
1097
1098static int lpuart_tty_insert_flip_string(struct tty_port *port,
1099 unsigned char *chars, size_t size, bool is_cs7)
1100{
1101 int i;
1102
1103 if (is_cs7)
1104 for (i = 0; i < size; i++)
1105 chars[i] &= 0x7F;
1106 return tty_insert_flip_string(port, chars, size);
1107}
1108
1109static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
1110{
1111 struct tty_port *port = &sport->port.state->port;
1112 struct dma_tx_state state;
1113 enum dma_status dmastat;
1114 struct dma_chan *chan = sport->dma_rx_chan;
1115 struct circ_buf *ring = &sport->rx_ring;
1116 unsigned long flags;
1117 int count, copied;
1118
1119 if (lpuart_is_32(sport)) {
1120 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
1121
1122 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
1123 /* Clear the error flags */
1124 lpuart32_write(&sport->port, sr, UARTSTAT);
1125
1126 if (sr & UARTSTAT_PE)
1127 sport->port.icount.parity++;
1128 else if (sr & UARTSTAT_FE)
1129 sport->port.icount.frame++;
1130 }
1131 } else {
1132 unsigned char sr = readb(sport->port.membase + UARTSR1);
1133
1134 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
1135 unsigned char cr2;
1136
1137 /* Disable receiver during this operation... */
1138 cr2 = readb(sport->port.membase + UARTCR2);
1139 cr2 &= ~UARTCR2_RE;
1140 writeb(cr2, sport->port.membase + UARTCR2);
1141
1142 /* Read DR to clear the error flags */
1143 readb(sport->port.membase + UARTDR);
1144
1145 if (sr & UARTSR1_PE)
1146 sport->port.icount.parity++;
1147 else if (sr & UARTSR1_FE)
1148 sport->port.icount.frame++;
1149 /*
1150 * At this point parity/framing error is
1151 * cleared However, since the DMA already read
1152 * the data register and we had to read it
1153 * again after reading the status register to
1154 * properly clear the flags, the FIFO actually
1155 * underflowed... This requires a clearing of
1156 * the FIFO...
1157 */
1158 if (readb(sport->port.membase + UARTSFIFO) &
1159 UARTSFIFO_RXUF) {
1160 writeb(UARTSFIFO_RXUF,
1161 sport->port.membase + UARTSFIFO);
1162 writeb(UARTCFIFO_RXFLUSH,
1163 sport->port.membase + UARTCFIFO);
1164 }
1165
1166 cr2 |= UARTCR2_RE;
1167 writeb(cr2, sport->port.membase + UARTCR2);
1168 }
1169 }
1170
1171 async_tx_ack(sport->dma_rx_desc);
1172
1173 uart_port_lock_irqsave(&sport->port, &flags);
1174
1175 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1176 if (dmastat == DMA_ERROR) {
1177 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1178 uart_port_unlock_irqrestore(&sport->port, flags);
1179 return;
1180 }
1181
1182 /* CPU claims ownership of RX DMA buffer */
1183 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,
1184 DMA_FROM_DEVICE);
1185
1186 /*
1187 * ring->head points to the end of data already written by the DMA.
1188 * ring->tail points to the beginning of data to be read by the
1189 * framework.
1190 * The current transfer size should not be larger than the dma buffer
1191 * length.
1192 */
1193 ring->head = sport->rx_sgl.length - state.residue;
1194 BUG_ON(ring->head > sport->rx_sgl.length);
1195
1196 /*
1197 * Silent handling of keys pressed in the sysrq timeframe
1198 */
1199 if (sport->port.sysrq) {
1200 lpuart_handle_sysrq(sport);
1201 goto exit;
1202 }
1203
1204 /*
1205 * At this point ring->head may point to the first byte right after the
1206 * last byte of the dma buffer:
1207 * 0 <= ring->head <= sport->rx_sgl.length
1208 *
1209 * However ring->tail must always points inside the dma buffer:
1210 * 0 <= ring->tail <= sport->rx_sgl.length - 1
1211 *
1212 * Since we use a ring buffer, we have to handle the case
1213 * where head is lower than tail. In such a case, we first read from
1214 * tail to the end of the buffer then reset tail.
1215 */
1216 if (ring->head < ring->tail) {
1217 count = sport->rx_sgl.length - ring->tail;
1218
1219 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
1220 count, sport->is_cs7);
1221 if (copied != count)
1222 sport->port.icount.buf_overrun++;
1223 ring->tail = 0;
1224 sport->port.icount.rx += copied;
1225 }
1226
1227 /* Finally we read data from tail to head */
1228 if (ring->tail < ring->head) {
1229 count = ring->head - ring->tail;
1230 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
1231 count, sport->is_cs7);
1232 if (copied != count)
1233 sport->port.icount.buf_overrun++;
1234 /* Wrap ring->head if needed */
1235 if (ring->head >= sport->rx_sgl.length)
1236 ring->head = 0;
1237 ring->tail = ring->head;
1238 sport->port.icount.rx += copied;
1239 }
1240
1241 sport->last_residue = state.residue;
1242
1243exit:
1244 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
1245 DMA_FROM_DEVICE);
1246
1247 uart_port_unlock_irqrestore(&sport->port, flags);
1248
1249 tty_flip_buffer_push(port);
1250 if (!sport->dma_idle_int)
1251 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1252}
1253
1254static void lpuart_dma_rx_complete(void *arg)
1255{
1256 struct lpuart_port *sport = arg;
1257
1258 lpuart_copy_rx_to_tty(sport);
1259}
1260
1261static void lpuart32_dma_idleint(struct lpuart_port *sport)
1262{
1263 enum dma_status dmastat;
1264 struct dma_chan *chan = sport->dma_rx_chan;
1265 struct circ_buf *ring = &sport->rx_ring;
1266 struct dma_tx_state state;
1267 int count = 0;
1268
1269 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1270 if (dmastat == DMA_ERROR) {
1271 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1272 return;
1273 }
1274
1275 ring->head = sport->rx_sgl.length - state.residue;
1276 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length);
1277
1278 /* Check if new data received before copying */
1279 if (count)
1280 lpuart_copy_rx_to_tty(sport);
1281}
1282
1283static irqreturn_t lpuart32_int(int irq, void *dev_id)
1284{
1285 struct lpuart_port *sport = dev_id;
1286 unsigned long sts, rxcount;
1287
1288 sts = lpuart32_read(&sport->port, UARTSTAT);
1289 rxcount = lpuart32_read(&sport->port, UARTWATER);
1290 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
1291
1292 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
1293 lpuart32_rxint(sport);
1294
1295 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
1296 lpuart32_txint(sport);
1297
1298 if ((sts & UARTSTAT_IDLE) && sport->lpuart_dma_rx_use && sport->dma_idle_int)
1299 lpuart32_dma_idleint(sport);
1300
1301 lpuart32_write(&sport->port, sts, UARTSTAT);
1302 return IRQ_HANDLED;
1303}
1304
1305/*
1306 * Timer function to simulate the hardware EOP (End Of Package) event.
1307 * The timer callback is to check for new RX data and copy to TTY buffer.
1308 * If no new data are received since last interval, the EOP condition is
1309 * met, complete the DMA transfer by copying the data. Otherwise, just
1310 * restart timer.
1311 */
1312static void lpuart_timer_func(struct timer_list *t)
1313{
1314 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1315 enum dma_status dmastat;
1316 struct dma_chan *chan = sport->dma_rx_chan;
1317 struct circ_buf *ring = &sport->rx_ring;
1318 struct dma_tx_state state;
1319 unsigned long flags;
1320 int count;
1321
1322 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1323 if (dmastat == DMA_ERROR) {
1324 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1325 return;
1326 }
1327
1328 ring->head = sport->rx_sgl.length - state.residue;
1329 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length);
1330
1331 /* Check if new data received before copying */
1332 if ((count != 0) && (sport->last_residue == state.residue))
1333 lpuart_copy_rx_to_tty(sport);
1334 else
1335 mod_timer(&sport->lpuart_timer,
1336 jiffies + sport->dma_rx_timeout);
1337
1338 if (uart_port_trylock_irqsave(&sport->port, &flags)) {
1339 sport->last_residue = state.residue;
1340 uart_port_unlock_irqrestore(&sport->port, flags);
1341 }
1342}
1343
1344static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1345{
1346 struct dma_slave_config dma_rx_sconfig = {};
1347 struct circ_buf *ring = &sport->rx_ring;
1348 int ret, nent;
1349 struct tty_port *port = &sport->port.state->port;
1350 struct tty_struct *tty = port->tty;
1351 struct ktermios *termios = &tty->termios;
1352 struct dma_chan *chan = sport->dma_rx_chan;
1353 unsigned int bits = tty_get_frame_size(termios->c_cflag);
1354 unsigned int baud = tty_get_baud_rate(tty);
1355
1356 /*
1357 * Calculate length of one DMA buffer size to keep latency below
1358 * 10ms at any baud rate.
1359 */
1360 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2;
1361 sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len));
1362 sport->rx_dma_rng_buf_len = max_t(int,
1363 sport->rxfifo_size * 2,
1364 sport->rx_dma_rng_buf_len);
1365 /*
1366 * Keep this condition check in case rxfifo_size is unavailable
1367 * for some SoCs.
1368 */
1369 if (sport->rx_dma_rng_buf_len < 16)
1370 sport->rx_dma_rng_buf_len = 16;
1371
1372 sport->last_residue = 0;
1373 sport->dma_rx_timeout = max(nsecs_to_jiffies(
1374 sport->port.frame_time * DMA_RX_IDLE_CHARS), 1UL);
1375
1376 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1377 if (!ring->buf)
1378 return -ENOMEM;
1379
1380 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1381 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,
1382 DMA_FROM_DEVICE);
1383
1384 if (!nent) {
1385 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1386 return -EINVAL;
1387 }
1388
1389 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1390 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1391 dma_rx_sconfig.src_maxburst = 1;
1392 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1393 ret = dmaengine_slave_config(chan, &dma_rx_sconfig);
1394
1395 if (ret < 0) {
1396 dev_err(sport->port.dev,
1397 "DMA Rx slave config failed, err = %d\n", ret);
1398 return ret;
1399 }
1400
1401 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,
1402 sg_dma_address(&sport->rx_sgl),
1403 sport->rx_sgl.length,
1404 sport->rx_sgl.length / 2,
1405 DMA_DEV_TO_MEM,
1406 DMA_PREP_INTERRUPT);
1407 if (!sport->dma_rx_desc) {
1408 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1409 return -EFAULT;
1410 }
1411
1412 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1413 sport->dma_rx_desc->callback_param = sport;
1414 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1415 dma_async_issue_pending(chan);
1416
1417 if (lpuart_is_32(sport)) {
1418 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1419
1420 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1421
1422 if (sport->dma_idle_int) {
1423 unsigned long ctrl = lpuart32_read(&sport->port, UARTCTRL);
1424
1425 lpuart32_write(&sport->port, ctrl | UARTCTRL_ILIE, UARTCTRL);
1426 }
1427 } else {
1428 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1429 sport->port.membase + UARTCR5);
1430 }
1431
1432 return 0;
1433}
1434
1435static void lpuart_dma_rx_free(struct uart_port *port)
1436{
1437 struct lpuart_port *sport = container_of(port,
1438 struct lpuart_port, port);
1439 struct dma_chan *chan = sport->dma_rx_chan;
1440
1441 dmaengine_terminate_sync(chan);
1442 if (!sport->dma_idle_int)
1443 del_timer_sync(&sport->lpuart_timer);
1444
1445 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1446 kfree(sport->rx_ring.buf);
1447 sport->rx_ring.tail = 0;
1448 sport->rx_ring.head = 0;
1449 sport->dma_rx_desc = NULL;
1450 sport->dma_rx_cookie = -EINVAL;
1451}
1452
1453static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios,
1454 struct serial_rs485 *rs485)
1455{
1456 struct lpuart_port *sport = container_of(port,
1457 struct lpuart_port, port);
1458
1459 u8 modem = readb(sport->port.membase + UARTMODEM) &
1460 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1461 writeb(modem, sport->port.membase + UARTMODEM);
1462
1463 if (rs485->flags & SER_RS485_ENABLED) {
1464 /* Enable auto RS-485 RTS mode */
1465 modem |= UARTMODEM_TXRTSE;
1466
1467 /*
1468 * The hardware defaults to RTS logic HIGH while transfer.
1469 * Switch polarity in case RTS shall be logic HIGH
1470 * after transfer.
1471 * Note: UART is assumed to be active high.
1472 */
1473 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1474 modem |= UARTMODEM_TXRTSPOL;
1475 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1476 modem &= ~UARTMODEM_TXRTSPOL;
1477 }
1478
1479 writeb(modem, sport->port.membase + UARTMODEM);
1480 return 0;
1481}
1482
1483static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termios,
1484 struct serial_rs485 *rs485)
1485{
1486 struct lpuart_port *sport = container_of(port,
1487 struct lpuart_port, port);
1488
1489 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
1490 & ~(UARTMODIR_TXRTSPOL | UARTMODIR_TXRTSE);
1491 lpuart32_write(&sport->port, modem, UARTMODIR);
1492
1493 if (rs485->flags & SER_RS485_ENABLED) {
1494 /* Enable auto RS-485 RTS mode */
1495 modem |= UARTMODIR_TXRTSE;
1496
1497 /*
1498 * The hardware defaults to RTS logic HIGH while transfer.
1499 * Switch polarity in case RTS shall be logic HIGH
1500 * after transfer.
1501 * Note: UART is assumed to be active high.
1502 */
1503 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1504 modem |= UARTMODIR_TXRTSPOL;
1505 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1506 modem &= ~UARTMODIR_TXRTSPOL;
1507 }
1508
1509 lpuart32_write(&sport->port, modem, UARTMODIR);
1510 return 0;
1511}
1512
1513static unsigned int lpuart_get_mctrl(struct uart_port *port)
1514{
1515 unsigned int mctrl = 0;
1516 u8 reg;
1517
1518 reg = readb(port->membase + UARTCR1);
1519 if (reg & UARTCR1_LOOPS)
1520 mctrl |= TIOCM_LOOP;
1521
1522 return mctrl;
1523}
1524
1525static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1526{
1527 unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1528 u32 reg;
1529
1530 reg = lpuart32_read(port, UARTCTRL);
1531 if (reg & UARTCTRL_LOOPS)
1532 mctrl |= TIOCM_LOOP;
1533
1534 return mctrl;
1535}
1536
1537static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1538{
1539 u8 reg;
1540
1541 reg = readb(port->membase + UARTCR1);
1542
1543 /* for internal loopback we need LOOPS=1 and RSRC=0 */
1544 reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC);
1545 if (mctrl & TIOCM_LOOP)
1546 reg |= UARTCR1_LOOPS;
1547
1548 writeb(reg, port->membase + UARTCR1);
1549}
1550
1551static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1552{
1553 u32 reg;
1554
1555 reg = lpuart32_read(port, UARTCTRL);
1556
1557 /* for internal loopback we need LOOPS=1 and RSRC=0 */
1558 reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC);
1559 if (mctrl & TIOCM_LOOP)
1560 reg |= UARTCTRL_LOOPS;
1561
1562 lpuart32_write(port, reg, UARTCTRL);
1563}
1564
1565static void lpuart_break_ctl(struct uart_port *port, int break_state)
1566{
1567 unsigned char temp;
1568
1569 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1570
1571 if (break_state != 0)
1572 temp |= UARTCR2_SBK;
1573
1574 writeb(temp, port->membase + UARTCR2);
1575}
1576
1577static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1578{
1579 unsigned long temp;
1580
1581 temp = lpuart32_read(port, UARTCTRL);
1582
1583 /*
1584 * LPUART IP now has two known bugs, one is CTS has higher priority than the
1585 * break signal, which causes the break signal sending through UARTCTRL_SBK
1586 * may impacted by the CTS input if the HW flow control is enabled. It
1587 * exists on all platforms we support in this driver.
1588 * Another bug is i.MX8QM LPUART may have an additional break character
1589 * being sent after SBK was cleared.
1590 * To avoid above two bugs, we use Transmit Data Inversion function to send
1591 * the break signal instead of UARTCTRL_SBK.
1592 */
1593 if (break_state != 0) {
1594 /*
1595 * Disable the transmitter to prevent any data from being sent out
1596 * during break, then invert the TX line to send break.
1597 */
1598 temp &= ~UARTCTRL_TE;
1599 lpuart32_write(port, temp, UARTCTRL);
1600 temp |= UARTCTRL_TXINV;
1601 lpuart32_write(port, temp, UARTCTRL);
1602 } else {
1603 /* Disable the TXINV to turn off break and re-enable transmitter. */
1604 temp &= ~UARTCTRL_TXINV;
1605 lpuart32_write(port, temp, UARTCTRL);
1606 temp |= UARTCTRL_TE;
1607 lpuart32_write(port, temp, UARTCTRL);
1608 }
1609}
1610
1611static void lpuart_setup_watermark(struct lpuart_port *sport)
1612{
1613 unsigned char val, cr2;
1614 unsigned char cr2_saved;
1615
1616 cr2 = readb(sport->port.membase + UARTCR2);
1617 cr2_saved = cr2;
1618 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1619 UARTCR2_RIE | UARTCR2_RE);
1620 writeb(cr2, sport->port.membase + UARTCR2);
1621
1622 val = readb(sport->port.membase + UARTPFIFO);
1623 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1624 sport->port.membase + UARTPFIFO);
1625
1626 /* flush Tx and Rx FIFO */
1627 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1628 sport->port.membase + UARTCFIFO);
1629
1630 /* explicitly clear RDRF */
1631 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1632 readb(sport->port.membase + UARTDR);
1633 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1634 }
1635
1636 if (uart_console(&sport->port))
1637 sport->rx_watermark = 1;
1638 writeb(0, sport->port.membase + UARTTWFIFO);
1639 writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO);
1640
1641 /* Restore cr2 */
1642 writeb(cr2_saved, sport->port.membase + UARTCR2);
1643}
1644
1645static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
1646{
1647 unsigned char cr2;
1648
1649 lpuart_setup_watermark(sport);
1650
1651 cr2 = readb(sport->port.membase + UARTCR2);
1652 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE;
1653 writeb(cr2, sport->port.membase + UARTCR2);
1654}
1655
1656static void lpuart32_setup_watermark(struct lpuart_port *sport)
1657{
1658 unsigned long val, ctrl;
1659 unsigned long ctrl_saved;
1660
1661 ctrl = lpuart32_read(&sport->port, UARTCTRL);
1662 ctrl_saved = ctrl;
1663 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1664 UARTCTRL_RIE | UARTCTRL_RE | UARTCTRL_ILIE);
1665 lpuart32_write(&sport->port, ctrl, UARTCTRL);
1666
1667 /* enable FIFO mode */
1668 val = lpuart32_read(&sport->port, UARTFIFO);
1669 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1670 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1671 val |= FIELD_PREP(UARTFIFO_RXIDEN, 0x3);
1672 lpuart32_write(&sport->port, val, UARTFIFO);
1673
1674 /* set the watermark */
1675 if (uart_console(&sport->port))
1676 sport->rx_watermark = 1;
1677 val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) |
1678 (0x0 << UARTWATER_TXWATER_OFF);
1679 lpuart32_write(&sport->port, val, UARTWATER);
1680
1681 /* set RTS watermark */
1682 if (!uart_console(&sport->port)) {
1683 val = lpuart32_read(&sport->port, UARTMODIR);
1684 val |= FIELD_PREP(UARTMODIR_RTSWATER, sport->rxfifo_size >> 1);
1685 lpuart32_write(&sport->port, val, UARTMODIR);
1686 }
1687
1688 /* Restore cr2 */
1689 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1690}
1691
1692static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
1693{
1694 u32 temp;
1695
1696 lpuart32_setup_watermark(sport);
1697
1698 temp = lpuart32_read(&sport->port, UARTCTRL);
1699 temp |= UARTCTRL_RE | UARTCTRL_TE;
1700 temp |= FIELD_PREP(UARTCTRL_IDLECFG, 0x7);
1701 lpuart32_write(&sport->port, temp, UARTCTRL);
1702}
1703
1704static void rx_dma_timer_init(struct lpuart_port *sport)
1705{
1706 if (sport->dma_idle_int)
1707 return;
1708
1709 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1710 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1711 add_timer(&sport->lpuart_timer);
1712}
1713
1714static void lpuart_request_dma(struct lpuart_port *sport)
1715{
1716 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");
1717 if (IS_ERR(sport->dma_tx_chan)) {
1718 dev_dbg_once(sport->port.dev,
1719 "DMA tx channel request failed, operating without tx DMA (%ld)\n",
1720 PTR_ERR(sport->dma_tx_chan));
1721 sport->dma_tx_chan = NULL;
1722 }
1723
1724 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");
1725 if (IS_ERR(sport->dma_rx_chan)) {
1726 dev_dbg_once(sport->port.dev,
1727 "DMA rx channel request failed, operating without rx DMA (%ld)\n",
1728 PTR_ERR(sport->dma_rx_chan));
1729 sport->dma_rx_chan = NULL;
1730 }
1731}
1732
1733static void lpuart_tx_dma_startup(struct lpuart_port *sport)
1734{
1735 u32 uartbaud;
1736 int ret;
1737
1738 if (uart_console(&sport->port))
1739 goto err;
1740
1741 if (!sport->dma_tx_chan)
1742 goto err;
1743
1744 ret = lpuart_dma_tx_request(&sport->port);
1745 if (ret)
1746 goto err;
1747
1748 init_waitqueue_head(&sport->dma_wait);
1749 sport->lpuart_dma_tx_use = true;
1750 if (lpuart_is_32(sport)) {
1751 uartbaud = lpuart32_read(&sport->port, UARTBAUD);
1752 lpuart32_write(&sport->port,
1753 uartbaud | UARTBAUD_TDMAE, UARTBAUD);
1754 } else {
1755 writeb(readb(sport->port.membase + UARTCR5) |
1756 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1757 }
1758
1759 return;
1760
1761err:
1762 sport->lpuart_dma_tx_use = false;
1763}
1764
1765static void lpuart_rx_dma_startup(struct lpuart_port *sport)
1766{
1767 int ret;
1768 unsigned char cr3;
1769
1770 if (uart_console(&sport->port))
1771 goto err;
1772
1773 if (!sport->dma_rx_chan)
1774 goto err;
1775
1776 /* set default Rx DMA timeout */
1777 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1778
1779 ret = lpuart_start_rx_dma(sport);
1780 if (ret)
1781 goto err;
1782
1783 if (!sport->dma_rx_timeout)
1784 sport->dma_rx_timeout = 1;
1785
1786 sport->lpuart_dma_rx_use = true;
1787 rx_dma_timer_init(sport);
1788
1789 if (sport->port.has_sysrq && !lpuart_is_32(sport)) {
1790 cr3 = readb(sport->port.membase + UARTCR3);
1791 cr3 |= UARTCR3_FEIE;
1792 writeb(cr3, sport->port.membase + UARTCR3);
1793 }
1794
1795 return;
1796
1797err:
1798 sport->lpuart_dma_rx_use = false;
1799}
1800
1801static void lpuart_hw_setup(struct lpuart_port *sport)
1802{
1803 unsigned long flags;
1804
1805 uart_port_lock_irqsave(&sport->port, &flags);
1806
1807 lpuart_setup_watermark_enable(sport);
1808
1809 lpuart_rx_dma_startup(sport);
1810 lpuart_tx_dma_startup(sport);
1811
1812 uart_port_unlock_irqrestore(&sport->port, flags);
1813}
1814
1815static int lpuart_startup(struct uart_port *port)
1816{
1817 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1818 unsigned char temp;
1819
1820 /* determine FIFO size and enable FIFO mode */
1821 temp = readb(sport->port.membase + UARTPFIFO);
1822
1823 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
1824 UARTPFIFO_FIFOSIZE_MASK);
1825 sport->port.fifosize = sport->txfifo_size;
1826
1827 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
1828 UARTPFIFO_FIFOSIZE_MASK);
1829
1830 lpuart_request_dma(sport);
1831 lpuart_hw_setup(sport);
1832
1833 return 0;
1834}
1835
1836static void lpuart32_hw_disable(struct lpuart_port *sport)
1837{
1838 unsigned long temp;
1839
1840 temp = lpuart32_read(&sport->port, UARTCTRL);
1841 temp &= ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE |
1842 UARTCTRL_TIE | UARTCTRL_TE);
1843 lpuart32_write(&sport->port, temp, UARTCTRL);
1844}
1845
1846static void lpuart32_configure(struct lpuart_port *sport)
1847{
1848 unsigned long temp;
1849
1850 temp = lpuart32_read(&sport->port, UARTCTRL);
1851 if (!sport->lpuart_dma_rx_use)
1852 temp |= UARTCTRL_RIE | UARTCTRL_ILIE;
1853 if (!sport->lpuart_dma_tx_use)
1854 temp |= UARTCTRL_TIE;
1855 lpuart32_write(&sport->port, temp, UARTCTRL);
1856}
1857
1858static void lpuart32_hw_setup(struct lpuart_port *sport)
1859{
1860 unsigned long flags;
1861
1862 uart_port_lock_irqsave(&sport->port, &flags);
1863
1864 lpuart32_hw_disable(sport);
1865
1866 lpuart_rx_dma_startup(sport);
1867 lpuart_tx_dma_startup(sport);
1868
1869 lpuart32_setup_watermark_enable(sport);
1870 lpuart32_configure(sport);
1871
1872 uart_port_unlock_irqrestore(&sport->port, flags);
1873}
1874
1875static int lpuart32_startup(struct uart_port *port)
1876{
1877 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1878 unsigned long temp;
1879
1880 /* determine FIFO size */
1881 temp = lpuart32_read(&sport->port, UARTFIFO);
1882
1883 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
1884 UARTFIFO_FIFOSIZE_MASK);
1885 sport->port.fifosize = sport->txfifo_size;
1886
1887 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
1888 UARTFIFO_FIFOSIZE_MASK);
1889
1890 /*
1891 * The LS1021A and LS1028A have a fixed FIFO depth of 16 words.
1892 * Although they support the RX/TXSIZE fields, their encoding is
1893 * different. Eg the reference manual states 0b101 is 16 words.
1894 */
1895 if (is_layerscape_lpuart(sport)) {
1896 sport->rxfifo_size = 16;
1897 sport->txfifo_size = 16;
1898 sport->port.fifosize = sport->txfifo_size;
1899 }
1900
1901 lpuart_request_dma(sport);
1902 lpuart32_hw_setup(sport);
1903
1904 return 0;
1905}
1906
1907static void lpuart_dma_shutdown(struct lpuart_port *sport)
1908{
1909 if (sport->lpuart_dma_rx_use) {
1910 lpuart_dma_rx_free(&sport->port);
1911 sport->lpuart_dma_rx_use = false;
1912 }
1913
1914 if (sport->lpuart_dma_tx_use) {
1915 if (wait_event_interruptible_timeout(sport->dma_wait,
1916 !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) {
1917 sport->dma_tx_in_progress = false;
1918 dmaengine_terminate_sync(sport->dma_tx_chan);
1919 }
1920 sport->lpuart_dma_tx_use = false;
1921 }
1922
1923 if (sport->dma_tx_chan)
1924 dma_release_channel(sport->dma_tx_chan);
1925 if (sport->dma_rx_chan)
1926 dma_release_channel(sport->dma_rx_chan);
1927}
1928
1929static void lpuart_shutdown(struct uart_port *port)
1930{
1931 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1932 unsigned char temp;
1933 unsigned long flags;
1934
1935 uart_port_lock_irqsave(port, &flags);
1936
1937 /* disable Rx/Tx and interrupts */
1938 temp = readb(port->membase + UARTCR2);
1939 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1940 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1941 writeb(temp, port->membase + UARTCR2);
1942
1943 uart_port_unlock_irqrestore(port, flags);
1944
1945 lpuart_dma_shutdown(sport);
1946}
1947
1948static void lpuart32_shutdown(struct uart_port *port)
1949{
1950 struct lpuart_port *sport =
1951 container_of(port, struct lpuart_port, port);
1952 unsigned long temp;
1953 unsigned long flags;
1954
1955 uart_port_lock_irqsave(port, &flags);
1956
1957 /* clear status */
1958 temp = lpuart32_read(&sport->port, UARTSTAT);
1959 lpuart32_write(&sport->port, temp, UARTSTAT);
1960
1961 /* disable Rx/Tx DMA */
1962 temp = lpuart32_read(port, UARTBAUD);
1963 temp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1964 lpuart32_write(port, temp, UARTBAUD);
1965
1966 /* disable Rx/Tx and interrupts and break condition */
1967 temp = lpuart32_read(port, UARTCTRL);
1968 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | UARTCTRL_ILIE |
1969 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE | UARTCTRL_SBK);
1970 lpuart32_write(port, temp, UARTCTRL);
1971
1972 uart_port_unlock_irqrestore(port, flags);
1973
1974 lpuart_dma_shutdown(sport);
1975}
1976
1977static void
1978lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1979 const struct ktermios *old)
1980{
1981 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1982 unsigned long flags;
1983 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1984 unsigned int baud;
1985 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1986 unsigned int sbr, brfa;
1987
1988 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1989 old_cr2 = readb(sport->port.membase + UARTCR2);
1990 cr3 = readb(sport->port.membase + UARTCR3);
1991 cr4 = readb(sport->port.membase + UARTCR4);
1992 bdh = readb(sport->port.membase + UARTBDH);
1993 modem = readb(sport->port.membase + UARTMODEM);
1994 /*
1995 * only support CS8 and CS7, and for CS7 must enable PE.
1996 * supported mode:
1997 * - (7,e/o,1)
1998 * - (8,n,1)
1999 * - (8,m/s,1)
2000 * - (8,e/o,1)
2001 */
2002 while ((termios->c_cflag & CSIZE) != CS8 &&
2003 (termios->c_cflag & CSIZE) != CS7) {
2004 termios->c_cflag &= ~CSIZE;
2005 termios->c_cflag |= old_csize;
2006 old_csize = CS8;
2007 }
2008
2009 if ((termios->c_cflag & CSIZE) == CS8 ||
2010 (termios->c_cflag & CSIZE) == CS7)
2011 cr1 = old_cr1 & ~UARTCR1_M;
2012
2013 if (termios->c_cflag & CMSPAR) {
2014 if ((termios->c_cflag & CSIZE) != CS8) {
2015 termios->c_cflag &= ~CSIZE;
2016 termios->c_cflag |= CS8;
2017 }
2018 cr1 |= UARTCR1_M;
2019 }
2020
2021 /*
2022 * When auto RS-485 RTS mode is enabled,
2023 * hardware flow control need to be disabled.
2024 */
2025 if (sport->port.rs485.flags & SER_RS485_ENABLED)
2026 termios->c_cflag &= ~CRTSCTS;
2027
2028 if (termios->c_cflag & CRTSCTS)
2029 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;
2030 else
2031 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
2032
2033 termios->c_cflag &= ~CSTOPB;
2034
2035 /* parity must be enabled when CS7 to match 8-bits format */
2036 if ((termios->c_cflag & CSIZE) == CS7)
2037 termios->c_cflag |= PARENB;
2038
2039 if (termios->c_cflag & PARENB) {
2040 if (termios->c_cflag & CMSPAR) {
2041 cr1 &= ~UARTCR1_PE;
2042 if (termios->c_cflag & PARODD)
2043 cr3 |= UARTCR3_T8;
2044 else
2045 cr3 &= ~UARTCR3_T8;
2046 } else {
2047 cr1 |= UARTCR1_PE;
2048 if ((termios->c_cflag & CSIZE) == CS8)
2049 cr1 |= UARTCR1_M;
2050 if (termios->c_cflag & PARODD)
2051 cr1 |= UARTCR1_PT;
2052 else
2053 cr1 &= ~UARTCR1_PT;
2054 }
2055 } else {
2056 cr1 &= ~UARTCR1_PE;
2057 }
2058
2059 /* ask the core to calculate the divisor */
2060 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
2061
2062 /*
2063 * Need to update the Ring buffer length according to the selected
2064 * baud rate and restart Rx DMA path.
2065 *
2066 * Since timer function acqures sport->port.lock, need to stop before
2067 * acquring same lock because otherwise del_timer_sync() can deadlock.
2068 */
2069 if (old && sport->lpuart_dma_rx_use)
2070 lpuart_dma_rx_free(&sport->port);
2071
2072 uart_port_lock_irqsave(&sport->port, &flags);
2073
2074 sport->port.read_status_mask = 0;
2075 if (termios->c_iflag & INPCK)
2076 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
2077 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2078 sport->port.read_status_mask |= UARTSR1_FE;
2079
2080 /* characters to ignore */
2081 sport->port.ignore_status_mask = 0;
2082 if (termios->c_iflag & IGNPAR)
2083 sport->port.ignore_status_mask |= UARTSR1_PE;
2084 if (termios->c_iflag & IGNBRK) {
2085 sport->port.ignore_status_mask |= UARTSR1_FE;
2086 /*
2087 * if we're ignoring parity and break indicators,
2088 * ignore overruns too (for real raw support).
2089 */
2090 if (termios->c_iflag & IGNPAR)
2091 sport->port.ignore_status_mask |= UARTSR1_OR;
2092 }
2093
2094 /* update the per-port timeout */
2095 uart_update_timeout(port, termios->c_cflag, baud);
2096
2097 /* wait transmit engin complete */
2098 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2099
2100 /* disable transmit and receive */
2101 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
2102 sport->port.membase + UARTCR2);
2103
2104 sbr = sport->port.uartclk / (16 * baud);
2105 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
2106 bdh &= ~UARTBDH_SBR_MASK;
2107 bdh |= (sbr >> 8) & 0x1F;
2108 cr4 &= ~UARTCR4_BRFA_MASK;
2109 brfa &= UARTCR4_BRFA_MASK;
2110 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
2111 writeb(bdh, sport->port.membase + UARTBDH);
2112 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
2113 writeb(cr3, sport->port.membase + UARTCR3);
2114 writeb(cr1, sport->port.membase + UARTCR1);
2115 writeb(modem, sport->port.membase + UARTMODEM);
2116
2117 /* restore control register */
2118 writeb(old_cr2, sport->port.membase + UARTCR2);
2119
2120 if (old && sport->lpuart_dma_rx_use) {
2121 if (!lpuart_start_rx_dma(sport))
2122 rx_dma_timer_init(sport);
2123 else
2124 sport->lpuart_dma_rx_use = false;
2125 }
2126
2127 uart_port_unlock_irqrestore(&sport->port, flags);
2128}
2129
2130static void __lpuart32_serial_setbrg(struct uart_port *port,
2131 unsigned int baudrate, bool use_rx_dma,
2132 bool use_tx_dma)
2133{
2134 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
2135 u32 clk = port->uartclk;
2136
2137 /*
2138 * The idea is to use the best OSR (over-sampling rate) possible.
2139 * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
2140 * Loop to find the best OSR value possible, one that generates minimum
2141 * baud_diff iterate through the rest of the supported values of OSR.
2142 *
2143 * Calculation Formula:
2144 * Baud Rate = baud clock / ((OSR+1) × SBR)
2145 */
2146 baud_diff = baudrate;
2147 osr = 0;
2148 sbr = 0;
2149
2150 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
2151 /* calculate the temporary sbr value */
2152 tmp_sbr = (clk / (baudrate * tmp_osr));
2153 if (tmp_sbr == 0)
2154 tmp_sbr = 1;
2155
2156 /*
2157 * calculate the baud rate difference based on the temporary
2158 * osr and sbr values
2159 */
2160 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
2161
2162 /* select best values between sbr and sbr+1 */
2163 tmp = clk / (tmp_osr * (tmp_sbr + 1));
2164 if (tmp_diff > (baudrate - tmp)) {
2165 tmp_diff = baudrate - tmp;
2166 tmp_sbr++;
2167 }
2168
2169 if (tmp_sbr > UARTBAUD_SBR_MASK)
2170 continue;
2171
2172 if (tmp_diff <= baud_diff) {
2173 baud_diff = tmp_diff;
2174 osr = tmp_osr;
2175 sbr = tmp_sbr;
2176
2177 if (!baud_diff)
2178 break;
2179 }
2180 }
2181
2182 /* handle buadrate outside acceptable rate */
2183 if (baud_diff > ((baudrate / 100) * 3))
2184 dev_warn(port->dev,
2185 "unacceptable baud rate difference of more than 3%%\n");
2186
2187 tmp = lpuart32_read(port, UARTBAUD);
2188
2189 if ((osr > 3) && (osr < 8))
2190 tmp |= UARTBAUD_BOTHEDGE;
2191
2192 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
2193 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
2194
2195 tmp &= ~UARTBAUD_SBR_MASK;
2196 tmp |= sbr & UARTBAUD_SBR_MASK;
2197
2198 if (!use_rx_dma)
2199 tmp &= ~UARTBAUD_RDMAE;
2200 if (!use_tx_dma)
2201 tmp &= ~UARTBAUD_TDMAE;
2202
2203 lpuart32_write(port, tmp, UARTBAUD);
2204}
2205
2206static void lpuart32_serial_setbrg(struct lpuart_port *sport,
2207 unsigned int baudrate)
2208{
2209 __lpuart32_serial_setbrg(&sport->port, baudrate,
2210 sport->lpuart_dma_rx_use,
2211 sport->lpuart_dma_tx_use);
2212}
2213
2214
2215static void
2216lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
2217 const struct ktermios *old)
2218{
2219 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
2220 unsigned long flags;
2221 unsigned long ctrl, old_ctrl, bd, modem;
2222 unsigned int baud;
2223 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
2224
2225 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
2226 bd = lpuart32_read(&sport->port, UARTBAUD);
2227 modem = lpuart32_read(&sport->port, UARTMODIR);
2228 sport->is_cs7 = false;
2229 /*
2230 * only support CS8 and CS7, and for CS7 must enable PE.
2231 * supported mode:
2232 * - (7,e/o,1)
2233 * - (8,n,1)
2234 * - (8,m/s,1)
2235 * - (8,e/o,1)
2236 */
2237 while ((termios->c_cflag & CSIZE) != CS8 &&
2238 (termios->c_cflag & CSIZE) != CS7) {
2239 termios->c_cflag &= ~CSIZE;
2240 termios->c_cflag |= old_csize;
2241 old_csize = CS8;
2242 }
2243
2244 if ((termios->c_cflag & CSIZE) == CS8 ||
2245 (termios->c_cflag & CSIZE) == CS7)
2246 ctrl = old_ctrl & ~UARTCTRL_M;
2247
2248 if (termios->c_cflag & CMSPAR) {
2249 if ((termios->c_cflag & CSIZE) != CS8) {
2250 termios->c_cflag &= ~CSIZE;
2251 termios->c_cflag |= CS8;
2252 }
2253 ctrl |= UARTCTRL_M;
2254 }
2255
2256 /*
2257 * When auto RS-485 RTS mode is enabled,
2258 * hardware flow control need to be disabled.
2259 */
2260 if (sport->port.rs485.flags & SER_RS485_ENABLED)
2261 termios->c_cflag &= ~CRTSCTS;
2262
2263 if (termios->c_cflag & CRTSCTS)
2264 modem |= UARTMODIR_RXRTSE | UARTMODIR_TXCTSE;
2265 else
2266 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2267
2268 if (termios->c_cflag & CSTOPB)
2269 bd |= UARTBAUD_SBNS;
2270 else
2271 bd &= ~UARTBAUD_SBNS;
2272
2273 /* parity must be enabled when CS7 to match 8-bits format */
2274 if ((termios->c_cflag & CSIZE) == CS7)
2275 termios->c_cflag |= PARENB;
2276
2277 if ((termios->c_cflag & PARENB)) {
2278 if (termios->c_cflag & CMSPAR) {
2279 ctrl &= ~UARTCTRL_PE;
2280 ctrl |= UARTCTRL_M;
2281 } else {
2282 ctrl |= UARTCTRL_PE;
2283 if ((termios->c_cflag & CSIZE) == CS8)
2284 ctrl |= UARTCTRL_M;
2285 if (termios->c_cflag & PARODD)
2286 ctrl |= UARTCTRL_PT;
2287 else
2288 ctrl &= ~UARTCTRL_PT;
2289 }
2290 } else {
2291 ctrl &= ~UARTCTRL_PE;
2292 }
2293
2294 /* ask the core to calculate the divisor */
2295 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
2296
2297 /*
2298 * Need to update the Ring buffer length according to the selected
2299 * baud rate and restart Rx DMA path.
2300 *
2301 * Since timer function acqures sport->port.lock, need to stop before
2302 * acquring same lock because otherwise del_timer_sync() can deadlock.
2303 */
2304 if (old && sport->lpuart_dma_rx_use)
2305 lpuart_dma_rx_free(&sport->port);
2306
2307 uart_port_lock_irqsave(&sport->port, &flags);
2308
2309 sport->port.read_status_mask = 0;
2310 if (termios->c_iflag & INPCK)
2311 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
2312 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2313 sport->port.read_status_mask |= UARTSTAT_FE;
2314
2315 /* characters to ignore */
2316 sport->port.ignore_status_mask = 0;
2317 if (termios->c_iflag & IGNPAR)
2318 sport->port.ignore_status_mask |= UARTSTAT_PE;
2319 if (termios->c_iflag & IGNBRK) {
2320 sport->port.ignore_status_mask |= UARTSTAT_FE;
2321 /*
2322 * if we're ignoring parity and break indicators,
2323 * ignore overruns too (for real raw support).
2324 */
2325 if (termios->c_iflag & IGNPAR)
2326 sport->port.ignore_status_mask |= UARTSTAT_OR;
2327 }
2328
2329 /* update the per-port timeout */
2330 uart_update_timeout(port, termios->c_cflag, baud);
2331
2332 /*
2333 * LPUART Transmission Complete Flag may never be set while queuing a break
2334 * character, so skip waiting for transmission complete when UARTCTRL_SBK is
2335 * asserted.
2336 */
2337 if (!(old_ctrl & UARTCTRL_SBK)) {
2338 lpuart32_write(&sport->port, 0, UARTMODIR);
2339 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2340 }
2341
2342 /* disable transmit and receive */
2343 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
2344 UARTCTRL);
2345
2346 lpuart32_write(&sport->port, bd, UARTBAUD);
2347 lpuart32_serial_setbrg(sport, baud);
2348 /* disable CTS before enabling UARTCTRL_TE to avoid pending idle preamble */
2349 lpuart32_write(&sport->port, modem & ~UARTMODIR_TXCTSE, UARTMODIR);
2350 /* restore control register */
2351 lpuart32_write(&sport->port, ctrl, UARTCTRL);
2352 /* re-enable the CTS if needed */
2353 lpuart32_write(&sport->port, modem, UARTMODIR);
2354
2355 if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE)
2356 sport->is_cs7 = true;
2357
2358 if (old && sport->lpuart_dma_rx_use) {
2359 if (!lpuart_start_rx_dma(sport))
2360 rx_dma_timer_init(sport);
2361 else
2362 sport->lpuart_dma_rx_use = false;
2363 }
2364
2365 uart_port_unlock_irqrestore(&sport->port, flags);
2366}
2367
2368static const char *lpuart_type(struct uart_port *port)
2369{
2370 return "FSL_LPUART";
2371}
2372
2373static void lpuart_release_port(struct uart_port *port)
2374{
2375 /* nothing to do */
2376}
2377
2378static int lpuart_request_port(struct uart_port *port)
2379{
2380 return 0;
2381}
2382
2383/* configure/autoconfigure the port */
2384static void lpuart_config_port(struct uart_port *port, int flags)
2385{
2386 if (flags & UART_CONFIG_TYPE)
2387 port->type = PORT_LPUART;
2388}
2389
2390static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
2391{
2392 int ret = 0;
2393
2394 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
2395 ret = -EINVAL;
2396 if (port->irq != ser->irq)
2397 ret = -EINVAL;
2398 if (ser->io_type != UPIO_MEM)
2399 ret = -EINVAL;
2400 if (port->uartclk / 16 != ser->baud_base)
2401 ret = -EINVAL;
2402 if (port->iobase != ser->port)
2403 ret = -EINVAL;
2404 if (ser->hub6 != 0)
2405 ret = -EINVAL;
2406 return ret;
2407}
2408
2409static const struct uart_ops lpuart_pops = {
2410 .tx_empty = lpuart_tx_empty,
2411 .set_mctrl = lpuart_set_mctrl,
2412 .get_mctrl = lpuart_get_mctrl,
2413 .stop_tx = lpuart_stop_tx,
2414 .start_tx = lpuart_start_tx,
2415 .stop_rx = lpuart_stop_rx,
2416 .break_ctl = lpuart_break_ctl,
2417 .startup = lpuart_startup,
2418 .shutdown = lpuart_shutdown,
2419 .set_termios = lpuart_set_termios,
2420 .pm = lpuart_uart_pm,
2421 .type = lpuart_type,
2422 .request_port = lpuart_request_port,
2423 .release_port = lpuart_release_port,
2424 .config_port = lpuart_config_port,
2425 .verify_port = lpuart_verify_port,
2426 .flush_buffer = lpuart_flush_buffer,
2427#if defined(CONFIG_CONSOLE_POLL)
2428 .poll_init = lpuart_poll_init,
2429 .poll_get_char = lpuart_poll_get_char,
2430 .poll_put_char = lpuart_poll_put_char,
2431#endif
2432};
2433
2434static const struct uart_ops lpuart32_pops = {
2435 .tx_empty = lpuart32_tx_empty,
2436 .set_mctrl = lpuart32_set_mctrl,
2437 .get_mctrl = lpuart32_get_mctrl,
2438 .stop_tx = lpuart32_stop_tx,
2439 .start_tx = lpuart32_start_tx,
2440 .stop_rx = lpuart32_stop_rx,
2441 .break_ctl = lpuart32_break_ctl,
2442 .startup = lpuart32_startup,
2443 .shutdown = lpuart32_shutdown,
2444 .set_termios = lpuart32_set_termios,
2445 .pm = lpuart_uart_pm,
2446 .type = lpuart_type,
2447 .request_port = lpuart_request_port,
2448 .release_port = lpuart_release_port,
2449 .config_port = lpuart_config_port,
2450 .verify_port = lpuart_verify_port,
2451 .flush_buffer = lpuart_flush_buffer,
2452#if defined(CONFIG_CONSOLE_POLL)
2453 .poll_init = lpuart32_poll_init,
2454 .poll_get_char = lpuart32_poll_get_char,
2455 .poll_put_char = lpuart32_poll_put_char,
2456#endif
2457};
2458
2459static struct lpuart_port *lpuart_ports[UART_NR];
2460
2461#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
2462static void lpuart_console_putchar(struct uart_port *port, unsigned char ch)
2463{
2464 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
2465 writeb(ch, port->membase + UARTDR);
2466}
2467
2468static void lpuart32_console_putchar(struct uart_port *port, unsigned char ch)
2469{
2470 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
2471 lpuart32_write(port, ch, UARTDATA);
2472}
2473
2474static void
2475lpuart_console_write(struct console *co, const char *s, unsigned int count)
2476{
2477 struct lpuart_port *sport = lpuart_ports[co->index];
2478 unsigned char old_cr2, cr2;
2479 unsigned long flags;
2480 int locked = 1;
2481
2482 if (oops_in_progress)
2483 locked = uart_port_trylock_irqsave(&sport->port, &flags);
2484 else
2485 uart_port_lock_irqsave(&sport->port, &flags);
2486
2487 /* first save CR2 and then disable interrupts */
2488 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2489 cr2 |= UARTCR2_TE | UARTCR2_RE;
2490 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
2491 writeb(cr2, sport->port.membase + UARTCR2);
2492
2493 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
2494
2495 /* wait for transmitter finish complete and restore CR2 */
2496 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2497
2498 writeb(old_cr2, sport->port.membase + UARTCR2);
2499
2500 if (locked)
2501 uart_port_unlock_irqrestore(&sport->port, flags);
2502}
2503
2504static void
2505lpuart32_console_write(struct console *co, const char *s, unsigned int count)
2506{
2507 struct lpuart_port *sport = lpuart_ports[co->index];
2508 unsigned long old_cr, cr;
2509 unsigned long flags;
2510 int locked = 1;
2511
2512 if (oops_in_progress)
2513 locked = uart_port_trylock_irqsave(&sport->port, &flags);
2514 else
2515 uart_port_lock_irqsave(&sport->port, &flags);
2516
2517 /* first save CR2 and then disable interrupts */
2518 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2519 cr |= UARTCTRL_TE | UARTCTRL_RE;
2520 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
2521 lpuart32_write(&sport->port, cr, UARTCTRL);
2522
2523 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2524
2525 /* wait for transmitter finish complete and restore CR2 */
2526 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2527
2528 lpuart32_write(&sport->port, old_cr, UARTCTRL);
2529
2530 if (locked)
2531 uart_port_unlock_irqrestore(&sport->port, flags);
2532}
2533
2534/*
2535 * if the port was already initialised (eg, by a boot loader),
2536 * try to determine the current setup.
2537 */
2538static void __init
2539lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2540 int *parity, int *bits)
2541{
2542 unsigned char cr, bdh, bdl, brfa;
2543 unsigned int sbr, uartclk, baud_raw;
2544
2545 cr = readb(sport->port.membase + UARTCR2);
2546 cr &= UARTCR2_TE | UARTCR2_RE;
2547 if (!cr)
2548 return;
2549
2550 /* ok, the port was enabled */
2551
2552 cr = readb(sport->port.membase + UARTCR1);
2553
2554 *parity = 'n';
2555 if (cr & UARTCR1_PE) {
2556 if (cr & UARTCR1_PT)
2557 *parity = 'o';
2558 else
2559 *parity = 'e';
2560 }
2561
2562 if (cr & UARTCR1_M)
2563 *bits = 9;
2564 else
2565 *bits = 8;
2566
2567 bdh = readb(sport->port.membase + UARTBDH);
2568 bdh &= UARTBDH_SBR_MASK;
2569 bdl = readb(sport->port.membase + UARTBDL);
2570 sbr = bdh;
2571 sbr <<= 8;
2572 sbr |= bdl;
2573 brfa = readb(sport->port.membase + UARTCR4);
2574 brfa &= UARTCR4_BRFA_MASK;
2575
2576 uartclk = lpuart_get_baud_clk_rate(sport);
2577 /*
2578 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2579 */
2580 baud_raw = uartclk / (16 * (sbr + brfa / 32));
2581
2582 if (*baud != baud_raw)
2583 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2584 "from %d to %d\n", baud_raw, *baud);
2585}
2586
2587static void __init
2588lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2589 int *parity, int *bits)
2590{
2591 unsigned long cr, bd;
2592 unsigned int sbr, uartclk, baud_raw;
2593
2594 cr = lpuart32_read(&sport->port, UARTCTRL);
2595 cr &= UARTCTRL_TE | UARTCTRL_RE;
2596 if (!cr)
2597 return;
2598
2599 /* ok, the port was enabled */
2600
2601 cr = lpuart32_read(&sport->port, UARTCTRL);
2602
2603 *parity = 'n';
2604 if (cr & UARTCTRL_PE) {
2605 if (cr & UARTCTRL_PT)
2606 *parity = 'o';
2607 else
2608 *parity = 'e';
2609 }
2610
2611 if (cr & UARTCTRL_M)
2612 *bits = 9;
2613 else
2614 *bits = 8;
2615
2616 bd = lpuart32_read(&sport->port, UARTBAUD);
2617 bd &= UARTBAUD_SBR_MASK;
2618 if (!bd)
2619 return;
2620
2621 sbr = bd;
2622 uartclk = lpuart_get_baud_clk_rate(sport);
2623 /*
2624 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2625 */
2626 baud_raw = uartclk / (16 * sbr);
2627
2628 if (*baud != baud_raw)
2629 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2630 "from %d to %d\n", baud_raw, *baud);
2631}
2632
2633static int __init lpuart_console_setup(struct console *co, char *options)
2634{
2635 struct lpuart_port *sport;
2636 int baud = 115200;
2637 int bits = 8;
2638 int parity = 'n';
2639 int flow = 'n';
2640
2641 /*
2642 * check whether an invalid uart number has been specified, and
2643 * if so, search for the first available port that does have
2644 * console support.
2645 */
2646 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2647 co->index = 0;
2648
2649 sport = lpuart_ports[co->index];
2650 if (sport == NULL)
2651 return -ENODEV;
2652
2653 if (options)
2654 uart_parse_options(options, &baud, &parity, &bits, &flow);
2655 else
2656 if (lpuart_is_32(sport))
2657 lpuart32_console_get_options(sport, &baud, &parity, &bits);
2658 else
2659 lpuart_console_get_options(sport, &baud, &parity, &bits);
2660
2661 if (lpuart_is_32(sport))
2662 lpuart32_setup_watermark(sport);
2663 else
2664 lpuart_setup_watermark(sport);
2665
2666 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2667}
2668
2669static struct uart_driver lpuart_reg;
2670static struct console lpuart_console = {
2671 .name = DEV_NAME,
2672 .write = lpuart_console_write,
2673 .device = uart_console_device,
2674 .setup = lpuart_console_setup,
2675 .flags = CON_PRINTBUFFER,
2676 .index = -1,
2677 .data = &lpuart_reg,
2678};
2679
2680static struct console lpuart32_console = {
2681 .name = DEV_NAME,
2682 .write = lpuart32_console_write,
2683 .device = uart_console_device,
2684 .setup = lpuart_console_setup,
2685 .flags = CON_PRINTBUFFER,
2686 .index = -1,
2687 .data = &lpuart_reg,
2688};
2689
2690static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2691{
2692 struct earlycon_device *dev = con->data;
2693
2694 uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2695}
2696
2697static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2698{
2699 struct earlycon_device *dev = con->data;
2700
2701 uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2702}
2703
2704static int __init lpuart_early_console_setup(struct earlycon_device *device,
2705 const char *opt)
2706{
2707 if (!device->port.membase)
2708 return -ENODEV;
2709
2710 device->con->write = lpuart_early_write;
2711 return 0;
2712}
2713
2714static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2715 const char *opt)
2716{
2717 if (!device->port.membase)
2718 return -ENODEV;
2719
2720 if (device->port.iotype != UPIO_MEM32)
2721 device->port.iotype = UPIO_MEM32BE;
2722
2723 device->con->write = lpuart32_early_write;
2724 return 0;
2725}
2726
2727static int __init ls1028a_early_console_setup(struct earlycon_device *device,
2728 const char *opt)
2729{
2730 u32 cr;
2731
2732 if (!device->port.membase)
2733 return -ENODEV;
2734
2735 device->port.iotype = UPIO_MEM32;
2736 device->con->write = lpuart32_early_write;
2737
2738 /* set the baudrate */
2739 if (device->port.uartclk && device->baud)
2740 __lpuart32_serial_setbrg(&device->port, device->baud,
2741 false, false);
2742
2743 /* enable transmitter */
2744 cr = lpuart32_read(&device->port, UARTCTRL);
2745 cr |= UARTCTRL_TE;
2746 lpuart32_write(&device->port, cr, UARTCTRL);
2747
2748 return 0;
2749}
2750
2751static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2752 const char *opt)
2753{
2754 if (!device->port.membase)
2755 return -ENODEV;
2756
2757 device->port.iotype = UPIO_MEM32;
2758 device->port.membase += IMX_REG_OFF;
2759 device->con->write = lpuart32_early_write;
2760
2761 return 0;
2762}
2763OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2764OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2765OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2766OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2767OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup);
2768OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
2769OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup);
2770EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2771EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2772
2773#define LPUART_CONSOLE (&lpuart_console)
2774#define LPUART32_CONSOLE (&lpuart32_console)
2775#else
2776#define LPUART_CONSOLE NULL
2777#define LPUART32_CONSOLE NULL
2778#endif
2779
2780static struct uart_driver lpuart_reg = {
2781 .owner = THIS_MODULE,
2782 .driver_name = DRIVER_NAME,
2783 .dev_name = DEV_NAME,
2784 .nr = ARRAY_SIZE(lpuart_ports),
2785 .cons = LPUART_CONSOLE,
2786};
2787
2788static const struct serial_rs485 lpuart_rs485_supported = {
2789 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
2790 /* delay_rts_* and RX_DURING_TX are not supported */
2791};
2792
2793static int lpuart_global_reset(struct lpuart_port *sport)
2794{
2795 struct uart_port *port = &sport->port;
2796 void __iomem *global_addr;
2797 unsigned long ctrl, bd;
2798 unsigned int val = 0;
2799 int ret;
2800
2801 ret = clk_prepare_enable(sport->ipg_clk);
2802 if (ret) {
2803 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);
2804 return ret;
2805 }
2806
2807 if (is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
2808 /*
2809 * If the transmitter is used by earlycon, wait for transmit engine to
2810 * complete and then reset.
2811 */
2812 ctrl = lpuart32_read(port, UARTCTRL);
2813 if (ctrl & UARTCTRL_TE) {
2814 bd = lpuart32_read(&sport->port, UARTBAUD);
2815 if (read_poll_timeout(lpuart32_tx_empty, val, val, 1, 100000, false,
2816 port)) {
2817 dev_warn(sport->port.dev,
2818 "timeout waiting for transmit engine to complete\n");
2819 clk_disable_unprepare(sport->ipg_clk);
2820 return 0;
2821 }
2822 }
2823
2824 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
2825 writel(UART_GLOBAL_RST, global_addr);
2826 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
2827 writel(0, global_addr);
2828 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
2829
2830 /* Recover the transmitter for earlycon. */
2831 if (ctrl & UARTCTRL_TE) {
2832 lpuart32_write(port, bd, UARTBAUD);
2833 lpuart32_write(port, ctrl, UARTCTRL);
2834 }
2835 }
2836
2837 clk_disable_unprepare(sport->ipg_clk);
2838 return 0;
2839}
2840
2841static int lpuart_probe(struct platform_device *pdev)
2842{
2843 const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev);
2844 struct device_node *np = pdev->dev.of_node;
2845 struct lpuart_port *sport;
2846 struct resource *res;
2847 irq_handler_t handler;
2848 int ret;
2849
2850 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2851 if (!sport)
2852 return -ENOMEM;
2853
2854 sport->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2855 if (IS_ERR(sport->port.membase))
2856 return PTR_ERR(sport->port.membase);
2857
2858 sport->port.membase += sdata->reg_off;
2859 sport->port.mapbase = res->start + sdata->reg_off;
2860 sport->port.dev = &pdev->dev;
2861 sport->port.type = PORT_LPUART;
2862 sport->devtype = sdata->devtype;
2863 sport->rx_watermark = sdata->rx_watermark;
2864 sport->dma_idle_int = is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) ||
2865 is_imx8qxp_lpuart(sport);
2866 ret = platform_get_irq(pdev, 0);
2867 if (ret < 0)
2868 return ret;
2869 sport->port.irq = ret;
2870 sport->port.iotype = sdata->iotype;
2871 if (lpuart_is_32(sport))
2872 sport->port.ops = &lpuart32_pops;
2873 else
2874 sport->port.ops = &lpuart_pops;
2875 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
2876 sport->port.flags = UPF_BOOT_AUTOCONF;
2877
2878 if (lpuart_is_32(sport))
2879 sport->port.rs485_config = lpuart32_config_rs485;
2880 else
2881 sport->port.rs485_config = lpuart_config_rs485;
2882 sport->port.rs485_supported = lpuart_rs485_supported;
2883
2884 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2885 if (IS_ERR(sport->ipg_clk)) {
2886 ret = PTR_ERR(sport->ipg_clk);
2887 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
2888 return ret;
2889 }
2890
2891 sport->baud_clk = NULL;
2892 if (is_imx8qxp_lpuart(sport)) {
2893 sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
2894 if (IS_ERR(sport->baud_clk)) {
2895 ret = PTR_ERR(sport->baud_clk);
2896 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
2897 return ret;
2898 }
2899 }
2900
2901 ret = of_alias_get_id(np, "serial");
2902 if (ret < 0) {
2903 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2904 return ret;
2905 }
2906 if (ret >= ARRAY_SIZE(lpuart_ports)) {
2907 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2908 return -EINVAL;
2909 }
2910 sport->port.line = ret;
2911
2912 ret = lpuart_enable_clks(sport);
2913 if (ret)
2914 return ret;
2915 sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2916
2917 lpuart_ports[sport->port.line] = sport;
2918
2919 platform_set_drvdata(pdev, &sport->port);
2920
2921 if (lpuart_is_32(sport)) {
2922 lpuart_reg.cons = LPUART32_CONSOLE;
2923 handler = lpuart32_int;
2924 } else {
2925 lpuart_reg.cons = LPUART_CONSOLE;
2926 handler = lpuart_int;
2927 }
2928
2929 pm_runtime_use_autosuspend(&pdev->dev);
2930 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
2931 pm_runtime_set_active(&pdev->dev);
2932 pm_runtime_enable(&pdev->dev);
2933
2934 ret = lpuart_global_reset(sport);
2935 if (ret)
2936 goto failed_reset;
2937
2938 ret = uart_get_rs485_mode(&sport->port);
2939 if (ret)
2940 goto failed_get_rs485;
2941
2942 ret = uart_add_one_port(&lpuart_reg, &sport->port);
2943 if (ret)
2944 goto failed_attach_port;
2945
2946 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0,
2947 DRIVER_NAME, sport);
2948 if (ret)
2949 goto failed_irq_request;
2950
2951 return 0;
2952
2953failed_irq_request:
2954 uart_remove_one_port(&lpuart_reg, &sport->port);
2955failed_attach_port:
2956failed_get_rs485:
2957failed_reset:
2958 pm_runtime_disable(&pdev->dev);
2959 pm_runtime_set_suspended(&pdev->dev);
2960 pm_runtime_dont_use_autosuspend(&pdev->dev);
2961 lpuart_disable_clks(sport);
2962 return ret;
2963}
2964
2965static void lpuart_remove(struct platform_device *pdev)
2966{
2967 struct lpuart_port *sport = platform_get_drvdata(pdev);
2968
2969 uart_remove_one_port(&lpuart_reg, &sport->port);
2970
2971 lpuart_disable_clks(sport);
2972
2973 if (sport->dma_tx_chan)
2974 dma_release_channel(sport->dma_tx_chan);
2975
2976 if (sport->dma_rx_chan)
2977 dma_release_channel(sport->dma_rx_chan);
2978
2979 pm_runtime_disable(&pdev->dev);
2980 pm_runtime_set_suspended(&pdev->dev);
2981 pm_runtime_dont_use_autosuspend(&pdev->dev);
2982}
2983
2984static int lpuart_runtime_suspend(struct device *dev)
2985{
2986 struct platform_device *pdev = to_platform_device(dev);
2987 struct lpuart_port *sport = platform_get_drvdata(pdev);
2988
2989 lpuart_disable_clks(sport);
2990
2991 return 0;
2992};
2993
2994static int lpuart_runtime_resume(struct device *dev)
2995{
2996 struct platform_device *pdev = to_platform_device(dev);
2997 struct lpuart_port *sport = platform_get_drvdata(pdev);
2998
2999 return lpuart_enable_clks(sport);
3000};
3001
3002static void serial_lpuart_enable_wakeup(struct lpuart_port *sport, bool on)
3003{
3004 unsigned int val, baud;
3005
3006 if (lpuart_is_32(sport)) {
3007 val = lpuart32_read(&sport->port, UARTCTRL);
3008 baud = lpuart32_read(&sport->port, UARTBAUD);
3009 if (on) {
3010 /* set rx_watermark to 0 in wakeup source mode */
3011 lpuart32_write(&sport->port, 0, UARTWATER);
3012 val |= UARTCTRL_RIE;
3013 /* clear RXEDGIF flag before enable RXEDGIE interrupt */
3014 lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT);
3015 baud |= UARTBAUD_RXEDGIE;
3016 } else {
3017 val &= ~UARTCTRL_RIE;
3018 baud &= ~UARTBAUD_RXEDGIE;
3019 }
3020 lpuart32_write(&sport->port, val, UARTCTRL);
3021 lpuart32_write(&sport->port, baud, UARTBAUD);
3022 } else {
3023 val = readb(sport->port.membase + UARTCR2);
3024 if (on)
3025 val |= UARTCR2_RIE;
3026 else
3027 val &= ~UARTCR2_RIE;
3028 writeb(val, sport->port.membase + UARTCR2);
3029 }
3030}
3031
3032static bool lpuart_uport_is_active(struct lpuart_port *sport)
3033{
3034 struct tty_port *port = &sport->port.state->port;
3035 struct tty_struct *tty;
3036 struct device *tty_dev;
3037 int may_wake = 0;
3038
3039 tty = tty_port_tty_get(port);
3040 if (tty) {
3041 tty_dev = tty->dev;
3042 may_wake = tty_dev && device_may_wakeup(tty_dev);
3043 tty_kref_put(tty);
3044 }
3045
3046 if ((tty_port_initialized(port) && may_wake) ||
3047 (!console_suspend_enabled && uart_console(&sport->port)))
3048 return true;
3049
3050 return false;
3051}
3052
3053static int lpuart_suspend_noirq(struct device *dev)
3054{
3055 struct lpuart_port *sport = dev_get_drvdata(dev);
3056 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
3057
3058 if (lpuart_uport_is_active(sport))
3059 serial_lpuart_enable_wakeup(sport, !!irq_wake);
3060
3061 pinctrl_pm_select_sleep_state(dev);
3062
3063 return 0;
3064}
3065
3066static int lpuart_resume_noirq(struct device *dev)
3067{
3068 struct lpuart_port *sport = dev_get_drvdata(dev);
3069 unsigned int val;
3070
3071 pinctrl_pm_select_default_state(dev);
3072
3073 if (lpuart_uport_is_active(sport)) {
3074 serial_lpuart_enable_wakeup(sport, false);
3075
3076 /* clear the wakeup flags */
3077 if (lpuart_is_32(sport)) {
3078 val = lpuart32_read(&sport->port, UARTSTAT);
3079 lpuart32_write(&sport->port, val, UARTSTAT);
3080 }
3081 }
3082
3083 return 0;
3084}
3085
3086static int lpuart_suspend(struct device *dev)
3087{
3088 struct lpuart_port *sport = dev_get_drvdata(dev);
3089 unsigned long temp, flags;
3090
3091 uart_suspend_port(&lpuart_reg, &sport->port);
3092
3093 if (lpuart_uport_is_active(sport)) {
3094 uart_port_lock_irqsave(&sport->port, &flags);
3095 if (lpuart_is_32(sport)) {
3096 /* disable Rx/Tx and interrupts */
3097 temp = lpuart32_read(&sport->port, UARTCTRL);
3098 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
3099 lpuart32_write(&sport->port, temp, UARTCTRL);
3100 } else {
3101 /* disable Rx/Tx and interrupts */
3102 temp = readb(sport->port.membase + UARTCR2);
3103 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
3104 writeb(temp, sport->port.membase + UARTCR2);
3105 }
3106 uart_port_unlock_irqrestore(&sport->port, flags);
3107
3108 if (sport->lpuart_dma_rx_use) {
3109 /*
3110 * EDMA driver during suspend will forcefully release any
3111 * non-idle DMA channels. If port wakeup is enabled or if port
3112 * is console port or 'no_console_suspend' is set the Rx DMA
3113 * cannot resume as expected, hence gracefully release the
3114 * Rx DMA path before suspend and start Rx DMA path on resume.
3115 */
3116 lpuart_dma_rx_free(&sport->port);
3117
3118 /* Disable Rx DMA to use UART port as wakeup source */
3119 uart_port_lock_irqsave(&sport->port, &flags);
3120 if (lpuart_is_32(sport)) {
3121 temp = lpuart32_read(&sport->port, UARTBAUD);
3122 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
3123 UARTBAUD);
3124 } else {
3125 writeb(readb(sport->port.membase + UARTCR5) &
3126 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
3127 }
3128 uart_port_unlock_irqrestore(&sport->port, flags);
3129 }
3130
3131 if (sport->lpuart_dma_tx_use) {
3132 uart_port_lock_irqsave(&sport->port, &flags);
3133 if (lpuart_is_32(sport)) {
3134 temp = lpuart32_read(&sport->port, UARTBAUD);
3135 temp &= ~UARTBAUD_TDMAE;
3136 lpuart32_write(&sport->port, temp, UARTBAUD);
3137 } else {
3138 temp = readb(sport->port.membase + UARTCR5);
3139 temp &= ~UARTCR5_TDMAS;
3140 writeb(temp, sport->port.membase + UARTCR5);
3141 }
3142 uart_port_unlock_irqrestore(&sport->port, flags);
3143 sport->dma_tx_in_progress = false;
3144 dmaengine_terminate_sync(sport->dma_tx_chan);
3145 }
3146 } else if (pm_runtime_active(sport->port.dev)) {
3147 lpuart_disable_clks(sport);
3148 pm_runtime_disable(sport->port.dev);
3149 pm_runtime_set_suspended(sport->port.dev);
3150 }
3151
3152 return 0;
3153}
3154
3155static void lpuart_console_fixup(struct lpuart_port *sport)
3156{
3157 struct tty_port *port = &sport->port.state->port;
3158 struct uart_port *uport = &sport->port;
3159 struct ktermios termios;
3160
3161 /* i.MX7ULP enter VLLS mode that lpuart module power off and registers
3162 * all lost no matter the port is wakeup source.
3163 * For console port, console baud rate setting lost and print messy
3164 * log when enable the console port as wakeup source. To avoid the
3165 * issue happen, user should not enable uart port as wakeup source
3166 * in VLLS mode, or restore console setting here.
3167 */
3168 if (is_imx7ulp_lpuart(sport) && lpuart_uport_is_active(sport) &&
3169 console_suspend_enabled && uart_console(&sport->port)) {
3170
3171 mutex_lock(&port->mutex);
3172 memset(&termios, 0, sizeof(struct ktermios));
3173 termios.c_cflag = uport->cons->cflag;
3174 if (port->tty && termios.c_cflag == 0)
3175 termios = port->tty->termios;
3176 uport->ops->set_termios(uport, &termios, NULL);
3177 mutex_unlock(&port->mutex);
3178 }
3179}
3180
3181static int lpuart_resume(struct device *dev)
3182{
3183 struct lpuart_port *sport = dev_get_drvdata(dev);
3184 int ret;
3185
3186 if (lpuart_uport_is_active(sport)) {
3187 if (lpuart_is_32(sport))
3188 lpuart32_hw_setup(sport);
3189 else
3190 lpuart_hw_setup(sport);
3191 } else if (pm_runtime_active(sport->port.dev)) {
3192 ret = lpuart_enable_clks(sport);
3193 if (ret)
3194 return ret;
3195 pm_runtime_set_active(sport->port.dev);
3196 pm_runtime_enable(sport->port.dev);
3197 }
3198
3199 lpuart_console_fixup(sport);
3200 uart_resume_port(&lpuart_reg, &sport->port);
3201
3202 return 0;
3203}
3204
3205static const struct dev_pm_ops lpuart_pm_ops = {
3206 RUNTIME_PM_OPS(lpuart_runtime_suspend,
3207 lpuart_runtime_resume, NULL)
3208 NOIRQ_SYSTEM_SLEEP_PM_OPS(lpuart_suspend_noirq,
3209 lpuart_resume_noirq)
3210 SYSTEM_SLEEP_PM_OPS(lpuart_suspend, lpuart_resume)
3211};
3212
3213static struct platform_driver lpuart_driver = {
3214 .probe = lpuart_probe,
3215 .remove_new = lpuart_remove,
3216 .driver = {
3217 .name = "fsl-lpuart",
3218 .of_match_table = lpuart_dt_ids,
3219 .pm = pm_ptr(&lpuart_pm_ops),
3220 },
3221};
3222
3223static int __init lpuart_serial_init(void)
3224{
3225 int ret = uart_register_driver(&lpuart_reg);
3226
3227 if (ret)
3228 return ret;
3229
3230 ret = platform_driver_register(&lpuart_driver);
3231 if (ret)
3232 uart_unregister_driver(&lpuart_reg);
3233
3234 return ret;
3235}
3236
3237static void __exit lpuart_serial_exit(void)
3238{
3239 platform_driver_unregister(&lpuart_driver);
3240 uart_unregister_driver(&lpuart_reg);
3241}
3242
3243module_init(lpuart_serial_init);
3244module_exit(lpuart_serial_exit);
3245
3246MODULE_DESCRIPTION("Freescale lpuart serial port driver");
3247MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Freescale lpuart serial port driver
4 *
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
6 */
7
8#include <linux/clk.h>
9#include <linux/console.h>
10#include <linux/delay.h>
11#include <linux/dma-mapping.h>
12#include <linux/dmaengine.h>
13#include <linux/dmapool.h>
14#include <linux/io.h>
15#include <linux/iopoll.h>
16#include <linux/irq.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/of_dma.h>
21#include <linux/pinctrl/consumer.h>
22#include <linux/pm_runtime.h>
23#include <linux/serial_core.h>
24#include <linux/slab.h>
25#include <linux/tty_flip.h>
26
27/* All registers are 8-bit width */
28#define UARTBDH 0x00
29#define UARTBDL 0x01
30#define UARTCR1 0x02
31#define UARTCR2 0x03
32#define UARTSR1 0x04
33#define UARTCR3 0x06
34#define UARTDR 0x07
35#define UARTCR4 0x0a
36#define UARTCR5 0x0b
37#define UARTMODEM 0x0d
38#define UARTPFIFO 0x10
39#define UARTCFIFO 0x11
40#define UARTSFIFO 0x12
41#define UARTTWFIFO 0x13
42#define UARTTCFIFO 0x14
43#define UARTRWFIFO 0x15
44
45#define UARTBDH_LBKDIE 0x80
46#define UARTBDH_RXEDGIE 0x40
47#define UARTBDH_SBR_MASK 0x1f
48
49#define UARTCR1_LOOPS 0x80
50#define UARTCR1_RSRC 0x20
51#define UARTCR1_M 0x10
52#define UARTCR1_WAKE 0x08
53#define UARTCR1_ILT 0x04
54#define UARTCR1_PE 0x02
55#define UARTCR1_PT 0x01
56
57#define UARTCR2_TIE 0x80
58#define UARTCR2_TCIE 0x40
59#define UARTCR2_RIE 0x20
60#define UARTCR2_ILIE 0x10
61#define UARTCR2_TE 0x08
62#define UARTCR2_RE 0x04
63#define UARTCR2_RWU 0x02
64#define UARTCR2_SBK 0x01
65
66#define UARTSR1_TDRE 0x80
67#define UARTSR1_TC 0x40
68#define UARTSR1_RDRF 0x20
69#define UARTSR1_IDLE 0x10
70#define UARTSR1_OR 0x08
71#define UARTSR1_NF 0x04
72#define UARTSR1_FE 0x02
73#define UARTSR1_PE 0x01
74
75#define UARTCR3_R8 0x80
76#define UARTCR3_T8 0x40
77#define UARTCR3_TXDIR 0x20
78#define UARTCR3_TXINV 0x10
79#define UARTCR3_ORIE 0x08
80#define UARTCR3_NEIE 0x04
81#define UARTCR3_FEIE 0x02
82#define UARTCR3_PEIE 0x01
83
84#define UARTCR4_MAEN1 0x80
85#define UARTCR4_MAEN2 0x40
86#define UARTCR4_M10 0x20
87#define UARTCR4_BRFA_MASK 0x1f
88#define UARTCR4_BRFA_OFF 0
89
90#define UARTCR5_TDMAS 0x80
91#define UARTCR5_RDMAS 0x20
92
93#define UARTMODEM_RXRTSE 0x08
94#define UARTMODEM_TXRTSPOL 0x04
95#define UARTMODEM_TXRTSE 0x02
96#define UARTMODEM_TXCTSE 0x01
97
98#define UARTPFIFO_TXFE 0x80
99#define UARTPFIFO_FIFOSIZE_MASK 0x7
100#define UARTPFIFO_TXSIZE_OFF 4
101#define UARTPFIFO_RXFE 0x08
102#define UARTPFIFO_RXSIZE_OFF 0
103
104#define UARTCFIFO_TXFLUSH 0x80
105#define UARTCFIFO_RXFLUSH 0x40
106#define UARTCFIFO_RXOFE 0x04
107#define UARTCFIFO_TXOFE 0x02
108#define UARTCFIFO_RXUFE 0x01
109
110#define UARTSFIFO_TXEMPT 0x80
111#define UARTSFIFO_RXEMPT 0x40
112#define UARTSFIFO_RXOF 0x04
113#define UARTSFIFO_TXOF 0x02
114#define UARTSFIFO_RXUF 0x01
115
116/* 32-bit global registers only for i.MX7ULP/i.MX8x
117 * Used to reset all internal logic and registers, except the Global Register.
118 */
119#define UART_GLOBAL 0x8
120
121/* 32-bit register definition */
122#define UARTBAUD 0x00
123#define UARTSTAT 0x04
124#define UARTCTRL 0x08
125#define UARTDATA 0x0C
126#define UARTMATCH 0x10
127#define UARTMODIR 0x14
128#define UARTFIFO 0x18
129#define UARTWATER 0x1c
130
131#define UARTBAUD_MAEN1 0x80000000
132#define UARTBAUD_MAEN2 0x40000000
133#define UARTBAUD_M10 0x20000000
134#define UARTBAUD_TDMAE 0x00800000
135#define UARTBAUD_RDMAE 0x00200000
136#define UARTBAUD_MATCFG 0x00400000
137#define UARTBAUD_BOTHEDGE 0x00020000
138#define UARTBAUD_RESYNCDIS 0x00010000
139#define UARTBAUD_LBKDIE 0x00008000
140#define UARTBAUD_RXEDGIE 0x00004000
141#define UARTBAUD_SBNS 0x00002000
142#define UARTBAUD_SBR 0x00000000
143#define UARTBAUD_SBR_MASK 0x1fff
144#define UARTBAUD_OSR_MASK 0x1f
145#define UARTBAUD_OSR_SHIFT 24
146
147#define UARTSTAT_LBKDIF 0x80000000
148#define UARTSTAT_RXEDGIF 0x40000000
149#define UARTSTAT_MSBF 0x20000000
150#define UARTSTAT_RXINV 0x10000000
151#define UARTSTAT_RWUID 0x08000000
152#define UARTSTAT_BRK13 0x04000000
153#define UARTSTAT_LBKDE 0x02000000
154#define UARTSTAT_RAF 0x01000000
155#define UARTSTAT_TDRE 0x00800000
156#define UARTSTAT_TC 0x00400000
157#define UARTSTAT_RDRF 0x00200000
158#define UARTSTAT_IDLE 0x00100000
159#define UARTSTAT_OR 0x00080000
160#define UARTSTAT_NF 0x00040000
161#define UARTSTAT_FE 0x00020000
162#define UARTSTAT_PE 0x00010000
163#define UARTSTAT_MA1F 0x00008000
164#define UARTSTAT_M21F 0x00004000
165
166#define UARTCTRL_R8T9 0x80000000
167#define UARTCTRL_R9T8 0x40000000
168#define UARTCTRL_TXDIR 0x20000000
169#define UARTCTRL_TXINV 0x10000000
170#define UARTCTRL_ORIE 0x08000000
171#define UARTCTRL_NEIE 0x04000000
172#define UARTCTRL_FEIE 0x02000000
173#define UARTCTRL_PEIE 0x01000000
174#define UARTCTRL_TIE 0x00800000
175#define UARTCTRL_TCIE 0x00400000
176#define UARTCTRL_RIE 0x00200000
177#define UARTCTRL_ILIE 0x00100000
178#define UARTCTRL_TE 0x00080000
179#define UARTCTRL_RE 0x00040000
180#define UARTCTRL_RWU 0x00020000
181#define UARTCTRL_SBK 0x00010000
182#define UARTCTRL_MA1IE 0x00008000
183#define UARTCTRL_MA2IE 0x00004000
184#define UARTCTRL_IDLECFG 0x00000100
185#define UARTCTRL_LOOPS 0x00000080
186#define UARTCTRL_DOZEEN 0x00000040
187#define UARTCTRL_RSRC 0x00000020
188#define UARTCTRL_M 0x00000010
189#define UARTCTRL_WAKE 0x00000008
190#define UARTCTRL_ILT 0x00000004
191#define UARTCTRL_PE 0x00000002
192#define UARTCTRL_PT 0x00000001
193
194#define UARTDATA_NOISY 0x00008000
195#define UARTDATA_PARITYE 0x00004000
196#define UARTDATA_FRETSC 0x00002000
197#define UARTDATA_RXEMPT 0x00001000
198#define UARTDATA_IDLINE 0x00000800
199#define UARTDATA_MASK 0x3ff
200
201#define UARTMODIR_IREN 0x00020000
202#define UARTMODIR_TXCTSSRC 0x00000020
203#define UARTMODIR_TXCTSC 0x00000010
204#define UARTMODIR_RXRTSE 0x00000008
205#define UARTMODIR_TXRTSPOL 0x00000004
206#define UARTMODIR_TXRTSE 0x00000002
207#define UARTMODIR_TXCTSE 0x00000001
208
209#define UARTFIFO_TXEMPT 0x00800000
210#define UARTFIFO_RXEMPT 0x00400000
211#define UARTFIFO_TXOF 0x00020000
212#define UARTFIFO_RXUF 0x00010000
213#define UARTFIFO_TXFLUSH 0x00008000
214#define UARTFIFO_RXFLUSH 0x00004000
215#define UARTFIFO_TXOFE 0x00000200
216#define UARTFIFO_RXUFE 0x00000100
217#define UARTFIFO_TXFE 0x00000080
218#define UARTFIFO_FIFOSIZE_MASK 0x7
219#define UARTFIFO_TXSIZE_OFF 4
220#define UARTFIFO_RXFE 0x00000008
221#define UARTFIFO_RXSIZE_OFF 0
222#define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0))
223
224#define UARTWATER_COUNT_MASK 0xff
225#define UARTWATER_TXCNT_OFF 8
226#define UARTWATER_RXCNT_OFF 24
227#define UARTWATER_WATER_MASK 0xff
228#define UARTWATER_TXWATER_OFF 0
229#define UARTWATER_RXWATER_OFF 16
230
231#define UART_GLOBAL_RST 0x2
232#define GLOBAL_RST_MIN_US 20
233#define GLOBAL_RST_MAX_US 40
234
235/* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
236#define DMA_RX_TIMEOUT (10)
237#define UART_AUTOSUSPEND_TIMEOUT 3000
238
239#define DRIVER_NAME "fsl-lpuart"
240#define DEV_NAME "ttyLP"
241#define UART_NR 6
242
243/* IMX lpuart has four extra unused regs located at the beginning */
244#define IMX_REG_OFF 0x10
245
246enum lpuart_type {
247 VF610_LPUART,
248 LS1021A_LPUART,
249 LS1028A_LPUART,
250 IMX7ULP_LPUART,
251 IMX8QXP_LPUART,
252 IMXRT1050_LPUART,
253};
254
255struct lpuart_port {
256 struct uart_port port;
257 enum lpuart_type devtype;
258 struct clk *ipg_clk;
259 struct clk *baud_clk;
260 unsigned int txfifo_size;
261 unsigned int rxfifo_size;
262
263 bool lpuart_dma_tx_use;
264 bool lpuart_dma_rx_use;
265 struct dma_chan *dma_tx_chan;
266 struct dma_chan *dma_rx_chan;
267 struct dma_async_tx_descriptor *dma_tx_desc;
268 struct dma_async_tx_descriptor *dma_rx_desc;
269 dma_cookie_t dma_tx_cookie;
270 dma_cookie_t dma_rx_cookie;
271 unsigned int dma_tx_bytes;
272 unsigned int dma_rx_bytes;
273 bool dma_tx_in_progress;
274 unsigned int dma_rx_timeout;
275 struct timer_list lpuart_timer;
276 struct scatterlist rx_sgl, tx_sgl[2];
277 struct circ_buf rx_ring;
278 int rx_dma_rng_buf_len;
279 unsigned int dma_tx_nents;
280 wait_queue_head_t dma_wait;
281 bool is_cs7; /* Set to true when character size is 7 */
282 /* and the parity is enabled */
283};
284
285struct lpuart_soc_data {
286 enum lpuart_type devtype;
287 char iotype;
288 u8 reg_off;
289};
290
291static const struct lpuart_soc_data vf_data = {
292 .devtype = VF610_LPUART,
293 .iotype = UPIO_MEM,
294};
295
296static const struct lpuart_soc_data ls1021a_data = {
297 .devtype = LS1021A_LPUART,
298 .iotype = UPIO_MEM32BE,
299};
300
301static const struct lpuart_soc_data ls1028a_data = {
302 .devtype = LS1028A_LPUART,
303 .iotype = UPIO_MEM32,
304};
305
306static struct lpuart_soc_data imx7ulp_data = {
307 .devtype = IMX7ULP_LPUART,
308 .iotype = UPIO_MEM32,
309 .reg_off = IMX_REG_OFF,
310};
311
312static struct lpuart_soc_data imx8qxp_data = {
313 .devtype = IMX8QXP_LPUART,
314 .iotype = UPIO_MEM32,
315 .reg_off = IMX_REG_OFF,
316};
317static struct lpuart_soc_data imxrt1050_data = {
318 .devtype = IMXRT1050_LPUART,
319 .iotype = UPIO_MEM32,
320 .reg_off = IMX_REG_OFF,
321};
322
323static const struct of_device_id lpuart_dt_ids[] = {
324 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
325 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
326 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, },
327 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
328 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, },
329 { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data},
330 { /* sentinel */ }
331};
332MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
333
334/* Forward declare this for the dma callbacks*/
335static void lpuart_dma_tx_complete(void *arg);
336
337static inline bool is_layerscape_lpuart(struct lpuart_port *sport)
338{
339 return (sport->devtype == LS1021A_LPUART ||
340 sport->devtype == LS1028A_LPUART);
341}
342
343static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport)
344{
345 return sport->devtype == IMX7ULP_LPUART;
346}
347
348static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
349{
350 return sport->devtype == IMX8QXP_LPUART;
351}
352
353static inline u32 lpuart32_read(struct uart_port *port, u32 off)
354{
355 switch (port->iotype) {
356 case UPIO_MEM32:
357 return readl(port->membase + off);
358 case UPIO_MEM32BE:
359 return ioread32be(port->membase + off);
360 default:
361 return 0;
362 }
363}
364
365static inline void lpuart32_write(struct uart_port *port, u32 val,
366 u32 off)
367{
368 switch (port->iotype) {
369 case UPIO_MEM32:
370 writel(val, port->membase + off);
371 break;
372 case UPIO_MEM32BE:
373 iowrite32be(val, port->membase + off);
374 break;
375 }
376}
377
378static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
379{
380 int ret = 0;
381
382 if (is_en) {
383 ret = clk_prepare_enable(sport->ipg_clk);
384 if (ret)
385 return ret;
386
387 ret = clk_prepare_enable(sport->baud_clk);
388 if (ret) {
389 clk_disable_unprepare(sport->ipg_clk);
390 return ret;
391 }
392 } else {
393 clk_disable_unprepare(sport->baud_clk);
394 clk_disable_unprepare(sport->ipg_clk);
395 }
396
397 return 0;
398}
399
400static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
401{
402 if (is_imx8qxp_lpuart(sport))
403 return clk_get_rate(sport->baud_clk);
404
405 return clk_get_rate(sport->ipg_clk);
406}
407
408#define lpuart_enable_clks(x) __lpuart_enable_clks(x, true)
409#define lpuart_disable_clks(x) __lpuart_enable_clks(x, false)
410
411static void lpuart_stop_tx(struct uart_port *port)
412{
413 unsigned char temp;
414
415 temp = readb(port->membase + UARTCR2);
416 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
417 writeb(temp, port->membase + UARTCR2);
418}
419
420static void lpuart32_stop_tx(struct uart_port *port)
421{
422 unsigned long temp;
423
424 temp = lpuart32_read(port, UARTCTRL);
425 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
426 lpuart32_write(port, temp, UARTCTRL);
427}
428
429static void lpuart_stop_rx(struct uart_port *port)
430{
431 unsigned char temp;
432
433 temp = readb(port->membase + UARTCR2);
434 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
435}
436
437static void lpuart32_stop_rx(struct uart_port *port)
438{
439 unsigned long temp;
440
441 temp = lpuart32_read(port, UARTCTRL);
442 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
443}
444
445static void lpuart_dma_tx(struct lpuart_port *sport)
446{
447 struct circ_buf *xmit = &sport->port.state->xmit;
448 struct scatterlist *sgl = sport->tx_sgl;
449 struct device *dev = sport->port.dev;
450 struct dma_chan *chan = sport->dma_tx_chan;
451 int ret;
452
453 if (sport->dma_tx_in_progress)
454 return;
455
456 sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
457
458 if (xmit->tail < xmit->head || xmit->head == 0) {
459 sport->dma_tx_nents = 1;
460 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
461 } else {
462 sport->dma_tx_nents = 2;
463 sg_init_table(sgl, 2);
464 sg_set_buf(sgl, xmit->buf + xmit->tail,
465 UART_XMIT_SIZE - xmit->tail);
466 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
467 }
468
469 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,
470 DMA_TO_DEVICE);
471 if (!ret) {
472 dev_err(dev, "DMA mapping error for TX.\n");
473 return;
474 }
475
476 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,
477 ret, DMA_MEM_TO_DEV,
478 DMA_PREP_INTERRUPT);
479 if (!sport->dma_tx_desc) {
480 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
481 DMA_TO_DEVICE);
482 dev_err(dev, "Cannot prepare TX slave DMA!\n");
483 return;
484 }
485
486 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
487 sport->dma_tx_desc->callback_param = sport;
488 sport->dma_tx_in_progress = true;
489 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
490 dma_async_issue_pending(chan);
491}
492
493static bool lpuart_stopped_or_empty(struct uart_port *port)
494{
495 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port);
496}
497
498static void lpuart_dma_tx_complete(void *arg)
499{
500 struct lpuart_port *sport = arg;
501 struct scatterlist *sgl = &sport->tx_sgl[0];
502 struct circ_buf *xmit = &sport->port.state->xmit;
503 struct dma_chan *chan = sport->dma_tx_chan;
504 unsigned long flags;
505
506 spin_lock_irqsave(&sport->port.lock, flags);
507 if (!sport->dma_tx_in_progress) {
508 spin_unlock_irqrestore(&sport->port.lock, flags);
509 return;
510 }
511
512 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
513 DMA_TO_DEVICE);
514
515 uart_xmit_advance(&sport->port, sport->dma_tx_bytes);
516 sport->dma_tx_in_progress = false;
517 spin_unlock_irqrestore(&sport->port.lock, flags);
518
519 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
520 uart_write_wakeup(&sport->port);
521
522 if (waitqueue_active(&sport->dma_wait)) {
523 wake_up(&sport->dma_wait);
524 return;
525 }
526
527 spin_lock_irqsave(&sport->port.lock, flags);
528
529 if (!lpuart_stopped_or_empty(&sport->port))
530 lpuart_dma_tx(sport);
531
532 spin_unlock_irqrestore(&sport->port.lock, flags);
533}
534
535static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
536{
537 switch (sport->port.iotype) {
538 case UPIO_MEM32:
539 return sport->port.mapbase + UARTDATA;
540 case UPIO_MEM32BE:
541 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
542 }
543 return sport->port.mapbase + UARTDR;
544}
545
546static int lpuart_dma_tx_request(struct uart_port *port)
547{
548 struct lpuart_port *sport = container_of(port,
549 struct lpuart_port, port);
550 struct dma_slave_config dma_tx_sconfig = {};
551 int ret;
552
553 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
554 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
555 dma_tx_sconfig.dst_maxburst = 1;
556 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
557 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
558
559 if (ret) {
560 dev_err(sport->port.dev,
561 "DMA slave config failed, err = %d\n", ret);
562 return ret;
563 }
564
565 return 0;
566}
567
568static bool lpuart_is_32(struct lpuart_port *sport)
569{
570 return sport->port.iotype == UPIO_MEM32 ||
571 sport->port.iotype == UPIO_MEM32BE;
572}
573
574static void lpuart_flush_buffer(struct uart_port *port)
575{
576 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
577 struct dma_chan *chan = sport->dma_tx_chan;
578 u32 val;
579
580 if (sport->lpuart_dma_tx_use) {
581 if (sport->dma_tx_in_progress) {
582 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],
583 sport->dma_tx_nents, DMA_TO_DEVICE);
584 sport->dma_tx_in_progress = false;
585 }
586 dmaengine_terminate_async(chan);
587 }
588
589 if (lpuart_is_32(sport)) {
590 val = lpuart32_read(&sport->port, UARTFIFO);
591 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
592 lpuart32_write(&sport->port, val, UARTFIFO);
593 } else {
594 val = readb(sport->port.membase + UARTCFIFO);
595 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
596 writeb(val, sport->port.membase + UARTCFIFO);
597 }
598}
599
600static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
601 u8 bit)
602{
603 while (!(readb(port->membase + offset) & bit))
604 cpu_relax();
605}
606
607static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
608 u32 bit)
609{
610 while (!(lpuart32_read(port, offset) & bit))
611 cpu_relax();
612}
613
614#if defined(CONFIG_CONSOLE_POLL)
615
616static int lpuart_poll_init(struct uart_port *port)
617{
618 struct lpuart_port *sport = container_of(port,
619 struct lpuart_port, port);
620 unsigned long flags;
621 unsigned char temp;
622
623 sport->port.fifosize = 0;
624
625 spin_lock_irqsave(&sport->port.lock, flags);
626 /* Disable Rx & Tx */
627 writeb(0, sport->port.membase + UARTCR2);
628
629 temp = readb(sport->port.membase + UARTPFIFO);
630 /* Enable Rx and Tx FIFO */
631 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
632 sport->port.membase + UARTPFIFO);
633
634 /* flush Tx and Rx FIFO */
635 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
636 sport->port.membase + UARTCFIFO);
637
638 /* explicitly clear RDRF */
639 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
640 readb(sport->port.membase + UARTDR);
641 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
642 }
643
644 writeb(0, sport->port.membase + UARTTWFIFO);
645 writeb(1, sport->port.membase + UARTRWFIFO);
646
647 /* Enable Rx and Tx */
648 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
649 spin_unlock_irqrestore(&sport->port.lock, flags);
650
651 return 0;
652}
653
654static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
655{
656 /* drain */
657 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
658 writeb(c, port->membase + UARTDR);
659}
660
661static int lpuart_poll_get_char(struct uart_port *port)
662{
663 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
664 return NO_POLL_CHAR;
665
666 return readb(port->membase + UARTDR);
667}
668
669static int lpuart32_poll_init(struct uart_port *port)
670{
671 unsigned long flags;
672 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
673 u32 temp;
674
675 sport->port.fifosize = 0;
676
677 spin_lock_irqsave(&sport->port.lock, flags);
678
679 /* Disable Rx & Tx */
680 lpuart32_write(&sport->port, 0, UARTCTRL);
681
682 temp = lpuart32_read(&sport->port, UARTFIFO);
683
684 /* Enable Rx and Tx FIFO */
685 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
686
687 /* flush Tx and Rx FIFO */
688 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
689
690 /* explicitly clear RDRF */
691 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
692 lpuart32_read(&sport->port, UARTDATA);
693 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
694 }
695
696 /* Enable Rx and Tx */
697 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
698 spin_unlock_irqrestore(&sport->port.lock, flags);
699
700 return 0;
701}
702
703static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
704{
705 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
706 lpuart32_write(port, c, UARTDATA);
707}
708
709static int lpuart32_poll_get_char(struct uart_port *port)
710{
711 if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF))
712 return NO_POLL_CHAR;
713
714 return lpuart32_read(port, UARTDATA);
715}
716#endif
717
718static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
719{
720 struct uart_port *port = &sport->port;
721 u8 ch;
722
723 uart_port_tx(port, ch,
724 readb(port->membase + UARTTCFIFO) < sport->txfifo_size,
725 writeb(ch, port->membase + UARTDR));
726}
727
728static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
729{
730 struct circ_buf *xmit = &sport->port.state->xmit;
731 unsigned long txcnt;
732
733 if (sport->port.x_char) {
734 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
735 sport->port.icount.tx++;
736 sport->port.x_char = 0;
737 return;
738 }
739
740 if (lpuart_stopped_or_empty(&sport->port)) {
741 lpuart32_stop_tx(&sport->port);
742 return;
743 }
744
745 txcnt = lpuart32_read(&sport->port, UARTWATER);
746 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
747 txcnt &= UARTWATER_COUNT_MASK;
748 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
749 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
750 uart_xmit_advance(&sport->port, 1);
751 txcnt = lpuart32_read(&sport->port, UARTWATER);
752 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
753 txcnt &= UARTWATER_COUNT_MASK;
754 }
755
756 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
757 uart_write_wakeup(&sport->port);
758
759 if (uart_circ_empty(xmit))
760 lpuart32_stop_tx(&sport->port);
761}
762
763static void lpuart_start_tx(struct uart_port *port)
764{
765 struct lpuart_port *sport = container_of(port,
766 struct lpuart_port, port);
767 unsigned char temp;
768
769 temp = readb(port->membase + UARTCR2);
770 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
771
772 if (sport->lpuart_dma_tx_use) {
773 if (!lpuart_stopped_or_empty(port))
774 lpuart_dma_tx(sport);
775 } else {
776 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
777 lpuart_transmit_buffer(sport);
778 }
779}
780
781static void lpuart32_start_tx(struct uart_port *port)
782{
783 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
784 unsigned long temp;
785
786 if (sport->lpuart_dma_tx_use) {
787 if (!lpuart_stopped_or_empty(port))
788 lpuart_dma_tx(sport);
789 } else {
790 temp = lpuart32_read(port, UARTCTRL);
791 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
792
793 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
794 lpuart32_transmit_buffer(sport);
795 }
796}
797
798static void
799lpuart_uart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
800{
801 switch (state) {
802 case UART_PM_STATE_OFF:
803 pm_runtime_mark_last_busy(port->dev);
804 pm_runtime_put_autosuspend(port->dev);
805 break;
806 default:
807 pm_runtime_get_sync(port->dev);
808 break;
809 }
810}
811
812/* return TIOCSER_TEMT when transmitter is not busy */
813static unsigned int lpuart_tx_empty(struct uart_port *port)
814{
815 struct lpuart_port *sport = container_of(port,
816 struct lpuart_port, port);
817 unsigned char sr1 = readb(port->membase + UARTSR1);
818 unsigned char sfifo = readb(port->membase + UARTSFIFO);
819
820 if (sport->dma_tx_in_progress)
821 return 0;
822
823 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
824 return TIOCSER_TEMT;
825
826 return 0;
827}
828
829static unsigned int lpuart32_tx_empty(struct uart_port *port)
830{
831 struct lpuart_port *sport = container_of(port,
832 struct lpuart_port, port);
833 unsigned long stat = lpuart32_read(port, UARTSTAT);
834 unsigned long sfifo = lpuart32_read(port, UARTFIFO);
835
836 if (sport->dma_tx_in_progress)
837 return 0;
838
839 if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT)
840 return TIOCSER_TEMT;
841
842 return 0;
843}
844
845static void lpuart_txint(struct lpuart_port *sport)
846{
847 spin_lock(&sport->port.lock);
848 lpuart_transmit_buffer(sport);
849 spin_unlock(&sport->port.lock);
850}
851
852static void lpuart_rxint(struct lpuart_port *sport)
853{
854 unsigned int flg, ignored = 0, overrun = 0;
855 struct tty_port *port = &sport->port.state->port;
856 unsigned char rx, sr;
857
858 spin_lock(&sport->port.lock);
859
860 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
861 flg = TTY_NORMAL;
862 sport->port.icount.rx++;
863 /*
864 * to clear the FE, OR, NF, FE, PE flags,
865 * read SR1 then read DR
866 */
867 sr = readb(sport->port.membase + UARTSR1);
868 rx = readb(sport->port.membase + UARTDR);
869
870 if (uart_prepare_sysrq_char(&sport->port, rx))
871 continue;
872
873 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
874 if (sr & UARTSR1_PE)
875 sport->port.icount.parity++;
876 else if (sr & UARTSR1_FE)
877 sport->port.icount.frame++;
878
879 if (sr & UARTSR1_OR)
880 overrun++;
881
882 if (sr & sport->port.ignore_status_mask) {
883 if (++ignored > 100)
884 goto out;
885 continue;
886 }
887
888 sr &= sport->port.read_status_mask;
889
890 if (sr & UARTSR1_PE)
891 flg = TTY_PARITY;
892 else if (sr & UARTSR1_FE)
893 flg = TTY_FRAME;
894
895 if (sr & UARTSR1_OR)
896 flg = TTY_OVERRUN;
897
898 sport->port.sysrq = 0;
899 }
900
901 if (tty_insert_flip_char(port, rx, flg) == 0)
902 sport->port.icount.buf_overrun++;
903 }
904
905out:
906 if (overrun) {
907 sport->port.icount.overrun += overrun;
908
909 /*
910 * Overruns cause FIFO pointers to become missaligned.
911 * Flushing the receive FIFO reinitializes the pointers.
912 */
913 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
914 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
915 }
916
917 uart_unlock_and_check_sysrq(&sport->port);
918
919 tty_flip_buffer_push(port);
920}
921
922static void lpuart32_txint(struct lpuart_port *sport)
923{
924 spin_lock(&sport->port.lock);
925 lpuart32_transmit_buffer(sport);
926 spin_unlock(&sport->port.lock);
927}
928
929static void lpuart32_rxint(struct lpuart_port *sport)
930{
931 unsigned int flg, ignored = 0;
932 struct tty_port *port = &sport->port.state->port;
933 unsigned long rx, sr;
934 bool is_break;
935
936 spin_lock(&sport->port.lock);
937
938 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
939 flg = TTY_NORMAL;
940 sport->port.icount.rx++;
941 /*
942 * to clear the FE, OR, NF, FE, PE flags,
943 * read STAT then read DATA reg
944 */
945 sr = lpuart32_read(&sport->port, UARTSTAT);
946 rx = lpuart32_read(&sport->port, UARTDATA);
947 rx &= UARTDATA_MASK;
948
949 /*
950 * The LPUART can't distinguish between a break and a framing error,
951 * thus we assume it is a break if the received data is zero.
952 */
953 is_break = (sr & UARTSTAT_FE) && !rx;
954
955 if (is_break && uart_handle_break(&sport->port))
956 continue;
957
958 if (uart_prepare_sysrq_char(&sport->port, rx))
959 continue;
960
961 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
962 if (sr & UARTSTAT_PE) {
963 sport->port.icount.parity++;
964 } else if (sr & UARTSTAT_FE) {
965 if (is_break)
966 sport->port.icount.brk++;
967 else
968 sport->port.icount.frame++;
969 }
970
971 if (sr & UARTSTAT_OR)
972 sport->port.icount.overrun++;
973
974 if (sr & sport->port.ignore_status_mask) {
975 if (++ignored > 100)
976 goto out;
977 continue;
978 }
979
980 sr &= sport->port.read_status_mask;
981
982 if (sr & UARTSTAT_PE) {
983 flg = TTY_PARITY;
984 } else if (sr & UARTSTAT_FE) {
985 if (is_break)
986 flg = TTY_BREAK;
987 else
988 flg = TTY_FRAME;
989 }
990
991 if (sr & UARTSTAT_OR)
992 flg = TTY_OVERRUN;
993 }
994
995 if (sport->is_cs7)
996 rx &= 0x7F;
997
998 if (tty_insert_flip_char(port, rx, flg) == 0)
999 sport->port.icount.buf_overrun++;
1000 }
1001
1002out:
1003 uart_unlock_and_check_sysrq(&sport->port);
1004
1005 tty_flip_buffer_push(port);
1006}
1007
1008static irqreturn_t lpuart_int(int irq, void *dev_id)
1009{
1010 struct lpuart_port *sport = dev_id;
1011 unsigned char sts;
1012
1013 sts = readb(sport->port.membase + UARTSR1);
1014
1015 /* SysRq, using dma, check for linebreak by framing err. */
1016 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) {
1017 readb(sport->port.membase + UARTDR);
1018 uart_handle_break(&sport->port);
1019 /* linebreak produces some garbage, removing it */
1020 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
1021 return IRQ_HANDLED;
1022 }
1023
1024 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
1025 lpuart_rxint(sport);
1026
1027 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
1028 lpuart_txint(sport);
1029
1030 return IRQ_HANDLED;
1031}
1032
1033static irqreturn_t lpuart32_int(int irq, void *dev_id)
1034{
1035 struct lpuart_port *sport = dev_id;
1036 unsigned long sts, rxcount;
1037
1038 sts = lpuart32_read(&sport->port, UARTSTAT);
1039 rxcount = lpuart32_read(&sport->port, UARTWATER);
1040 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
1041
1042 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
1043 lpuart32_rxint(sport);
1044
1045 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
1046 lpuart32_txint(sport);
1047
1048 lpuart32_write(&sport->port, sts, UARTSTAT);
1049 return IRQ_HANDLED;
1050}
1051
1052
1053static inline void lpuart_handle_sysrq_chars(struct uart_port *port,
1054 unsigned char *p, int count)
1055{
1056 while (count--) {
1057 if (*p && uart_handle_sysrq_char(port, *p))
1058 return;
1059 p++;
1060 }
1061}
1062
1063static void lpuart_handle_sysrq(struct lpuart_port *sport)
1064{
1065 struct circ_buf *ring = &sport->rx_ring;
1066 int count;
1067
1068 if (ring->head < ring->tail) {
1069 count = sport->rx_sgl.length - ring->tail;
1070 lpuart_handle_sysrq_chars(&sport->port,
1071 ring->buf + ring->tail, count);
1072 ring->tail = 0;
1073 }
1074
1075 if (ring->head > ring->tail) {
1076 count = ring->head - ring->tail;
1077 lpuart_handle_sysrq_chars(&sport->port,
1078 ring->buf + ring->tail, count);
1079 ring->tail = ring->head;
1080 }
1081}
1082
1083static int lpuart_tty_insert_flip_string(struct tty_port *port,
1084 unsigned char *chars, size_t size, bool is_cs7)
1085{
1086 int i;
1087
1088 if (is_cs7)
1089 for (i = 0; i < size; i++)
1090 chars[i] &= 0x7F;
1091 return tty_insert_flip_string(port, chars, size);
1092}
1093
1094static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
1095{
1096 struct tty_port *port = &sport->port.state->port;
1097 struct dma_tx_state state;
1098 enum dma_status dmastat;
1099 struct dma_chan *chan = sport->dma_rx_chan;
1100 struct circ_buf *ring = &sport->rx_ring;
1101 unsigned long flags;
1102 int count, copied;
1103
1104 if (lpuart_is_32(sport)) {
1105 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
1106
1107 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
1108 /* Read DR to clear the error flags */
1109 lpuart32_read(&sport->port, UARTDATA);
1110
1111 if (sr & UARTSTAT_PE)
1112 sport->port.icount.parity++;
1113 else if (sr & UARTSTAT_FE)
1114 sport->port.icount.frame++;
1115 }
1116 } else {
1117 unsigned char sr = readb(sport->port.membase + UARTSR1);
1118
1119 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
1120 unsigned char cr2;
1121
1122 /* Disable receiver during this operation... */
1123 cr2 = readb(sport->port.membase + UARTCR2);
1124 cr2 &= ~UARTCR2_RE;
1125 writeb(cr2, sport->port.membase + UARTCR2);
1126
1127 /* Read DR to clear the error flags */
1128 readb(sport->port.membase + UARTDR);
1129
1130 if (sr & UARTSR1_PE)
1131 sport->port.icount.parity++;
1132 else if (sr & UARTSR1_FE)
1133 sport->port.icount.frame++;
1134 /*
1135 * At this point parity/framing error is
1136 * cleared However, since the DMA already read
1137 * the data register and we had to read it
1138 * again after reading the status register to
1139 * properly clear the flags, the FIFO actually
1140 * underflowed... This requires a clearing of
1141 * the FIFO...
1142 */
1143 if (readb(sport->port.membase + UARTSFIFO) &
1144 UARTSFIFO_RXUF) {
1145 writeb(UARTSFIFO_RXUF,
1146 sport->port.membase + UARTSFIFO);
1147 writeb(UARTCFIFO_RXFLUSH,
1148 sport->port.membase + UARTCFIFO);
1149 }
1150
1151 cr2 |= UARTCR2_RE;
1152 writeb(cr2, sport->port.membase + UARTCR2);
1153 }
1154 }
1155
1156 async_tx_ack(sport->dma_rx_desc);
1157
1158 spin_lock_irqsave(&sport->port.lock, flags);
1159
1160 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1161 if (dmastat == DMA_ERROR) {
1162 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1163 spin_unlock_irqrestore(&sport->port.lock, flags);
1164 return;
1165 }
1166
1167 /* CPU claims ownership of RX DMA buffer */
1168 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,
1169 DMA_FROM_DEVICE);
1170
1171 /*
1172 * ring->head points to the end of data already written by the DMA.
1173 * ring->tail points to the beginning of data to be read by the
1174 * framework.
1175 * The current transfer size should not be larger than the dma buffer
1176 * length.
1177 */
1178 ring->head = sport->rx_sgl.length - state.residue;
1179 BUG_ON(ring->head > sport->rx_sgl.length);
1180
1181 /*
1182 * Silent handling of keys pressed in the sysrq timeframe
1183 */
1184 if (sport->port.sysrq) {
1185 lpuart_handle_sysrq(sport);
1186 goto exit;
1187 }
1188
1189 /*
1190 * At this point ring->head may point to the first byte right after the
1191 * last byte of the dma buffer:
1192 * 0 <= ring->head <= sport->rx_sgl.length
1193 *
1194 * However ring->tail must always points inside the dma buffer:
1195 * 0 <= ring->tail <= sport->rx_sgl.length - 1
1196 *
1197 * Since we use a ring buffer, we have to handle the case
1198 * where head is lower than tail. In such a case, we first read from
1199 * tail to the end of the buffer then reset tail.
1200 */
1201 if (ring->head < ring->tail) {
1202 count = sport->rx_sgl.length - ring->tail;
1203
1204 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
1205 count, sport->is_cs7);
1206 if (copied != count)
1207 sport->port.icount.buf_overrun++;
1208 ring->tail = 0;
1209 sport->port.icount.rx += copied;
1210 }
1211
1212 /* Finally we read data from tail to head */
1213 if (ring->tail < ring->head) {
1214 count = ring->head - ring->tail;
1215 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
1216 count, sport->is_cs7);
1217 if (copied != count)
1218 sport->port.icount.buf_overrun++;
1219 /* Wrap ring->head if needed */
1220 if (ring->head >= sport->rx_sgl.length)
1221 ring->head = 0;
1222 ring->tail = ring->head;
1223 sport->port.icount.rx += copied;
1224 }
1225
1226exit:
1227 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
1228 DMA_FROM_DEVICE);
1229
1230 spin_unlock_irqrestore(&sport->port.lock, flags);
1231
1232 tty_flip_buffer_push(port);
1233 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1234}
1235
1236static void lpuart_dma_rx_complete(void *arg)
1237{
1238 struct lpuart_port *sport = arg;
1239
1240 lpuart_copy_rx_to_tty(sport);
1241}
1242
1243static void lpuart_timer_func(struct timer_list *t)
1244{
1245 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1246
1247 lpuart_copy_rx_to_tty(sport);
1248}
1249
1250static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1251{
1252 struct dma_slave_config dma_rx_sconfig = {};
1253 struct circ_buf *ring = &sport->rx_ring;
1254 int ret, nent;
1255 struct tty_port *port = &sport->port.state->port;
1256 struct tty_struct *tty = port->tty;
1257 struct ktermios *termios = &tty->termios;
1258 struct dma_chan *chan = sport->dma_rx_chan;
1259 unsigned int bits = tty_get_frame_size(termios->c_cflag);
1260 unsigned int baud = tty_get_baud_rate(tty);
1261
1262 /*
1263 * Calculate length of one DMA buffer size to keep latency below
1264 * 10ms at any baud rate.
1265 */
1266 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2;
1267 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
1268 if (sport->rx_dma_rng_buf_len < 16)
1269 sport->rx_dma_rng_buf_len = 16;
1270
1271 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1272 if (!ring->buf)
1273 return -ENOMEM;
1274
1275 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1276 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,
1277 DMA_FROM_DEVICE);
1278
1279 if (!nent) {
1280 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1281 return -EINVAL;
1282 }
1283
1284 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1285 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1286 dma_rx_sconfig.src_maxburst = 1;
1287 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1288 ret = dmaengine_slave_config(chan, &dma_rx_sconfig);
1289
1290 if (ret < 0) {
1291 dev_err(sport->port.dev,
1292 "DMA Rx slave config failed, err = %d\n", ret);
1293 return ret;
1294 }
1295
1296 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,
1297 sg_dma_address(&sport->rx_sgl),
1298 sport->rx_sgl.length,
1299 sport->rx_sgl.length / 2,
1300 DMA_DEV_TO_MEM,
1301 DMA_PREP_INTERRUPT);
1302 if (!sport->dma_rx_desc) {
1303 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1304 return -EFAULT;
1305 }
1306
1307 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1308 sport->dma_rx_desc->callback_param = sport;
1309 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1310 dma_async_issue_pending(chan);
1311
1312 if (lpuart_is_32(sport)) {
1313 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1314
1315 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1316 } else {
1317 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1318 sport->port.membase + UARTCR5);
1319 }
1320
1321 return 0;
1322}
1323
1324static void lpuart_dma_rx_free(struct uart_port *port)
1325{
1326 struct lpuart_port *sport = container_of(port,
1327 struct lpuart_port, port);
1328 struct dma_chan *chan = sport->dma_rx_chan;
1329
1330 dmaengine_terminate_sync(chan);
1331 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1332 kfree(sport->rx_ring.buf);
1333 sport->rx_ring.tail = 0;
1334 sport->rx_ring.head = 0;
1335 sport->dma_rx_desc = NULL;
1336 sport->dma_rx_cookie = -EINVAL;
1337}
1338
1339static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios,
1340 struct serial_rs485 *rs485)
1341{
1342 struct lpuart_port *sport = container_of(port,
1343 struct lpuart_port, port);
1344
1345 u8 modem = readb(sport->port.membase + UARTMODEM) &
1346 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1347 writeb(modem, sport->port.membase + UARTMODEM);
1348
1349 if (rs485->flags & SER_RS485_ENABLED) {
1350 /* Enable auto RS-485 RTS mode */
1351 modem |= UARTMODEM_TXRTSE;
1352
1353 /*
1354 * The hardware defaults to RTS logic HIGH while transfer.
1355 * Switch polarity in case RTS shall be logic HIGH
1356 * after transfer.
1357 * Note: UART is assumed to be active high.
1358 */
1359 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1360 modem |= UARTMODEM_TXRTSPOL;
1361 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1362 modem &= ~UARTMODEM_TXRTSPOL;
1363 }
1364
1365 writeb(modem, sport->port.membase + UARTMODEM);
1366 return 0;
1367}
1368
1369static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termios,
1370 struct serial_rs485 *rs485)
1371{
1372 struct lpuart_port *sport = container_of(port,
1373 struct lpuart_port, port);
1374
1375 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
1376 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1377 lpuart32_write(&sport->port, modem, UARTMODIR);
1378
1379 if (rs485->flags & SER_RS485_ENABLED) {
1380 /* Enable auto RS-485 RTS mode */
1381 modem |= UARTMODEM_TXRTSE;
1382
1383 /*
1384 * The hardware defaults to RTS logic HIGH while transfer.
1385 * Switch polarity in case RTS shall be logic HIGH
1386 * after transfer.
1387 * Note: UART is assumed to be active high.
1388 */
1389 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1390 modem &= ~UARTMODEM_TXRTSPOL;
1391 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1392 modem |= UARTMODEM_TXRTSPOL;
1393 }
1394
1395 lpuart32_write(&sport->port, modem, UARTMODIR);
1396 return 0;
1397}
1398
1399static unsigned int lpuart_get_mctrl(struct uart_port *port)
1400{
1401 unsigned int mctrl = 0;
1402 u8 reg;
1403
1404 reg = readb(port->membase + UARTCR1);
1405 if (reg & UARTCR1_LOOPS)
1406 mctrl |= TIOCM_LOOP;
1407
1408 return mctrl;
1409}
1410
1411static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1412{
1413 unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1414 u32 reg;
1415
1416 reg = lpuart32_read(port, UARTCTRL);
1417 if (reg & UARTCTRL_LOOPS)
1418 mctrl |= TIOCM_LOOP;
1419
1420 return mctrl;
1421}
1422
1423static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1424{
1425 u8 reg;
1426
1427 reg = readb(port->membase + UARTCR1);
1428
1429 /* for internal loopback we need LOOPS=1 and RSRC=0 */
1430 reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC);
1431 if (mctrl & TIOCM_LOOP)
1432 reg |= UARTCR1_LOOPS;
1433
1434 writeb(reg, port->membase + UARTCR1);
1435}
1436
1437static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1438{
1439 u32 reg;
1440
1441 reg = lpuart32_read(port, UARTCTRL);
1442
1443 /* for internal loopback we need LOOPS=1 and RSRC=0 */
1444 reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC);
1445 if (mctrl & TIOCM_LOOP)
1446 reg |= UARTCTRL_LOOPS;
1447
1448 lpuart32_write(port, reg, UARTCTRL);
1449}
1450
1451static void lpuart_break_ctl(struct uart_port *port, int break_state)
1452{
1453 unsigned char temp;
1454
1455 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1456
1457 if (break_state != 0)
1458 temp |= UARTCR2_SBK;
1459
1460 writeb(temp, port->membase + UARTCR2);
1461}
1462
1463static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1464{
1465 unsigned long temp;
1466
1467 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
1468
1469 if (break_state != 0)
1470 temp |= UARTCTRL_SBK;
1471
1472 lpuart32_write(port, temp, UARTCTRL);
1473}
1474
1475static void lpuart_setup_watermark(struct lpuart_port *sport)
1476{
1477 unsigned char val, cr2;
1478 unsigned char cr2_saved;
1479
1480 cr2 = readb(sport->port.membase + UARTCR2);
1481 cr2_saved = cr2;
1482 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1483 UARTCR2_RIE | UARTCR2_RE);
1484 writeb(cr2, sport->port.membase + UARTCR2);
1485
1486 val = readb(sport->port.membase + UARTPFIFO);
1487 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1488 sport->port.membase + UARTPFIFO);
1489
1490 /* flush Tx and Rx FIFO */
1491 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1492 sport->port.membase + UARTCFIFO);
1493
1494 /* explicitly clear RDRF */
1495 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1496 readb(sport->port.membase + UARTDR);
1497 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1498 }
1499
1500 writeb(0, sport->port.membase + UARTTWFIFO);
1501 writeb(1, sport->port.membase + UARTRWFIFO);
1502
1503 /* Restore cr2 */
1504 writeb(cr2_saved, sport->port.membase + UARTCR2);
1505}
1506
1507static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
1508{
1509 unsigned char cr2;
1510
1511 lpuart_setup_watermark(sport);
1512
1513 cr2 = readb(sport->port.membase + UARTCR2);
1514 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE;
1515 writeb(cr2, sport->port.membase + UARTCR2);
1516}
1517
1518static void lpuart32_setup_watermark(struct lpuart_port *sport)
1519{
1520 unsigned long val, ctrl;
1521 unsigned long ctrl_saved;
1522
1523 ctrl = lpuart32_read(&sport->port, UARTCTRL);
1524 ctrl_saved = ctrl;
1525 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1526 UARTCTRL_RIE | UARTCTRL_RE);
1527 lpuart32_write(&sport->port, ctrl, UARTCTRL);
1528
1529 /* enable FIFO mode */
1530 val = lpuart32_read(&sport->port, UARTFIFO);
1531 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1532 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1533 lpuart32_write(&sport->port, val, UARTFIFO);
1534
1535 /* set the watermark */
1536 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1537 lpuart32_write(&sport->port, val, UARTWATER);
1538
1539 /* Restore cr2 */
1540 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1541}
1542
1543static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
1544{
1545 u32 temp;
1546
1547 lpuart32_setup_watermark(sport);
1548
1549 temp = lpuart32_read(&sport->port, UARTCTRL);
1550 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE;
1551 lpuart32_write(&sport->port, temp, UARTCTRL);
1552}
1553
1554static void rx_dma_timer_init(struct lpuart_port *sport)
1555{
1556 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1557 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1558 add_timer(&sport->lpuart_timer);
1559}
1560
1561static void lpuart_request_dma(struct lpuart_port *sport)
1562{
1563 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");
1564 if (IS_ERR(sport->dma_tx_chan)) {
1565 dev_dbg_once(sport->port.dev,
1566 "DMA tx channel request failed, operating without tx DMA (%ld)\n",
1567 PTR_ERR(sport->dma_tx_chan));
1568 sport->dma_tx_chan = NULL;
1569 }
1570
1571 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");
1572 if (IS_ERR(sport->dma_rx_chan)) {
1573 dev_dbg_once(sport->port.dev,
1574 "DMA rx channel request failed, operating without rx DMA (%ld)\n",
1575 PTR_ERR(sport->dma_rx_chan));
1576 sport->dma_rx_chan = NULL;
1577 }
1578}
1579
1580static void lpuart_tx_dma_startup(struct lpuart_port *sport)
1581{
1582 u32 uartbaud;
1583 int ret;
1584
1585 if (uart_console(&sport->port))
1586 goto err;
1587
1588 if (!sport->dma_tx_chan)
1589 goto err;
1590
1591 ret = lpuart_dma_tx_request(&sport->port);
1592 if (ret)
1593 goto err;
1594
1595 init_waitqueue_head(&sport->dma_wait);
1596 sport->lpuart_dma_tx_use = true;
1597 if (lpuart_is_32(sport)) {
1598 uartbaud = lpuart32_read(&sport->port, UARTBAUD);
1599 lpuart32_write(&sport->port,
1600 uartbaud | UARTBAUD_TDMAE, UARTBAUD);
1601 } else {
1602 writeb(readb(sport->port.membase + UARTCR5) |
1603 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1604 }
1605
1606 return;
1607
1608err:
1609 sport->lpuart_dma_tx_use = false;
1610}
1611
1612static void lpuart_rx_dma_startup(struct lpuart_port *sport)
1613{
1614 int ret;
1615 unsigned char cr3;
1616
1617 if (uart_console(&sport->port))
1618 goto err;
1619
1620 if (!sport->dma_rx_chan)
1621 goto err;
1622
1623 ret = lpuart_start_rx_dma(sport);
1624 if (ret)
1625 goto err;
1626
1627 /* set Rx DMA timeout */
1628 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1629 if (!sport->dma_rx_timeout)
1630 sport->dma_rx_timeout = 1;
1631
1632 sport->lpuart_dma_rx_use = true;
1633 rx_dma_timer_init(sport);
1634
1635 if (sport->port.has_sysrq && !lpuart_is_32(sport)) {
1636 cr3 = readb(sport->port.membase + UARTCR3);
1637 cr3 |= UARTCR3_FEIE;
1638 writeb(cr3, sport->port.membase + UARTCR3);
1639 }
1640
1641 return;
1642
1643err:
1644 sport->lpuart_dma_rx_use = false;
1645}
1646
1647static void lpuart_hw_setup(struct lpuart_port *sport)
1648{
1649 unsigned long flags;
1650
1651 spin_lock_irqsave(&sport->port.lock, flags);
1652
1653 lpuart_setup_watermark_enable(sport);
1654
1655 lpuart_rx_dma_startup(sport);
1656 lpuart_tx_dma_startup(sport);
1657
1658 spin_unlock_irqrestore(&sport->port.lock, flags);
1659}
1660
1661static int lpuart_startup(struct uart_port *port)
1662{
1663 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1664 unsigned char temp;
1665
1666 /* determine FIFO size and enable FIFO mode */
1667 temp = readb(sport->port.membase + UARTPFIFO);
1668
1669 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
1670 UARTPFIFO_FIFOSIZE_MASK);
1671 sport->port.fifosize = sport->txfifo_size;
1672
1673 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
1674 UARTPFIFO_FIFOSIZE_MASK);
1675
1676 lpuart_request_dma(sport);
1677 lpuart_hw_setup(sport);
1678
1679 return 0;
1680}
1681
1682static void lpuart32_configure(struct lpuart_port *sport)
1683{
1684 unsigned long temp;
1685
1686 if (sport->lpuart_dma_rx_use) {
1687 /* RXWATER must be 0 */
1688 temp = lpuart32_read(&sport->port, UARTWATER);
1689 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF);
1690 lpuart32_write(&sport->port, temp, UARTWATER);
1691 }
1692 temp = lpuart32_read(&sport->port, UARTCTRL);
1693 if (!sport->lpuart_dma_rx_use)
1694 temp |= UARTCTRL_RIE;
1695 if (!sport->lpuart_dma_tx_use)
1696 temp |= UARTCTRL_TIE;
1697 lpuart32_write(&sport->port, temp, UARTCTRL);
1698}
1699
1700static void lpuart32_hw_setup(struct lpuart_port *sport)
1701{
1702 unsigned long flags;
1703
1704 spin_lock_irqsave(&sport->port.lock, flags);
1705
1706 lpuart32_setup_watermark_enable(sport);
1707
1708 lpuart_rx_dma_startup(sport);
1709 lpuart_tx_dma_startup(sport);
1710
1711 lpuart32_configure(sport);
1712
1713 spin_unlock_irqrestore(&sport->port.lock, flags);
1714}
1715
1716static int lpuart32_startup(struct uart_port *port)
1717{
1718 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1719 unsigned long temp;
1720
1721 /* determine FIFO size */
1722 temp = lpuart32_read(&sport->port, UARTFIFO);
1723
1724 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
1725 UARTFIFO_FIFOSIZE_MASK);
1726 sport->port.fifosize = sport->txfifo_size;
1727
1728 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
1729 UARTFIFO_FIFOSIZE_MASK);
1730
1731 /*
1732 * The LS1021A and LS1028A have a fixed FIFO depth of 16 words.
1733 * Although they support the RX/TXSIZE fields, their encoding is
1734 * different. Eg the reference manual states 0b101 is 16 words.
1735 */
1736 if (is_layerscape_lpuart(sport)) {
1737 sport->rxfifo_size = 16;
1738 sport->txfifo_size = 16;
1739 sport->port.fifosize = sport->txfifo_size;
1740 }
1741
1742 lpuart_request_dma(sport);
1743 lpuart32_hw_setup(sport);
1744
1745 return 0;
1746}
1747
1748static void lpuart_dma_shutdown(struct lpuart_port *sport)
1749{
1750 if (sport->lpuart_dma_rx_use) {
1751 del_timer_sync(&sport->lpuart_timer);
1752 lpuart_dma_rx_free(&sport->port);
1753 sport->lpuart_dma_rx_use = false;
1754 }
1755
1756 if (sport->lpuart_dma_tx_use) {
1757 if (wait_event_interruptible_timeout(sport->dma_wait,
1758 !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) {
1759 sport->dma_tx_in_progress = false;
1760 dmaengine_terminate_sync(sport->dma_tx_chan);
1761 }
1762 sport->lpuart_dma_tx_use = false;
1763 }
1764
1765 if (sport->dma_tx_chan)
1766 dma_release_channel(sport->dma_tx_chan);
1767 if (sport->dma_rx_chan)
1768 dma_release_channel(sport->dma_rx_chan);
1769}
1770
1771static void lpuart_shutdown(struct uart_port *port)
1772{
1773 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1774 unsigned char temp;
1775 unsigned long flags;
1776
1777 spin_lock_irqsave(&port->lock, flags);
1778
1779 /* disable Rx/Tx and interrupts */
1780 temp = readb(port->membase + UARTCR2);
1781 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1782 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1783 writeb(temp, port->membase + UARTCR2);
1784
1785 spin_unlock_irqrestore(&port->lock, flags);
1786
1787 lpuart_dma_shutdown(sport);
1788}
1789
1790static void lpuart32_shutdown(struct uart_port *port)
1791{
1792 struct lpuart_port *sport =
1793 container_of(port, struct lpuart_port, port);
1794 unsigned long temp;
1795 unsigned long flags;
1796
1797 spin_lock_irqsave(&port->lock, flags);
1798
1799 /* disable Rx/Tx and interrupts */
1800 temp = lpuart32_read(port, UARTCTRL);
1801 temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1802 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1803 lpuart32_write(port, temp, UARTCTRL);
1804
1805 spin_unlock_irqrestore(&port->lock, flags);
1806
1807 lpuart_dma_shutdown(sport);
1808}
1809
1810static void
1811lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1812 const struct ktermios *old)
1813{
1814 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1815 unsigned long flags;
1816 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1817 unsigned int baud;
1818 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1819 unsigned int sbr, brfa;
1820
1821 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1822 old_cr2 = readb(sport->port.membase + UARTCR2);
1823 cr3 = readb(sport->port.membase + UARTCR3);
1824 cr4 = readb(sport->port.membase + UARTCR4);
1825 bdh = readb(sport->port.membase + UARTBDH);
1826 modem = readb(sport->port.membase + UARTMODEM);
1827 /*
1828 * only support CS8 and CS7, and for CS7 must enable PE.
1829 * supported mode:
1830 * - (7,e/o,1)
1831 * - (8,n,1)
1832 * - (8,m/s,1)
1833 * - (8,e/o,1)
1834 */
1835 while ((termios->c_cflag & CSIZE) != CS8 &&
1836 (termios->c_cflag & CSIZE) != CS7) {
1837 termios->c_cflag &= ~CSIZE;
1838 termios->c_cflag |= old_csize;
1839 old_csize = CS8;
1840 }
1841
1842 if ((termios->c_cflag & CSIZE) == CS8 ||
1843 (termios->c_cflag & CSIZE) == CS7)
1844 cr1 = old_cr1 & ~UARTCR1_M;
1845
1846 if (termios->c_cflag & CMSPAR) {
1847 if ((termios->c_cflag & CSIZE) != CS8) {
1848 termios->c_cflag &= ~CSIZE;
1849 termios->c_cflag |= CS8;
1850 }
1851 cr1 |= UARTCR1_M;
1852 }
1853
1854 /*
1855 * When auto RS-485 RTS mode is enabled,
1856 * hardware flow control need to be disabled.
1857 */
1858 if (sport->port.rs485.flags & SER_RS485_ENABLED)
1859 termios->c_cflag &= ~CRTSCTS;
1860
1861 if (termios->c_cflag & CRTSCTS)
1862 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;
1863 else
1864 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1865
1866 termios->c_cflag &= ~CSTOPB;
1867
1868 /* parity must be enabled when CS7 to match 8-bits format */
1869 if ((termios->c_cflag & CSIZE) == CS7)
1870 termios->c_cflag |= PARENB;
1871
1872 if (termios->c_cflag & PARENB) {
1873 if (termios->c_cflag & CMSPAR) {
1874 cr1 &= ~UARTCR1_PE;
1875 if (termios->c_cflag & PARODD)
1876 cr3 |= UARTCR3_T8;
1877 else
1878 cr3 &= ~UARTCR3_T8;
1879 } else {
1880 cr1 |= UARTCR1_PE;
1881 if ((termios->c_cflag & CSIZE) == CS8)
1882 cr1 |= UARTCR1_M;
1883 if (termios->c_cflag & PARODD)
1884 cr1 |= UARTCR1_PT;
1885 else
1886 cr1 &= ~UARTCR1_PT;
1887 }
1888 } else {
1889 cr1 &= ~UARTCR1_PE;
1890 }
1891
1892 /* ask the core to calculate the divisor */
1893 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1894
1895 /*
1896 * Need to update the Ring buffer length according to the selected
1897 * baud rate and restart Rx DMA path.
1898 *
1899 * Since timer function acqures sport->port.lock, need to stop before
1900 * acquring same lock because otherwise del_timer_sync() can deadlock.
1901 */
1902 if (old && sport->lpuart_dma_rx_use) {
1903 del_timer_sync(&sport->lpuart_timer);
1904 lpuart_dma_rx_free(&sport->port);
1905 }
1906
1907 spin_lock_irqsave(&sport->port.lock, flags);
1908
1909 sport->port.read_status_mask = 0;
1910 if (termios->c_iflag & INPCK)
1911 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
1912 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1913 sport->port.read_status_mask |= UARTSR1_FE;
1914
1915 /* characters to ignore */
1916 sport->port.ignore_status_mask = 0;
1917 if (termios->c_iflag & IGNPAR)
1918 sport->port.ignore_status_mask |= UARTSR1_PE;
1919 if (termios->c_iflag & IGNBRK) {
1920 sport->port.ignore_status_mask |= UARTSR1_FE;
1921 /*
1922 * if we're ignoring parity and break indicators,
1923 * ignore overruns too (for real raw support).
1924 */
1925 if (termios->c_iflag & IGNPAR)
1926 sport->port.ignore_status_mask |= UARTSR1_OR;
1927 }
1928
1929 /* update the per-port timeout */
1930 uart_update_timeout(port, termios->c_cflag, baud);
1931
1932 /* wait transmit engin complete */
1933 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
1934
1935 /* disable transmit and receive */
1936 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1937 sport->port.membase + UARTCR2);
1938
1939 sbr = sport->port.uartclk / (16 * baud);
1940 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1941 bdh &= ~UARTBDH_SBR_MASK;
1942 bdh |= (sbr >> 8) & 0x1F;
1943 cr4 &= ~UARTCR4_BRFA_MASK;
1944 brfa &= UARTCR4_BRFA_MASK;
1945 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1946 writeb(bdh, sport->port.membase + UARTBDH);
1947 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1948 writeb(cr3, sport->port.membase + UARTCR3);
1949 writeb(cr1, sport->port.membase + UARTCR1);
1950 writeb(modem, sport->port.membase + UARTMODEM);
1951
1952 /* restore control register */
1953 writeb(old_cr2, sport->port.membase + UARTCR2);
1954
1955 if (old && sport->lpuart_dma_rx_use) {
1956 if (!lpuart_start_rx_dma(sport))
1957 rx_dma_timer_init(sport);
1958 else
1959 sport->lpuart_dma_rx_use = false;
1960 }
1961
1962 spin_unlock_irqrestore(&sport->port.lock, flags);
1963}
1964
1965static void __lpuart32_serial_setbrg(struct uart_port *port,
1966 unsigned int baudrate, bool use_rx_dma,
1967 bool use_tx_dma)
1968{
1969 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
1970 u32 clk = port->uartclk;
1971
1972 /*
1973 * The idea is to use the best OSR (over-sampling rate) possible.
1974 * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
1975 * Loop to find the best OSR value possible, one that generates minimum
1976 * baud_diff iterate through the rest of the supported values of OSR.
1977 *
1978 * Calculation Formula:
1979 * Baud Rate = baud clock / ((OSR+1) × SBR)
1980 */
1981 baud_diff = baudrate;
1982 osr = 0;
1983 sbr = 0;
1984
1985 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
1986 /* calculate the temporary sbr value */
1987 tmp_sbr = (clk / (baudrate * tmp_osr));
1988 if (tmp_sbr == 0)
1989 tmp_sbr = 1;
1990
1991 /*
1992 * calculate the baud rate difference based on the temporary
1993 * osr and sbr values
1994 */
1995 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
1996
1997 /* select best values between sbr and sbr+1 */
1998 tmp = clk / (tmp_osr * (tmp_sbr + 1));
1999 if (tmp_diff > (baudrate - tmp)) {
2000 tmp_diff = baudrate - tmp;
2001 tmp_sbr++;
2002 }
2003
2004 if (tmp_sbr > UARTBAUD_SBR_MASK)
2005 continue;
2006
2007 if (tmp_diff <= baud_diff) {
2008 baud_diff = tmp_diff;
2009 osr = tmp_osr;
2010 sbr = tmp_sbr;
2011
2012 if (!baud_diff)
2013 break;
2014 }
2015 }
2016
2017 /* handle buadrate outside acceptable rate */
2018 if (baud_diff > ((baudrate / 100) * 3))
2019 dev_warn(port->dev,
2020 "unacceptable baud rate difference of more than 3%%\n");
2021
2022 tmp = lpuart32_read(port, UARTBAUD);
2023
2024 if ((osr > 3) && (osr < 8))
2025 tmp |= UARTBAUD_BOTHEDGE;
2026
2027 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
2028 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
2029
2030 tmp &= ~UARTBAUD_SBR_MASK;
2031 tmp |= sbr & UARTBAUD_SBR_MASK;
2032
2033 if (!use_rx_dma)
2034 tmp &= ~UARTBAUD_RDMAE;
2035 if (!use_tx_dma)
2036 tmp &= ~UARTBAUD_TDMAE;
2037
2038 lpuart32_write(port, tmp, UARTBAUD);
2039}
2040
2041static void lpuart32_serial_setbrg(struct lpuart_port *sport,
2042 unsigned int baudrate)
2043{
2044 __lpuart32_serial_setbrg(&sport->port, baudrate,
2045 sport->lpuart_dma_rx_use,
2046 sport->lpuart_dma_tx_use);
2047}
2048
2049
2050static void
2051lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
2052 const struct ktermios *old)
2053{
2054 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
2055 unsigned long flags;
2056 unsigned long ctrl, old_ctrl, bd, modem;
2057 unsigned int baud;
2058 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
2059
2060 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
2061 bd = lpuart32_read(&sport->port, UARTBAUD);
2062 modem = lpuart32_read(&sport->port, UARTMODIR);
2063 sport->is_cs7 = false;
2064 /*
2065 * only support CS8 and CS7, and for CS7 must enable PE.
2066 * supported mode:
2067 * - (7,e/o,1)
2068 * - (8,n,1)
2069 * - (8,m/s,1)
2070 * - (8,e/o,1)
2071 */
2072 while ((termios->c_cflag & CSIZE) != CS8 &&
2073 (termios->c_cflag & CSIZE) != CS7) {
2074 termios->c_cflag &= ~CSIZE;
2075 termios->c_cflag |= old_csize;
2076 old_csize = CS8;
2077 }
2078
2079 if ((termios->c_cflag & CSIZE) == CS8 ||
2080 (termios->c_cflag & CSIZE) == CS7)
2081 ctrl = old_ctrl & ~UARTCTRL_M;
2082
2083 if (termios->c_cflag & CMSPAR) {
2084 if ((termios->c_cflag & CSIZE) != CS8) {
2085 termios->c_cflag &= ~CSIZE;
2086 termios->c_cflag |= CS8;
2087 }
2088 ctrl |= UARTCTRL_M;
2089 }
2090
2091 /*
2092 * When auto RS-485 RTS mode is enabled,
2093 * hardware flow control need to be disabled.
2094 */
2095 if (sport->port.rs485.flags & SER_RS485_ENABLED)
2096 termios->c_cflag &= ~CRTSCTS;
2097
2098 if (termios->c_cflag & CRTSCTS)
2099 modem |= UARTMODIR_RXRTSE | UARTMODIR_TXCTSE;
2100 else
2101 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2102
2103 if (termios->c_cflag & CSTOPB)
2104 bd |= UARTBAUD_SBNS;
2105 else
2106 bd &= ~UARTBAUD_SBNS;
2107
2108 /* parity must be enabled when CS7 to match 8-bits format */
2109 if ((termios->c_cflag & CSIZE) == CS7)
2110 termios->c_cflag |= PARENB;
2111
2112 if ((termios->c_cflag & PARENB)) {
2113 if (termios->c_cflag & CMSPAR) {
2114 ctrl &= ~UARTCTRL_PE;
2115 ctrl |= UARTCTRL_M;
2116 } else {
2117 ctrl |= UARTCTRL_PE;
2118 if ((termios->c_cflag & CSIZE) == CS8)
2119 ctrl |= UARTCTRL_M;
2120 if (termios->c_cflag & PARODD)
2121 ctrl |= UARTCTRL_PT;
2122 else
2123 ctrl &= ~UARTCTRL_PT;
2124 }
2125 } else {
2126 ctrl &= ~UARTCTRL_PE;
2127 }
2128
2129 /* ask the core to calculate the divisor */
2130 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
2131
2132 /*
2133 * Need to update the Ring buffer length according to the selected
2134 * baud rate and restart Rx DMA path.
2135 *
2136 * Since timer function acqures sport->port.lock, need to stop before
2137 * acquring same lock because otherwise del_timer_sync() can deadlock.
2138 */
2139 if (old && sport->lpuart_dma_rx_use) {
2140 del_timer_sync(&sport->lpuart_timer);
2141 lpuart_dma_rx_free(&sport->port);
2142 }
2143
2144 spin_lock_irqsave(&sport->port.lock, flags);
2145
2146 sport->port.read_status_mask = 0;
2147 if (termios->c_iflag & INPCK)
2148 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
2149 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2150 sport->port.read_status_mask |= UARTSTAT_FE;
2151
2152 /* characters to ignore */
2153 sport->port.ignore_status_mask = 0;
2154 if (termios->c_iflag & IGNPAR)
2155 sport->port.ignore_status_mask |= UARTSTAT_PE;
2156 if (termios->c_iflag & IGNBRK) {
2157 sport->port.ignore_status_mask |= UARTSTAT_FE;
2158 /*
2159 * if we're ignoring parity and break indicators,
2160 * ignore overruns too (for real raw support).
2161 */
2162 if (termios->c_iflag & IGNPAR)
2163 sport->port.ignore_status_mask |= UARTSTAT_OR;
2164 }
2165
2166 /* update the per-port timeout */
2167 uart_update_timeout(port, termios->c_cflag, baud);
2168
2169 /* wait transmit engin complete */
2170 lpuart32_write(&sport->port, 0, UARTMODIR);
2171 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2172
2173 /* disable transmit and receive */
2174 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
2175 UARTCTRL);
2176
2177 lpuart32_write(&sport->port, bd, UARTBAUD);
2178 lpuart32_serial_setbrg(sport, baud);
2179 lpuart32_write(&sport->port, modem, UARTMODIR);
2180 lpuart32_write(&sport->port, ctrl, UARTCTRL);
2181 /* restore control register */
2182
2183 if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE)
2184 sport->is_cs7 = true;
2185
2186 if (old && sport->lpuart_dma_rx_use) {
2187 if (!lpuart_start_rx_dma(sport))
2188 rx_dma_timer_init(sport);
2189 else
2190 sport->lpuart_dma_rx_use = false;
2191 }
2192
2193 spin_unlock_irqrestore(&sport->port.lock, flags);
2194}
2195
2196static const char *lpuart_type(struct uart_port *port)
2197{
2198 return "FSL_LPUART";
2199}
2200
2201static void lpuart_release_port(struct uart_port *port)
2202{
2203 /* nothing to do */
2204}
2205
2206static int lpuart_request_port(struct uart_port *port)
2207{
2208 return 0;
2209}
2210
2211/* configure/autoconfigure the port */
2212static void lpuart_config_port(struct uart_port *port, int flags)
2213{
2214 if (flags & UART_CONFIG_TYPE)
2215 port->type = PORT_LPUART;
2216}
2217
2218static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
2219{
2220 int ret = 0;
2221
2222 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
2223 ret = -EINVAL;
2224 if (port->irq != ser->irq)
2225 ret = -EINVAL;
2226 if (ser->io_type != UPIO_MEM)
2227 ret = -EINVAL;
2228 if (port->uartclk / 16 != ser->baud_base)
2229 ret = -EINVAL;
2230 if (port->iobase != ser->port)
2231 ret = -EINVAL;
2232 if (ser->hub6 != 0)
2233 ret = -EINVAL;
2234 return ret;
2235}
2236
2237static const struct uart_ops lpuart_pops = {
2238 .tx_empty = lpuart_tx_empty,
2239 .set_mctrl = lpuart_set_mctrl,
2240 .get_mctrl = lpuart_get_mctrl,
2241 .stop_tx = lpuart_stop_tx,
2242 .start_tx = lpuart_start_tx,
2243 .stop_rx = lpuart_stop_rx,
2244 .break_ctl = lpuart_break_ctl,
2245 .startup = lpuart_startup,
2246 .shutdown = lpuart_shutdown,
2247 .set_termios = lpuart_set_termios,
2248 .pm = lpuart_uart_pm,
2249 .type = lpuart_type,
2250 .request_port = lpuart_request_port,
2251 .release_port = lpuart_release_port,
2252 .config_port = lpuart_config_port,
2253 .verify_port = lpuart_verify_port,
2254 .flush_buffer = lpuart_flush_buffer,
2255#if defined(CONFIG_CONSOLE_POLL)
2256 .poll_init = lpuart_poll_init,
2257 .poll_get_char = lpuart_poll_get_char,
2258 .poll_put_char = lpuart_poll_put_char,
2259#endif
2260};
2261
2262static const struct uart_ops lpuart32_pops = {
2263 .tx_empty = lpuart32_tx_empty,
2264 .set_mctrl = lpuart32_set_mctrl,
2265 .get_mctrl = lpuart32_get_mctrl,
2266 .stop_tx = lpuart32_stop_tx,
2267 .start_tx = lpuart32_start_tx,
2268 .stop_rx = lpuart32_stop_rx,
2269 .break_ctl = lpuart32_break_ctl,
2270 .startup = lpuart32_startup,
2271 .shutdown = lpuart32_shutdown,
2272 .set_termios = lpuart32_set_termios,
2273 .pm = lpuart_uart_pm,
2274 .type = lpuart_type,
2275 .request_port = lpuart_request_port,
2276 .release_port = lpuart_release_port,
2277 .config_port = lpuart_config_port,
2278 .verify_port = lpuart_verify_port,
2279 .flush_buffer = lpuart_flush_buffer,
2280#if defined(CONFIG_CONSOLE_POLL)
2281 .poll_init = lpuart32_poll_init,
2282 .poll_get_char = lpuart32_poll_get_char,
2283 .poll_put_char = lpuart32_poll_put_char,
2284#endif
2285};
2286
2287static struct lpuart_port *lpuart_ports[UART_NR];
2288
2289#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
2290static void lpuart_console_putchar(struct uart_port *port, unsigned char ch)
2291{
2292 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
2293 writeb(ch, port->membase + UARTDR);
2294}
2295
2296static void lpuart32_console_putchar(struct uart_port *port, unsigned char ch)
2297{
2298 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
2299 lpuart32_write(port, ch, UARTDATA);
2300}
2301
2302static void
2303lpuart_console_write(struct console *co, const char *s, unsigned int count)
2304{
2305 struct lpuart_port *sport = lpuart_ports[co->index];
2306 unsigned char old_cr2, cr2;
2307 unsigned long flags;
2308 int locked = 1;
2309
2310 if (oops_in_progress)
2311 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2312 else
2313 spin_lock_irqsave(&sport->port.lock, flags);
2314
2315 /* first save CR2 and then disable interrupts */
2316 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2317 cr2 |= UARTCR2_TE | UARTCR2_RE;
2318 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
2319 writeb(cr2, sport->port.membase + UARTCR2);
2320
2321 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
2322
2323 /* wait for transmitter finish complete and restore CR2 */
2324 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2325
2326 writeb(old_cr2, sport->port.membase + UARTCR2);
2327
2328 if (locked)
2329 spin_unlock_irqrestore(&sport->port.lock, flags);
2330}
2331
2332static void
2333lpuart32_console_write(struct console *co, const char *s, unsigned int count)
2334{
2335 struct lpuart_port *sport = lpuart_ports[co->index];
2336 unsigned long old_cr, cr;
2337 unsigned long flags;
2338 int locked = 1;
2339
2340 if (oops_in_progress)
2341 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2342 else
2343 spin_lock_irqsave(&sport->port.lock, flags);
2344
2345 /* first save CR2 and then disable interrupts */
2346 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2347 cr |= UARTCTRL_TE | UARTCTRL_RE;
2348 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
2349 lpuart32_write(&sport->port, cr, UARTCTRL);
2350
2351 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2352
2353 /* wait for transmitter finish complete and restore CR2 */
2354 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2355
2356 lpuart32_write(&sport->port, old_cr, UARTCTRL);
2357
2358 if (locked)
2359 spin_unlock_irqrestore(&sport->port.lock, flags);
2360}
2361
2362/*
2363 * if the port was already initialised (eg, by a boot loader),
2364 * try to determine the current setup.
2365 */
2366static void __init
2367lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2368 int *parity, int *bits)
2369{
2370 unsigned char cr, bdh, bdl, brfa;
2371 unsigned int sbr, uartclk, baud_raw;
2372
2373 cr = readb(sport->port.membase + UARTCR2);
2374 cr &= UARTCR2_TE | UARTCR2_RE;
2375 if (!cr)
2376 return;
2377
2378 /* ok, the port was enabled */
2379
2380 cr = readb(sport->port.membase + UARTCR1);
2381
2382 *parity = 'n';
2383 if (cr & UARTCR1_PE) {
2384 if (cr & UARTCR1_PT)
2385 *parity = 'o';
2386 else
2387 *parity = 'e';
2388 }
2389
2390 if (cr & UARTCR1_M)
2391 *bits = 9;
2392 else
2393 *bits = 8;
2394
2395 bdh = readb(sport->port.membase + UARTBDH);
2396 bdh &= UARTBDH_SBR_MASK;
2397 bdl = readb(sport->port.membase + UARTBDL);
2398 sbr = bdh;
2399 sbr <<= 8;
2400 sbr |= bdl;
2401 brfa = readb(sport->port.membase + UARTCR4);
2402 brfa &= UARTCR4_BRFA_MASK;
2403
2404 uartclk = lpuart_get_baud_clk_rate(sport);
2405 /*
2406 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2407 */
2408 baud_raw = uartclk / (16 * (sbr + brfa / 32));
2409
2410 if (*baud != baud_raw)
2411 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2412 "from %d to %d\n", baud_raw, *baud);
2413}
2414
2415static void __init
2416lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2417 int *parity, int *bits)
2418{
2419 unsigned long cr, bd;
2420 unsigned int sbr, uartclk, baud_raw;
2421
2422 cr = lpuart32_read(&sport->port, UARTCTRL);
2423 cr &= UARTCTRL_TE | UARTCTRL_RE;
2424 if (!cr)
2425 return;
2426
2427 /* ok, the port was enabled */
2428
2429 cr = lpuart32_read(&sport->port, UARTCTRL);
2430
2431 *parity = 'n';
2432 if (cr & UARTCTRL_PE) {
2433 if (cr & UARTCTRL_PT)
2434 *parity = 'o';
2435 else
2436 *parity = 'e';
2437 }
2438
2439 if (cr & UARTCTRL_M)
2440 *bits = 9;
2441 else
2442 *bits = 8;
2443
2444 bd = lpuart32_read(&sport->port, UARTBAUD);
2445 bd &= UARTBAUD_SBR_MASK;
2446 if (!bd)
2447 return;
2448
2449 sbr = bd;
2450 uartclk = lpuart_get_baud_clk_rate(sport);
2451 /*
2452 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2453 */
2454 baud_raw = uartclk / (16 * sbr);
2455
2456 if (*baud != baud_raw)
2457 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2458 "from %d to %d\n", baud_raw, *baud);
2459}
2460
2461static int __init lpuart_console_setup(struct console *co, char *options)
2462{
2463 struct lpuart_port *sport;
2464 int baud = 115200;
2465 int bits = 8;
2466 int parity = 'n';
2467 int flow = 'n';
2468
2469 /*
2470 * check whether an invalid uart number has been specified, and
2471 * if so, search for the first available port that does have
2472 * console support.
2473 */
2474 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2475 co->index = 0;
2476
2477 sport = lpuart_ports[co->index];
2478 if (sport == NULL)
2479 return -ENODEV;
2480
2481 if (options)
2482 uart_parse_options(options, &baud, &parity, &bits, &flow);
2483 else
2484 if (lpuart_is_32(sport))
2485 lpuart32_console_get_options(sport, &baud, &parity, &bits);
2486 else
2487 lpuart_console_get_options(sport, &baud, &parity, &bits);
2488
2489 if (lpuart_is_32(sport))
2490 lpuart32_setup_watermark(sport);
2491 else
2492 lpuart_setup_watermark(sport);
2493
2494 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2495}
2496
2497static struct uart_driver lpuart_reg;
2498static struct console lpuart_console = {
2499 .name = DEV_NAME,
2500 .write = lpuart_console_write,
2501 .device = uart_console_device,
2502 .setup = lpuart_console_setup,
2503 .flags = CON_PRINTBUFFER,
2504 .index = -1,
2505 .data = &lpuart_reg,
2506};
2507
2508static struct console lpuart32_console = {
2509 .name = DEV_NAME,
2510 .write = lpuart32_console_write,
2511 .device = uart_console_device,
2512 .setup = lpuart_console_setup,
2513 .flags = CON_PRINTBUFFER,
2514 .index = -1,
2515 .data = &lpuart_reg,
2516};
2517
2518static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2519{
2520 struct earlycon_device *dev = con->data;
2521
2522 uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2523}
2524
2525static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2526{
2527 struct earlycon_device *dev = con->data;
2528
2529 uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2530}
2531
2532static int __init lpuart_early_console_setup(struct earlycon_device *device,
2533 const char *opt)
2534{
2535 if (!device->port.membase)
2536 return -ENODEV;
2537
2538 device->con->write = lpuart_early_write;
2539 return 0;
2540}
2541
2542static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2543 const char *opt)
2544{
2545 if (!device->port.membase)
2546 return -ENODEV;
2547
2548 if (device->port.iotype != UPIO_MEM32)
2549 device->port.iotype = UPIO_MEM32BE;
2550
2551 device->con->write = lpuart32_early_write;
2552 return 0;
2553}
2554
2555static int __init ls1028a_early_console_setup(struct earlycon_device *device,
2556 const char *opt)
2557{
2558 u32 cr;
2559
2560 if (!device->port.membase)
2561 return -ENODEV;
2562
2563 device->port.iotype = UPIO_MEM32;
2564 device->con->write = lpuart32_early_write;
2565
2566 /* set the baudrate */
2567 if (device->port.uartclk && device->baud)
2568 __lpuart32_serial_setbrg(&device->port, device->baud,
2569 false, false);
2570
2571 /* enable transmitter */
2572 cr = lpuart32_read(&device->port, UARTCTRL);
2573 cr |= UARTCTRL_TE;
2574 lpuart32_write(&device->port, cr, UARTCTRL);
2575
2576 return 0;
2577}
2578
2579static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2580 const char *opt)
2581{
2582 if (!device->port.membase)
2583 return -ENODEV;
2584
2585 device->port.iotype = UPIO_MEM32;
2586 device->port.membase += IMX_REG_OFF;
2587 device->con->write = lpuart32_early_write;
2588
2589 return 0;
2590}
2591OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2592OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2593OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2594OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2595OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
2596OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup);
2597EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2598EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2599
2600#define LPUART_CONSOLE (&lpuart_console)
2601#define LPUART32_CONSOLE (&lpuart32_console)
2602#else
2603#define LPUART_CONSOLE NULL
2604#define LPUART32_CONSOLE NULL
2605#endif
2606
2607static struct uart_driver lpuart_reg = {
2608 .owner = THIS_MODULE,
2609 .driver_name = DRIVER_NAME,
2610 .dev_name = DEV_NAME,
2611 .nr = ARRAY_SIZE(lpuart_ports),
2612 .cons = LPUART_CONSOLE,
2613};
2614
2615static const struct serial_rs485 lpuart_rs485_supported = {
2616 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
2617 /* delay_rts_* and RX_DURING_TX are not supported */
2618};
2619
2620static int lpuart_global_reset(struct lpuart_port *sport)
2621{
2622 struct uart_port *port = &sport->port;
2623 void __iomem *global_addr;
2624 unsigned long ctrl, bd;
2625 unsigned int val = 0;
2626 int ret;
2627
2628 ret = clk_prepare_enable(sport->ipg_clk);
2629 if (ret) {
2630 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);
2631 return ret;
2632 }
2633
2634 if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
2635 /*
2636 * If the transmitter is used by earlycon, wait for transmit engine to
2637 * complete and then reset.
2638 */
2639 ctrl = lpuart32_read(port, UARTCTRL);
2640 if (ctrl & UARTCTRL_TE) {
2641 bd = lpuart32_read(&sport->port, UARTBAUD);
2642 if (read_poll_timeout(lpuart32_tx_empty, val, val, 1, 100000, false,
2643 port)) {
2644 dev_warn(sport->port.dev,
2645 "timeout waiting for transmit engine to complete\n");
2646 clk_disable_unprepare(sport->ipg_clk);
2647 return 0;
2648 }
2649 }
2650
2651 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
2652 writel(UART_GLOBAL_RST, global_addr);
2653 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
2654 writel(0, global_addr);
2655 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
2656
2657 /* Recover the transmitter for earlycon. */
2658 if (ctrl & UARTCTRL_TE) {
2659 lpuart32_write(port, bd, UARTBAUD);
2660 lpuart32_write(port, ctrl, UARTCTRL);
2661 }
2662 }
2663
2664 clk_disable_unprepare(sport->ipg_clk);
2665 return 0;
2666}
2667
2668static int lpuart_probe(struct platform_device *pdev)
2669{
2670 const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev);
2671 struct device_node *np = pdev->dev.of_node;
2672 struct lpuart_port *sport;
2673 struct resource *res;
2674 irq_handler_t handler;
2675 int ret;
2676
2677 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2678 if (!sport)
2679 return -ENOMEM;
2680
2681 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2682 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2683 if (IS_ERR(sport->port.membase))
2684 return PTR_ERR(sport->port.membase);
2685
2686 sport->port.membase += sdata->reg_off;
2687 sport->port.mapbase = res->start + sdata->reg_off;
2688 sport->port.dev = &pdev->dev;
2689 sport->port.type = PORT_LPUART;
2690 sport->devtype = sdata->devtype;
2691 ret = platform_get_irq(pdev, 0);
2692 if (ret < 0)
2693 return ret;
2694 sport->port.irq = ret;
2695 sport->port.iotype = sdata->iotype;
2696 if (lpuart_is_32(sport))
2697 sport->port.ops = &lpuart32_pops;
2698 else
2699 sport->port.ops = &lpuart_pops;
2700 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
2701 sport->port.flags = UPF_BOOT_AUTOCONF;
2702
2703 if (lpuart_is_32(sport))
2704 sport->port.rs485_config = lpuart32_config_rs485;
2705 else
2706 sport->port.rs485_config = lpuart_config_rs485;
2707 sport->port.rs485_supported = lpuart_rs485_supported;
2708
2709 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2710 if (IS_ERR(sport->ipg_clk)) {
2711 ret = PTR_ERR(sport->ipg_clk);
2712 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
2713 return ret;
2714 }
2715
2716 sport->baud_clk = NULL;
2717 if (is_imx8qxp_lpuart(sport)) {
2718 sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
2719 if (IS_ERR(sport->baud_clk)) {
2720 ret = PTR_ERR(sport->baud_clk);
2721 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
2722 return ret;
2723 }
2724 }
2725
2726 ret = of_alias_get_id(np, "serial");
2727 if (ret < 0) {
2728 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2729 return ret;
2730 }
2731 if (ret >= ARRAY_SIZE(lpuart_ports)) {
2732 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2733 return -EINVAL;
2734 }
2735 sport->port.line = ret;
2736
2737 ret = lpuart_enable_clks(sport);
2738 if (ret)
2739 return ret;
2740 sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2741
2742 lpuart_ports[sport->port.line] = sport;
2743
2744 platform_set_drvdata(pdev, &sport->port);
2745
2746 if (lpuart_is_32(sport)) {
2747 lpuart_reg.cons = LPUART32_CONSOLE;
2748 handler = lpuart32_int;
2749 } else {
2750 lpuart_reg.cons = LPUART_CONSOLE;
2751 handler = lpuart_int;
2752 }
2753
2754 pm_runtime_use_autosuspend(&pdev->dev);
2755 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
2756 pm_runtime_set_active(&pdev->dev);
2757 pm_runtime_enable(&pdev->dev);
2758
2759 ret = lpuart_global_reset(sport);
2760 if (ret)
2761 goto failed_reset;
2762
2763 ret = uart_get_rs485_mode(&sport->port);
2764 if (ret)
2765 goto failed_get_rs485;
2766
2767 ret = uart_add_one_port(&lpuart_reg, &sport->port);
2768 if (ret)
2769 goto failed_attach_port;
2770
2771 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0,
2772 DRIVER_NAME, sport);
2773 if (ret)
2774 goto failed_irq_request;
2775
2776 return 0;
2777
2778failed_irq_request:
2779 uart_remove_one_port(&lpuart_reg, &sport->port);
2780failed_attach_port:
2781failed_get_rs485:
2782failed_reset:
2783 pm_runtime_disable(&pdev->dev);
2784 pm_runtime_set_suspended(&pdev->dev);
2785 pm_runtime_dont_use_autosuspend(&pdev->dev);
2786 lpuart_disable_clks(sport);
2787 return ret;
2788}
2789
2790static int lpuart_remove(struct platform_device *pdev)
2791{
2792 struct lpuart_port *sport = platform_get_drvdata(pdev);
2793
2794 uart_remove_one_port(&lpuart_reg, &sport->port);
2795
2796 lpuart_disable_clks(sport);
2797
2798 if (sport->dma_tx_chan)
2799 dma_release_channel(sport->dma_tx_chan);
2800
2801 if (sport->dma_rx_chan)
2802 dma_release_channel(sport->dma_rx_chan);
2803
2804 pm_runtime_disable(&pdev->dev);
2805 pm_runtime_set_suspended(&pdev->dev);
2806 pm_runtime_dont_use_autosuspend(&pdev->dev);
2807 return 0;
2808}
2809
2810static int lpuart_runtime_suspend(struct device *dev)
2811{
2812 struct platform_device *pdev = to_platform_device(dev);
2813 struct lpuart_port *sport = platform_get_drvdata(pdev);
2814
2815 lpuart_disable_clks(sport);
2816
2817 return 0;
2818};
2819
2820static int lpuart_runtime_resume(struct device *dev)
2821{
2822 struct platform_device *pdev = to_platform_device(dev);
2823 struct lpuart_port *sport = platform_get_drvdata(pdev);
2824
2825 return lpuart_enable_clks(sport);
2826};
2827
2828static void serial_lpuart_enable_wakeup(struct lpuart_port *sport, bool on)
2829{
2830 unsigned int val, baud;
2831
2832 if (lpuart_is_32(sport)) {
2833 val = lpuart32_read(&sport->port, UARTCTRL);
2834 baud = lpuart32_read(&sport->port, UARTBAUD);
2835 if (on) {
2836 /* set rx_watermark to 0 in wakeup source mode */
2837 lpuart32_write(&sport->port, 0, UARTWATER);
2838 val |= UARTCTRL_RIE;
2839 /* clear RXEDGIF flag before enable RXEDGIE interrupt */
2840 lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT);
2841 baud |= UARTBAUD_RXEDGIE;
2842 } else {
2843 val &= ~UARTCTRL_RIE;
2844 baud &= ~UARTBAUD_RXEDGIE;
2845 }
2846 lpuart32_write(&sport->port, val, UARTCTRL);
2847 lpuart32_write(&sport->port, baud, UARTBAUD);
2848 } else {
2849 val = readb(sport->port.membase + UARTCR2);
2850 if (on)
2851 val |= UARTCR2_RIE;
2852 else
2853 val &= ~UARTCR2_RIE;
2854 writeb(val, sport->port.membase + UARTCR2);
2855 }
2856}
2857
2858static bool lpuart_uport_is_active(struct lpuart_port *sport)
2859{
2860 struct tty_port *port = &sport->port.state->port;
2861 struct tty_struct *tty;
2862 struct device *tty_dev;
2863 int may_wake = 0;
2864
2865 tty = tty_port_tty_get(port);
2866 if (tty) {
2867 tty_dev = tty->dev;
2868 may_wake = device_may_wakeup(tty_dev);
2869 tty_kref_put(tty);
2870 }
2871
2872 if ((tty_port_initialized(port) && may_wake) ||
2873 (!console_suspend_enabled && uart_console(&sport->port)))
2874 return true;
2875
2876 return false;
2877}
2878
2879static int lpuart_suspend_noirq(struct device *dev)
2880{
2881 struct lpuart_port *sport = dev_get_drvdata(dev);
2882 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2883
2884 if (lpuart_uport_is_active(sport))
2885 serial_lpuart_enable_wakeup(sport, !!irq_wake);
2886
2887 pinctrl_pm_select_sleep_state(dev);
2888
2889 return 0;
2890}
2891
2892static int lpuart_resume_noirq(struct device *dev)
2893{
2894 struct lpuart_port *sport = dev_get_drvdata(dev);
2895 unsigned int val;
2896
2897 pinctrl_pm_select_default_state(dev);
2898
2899 if (lpuart_uport_is_active(sport)) {
2900 serial_lpuart_enable_wakeup(sport, false);
2901
2902 /* clear the wakeup flags */
2903 if (lpuart_is_32(sport)) {
2904 val = lpuart32_read(&sport->port, UARTSTAT);
2905 lpuart32_write(&sport->port, val, UARTSTAT);
2906 }
2907 }
2908
2909 return 0;
2910}
2911
2912static int lpuart_suspend(struct device *dev)
2913{
2914 struct lpuart_port *sport = dev_get_drvdata(dev);
2915 unsigned long temp, flags;
2916
2917 uart_suspend_port(&lpuart_reg, &sport->port);
2918
2919 if (lpuart_uport_is_active(sport)) {
2920 spin_lock_irqsave(&sport->port.lock, flags);
2921 if (lpuart_is_32(sport)) {
2922 /* disable Rx/Tx and interrupts */
2923 temp = lpuart32_read(&sport->port, UARTCTRL);
2924 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
2925 lpuart32_write(&sport->port, temp, UARTCTRL);
2926 } else {
2927 /* disable Rx/Tx and interrupts */
2928 temp = readb(sport->port.membase + UARTCR2);
2929 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2930 writeb(temp, sport->port.membase + UARTCR2);
2931 }
2932 spin_unlock_irqrestore(&sport->port.lock, flags);
2933
2934 if (sport->lpuart_dma_rx_use) {
2935 /*
2936 * EDMA driver during suspend will forcefully release any
2937 * non-idle DMA channels. If port wakeup is enabled or if port
2938 * is console port or 'no_console_suspend' is set the Rx DMA
2939 * cannot resume as expected, hence gracefully release the
2940 * Rx DMA path before suspend and start Rx DMA path on resume.
2941 */
2942 del_timer_sync(&sport->lpuart_timer);
2943 lpuart_dma_rx_free(&sport->port);
2944
2945 /* Disable Rx DMA to use UART port as wakeup source */
2946 spin_lock_irqsave(&sport->port.lock, flags);
2947 if (lpuart_is_32(sport)) {
2948 temp = lpuart32_read(&sport->port, UARTBAUD);
2949 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
2950 UARTBAUD);
2951 } else {
2952 writeb(readb(sport->port.membase + UARTCR5) &
2953 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
2954 }
2955 spin_unlock_irqrestore(&sport->port.lock, flags);
2956 }
2957
2958 if (sport->lpuart_dma_tx_use) {
2959 spin_lock_irqsave(&sport->port.lock, flags);
2960 if (lpuart_is_32(sport)) {
2961 temp = lpuart32_read(&sport->port, UARTBAUD);
2962 temp &= ~UARTBAUD_TDMAE;
2963 lpuart32_write(&sport->port, temp, UARTBAUD);
2964 } else {
2965 temp = readb(sport->port.membase + UARTCR5);
2966 temp &= ~UARTCR5_TDMAS;
2967 writeb(temp, sport->port.membase + UARTCR5);
2968 }
2969 spin_unlock_irqrestore(&sport->port.lock, flags);
2970 sport->dma_tx_in_progress = false;
2971 dmaengine_terminate_sync(sport->dma_tx_chan);
2972 }
2973 } else if (pm_runtime_active(sport->port.dev)) {
2974 lpuart_disable_clks(sport);
2975 pm_runtime_disable(sport->port.dev);
2976 pm_runtime_set_suspended(sport->port.dev);
2977 }
2978
2979 return 0;
2980}
2981
2982static void lpuart_console_fixup(struct lpuart_port *sport)
2983{
2984 struct tty_port *port = &sport->port.state->port;
2985 struct uart_port *uport = &sport->port;
2986 struct ktermios termios;
2987
2988 /* i.MX7ULP enter VLLS mode that lpuart module power off and registers
2989 * all lost no matter the port is wakeup source.
2990 * For console port, console baud rate setting lost and print messy
2991 * log when enable the console port as wakeup source. To avoid the
2992 * issue happen, user should not enable uart port as wakeup source
2993 * in VLLS mode, or restore console setting here.
2994 */
2995 if (is_imx7ulp_lpuart(sport) && lpuart_uport_is_active(sport) &&
2996 console_suspend_enabled && uart_console(&sport->port)) {
2997
2998 mutex_lock(&port->mutex);
2999 memset(&termios, 0, sizeof(struct ktermios));
3000 termios.c_cflag = uport->cons->cflag;
3001 if (port->tty && termios.c_cflag == 0)
3002 termios = port->tty->termios;
3003 uport->ops->set_termios(uport, &termios, NULL);
3004 mutex_unlock(&port->mutex);
3005 }
3006}
3007
3008static int lpuart_resume(struct device *dev)
3009{
3010 struct lpuart_port *sport = dev_get_drvdata(dev);
3011 int ret;
3012
3013 if (lpuart_uport_is_active(sport)) {
3014 if (lpuart_is_32(sport))
3015 lpuart32_hw_setup(sport);
3016 else
3017 lpuart_hw_setup(sport);
3018 } else if (pm_runtime_active(sport->port.dev)) {
3019 ret = lpuart_enable_clks(sport);
3020 if (ret)
3021 return ret;
3022 pm_runtime_set_active(sport->port.dev);
3023 pm_runtime_enable(sport->port.dev);
3024 }
3025
3026 lpuart_console_fixup(sport);
3027 uart_resume_port(&lpuart_reg, &sport->port);
3028
3029 return 0;
3030}
3031
3032static const struct dev_pm_ops lpuart_pm_ops = {
3033 RUNTIME_PM_OPS(lpuart_runtime_suspend,
3034 lpuart_runtime_resume, NULL)
3035 NOIRQ_SYSTEM_SLEEP_PM_OPS(lpuart_suspend_noirq,
3036 lpuart_resume_noirq)
3037 SYSTEM_SLEEP_PM_OPS(lpuart_suspend, lpuart_resume)
3038};
3039
3040static struct platform_driver lpuart_driver = {
3041 .probe = lpuart_probe,
3042 .remove = lpuart_remove,
3043 .driver = {
3044 .name = "fsl-lpuart",
3045 .of_match_table = lpuart_dt_ids,
3046 .pm = pm_ptr(&lpuart_pm_ops),
3047 },
3048};
3049
3050static int __init lpuart_serial_init(void)
3051{
3052 int ret = uart_register_driver(&lpuart_reg);
3053
3054 if (ret)
3055 return ret;
3056
3057 ret = platform_driver_register(&lpuart_driver);
3058 if (ret)
3059 uart_unregister_driver(&lpuart_reg);
3060
3061 return ret;
3062}
3063
3064static void __exit lpuart_serial_exit(void)
3065{
3066 platform_driver_unregister(&lpuart_driver);
3067 uart_unregister_driver(&lpuart_reg);
3068}
3069
3070module_init(lpuart_serial_init);
3071module_exit(lpuart_serial_exit);
3072
3073MODULE_DESCRIPTION("Freescale lpuart serial port driver");
3074MODULE_LICENSE("GPL v2");