1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * Synopsys DesignWare 8250 driver.
  4 *
  5 * Copyright 2011 Picochip, Jamie Iles.
  6 * Copyright 2013 Intel Corporation
  7 *
  8 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
  9 * LCR is written whilst busy.  If it is, then a busy detect interrupt is
 10 * raised, the LCR needs to be rewritten and the uart status register read.
 11 */
 12#include <linux/acpi.h>
 13#include <linux/clk.h>
 14#include <linux/delay.h>
 15#include <linux/device.h>
 16#include <linux/io.h>
 17#include <linux/mod_devicetable.h>
 18#include <linux/module.h>
 19#include <linux/notifier.h>
 20#include <linux/of.h>
 21#include <linux/platform_device.h>
 22#include <linux/pm_runtime.h>
 23#include <linux/property.h>
 24#include <linux/reset.h>
 25#include <linux/slab.h>
 26#include <linux/workqueue.h>
 27
 28#include <asm/byteorder.h>
 29
 30#include <linux/serial_8250.h>
 31#include <linux/serial_reg.h>
 32
 33#include "8250_dwlib.h"
 34
 35/* Offsets for the DesignWare specific registers */
 36#define DW_UART_USR	0x1f /* UART Status Register */
 37#define DW_UART_DMASA	0xa8 /* DMA Software Ack */
 38
 39#define OCTEON_UART_USR	0x27 /* UART Status Register */
 40
 41#define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
 42#define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
 43
 44/* DesignWare specific register fields */
 45#define DW_UART_MCR_SIRE		BIT(6)
 46
 47/* Renesas specific register fields */
 48#define RZN1_UART_xDMACR_DMA_EN		BIT(0)
 49#define RZN1_UART_xDMACR_1_WORD_BURST	(0 << 1)
 50#define RZN1_UART_xDMACR_4_WORD_BURST	(1 << 1)
 51#define RZN1_UART_xDMACR_8_WORD_BURST	(2 << 1)
 52#define RZN1_UART_xDMACR_BLK_SZ(x)	((x) << 3)
 53
 54/* Quirks */
 55#define DW_UART_QUIRK_OCTEON		BIT(0)
 56#define DW_UART_QUIRK_ARMADA_38X	BIT(1)
 57#define DW_UART_QUIRK_SKIP_SET_RATE	BIT(2)
 58#define DW_UART_QUIRK_IS_DMA_FC		BIT(3)
 59
 60static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
 61{
 62	return container_of(nb, struct dw8250_data, clk_notifier);
 63}
 64
 65static inline struct dw8250_data *work_to_dw8250_data(struct work_struct *work)
 66{
 67	return container_of(work, struct dw8250_data, clk_work);
 68}
 69
 70static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
 71{
 72	struct dw8250_data *d = to_dw8250_data(p->private_data);
 73
 74	/* Override any modem control signals if needed */
 75	if (offset == UART_MSR) {
 76		value |= d->msr_mask_on;
 77		value &= ~d->msr_mask_off;
 78	}
 79
 80	return value;
 81}
 82
 83static void dw8250_force_idle(struct uart_port *p)
 84{
 85	struct uart_8250_port *up = up_to_u8250p(p);
 86	unsigned int lsr;
 87
 88	serial8250_clear_and_reinit_fifos(up);
 89
 90	/*
 91	 * With PSLVERR_RESP_EN parameter set to 1, the device generates an
 92	 * error response when an attempt to read an empty RBR with FIFO
 93	 * enabled.
 94	 */
 95	if (up->fcr & UART_FCR_ENABLE_FIFO) {
 96		lsr = p->serial_in(p, UART_LSR);
 97		if (!(lsr & UART_LSR_DR))
 98			return;
 99	}
100
101	(void)p->serial_in(p, UART_RX);
102}
103
104static void dw8250_check_lcr(struct uart_port *p, int value)
105{
106	void __iomem *offset = p->membase + (UART_LCR << p->regshift);
107	int tries = 1000;
108
109	/* Make sure LCR write wasn't ignored */
110	while (tries--) {
111		unsigned int lcr = p->serial_in(p, UART_LCR);
112
113		if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
114			return;
115
116		dw8250_force_idle(p);
117
118#ifdef CONFIG_64BIT
119		if (p->type == PORT_OCTEON)
120			__raw_writeq(value & 0xff, offset);
121		else
122#endif
123		if (p->iotype == UPIO_MEM32)
124			writel(value, offset);
125		else if (p->iotype == UPIO_MEM32BE)
126			iowrite32be(value, offset);
127		else
128			writeb(value, offset);
129	}
130	/*
131	 * FIXME: this deadlocks if port->lock is already held
132	 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
133	 */
134}
135
136/* Returns once the transmitter is empty or we run out of retries */
137static void dw8250_tx_wait_empty(struct uart_port *p)
138{
139	struct uart_8250_port *up = up_to_u8250p(p);
140	unsigned int tries = 20000;
141	unsigned int delay_threshold = tries - 1000;
142	unsigned int lsr;
143
144	while (tries--) {
145		lsr = readb (p->membase + (UART_LSR << p->regshift));
146		up->lsr_saved_flags |= lsr & up->lsr_save_mask;
147
148		if (lsr & UART_LSR_TEMT)
149			break;
150
151		/* The device is first given a chance to empty without delay,
152		 * to avoid slowdowns at high bitrates. If after 1000 tries
153		 * the buffer has still not emptied, allow more time for low-
154		 * speed links. */
155		if (tries < delay_threshold)
156			udelay (1);
157	}
158}
159
160static void dw8250_serial_out(struct uart_port *p, int offset, int value)
161{
162	struct dw8250_data *d = to_dw8250_data(p->private_data);
163
164	writeb(value, p->membase + (offset << p->regshift));
165
166	if (offset == UART_LCR && !d->uart_16550_compatible)
167		dw8250_check_lcr(p, value);
168}
169
170static void dw8250_serial_out38x(struct uart_port *p, int offset, int value)
171{
172	/* Allow the TX to drain before we reconfigure */
173	if (offset == UART_LCR)
174		dw8250_tx_wait_empty(p);
175
176	dw8250_serial_out(p, offset, value);
177}
178
179static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
180{
181	unsigned int value = readb(p->membase + (offset << p->regshift));
182
183	return dw8250_modify_msr(p, offset, value);
184}
185
186#ifdef CONFIG_64BIT
187static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
188{
189	unsigned int value;
190
191	value = (u8)__raw_readq(p->membase + (offset << p->regshift));
192
193	return dw8250_modify_msr(p, offset, value);
194}
195
196static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
197{
198	struct dw8250_data *d = to_dw8250_data(p->private_data);
199
200	value &= 0xff;
201	__raw_writeq(value, p->membase + (offset << p->regshift));
202	/* Read back to ensure register write ordering. */
203	__raw_readq(p->membase + (UART_LCR << p->regshift));
204
205	if (offset == UART_LCR && !d->uart_16550_compatible)
206		dw8250_check_lcr(p, value);
207}
208#endif /* CONFIG_64BIT */
209
210static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
211{
212	struct dw8250_data *d = to_dw8250_data(p->private_data);
213
214	writel(value, p->membase + (offset << p->regshift));
215
216	if (offset == UART_LCR && !d->uart_16550_compatible)
217		dw8250_check_lcr(p, value);
218}
219
220static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
221{
222	unsigned int value = readl(p->membase + (offset << p->regshift));
223
224	return dw8250_modify_msr(p, offset, value);
225}
226
227static void dw8250_serial_out32be(struct uart_port *p, int offset, int value)
228{
229	struct dw8250_data *d = to_dw8250_data(p->private_data);
230
231	iowrite32be(value, p->membase + (offset << p->regshift));
232
233	if (offset == UART_LCR && !d->uart_16550_compatible)
234		dw8250_check_lcr(p, value);
235}
236
237static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset)
238{
239       unsigned int value = ioread32be(p->membase + (offset << p->regshift));
240
241       return dw8250_modify_msr(p, offset, value);
242}
243
244
245static int dw8250_handle_irq(struct uart_port *p)
246{
247	struct uart_8250_port *up = up_to_u8250p(p);
248	struct dw8250_data *d = to_dw8250_data(p->private_data);
249	unsigned int iir = p->serial_in(p, UART_IIR);
250	bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;
251	unsigned int quirks = d->pdata->quirks;
252	unsigned int status;
253	unsigned long flags;
254
255	/*
256	 * There are ways to get Designware-based UARTs into a state where
257	 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual
258	 * data available.  If we see such a case then we'll do a bogus
259	 * read.  If we don't do this then the "RX TIMEOUT" interrupt will
260	 * fire forever.
261	 *
262	 * This problem has only been observed so far when not in DMA mode
263	 * so we limit the workaround only to non-DMA mode.
264	 */
265	if (!up->dma && rx_timeout) {
266		uart_port_lock_irqsave(p, &flags);
267		status = serial_lsr_in(up);
268
269		if (!(status & (UART_LSR_DR | UART_LSR_BI)))
270			(void) p->serial_in(p, UART_RX);
271
272		uart_port_unlock_irqrestore(p, flags);
273	}
274
275	/* Manually stop the Rx DMA transfer when acting as flow controller */
276	if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) {
277		uart_port_lock_irqsave(p, &flags);
278		status = serial_lsr_in(up);
279		uart_port_unlock_irqrestore(p, flags);
280
281		if (status & (UART_LSR_DR | UART_LSR_BI)) {
282			dw8250_writel_ext(p, RZN1_UART_RDMACR, 0);
283			dw8250_writel_ext(p, DW_UART_DMASA, 1);
284		}
285	}
286
287	if (serial8250_handle_irq(p, iir))
288		return 1;
289
290	if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
291		/* Clear the USR */
292		(void)p->serial_in(p, d->pdata->usr_reg);
293
294		return 1;
295	}
296
297	return 0;
298}
299
300static void dw8250_clk_work_cb(struct work_struct *work)
301{
302	struct dw8250_data *d = work_to_dw8250_data(work);
303	struct uart_8250_port *up;
304	unsigned long rate;
305
306	rate = clk_get_rate(d->clk);
307	if (rate <= 0)
308		return;
309
310	up = serial8250_get_port(d->data.line);
311
312	serial8250_update_uartclk(&up->port, rate);
313}
314
315static int dw8250_clk_notifier_cb(struct notifier_block *nb,
316				  unsigned long event, void *data)
317{
318	struct dw8250_data *d = clk_to_dw8250_data(nb);
319
320	/*
321	 * We have no choice but to defer the uartclk update due to two
322	 * deadlocks. First one is caused by a recursive mutex lock which
323	 * happens when clk_set_rate() is called from dw8250_set_termios().
324	 * Second deadlock is more tricky and is caused by an inverted order of
325	 * the clk and tty-port mutexes lock. It happens if clock rate change
326	 * is requested asynchronously while set_termios() is executed between
327	 * tty-port mutex lock and clk_set_rate() function invocation and
328	 * vise-versa. Anyway if we didn't have the reference clock alteration
329	 * in the dw8250_set_termios() method we wouldn't have needed this
330	 * deferred event handling complication.
331	 */
332	if (event == POST_RATE_CHANGE) {
333		queue_work(system_unbound_wq, &d->clk_work);
334		return NOTIFY_OK;
335	}
336
337	return NOTIFY_DONE;
338}
339
340static void
341dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
342{
343	if (!state)
344		pm_runtime_get_sync(port->dev);
345
346	serial8250_do_pm(port, state, old);
347
348	if (state)
349		pm_runtime_put_sync_suspend(port->dev);
350}
351
352static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
353			       const struct ktermios *old)
354{
355	unsigned long newrate = tty_termios_baud_rate(termios) * 16;
356	struct dw8250_data *d = to_dw8250_data(p->private_data);
357	long rate;
358	int ret;
359
 
360	rate = clk_round_rate(d->clk, newrate);
361	if (rate > 0 && p->uartclk != rate) {
362		clk_disable_unprepare(d->clk);
363		/*
364		 * Note that any clock-notifer worker will block in
365		 * serial8250_update_uartclk() until we are done.
366		 */
367		ret = clk_set_rate(d->clk, newrate);
368		if (!ret)
369			p->uartclk = rate;
370		clk_prepare_enable(d->clk);
371	}
 
372
373	dw8250_do_set_termios(p, termios, old);
374}
375
376static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios)
377{
378	struct uart_8250_port *up = up_to_u8250p(p);
379	unsigned int mcr = p->serial_in(p, UART_MCR);
380
381	if (up->capabilities & UART_CAP_IRDA) {
382		if (termios->c_line == N_IRDA)
383			mcr |= DW_UART_MCR_SIRE;
384		else
385			mcr &= ~DW_UART_MCR_SIRE;
386
387		p->serial_out(p, UART_MCR, mcr);
388	}
389	serial8250_do_set_ldisc(p, termios);
390}
391
392/*
393 * dw8250_fallback_dma_filter will prevent the UART from getting just any free
394 * channel on platforms that have DMA engines, but don't have any channels
395 * assigned to the UART.
396 *
397 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the
398 * core problem is fixed, this function is no longer needed.
399 */
400static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
401{
402	return false;
403}
404
405static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
406{
407	return param == chan->device->dev;
408}
409
410static u32 dw8250_rzn1_get_dmacr_burst(int max_burst)
411{
412	if (max_burst >= 8)
413		return RZN1_UART_xDMACR_8_WORD_BURST;
414	else if (max_burst >= 4)
415		return RZN1_UART_xDMACR_4_WORD_BURST;
416	else
417		return RZN1_UART_xDMACR_1_WORD_BURST;
418}
419
420static void dw8250_prepare_tx_dma(struct uart_8250_port *p)
421{
422	struct uart_port *up = &p->port;
423	struct uart_8250_dma *dma = p->dma;
424	u32 val;
425
426	dw8250_writel_ext(up, RZN1_UART_TDMACR, 0);
427	val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) |
428	      RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) |
429	      RZN1_UART_xDMACR_DMA_EN;
430	dw8250_writel_ext(up, RZN1_UART_TDMACR, val);
431}
432
433static void dw8250_prepare_rx_dma(struct uart_8250_port *p)
434{
435	struct uart_port *up = &p->port;
436	struct uart_8250_dma *dma = p->dma;
437	u32 val;
438
439	dw8250_writel_ext(up, RZN1_UART_RDMACR, 0);
440	val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) |
441	      RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) |
442	      RZN1_UART_xDMACR_DMA_EN;
443	dw8250_writel_ext(up, RZN1_UART_RDMACR, val);
444}
445
446static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
447{
448	struct device_node *np = p->dev->of_node;
449
450	if (np) {
451		unsigned int quirks = data->pdata->quirks;
452		int id;
453
454		/* get index of serial line, if found in DT aliases */
455		id = of_alias_get_id(np, "serial");
456		if (id >= 0)
457			p->line = id;
458#ifdef CONFIG_64BIT
459		if (quirks & DW_UART_QUIRK_OCTEON) {
460			p->serial_in = dw8250_serial_inq;
461			p->serial_out = dw8250_serial_outq;
462			p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
463			p->type = PORT_OCTEON;
464			data->skip_autocfg = true;
465		}
466#endif
467
468		if (of_device_is_big_endian(np)) {
469			p->iotype = UPIO_MEM32BE;
470			p->serial_in = dw8250_serial_in32be;
471			p->serial_out = dw8250_serial_out32be;
472		}
473
474		if (quirks & DW_UART_QUIRK_ARMADA_38X)
475			p->serial_out = dw8250_serial_out38x;
476		if (quirks & DW_UART_QUIRK_SKIP_SET_RATE)
477			p->set_termios = dw8250_do_set_termios;
478		if (quirks & DW_UART_QUIRK_IS_DMA_FC) {
479			data->data.dma.txconf.device_fc = 1;
480			data->data.dma.rxconf.device_fc = 1;
481			data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma;
482			data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma;
483		}
484
485	} else if (acpi_dev_present("APMC0D08", NULL, -1)) {
486		p->iotype = UPIO_MEM32;
487		p->regshift = 2;
488		p->serial_in = dw8250_serial_in32;
489		data->uart_16550_compatible = true;
490	}
491
492	/* Platforms with iDMA 64-bit */
493	if (platform_get_resource_byname(to_platform_device(p->dev),
494					 IORESOURCE_MEM, "lpss_priv")) {
495		data->data.dma.rx_param = p->dev->parent;
496		data->data.dma.tx_param = p->dev->parent;
497		data->data.dma.fn = dw8250_idma_filter;
498	}
499}
500
 
 
 
 
 
501static void dw8250_reset_control_assert(void *data)
502{
503	reset_control_assert(data);
504}
505
506static int dw8250_probe(struct platform_device *pdev)
507{
508	struct uart_8250_port uart = {}, *up = &uart;
509	struct uart_port *p = &up->port;
510	struct device *dev = &pdev->dev;
511	struct dw8250_data *data;
512	struct resource *regs;
513	int irq;
514	int err;
515	u32 val;
516
517	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
518	if (!regs)
519		return dev_err_probe(dev, -EINVAL, "no registers defined\n");
520
521	irq = platform_get_irq_optional(pdev, 0);
522	/* no interrupt -> fall back to polling */
523	if (irq == -ENXIO)
524		irq = 0;
525	if (irq < 0)
526		return irq;
527
528	spin_lock_init(&p->lock);
529	p->mapbase	= regs->start;
530	p->irq		= irq;
531	p->handle_irq	= dw8250_handle_irq;
532	p->pm		= dw8250_do_pm;
533	p->type		= PORT_8250;
534	p->flags	= UPF_SHARE_IRQ | UPF_FIXED_PORT;
535	p->dev		= dev;
536	p->iotype	= UPIO_MEM;
537	p->serial_in	= dw8250_serial_in;
538	p->serial_out	= dw8250_serial_out;
539	p->set_ldisc	= dw8250_set_ldisc;
540	p->set_termios	= dw8250_set_termios;
541
542	p->membase = devm_ioremap(dev, regs->start, resource_size(regs));
543	if (!p->membase)
544		return -ENOMEM;
545
546	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
547	if (!data)
548		return -ENOMEM;
549
550	data->data.dma.fn = dw8250_fallback_dma_filter;
551	data->pdata = device_get_match_data(p->dev);
552	p->private_data = &data->data;
553
554	data->uart_16550_compatible = device_property_read_bool(dev,
555						"snps,uart-16550-compatible");
556
557	err = device_property_read_u32(dev, "reg-shift", &val);
558	if (!err)
559		p->regshift = val;
560
561	err = device_property_read_u32(dev, "reg-io-width", &val);
562	if (!err && val == 4) {
563		p->iotype = UPIO_MEM32;
564		p->serial_in = dw8250_serial_in32;
565		p->serial_out = dw8250_serial_out32;
566	}
567
568	if (device_property_read_bool(dev, "dcd-override")) {
569		/* Always report DCD as active */
570		data->msr_mask_on |= UART_MSR_DCD;
571		data->msr_mask_off |= UART_MSR_DDCD;
572	}
573
574	if (device_property_read_bool(dev, "dsr-override")) {
575		/* Always report DSR as active */
576		data->msr_mask_on |= UART_MSR_DSR;
577		data->msr_mask_off |= UART_MSR_DDSR;
578	}
579
580	if (device_property_read_bool(dev, "cts-override")) {
581		/* Always report CTS as active */
582		data->msr_mask_on |= UART_MSR_CTS;
583		data->msr_mask_off |= UART_MSR_DCTS;
584	}
585
586	if (device_property_read_bool(dev, "ri-override")) {
587		/* Always report Ring indicator as inactive */
588		data->msr_mask_off |= UART_MSR_RI;
589		data->msr_mask_off |= UART_MSR_TERI;
590	}
591
592	/* Always ask for fixed clock rate from a property. */
593	device_property_read_u32(dev, "clock-frequency", &p->uartclk);
594
595	/* If there is separate baudclk, get the rate from it. */
596	data->clk = devm_clk_get_optional_enabled(dev, "baudclk");
597	if (data->clk == NULL)
598		data->clk = devm_clk_get_optional_enabled(dev, NULL);
599	if (IS_ERR(data->clk))
600		return PTR_ERR(data->clk);
601
602	INIT_WORK(&data->clk_work, dw8250_clk_work_cb);
603	data->clk_notifier.notifier_call = dw8250_clk_notifier_cb;
604
 
 
 
 
 
 
 
 
605	if (data->clk)
606		p->uartclk = clk_get_rate(data->clk);
607
608	/* If no clock rate is defined, fail. */
609	if (!p->uartclk)
610		return dev_err_probe(dev, -EINVAL, "clock rate not defined\n");
611
612	data->pclk = devm_clk_get_optional_enabled(dev, "apb_pclk");
613	if (IS_ERR(data->pclk))
614		return PTR_ERR(data->pclk);
615
 
 
 
 
 
 
 
 
616	data->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
617	if (IS_ERR(data->rst))
618		return PTR_ERR(data->rst);
619
620	reset_control_deassert(data->rst);
621
622	err = devm_add_action_or_reset(dev, dw8250_reset_control_assert, data->rst);
623	if (err)
624		return err;
625
626	dw8250_quirks(p, data);
627
628	/* If the Busy Functionality is not implemented, don't handle it */
629	if (data->uart_16550_compatible)
630		p->handle_irq = NULL;
631
632	if (!data->skip_autocfg)
633		dw8250_setup_port(p);
634
635	/* If we have a valid fifosize, try hooking up DMA */
636	if (p->fifosize) {
637		data->data.dma.rxconf.src_maxburst = p->fifosize / 4;
638		data->data.dma.txconf.dst_maxburst = p->fifosize / 4;
639		up->dma = &data->data.dma;
640	}
641
642	data->data.line = serial8250_register_8250_port(up);
643	if (data->data.line < 0)
644		return data->data.line;
645
646	/*
647	 * Some platforms may provide a reference clock shared between several
648	 * devices. In this case any clock state change must be known to the
649	 * UART port at least post factum.
650	 */
651	if (data->clk) {
652		err = clk_notifier_register(data->clk, &data->clk_notifier);
653		if (err)
654			return dev_err_probe(dev, err, "Failed to set the clock notifier\n");
655		queue_work(system_unbound_wq, &data->clk_work);
656	}
657
658	platform_set_drvdata(pdev, data);
659
660	pm_runtime_set_active(dev);
661	pm_runtime_enable(dev);
662
663	return 0;
664}
665
666static void dw8250_remove(struct platform_device *pdev)
667{
668	struct dw8250_data *data = platform_get_drvdata(pdev);
669	struct device *dev = &pdev->dev;
670
671	pm_runtime_get_sync(dev);
672
673	if (data->clk) {
674		clk_notifier_unregister(data->clk, &data->clk_notifier);
675
676		flush_work(&data->clk_work);
677	}
678
679	serial8250_unregister_port(data->data.line);
680
681	pm_runtime_disable(dev);
682	pm_runtime_put_noidle(dev);
 
 
683}
684
685static int dw8250_suspend(struct device *dev)
686{
687	struct dw8250_data *data = dev_get_drvdata(dev);
688
689	serial8250_suspend_port(data->data.line);
690
691	return 0;
692}
693
694static int dw8250_resume(struct device *dev)
695{
696	struct dw8250_data *data = dev_get_drvdata(dev);
697
698	serial8250_resume_port(data->data.line);
699
700	return 0;
701}
702
703static int dw8250_runtime_suspend(struct device *dev)
704{
705	struct dw8250_data *data = dev_get_drvdata(dev);
706
707	clk_disable_unprepare(data->clk);
708
709	clk_disable_unprepare(data->pclk);
710
711	return 0;
712}
713
714static int dw8250_runtime_resume(struct device *dev)
715{
716	struct dw8250_data *data = dev_get_drvdata(dev);
717
718	clk_prepare_enable(data->pclk);
719
720	clk_prepare_enable(data->clk);
721
722	return 0;
723}
724
725static const struct dev_pm_ops dw8250_pm_ops = {
726	SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
727	RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
728};
729
730static const struct dw8250_platform_data dw8250_dw_apb = {
731	.usr_reg = DW_UART_USR,
732};
733
734static const struct dw8250_platform_data dw8250_octeon_3860_data = {
735	.usr_reg = OCTEON_UART_USR,
736	.quirks = DW_UART_QUIRK_OCTEON,
737};
738
739static const struct dw8250_platform_data dw8250_armada_38x_data = {
740	.usr_reg = DW_UART_USR,
741	.quirks = DW_UART_QUIRK_ARMADA_38X,
742};
743
744static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
745	.usr_reg = DW_UART_USR,
746	.cpr_val = 0x00012f32,
747	.quirks = DW_UART_QUIRK_IS_DMA_FC,
748};
749
750static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
751	.usr_reg = DW_UART_USR,
752	.quirks = DW_UART_QUIRK_SKIP_SET_RATE,
753};
754
755static const struct of_device_id dw8250_of_match[] = {
756	{ .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
757	{ .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
758	{ .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
759	{ .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
760	{ .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
761	{ /* Sentinel */ }
762};
763MODULE_DEVICE_TABLE(of, dw8250_of_match);
764
765static const struct acpi_device_id dw8250_acpi_match[] = {
766	{ "80860F0A", (kernel_ulong_t)&dw8250_dw_apb },
767	{ "8086228A", (kernel_ulong_t)&dw8250_dw_apb },
768	{ "AMD0020", (kernel_ulong_t)&dw8250_dw_apb },
769	{ "AMDI0020", (kernel_ulong_t)&dw8250_dw_apb },
770	{ "AMDI0022", (kernel_ulong_t)&dw8250_dw_apb },
771	{ "APMC0D08", (kernel_ulong_t)&dw8250_dw_apb},
772	{ "BRCM2032", (kernel_ulong_t)&dw8250_dw_apb },
773	{ "HISI0031", (kernel_ulong_t)&dw8250_dw_apb },
774	{ "INT33C4", (kernel_ulong_t)&dw8250_dw_apb },
775	{ "INT33C5", (kernel_ulong_t)&dw8250_dw_apb },
776	{ "INT3434", (kernel_ulong_t)&dw8250_dw_apb },
777	{ "INT3435", (kernel_ulong_t)&dw8250_dw_apb },
778	{ "INTC10EE", (kernel_ulong_t)&dw8250_dw_apb },
779	{ },
780};
781MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
782
783static struct platform_driver dw8250_platform_driver = {
784	.driver = {
785		.name		= "dw-apb-uart",
786		.pm		= pm_ptr(&dw8250_pm_ops),
787		.of_match_table	= dw8250_of_match,
788		.acpi_match_table = dw8250_acpi_match,
789	},
790	.probe			= dw8250_probe,
791	.remove_new		= dw8250_remove,
792};
793
794module_platform_driver(dw8250_platform_driver);
795
796MODULE_AUTHOR("Jamie Iles");
797MODULE_LICENSE("GPL");
798MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
799MODULE_ALIAS("platform:dw-apb-uart");