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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Serial port driver for BCM2835AUX UART
4 *
5 * Copyright (C) 2016 Martin Sperl <kernel@martin.sperl.org>
6 *
7 * Based on 8250_lpc18xx.c:
8 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
9 *
10 * The bcm2835aux is capable of RTS auto flow-control, but this driver doesn't
11 * take advantage of it yet. When adding support, be sure not to enable it
12 * simultaneously to rs485.
13 */
14
15#include <linux/clk.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/property.h>
21
22#include "8250.h"
23
24#define BCM2835_AUX_UART_CNTL 8
25#define BCM2835_AUX_UART_CNTL_RXEN 0x01 /* Receiver enable */
26#define BCM2835_AUX_UART_CNTL_TXEN 0x02 /* Transmitter enable */
27#define BCM2835_AUX_UART_CNTL_AUTORTS 0x04 /* RTS set by RX fill level */
28#define BCM2835_AUX_UART_CNTL_AUTOCTS 0x08 /* CTS stops transmitter */
29#define BCM2835_AUX_UART_CNTL_RTS3 0x00 /* RTS set until 3 chars left */
30#define BCM2835_AUX_UART_CNTL_RTS2 0x10 /* RTS set until 2 chars left */
31#define BCM2835_AUX_UART_CNTL_RTS1 0x20 /* RTS set until 1 chars left */
32#define BCM2835_AUX_UART_CNTL_RTS4 0x30 /* RTS set until 4 chars left */
33#define BCM2835_AUX_UART_CNTL_RTSINV 0x40 /* Invert auto RTS polarity */
34#define BCM2835_AUX_UART_CNTL_CTSINV 0x80 /* Invert auto CTS polarity */
35
36/**
37 * struct bcm2835aux_data - driver private data of BCM2835 auxiliary UART
38 * @clk: clock producer of the port's uartclk
39 * @line: index of the port's serial8250_ports[] entry
40 * @cntl: cached copy of CNTL register
41 */
42struct bcm2835aux_data {
43 struct clk *clk;
44 int line;
45 u32 cntl;
46};
47
48struct bcm2835_aux_serial_driver_data {
49 resource_size_t offset;
50};
51
52static void bcm2835aux_rs485_start_tx(struct uart_8250_port *up)
53{
54 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
55 struct bcm2835aux_data *data = dev_get_drvdata(up->port.dev);
56
57 data->cntl &= ~BCM2835_AUX_UART_CNTL_RXEN;
58 serial_out(up, BCM2835_AUX_UART_CNTL, data->cntl);
59 }
60
61 /*
62 * On the bcm2835aux, the MCR register contains no other
63 * flags besides RTS. So no need for a read-modify-write.
64 */
65 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
66 serial8250_out_MCR(up, 0);
67 else
68 serial8250_out_MCR(up, UART_MCR_RTS);
69}
70
71static void bcm2835aux_rs485_stop_tx(struct uart_8250_port *up)
72{
73 if (up->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
74 serial8250_out_MCR(up, 0);
75 else
76 serial8250_out_MCR(up, UART_MCR_RTS);
77
78 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
79 struct bcm2835aux_data *data = dev_get_drvdata(up->port.dev);
80
81 data->cntl |= BCM2835_AUX_UART_CNTL_RXEN;
82 serial_out(up, BCM2835_AUX_UART_CNTL, data->cntl);
83 }
84}
85
86static int bcm2835aux_serial_probe(struct platform_device *pdev)
87{
88 const struct bcm2835_aux_serial_driver_data *bcm_data;
89 struct uart_8250_port up = { };
90 struct bcm2835aux_data *data;
91 resource_size_t offset = 0;
92 struct resource *res;
93 unsigned int uartclk;
94 int ret;
95
96 /* allocate the custom structure */
97 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
98 if (!data)
99 return -ENOMEM;
100
101 /* initialize data */
102 up.capabilities = UART_CAP_FIFO | UART_CAP_MINI;
103 up.port.dev = &pdev->dev;
104 up.port.regshift = 2;
105 up.port.type = PORT_16550;
106 up.port.iotype = UPIO_MEM;
107 up.port.fifosize = 8;
108 up.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT | UPF_FIXED_TYPE |
109 UPF_SKIP_TEST | UPF_IOREMAP;
110 up.port.rs485_config = serial8250_em485_config;
111 up.port.rs485_supported = serial8250_em485_supported;
112 up.rs485_start_tx = bcm2835aux_rs485_start_tx;
113 up.rs485_stop_tx = bcm2835aux_rs485_stop_tx;
114
115 /* initialize cached copy with power-on reset value */
116 data->cntl = BCM2835_AUX_UART_CNTL_RXEN | BCM2835_AUX_UART_CNTL_TXEN;
117
118 platform_set_drvdata(pdev, data);
119
120 /* get the clock - this also enables the HW */
121 data->clk = devm_clk_get_optional(&pdev->dev, NULL);
122 if (IS_ERR(data->clk))
123 return dev_err_probe(&pdev->dev, PTR_ERR(data->clk), "could not get clk\n");
124
125 /* get the interrupt */
126 ret = platform_get_irq(pdev, 0);
127 if (ret < 0)
128 return ret;
129 up.port.irq = ret;
130
131 /* map the main registers */
132 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
133 if (!res) {
134 dev_err(&pdev->dev, "memory resource not found");
135 return -EINVAL;
136 }
137
138 bcm_data = device_get_match_data(&pdev->dev);
139
140 /* Some UEFI implementations (e.g. tianocore/edk2 for the Raspberry Pi)
141 * describe the miniuart with a base address that encompasses the auxiliary
142 * registers shared between the miniuart and spi.
143 *
144 * This is due to historical reasons, see discussion here :
145 * https://edk2.groups.io/g/devel/topic/87501357#84349
146 *
147 * We need to add the offset between the miniuart and auxiliary
148 * registers to get the real miniuart base address.
149 */
150 if (bcm_data)
151 offset = bcm_data->offset;
152
153 up.port.mapbase = res->start + offset;
154 up.port.mapsize = resource_size(res) - offset;
155
156 /* Check for a fixed line number */
157 ret = of_alias_get_id(pdev->dev.of_node, "serial");
158 if (ret >= 0)
159 up.port.line = ret;
160
161 /* enable the clock as a last step */
162 ret = clk_prepare_enable(data->clk);
163 if (ret) {
164 dev_err(&pdev->dev, "unable to enable uart clock - %d\n",
165 ret);
166 return ret;
167 }
168
169 uartclk = clk_get_rate(data->clk);
170 if (!uartclk) {
171 ret = device_property_read_u32(&pdev->dev, "clock-frequency", &uartclk);
172 if (ret) {
173 dev_err_probe(&pdev->dev, ret, "could not get clk rate\n");
174 goto dis_clk;
175 }
176 }
177
178 /* the HW-clock divider for bcm2835aux is 8,
179 * but 8250 expects a divider of 16,
180 * so we have to multiply the actual clock by 2
181 * to get identical baudrates.
182 */
183 up.port.uartclk = uartclk * 2;
184
185 /* register the port */
186 ret = serial8250_register_8250_port(&up);
187 if (ret < 0) {
188 dev_err_probe(&pdev->dev, ret, "unable to register 8250 port\n");
189 goto dis_clk;
190 }
191 data->line = ret;
192
193 return 0;
194
195dis_clk:
196 clk_disable_unprepare(data->clk);
197 return ret;
198}
199
200static void bcm2835aux_serial_remove(struct platform_device *pdev)
201{
202 struct bcm2835aux_data *data = platform_get_drvdata(pdev);
203
204 serial8250_unregister_port(data->line);
205 clk_disable_unprepare(data->clk);
206}
207
208static const struct bcm2835_aux_serial_driver_data bcm2835_acpi_data = {
209 .offset = 0x40,
210};
211
212static const struct of_device_id bcm2835aux_serial_match[] = {
213 { .compatible = "brcm,bcm2835-aux-uart" },
214 { },
215};
216MODULE_DEVICE_TABLE(of, bcm2835aux_serial_match);
217
218static const struct acpi_device_id bcm2835aux_serial_acpi_match[] = {
219 { "BCM2836", (kernel_ulong_t)&bcm2835_acpi_data },
220 { }
221};
222MODULE_DEVICE_TABLE(acpi, bcm2835aux_serial_acpi_match);
223
224static struct platform_driver bcm2835aux_serial_driver = {
225 .driver = {
226 .name = "bcm2835-aux-uart",
227 .of_match_table = bcm2835aux_serial_match,
228 .acpi_match_table = bcm2835aux_serial_acpi_match,
229 },
230 .probe = bcm2835aux_serial_probe,
231 .remove_new = bcm2835aux_serial_remove,
232};
233module_platform_driver(bcm2835aux_serial_driver);
234
235#ifdef CONFIG_SERIAL_8250_CONSOLE
236
237static int __init early_bcm2835aux_setup(struct earlycon_device *device,
238 const char *options)
239{
240 if (!device->port.membase)
241 return -ENODEV;
242
243 device->port.iotype = UPIO_MEM32;
244 device->port.regshift = 2;
245
246 return early_serial8250_setup(device, NULL);
247}
248
249OF_EARLYCON_DECLARE(bcm2835aux, "brcm,bcm2835-aux-uart",
250 early_bcm2835aux_setup);
251#endif
252
253MODULE_DESCRIPTION("BCM2835 auxiliar UART driver");
254MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>");
255MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Serial port driver for BCM2835AUX UART
4 *
5 * Copyright (C) 2016 Martin Sperl <kernel@martin.sperl.org>
6 *
7 * Based on 8250_lpc18xx.c:
8 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
9 *
10 * The bcm2835aux is capable of RTS auto flow-control, but this driver doesn't
11 * take advantage of it yet. When adding support, be sure not to enable it
12 * simultaneously to rs485.
13 */
14
15#include <linux/clk.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/property.h>
21
22#include "8250.h"
23
24#define BCM2835_AUX_UART_CNTL 8
25#define BCM2835_AUX_UART_CNTL_RXEN 0x01 /* Receiver enable */
26#define BCM2835_AUX_UART_CNTL_TXEN 0x02 /* Transmitter enable */
27#define BCM2835_AUX_UART_CNTL_AUTORTS 0x04 /* RTS set by RX fill level */
28#define BCM2835_AUX_UART_CNTL_AUTOCTS 0x08 /* CTS stops transmitter */
29#define BCM2835_AUX_UART_CNTL_RTS3 0x00 /* RTS set until 3 chars left */
30#define BCM2835_AUX_UART_CNTL_RTS2 0x10 /* RTS set until 2 chars left */
31#define BCM2835_AUX_UART_CNTL_RTS1 0x20 /* RTS set until 1 chars left */
32#define BCM2835_AUX_UART_CNTL_RTS4 0x30 /* RTS set until 4 chars left */
33#define BCM2835_AUX_UART_CNTL_RTSINV 0x40 /* Invert auto RTS polarity */
34#define BCM2835_AUX_UART_CNTL_CTSINV 0x80 /* Invert auto CTS polarity */
35
36/**
37 * struct bcm2835aux_data - driver private data of BCM2835 auxiliary UART
38 * @clk: clock producer of the port's uartclk
39 * @line: index of the port's serial8250_ports[] entry
40 * @cntl: cached copy of CNTL register
41 */
42struct bcm2835aux_data {
43 struct clk *clk;
44 int line;
45 u32 cntl;
46};
47
48struct bcm2835_aux_serial_driver_data {
49 resource_size_t offset;
50};
51
52static void bcm2835aux_rs485_start_tx(struct uart_8250_port *up)
53{
54 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
55 struct bcm2835aux_data *data = dev_get_drvdata(up->port.dev);
56
57 data->cntl &= ~BCM2835_AUX_UART_CNTL_RXEN;
58 serial_out(up, BCM2835_AUX_UART_CNTL, data->cntl);
59 }
60
61 /*
62 * On the bcm2835aux, the MCR register contains no other
63 * flags besides RTS. So no need for a read-modify-write.
64 */
65 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
66 serial8250_out_MCR(up, 0);
67 else
68 serial8250_out_MCR(up, UART_MCR_RTS);
69}
70
71static void bcm2835aux_rs485_stop_tx(struct uart_8250_port *up)
72{
73 if (up->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
74 serial8250_out_MCR(up, 0);
75 else
76 serial8250_out_MCR(up, UART_MCR_RTS);
77
78 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
79 struct bcm2835aux_data *data = dev_get_drvdata(up->port.dev);
80
81 data->cntl |= BCM2835_AUX_UART_CNTL_RXEN;
82 serial_out(up, BCM2835_AUX_UART_CNTL, data->cntl);
83 }
84}
85
86static int bcm2835aux_serial_probe(struct platform_device *pdev)
87{
88 const struct bcm2835_aux_serial_driver_data *bcm_data;
89 struct uart_8250_port up = { };
90 struct bcm2835aux_data *data;
91 resource_size_t offset = 0;
92 struct resource *res;
93 unsigned int uartclk;
94 int ret;
95
96 /* allocate the custom structure */
97 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
98 if (!data)
99 return -ENOMEM;
100
101 /* initialize data */
102 up.capabilities = UART_CAP_FIFO | UART_CAP_MINI;
103 up.port.dev = &pdev->dev;
104 up.port.regshift = 2;
105 up.port.type = PORT_16550;
106 up.port.iotype = UPIO_MEM;
107 up.port.fifosize = 8;
108 up.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT | UPF_FIXED_TYPE |
109 UPF_SKIP_TEST | UPF_IOREMAP;
110 up.port.rs485_config = serial8250_em485_config;
111 up.port.rs485_supported = serial8250_em485_supported;
112 up.rs485_start_tx = bcm2835aux_rs485_start_tx;
113 up.rs485_stop_tx = bcm2835aux_rs485_stop_tx;
114
115 /* initialize cached copy with power-on reset value */
116 data->cntl = BCM2835_AUX_UART_CNTL_RXEN | BCM2835_AUX_UART_CNTL_TXEN;
117
118 platform_set_drvdata(pdev, data);
119
120 /* get the clock - this also enables the HW */
121 data->clk = devm_clk_get_optional(&pdev->dev, NULL);
122
123 /* get the interrupt */
124 ret = platform_get_irq(pdev, 0);
125 if (ret < 0)
126 return ret;
127 up.port.irq = ret;
128
129 /* map the main registers */
130 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
131 if (!res) {
132 dev_err(&pdev->dev, "memory resource not found");
133 return -EINVAL;
134 }
135
136 bcm_data = device_get_match_data(&pdev->dev);
137
138 /* Some UEFI implementations (e.g. tianocore/edk2 for the Raspberry Pi)
139 * describe the miniuart with a base address that encompasses the auxiliary
140 * registers shared between the miniuart and spi.
141 *
142 * This is due to historical reasons, see discussion here :
143 * https://edk2.groups.io/g/devel/topic/87501357#84349
144 *
145 * We need to add the offset between the miniuart and auxiliary
146 * registers to get the real miniuart base address.
147 */
148 if (bcm_data)
149 offset = bcm_data->offset;
150
151 up.port.mapbase = res->start + offset;
152 up.port.mapsize = resource_size(res) - offset;
153
154 /* Check for a fixed line number */
155 ret = of_alias_get_id(pdev->dev.of_node, "serial");
156 if (ret >= 0)
157 up.port.line = ret;
158
159 /* enable the clock as a last step */
160 ret = clk_prepare_enable(data->clk);
161 if (ret) {
162 dev_err(&pdev->dev, "unable to enable uart clock - %d\n",
163 ret);
164 return ret;
165 }
166
167 uartclk = clk_get_rate(data->clk);
168 if (!uartclk) {
169 ret = device_property_read_u32(&pdev->dev, "clock-frequency", &uartclk);
170 if (ret) {
171 dev_err_probe(&pdev->dev, ret, "could not get clk rate\n");
172 goto dis_clk;
173 }
174 }
175
176 /* the HW-clock divider for bcm2835aux is 8,
177 * but 8250 expects a divider of 16,
178 * so we have to multiply the actual clock by 2
179 * to get identical baudrates.
180 */
181 up.port.uartclk = uartclk * 2;
182
183 /* register the port */
184 ret = serial8250_register_8250_port(&up);
185 if (ret < 0) {
186 dev_err_probe(&pdev->dev, ret, "unable to register 8250 port\n");
187 goto dis_clk;
188 }
189 data->line = ret;
190
191 return 0;
192
193dis_clk:
194 clk_disable_unprepare(data->clk);
195 return ret;
196}
197
198static int bcm2835aux_serial_remove(struct platform_device *pdev)
199{
200 struct bcm2835aux_data *data = platform_get_drvdata(pdev);
201
202 serial8250_unregister_port(data->line);
203 clk_disable_unprepare(data->clk);
204
205 return 0;
206}
207
208static const struct bcm2835_aux_serial_driver_data bcm2835_acpi_data = {
209 .offset = 0x40,
210};
211
212static const struct of_device_id bcm2835aux_serial_match[] = {
213 { .compatible = "brcm,bcm2835-aux-uart" },
214 { },
215};
216MODULE_DEVICE_TABLE(of, bcm2835aux_serial_match);
217
218static const struct acpi_device_id bcm2835aux_serial_acpi_match[] = {
219 { "BCM2836", (kernel_ulong_t)&bcm2835_acpi_data },
220 { }
221};
222MODULE_DEVICE_TABLE(acpi, bcm2835aux_serial_acpi_match);
223
224static struct platform_driver bcm2835aux_serial_driver = {
225 .driver = {
226 .name = "bcm2835-aux-uart",
227 .of_match_table = bcm2835aux_serial_match,
228 .acpi_match_table = bcm2835aux_serial_acpi_match,
229 },
230 .probe = bcm2835aux_serial_probe,
231 .remove = bcm2835aux_serial_remove,
232};
233module_platform_driver(bcm2835aux_serial_driver);
234
235#ifdef CONFIG_SERIAL_8250_CONSOLE
236
237static int __init early_bcm2835aux_setup(struct earlycon_device *device,
238 const char *options)
239{
240 if (!device->port.membase)
241 return -ENODEV;
242
243 device->port.iotype = UPIO_MEM32;
244 device->port.regshift = 2;
245
246 return early_serial8250_setup(device, NULL);
247}
248
249OF_EARLYCON_DECLARE(bcm2835aux, "brcm,bcm2835-aux-uart",
250 early_bcm2835aux_setup);
251#endif
252
253MODULE_DESCRIPTION("BCM2835 auxiliar UART driver");
254MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>");
255MODULE_LICENSE("GPL v2");