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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * An RTC driver for Allwinner A31/A23
4 *
5 * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org>
6 *
7 * based on rtc-sunxi.c
8 *
9 * An RTC driver for Allwinner A10/A20
10 *
11 * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
12 */
13
14#include <linux/clk.h>
15#include <linux/clk-provider.h>
16#include <linux/clk/sunxi-ng.h>
17#include <linux/delay.h>
18#include <linux/err.h>
19#include <linux/fs.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/of_address.h>
27#include <linux/platform_device.h>
28#include <linux/rtc.h>
29#include <linux/slab.h>
30#include <linux/types.h>
31
32/* Control register */
33#define SUN6I_LOSC_CTRL 0x0000
34#define SUN6I_LOSC_CTRL_KEY (0x16aa << 16)
35#define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15)
36#define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9)
37#define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8)
38#define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7)
39#define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4)
40#define SUN6I_LOSC_CTRL_EXT_OSC BIT(0)
41#define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7)
42
43#define SUN6I_LOSC_CLK_PRESCAL 0x0008
44
45/* RTC */
46#define SUN6I_RTC_YMD 0x0010
47#define SUN6I_RTC_HMS 0x0014
48
49/* Alarm 0 (counter) */
50#define SUN6I_ALRM_COUNTER 0x0020
51/* This holds the remaining alarm seconds on older SoCs (current value) */
52#define SUN6I_ALRM_COUNTER_HMS 0x0024
53#define SUN6I_ALRM_EN 0x0028
54#define SUN6I_ALRM_EN_CNT_EN BIT(0)
55#define SUN6I_ALRM_IRQ_EN 0x002c
56#define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0)
57#define SUN6I_ALRM_IRQ_STA 0x0030
58#define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0)
59
60/* Alarm 1 (wall clock) */
61#define SUN6I_ALRM1_EN 0x0044
62#define SUN6I_ALRM1_IRQ_EN 0x0048
63#define SUN6I_ALRM1_IRQ_STA 0x004c
64#define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0)
65
66/* Alarm config */
67#define SUN6I_ALARM_CONFIG 0x0050
68#define SUN6I_ALARM_CONFIG_WAKEUP BIT(0)
69
70#define SUN6I_LOSC_OUT_GATING 0x0060
71#define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0
72
73/* General-purpose data */
74#define SUN6I_GP_DATA 0x0100
75#define SUN6I_GP_DATA_SIZE 0x20
76
77/*
78 * Get date values
79 */
80#define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f)
81#define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8)
82#define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16)
83#define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22)
84
85/*
86 * Get time values
87 */
88#define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f)
89#define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8)
90#define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16)
91
92/*
93 * Set date values
94 */
95#define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f)
96#define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00)
97#define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000)
98#define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000)
99
100/*
101 * Set time values
102 */
103#define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f)
104#define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00)
105#define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000)
106
107/*
108 * The year parameter passed to the driver is usually an offset relative to
109 * the year 1900. This macro is used to convert this offset to another one
110 * relative to the minimum year allowed by the hardware.
111 *
112 * The year range is 1970 - 2033. This range is selected to match Allwinner's
113 * driver, even though it is somewhat limited.
114 */
115#define SUN6I_YEAR_MIN 1970
116#define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900)
117
118#define SECS_PER_DAY (24 * 3600ULL)
119
120/*
121 * There are other differences between models, including:
122 *
123 * - number of GPIO pins that can be configured to hold a certain level
124 * - crypto-key related registers (H5, H6)
125 * - boot process related (super standby, secondary processor entry address)
126 * registers (R40, H6)
127 * - SYS power domain controls (R40)
128 * - DCXO controls (H6)
129 * - RC oscillator calibration (H6)
130 *
131 * These functions are not covered by this driver.
132 */
133struct sun6i_rtc_clk_data {
134 unsigned long rc_osc_rate;
135 unsigned int fixed_prescaler : 16;
136 unsigned int has_prescaler : 1;
137 unsigned int has_out_clk : 1;
138 unsigned int has_losc_en : 1;
139 unsigned int has_auto_swt : 1;
140};
141
142#define RTC_LINEAR_DAY BIT(0)
143
144struct sun6i_rtc_dev {
145 struct rtc_device *rtc;
146 const struct sun6i_rtc_clk_data *data;
147 void __iomem *base;
148 int irq;
149 time64_t alarm;
150 unsigned long flags;
151
152 struct clk_hw hw;
153 struct clk_hw *int_osc;
154 struct clk *losc;
155 struct clk *ext_losc;
156
157 spinlock_t lock;
158};
159
160static struct sun6i_rtc_dev *sun6i_rtc;
161
162static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw,
163 unsigned long parent_rate)
164{
165 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
166 u32 val = 0;
167
168 val = readl(rtc->base + SUN6I_LOSC_CTRL);
169 if (val & SUN6I_LOSC_CTRL_EXT_OSC)
170 return parent_rate;
171
172 if (rtc->data->fixed_prescaler)
173 parent_rate /= rtc->data->fixed_prescaler;
174
175 if (rtc->data->has_prescaler) {
176 val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL);
177 val &= GENMASK(4, 0);
178 }
179
180 return parent_rate / (val + 1);
181}
182
183static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw)
184{
185 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
186
187 return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC;
188}
189
190static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index)
191{
192 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
193 unsigned long flags;
194 u32 val;
195
196 if (index > 1)
197 return -EINVAL;
198
199 spin_lock_irqsave(&rtc->lock, flags);
200 val = readl(rtc->base + SUN6I_LOSC_CTRL);
201 val &= ~SUN6I_LOSC_CTRL_EXT_OSC;
202 val |= SUN6I_LOSC_CTRL_KEY;
203 val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0;
204 if (rtc->data->has_losc_en) {
205 val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN;
206 val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0;
207 }
208 writel(val, rtc->base + SUN6I_LOSC_CTRL);
209 spin_unlock_irqrestore(&rtc->lock, flags);
210
211 return 0;
212}
213
214static const struct clk_ops sun6i_rtc_osc_ops = {
215 .recalc_rate = sun6i_rtc_osc_recalc_rate,
216 .determine_rate = clk_hw_determine_rate_no_reparent,
217
218 .get_parent = sun6i_rtc_osc_get_parent,
219 .set_parent = sun6i_rtc_osc_set_parent,
220};
221
222static void __init sun6i_rtc_clk_init(struct device_node *node,
223 const struct sun6i_rtc_clk_data *data)
224{
225 struct clk_hw_onecell_data *clk_data;
226 struct sun6i_rtc_dev *rtc;
227 struct clk_init_data init = {
228 .ops = &sun6i_rtc_osc_ops,
229 .name = "losc",
230 };
231 const char *iosc_name = "rtc-int-osc";
232 const char *clkout_name = "osc32k-out";
233 const char *parents[2];
234 u32 reg;
235
236 rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
237 if (!rtc)
238 return;
239
240 rtc->data = data;
241 clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL);
242 if (!clk_data) {
243 kfree(rtc);
244 return;
245 }
246
247 spin_lock_init(&rtc->lock);
248
249 rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node));
250 if (IS_ERR(rtc->base)) {
251 pr_crit("Can't map RTC registers");
252 goto err;
253 }
254
255 reg = SUN6I_LOSC_CTRL_KEY;
256 if (rtc->data->has_auto_swt) {
257 /* Bypass auto-switch to int osc, on ext losc failure */
258 reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS;
259 writel(reg, rtc->base + SUN6I_LOSC_CTRL);
260 }
261
262 /* Switch to the external, more precise, oscillator, if present */
263 if (of_property_present(node, "clocks")) {
264 reg |= SUN6I_LOSC_CTRL_EXT_OSC;
265 if (rtc->data->has_losc_en)
266 reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN;
267 }
268 writel(reg, rtc->base + SUN6I_LOSC_CTRL);
269
270 /* Yes, I know, this is ugly. */
271 sun6i_rtc = rtc;
272
273 of_property_read_string_index(node, "clock-output-names", 2,
274 &iosc_name);
275
276 rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL,
277 iosc_name,
278 NULL, 0,
279 rtc->data->rc_osc_rate,
280 300000000);
281 if (IS_ERR(rtc->int_osc)) {
282 pr_crit("Couldn't register the internal oscillator\n");
283 goto err;
284 }
285
286 parents[0] = clk_hw_get_name(rtc->int_osc);
287 /* If there is no external oscillator, this will be NULL and ... */
288 parents[1] = of_clk_get_parent_name(node, 0);
289
290 rtc->hw.init = &init;
291
292 init.parent_names = parents;
293 /* ... number of clock parents will be 1. */
294 init.num_parents = of_clk_get_parent_count(node) + 1;
295 of_property_read_string_index(node, "clock-output-names", 0,
296 &init.name);
297
298 rtc->losc = clk_register(NULL, &rtc->hw);
299 if (IS_ERR(rtc->losc)) {
300 pr_crit("Couldn't register the LOSC clock\n");
301 goto err_register;
302 }
303
304 of_property_read_string_index(node, "clock-output-names", 1,
305 &clkout_name);
306 rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name,
307 0, rtc->base + SUN6I_LOSC_OUT_GATING,
308 SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,
309 &rtc->lock);
310 if (IS_ERR(rtc->ext_losc)) {
311 pr_crit("Couldn't register the LOSC external gate\n");
312 goto err_register;
313 }
314
315 clk_data->num = 3;
316 clk_data->hws[0] = &rtc->hw;
317 clk_data->hws[1] = __clk_get_hw(rtc->ext_losc);
318 clk_data->hws[2] = rtc->int_osc;
319 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
320 return;
321
322err_register:
323 clk_hw_unregister_fixed_rate(rtc->int_osc);
324err:
325 kfree(clk_data);
326}
327
328static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = {
329 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
330 .has_prescaler = 1,
331};
332
333static void __init sun6i_a31_rtc_clk_init(struct device_node *node)
334{
335 sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data);
336}
337CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc",
338 sun6i_a31_rtc_clk_init);
339
340static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = {
341 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
342 .has_prescaler = 1,
343 .has_out_clk = 1,
344};
345
346static void __init sun8i_a23_rtc_clk_init(struct device_node *node)
347{
348 sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data);
349}
350CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc",
351 sun8i_a23_rtc_clk_init);
352
353static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = {
354 .rc_osc_rate = 16000000,
355 .fixed_prescaler = 32,
356 .has_prescaler = 1,
357 .has_out_clk = 1,
358};
359
360static void __init sun8i_h3_rtc_clk_init(struct device_node *node)
361{
362 sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data);
363}
364CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc",
365 sun8i_h3_rtc_clk_init);
366/* As far as we are concerned, clocks for H5 are the same as H3 */
367CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc",
368 sun8i_h3_rtc_clk_init);
369
370static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = {
371 .rc_osc_rate = 16000000,
372 .fixed_prescaler = 32,
373 .has_prescaler = 1,
374 .has_out_clk = 1,
375 .has_losc_en = 1,
376 .has_auto_swt = 1,
377};
378
379static void __init sun50i_h6_rtc_clk_init(struct device_node *node)
380{
381 sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data);
382}
383CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",
384 sun50i_h6_rtc_clk_init);
385
386/*
387 * The R40 user manual is self-conflicting on whether the prescaler is
388 * fixed or configurable. The clock diagram shows it as fixed, but there
389 * is also a configurable divider in the RTC block.
390 */
391static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = {
392 .rc_osc_rate = 16000000,
393 .fixed_prescaler = 512,
394};
395static void __init sun8i_r40_rtc_clk_init(struct device_node *node)
396{
397 sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data);
398}
399CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc",
400 sun8i_r40_rtc_clk_init);
401
402static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = {
403 .rc_osc_rate = 32000,
404 .has_out_clk = 1,
405};
406
407static void __init sun8i_v3_rtc_clk_init(struct device_node *node)
408{
409 sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data);
410}
411CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc",
412 sun8i_v3_rtc_clk_init);
413
414static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id)
415{
416 struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id;
417 irqreturn_t ret = IRQ_NONE;
418 u32 val;
419
420 spin_lock(&chip->lock);
421 val = readl(chip->base + SUN6I_ALRM_IRQ_STA);
422
423 if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) {
424 val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND;
425 writel(val, chip->base + SUN6I_ALRM_IRQ_STA);
426
427 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
428
429 ret = IRQ_HANDLED;
430 }
431 spin_unlock(&chip->lock);
432
433 return ret;
434}
435
436static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip)
437{
438 u32 alrm_val = 0;
439 u32 alrm_irq_val = 0;
440 u32 alrm_wake_val = 0;
441 unsigned long flags;
442
443 if (to) {
444 alrm_val = SUN6I_ALRM_EN_CNT_EN;
445 alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN;
446 alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP;
447 } else {
448 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
449 chip->base + SUN6I_ALRM_IRQ_STA);
450 }
451
452 spin_lock_irqsave(&chip->lock, flags);
453 writel(alrm_val, chip->base + SUN6I_ALRM_EN);
454 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);
455 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);
456 spin_unlock_irqrestore(&chip->lock, flags);
457}
458
459static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
460{
461 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
462 u32 date, time;
463
464 /*
465 * read again in case it changes
466 */
467 do {
468 date = readl(chip->base + SUN6I_RTC_YMD);
469 time = readl(chip->base + SUN6I_RTC_HMS);
470 } while ((date != readl(chip->base + SUN6I_RTC_YMD)) ||
471 (time != readl(chip->base + SUN6I_RTC_HMS)));
472
473 if (chip->flags & RTC_LINEAR_DAY) {
474 /*
475 * Newer chips store a linear day number, the manual
476 * does not mandate any epoch base. The BSP driver uses
477 * the UNIX epoch, let's just copy that, as it's the
478 * easiest anyway.
479 */
480 rtc_time64_to_tm((date & 0xffff) * SECS_PER_DAY, rtc_tm);
481 } else {
482 rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
483 rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date) - 1;
484 rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);
485
486 /*
487 * switch from (data_year->min)-relative offset to
488 * a (1900)-relative one
489 */
490 rtc_tm->tm_year += SUN6I_YEAR_OFF;
491 }
492
493 rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time);
494 rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time);
495 rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time);
496
497 return 0;
498}
499
500static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
501{
502 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
503 unsigned long flags;
504 u32 alrm_st;
505 u32 alrm_en;
506
507 spin_lock_irqsave(&chip->lock, flags);
508 alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN);
509 alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA);
510 spin_unlock_irqrestore(&chip->lock, flags);
511
512 wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN);
513 wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN);
514 rtc_time64_to_tm(chip->alarm, &wkalrm->time);
515
516 return 0;
517}
518
519static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
520{
521 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
522 struct rtc_time *alrm_tm = &wkalrm->time;
523 struct rtc_time tm_now;
524 time64_t time_set;
525 u32 counter_val, counter_val_hms;
526 int ret;
527
528 time_set = rtc_tm_to_time64(alrm_tm);
529
530 if (chip->flags & RTC_LINEAR_DAY) {
531 /*
532 * The alarm registers hold the actual alarm time, encoded
533 * in the same way (linear day + HMS) as the current time.
534 */
535 counter_val_hms = SUN6I_TIME_SET_SEC_VALUE(alrm_tm->tm_sec) |
536 SUN6I_TIME_SET_MIN_VALUE(alrm_tm->tm_min) |
537 SUN6I_TIME_SET_HOUR_VALUE(alrm_tm->tm_hour);
538 /* The division will cut off the H:M:S part of alrm_tm. */
539 counter_val = div_u64(rtc_tm_to_time64(alrm_tm), SECS_PER_DAY);
540 } else {
541 /* The alarm register holds the number of seconds left. */
542 time64_t time_now;
543
544 ret = sun6i_rtc_gettime(dev, &tm_now);
545 if (ret < 0) {
546 dev_err(dev, "Error in getting time\n");
547 return -EINVAL;
548 }
549
550 time_now = rtc_tm_to_time64(&tm_now);
551 if (time_set <= time_now) {
552 dev_err(dev, "Date to set in the past\n");
553 return -EINVAL;
554 }
555 if ((time_set - time_now) > U32_MAX) {
556 dev_err(dev, "Date too far in the future\n");
557 return -EINVAL;
558 }
559
560 counter_val = time_set - time_now;
561 }
562
563 sun6i_rtc_setaie(0, chip);
564 writel(0, chip->base + SUN6I_ALRM_COUNTER);
565 if (chip->flags & RTC_LINEAR_DAY)
566 writel(0, chip->base + SUN6I_ALRM_COUNTER_HMS);
567 usleep_range(100, 300);
568
569 writel(counter_val, chip->base + SUN6I_ALRM_COUNTER);
570 if (chip->flags & RTC_LINEAR_DAY)
571 writel(counter_val_hms, chip->base + SUN6I_ALRM_COUNTER_HMS);
572 chip->alarm = time_set;
573
574 sun6i_rtc_setaie(wkalrm->enabled, chip);
575
576 return 0;
577}
578
579static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset,
580 unsigned int mask, unsigned int ms_timeout)
581{
582 const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
583 u32 reg;
584
585 do {
586 reg = readl(chip->base + offset);
587 reg &= mask;
588
589 if (!reg)
590 return 0;
591
592 } while (time_before(jiffies, timeout));
593
594 return -ETIMEDOUT;
595}
596
597static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
598{
599 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
600 u32 date = 0;
601 u32 time = 0;
602
603 time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) |
604 SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) |
605 SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
606
607 if (chip->flags & RTC_LINEAR_DAY) {
608 /* The division will cut off the H:M:S part of rtc_tm. */
609 date = div_u64(rtc_tm_to_time64(rtc_tm), SECS_PER_DAY);
610 } else {
611 rtc_tm->tm_year -= SUN6I_YEAR_OFF;
612 rtc_tm->tm_mon += 1;
613
614 date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
615 SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
616 SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
617
618 if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN))
619 date |= SUN6I_LEAP_SET_VALUE(1);
620 }
621
622 /* Check whether registers are writable */
623 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
624 SUN6I_LOSC_CTRL_ACC_MASK, 50)) {
625 dev_err(dev, "rtc is still busy.\n");
626 return -EBUSY;
627 }
628
629 writel(time, chip->base + SUN6I_RTC_HMS);
630
631 /*
632 * After writing the RTC HH-MM-SS register, the
633 * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
634 * be cleared until the real writing operation is finished
635 */
636
637 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
638 SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) {
639 dev_err(dev, "Failed to set rtc time.\n");
640 return -ETIMEDOUT;
641 }
642
643 writel(date, chip->base + SUN6I_RTC_YMD);
644
645 /*
646 * After writing the RTC YY-MM-DD register, the
647 * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
648 * be cleared until the real writing operation is finished
649 */
650
651 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
652 SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) {
653 dev_err(dev, "Failed to set rtc time.\n");
654 return -ETIMEDOUT;
655 }
656
657 return 0;
658}
659
660static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
661{
662 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
663
664 if (!enabled)
665 sun6i_rtc_setaie(enabled, chip);
666
667 return 0;
668}
669
670static const struct rtc_class_ops sun6i_rtc_ops = {
671 .read_time = sun6i_rtc_gettime,
672 .set_time = sun6i_rtc_settime,
673 .read_alarm = sun6i_rtc_getalarm,
674 .set_alarm = sun6i_rtc_setalarm,
675 .alarm_irq_enable = sun6i_rtc_alarm_irq_enable
676};
677
678static int sun6i_rtc_nvmem_read(void *priv, unsigned int offset, void *_val, size_t bytes)
679{
680 struct sun6i_rtc_dev *chip = priv;
681 u32 *val = _val;
682 int i;
683
684 for (i = 0; i < bytes / 4; ++i)
685 val[i] = readl(chip->base + SUN6I_GP_DATA + offset + 4 * i);
686
687 return 0;
688}
689
690static int sun6i_rtc_nvmem_write(void *priv, unsigned int offset, void *_val, size_t bytes)
691{
692 struct sun6i_rtc_dev *chip = priv;
693 u32 *val = _val;
694 int i;
695
696 for (i = 0; i < bytes / 4; ++i)
697 writel(val[i], chip->base + SUN6I_GP_DATA + offset + 4 * i);
698
699 return 0;
700}
701
702static struct nvmem_config sun6i_rtc_nvmem_cfg = {
703 .type = NVMEM_TYPE_BATTERY_BACKED,
704 .reg_read = sun6i_rtc_nvmem_read,
705 .reg_write = sun6i_rtc_nvmem_write,
706 .size = SUN6I_GP_DATA_SIZE,
707 .word_size = 4,
708 .stride = 4,
709};
710
711#ifdef CONFIG_PM_SLEEP
712/* Enable IRQ wake on suspend, to wake up from RTC. */
713static int sun6i_rtc_suspend(struct device *dev)
714{
715 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
716
717 if (device_may_wakeup(dev))
718 enable_irq_wake(chip->irq);
719
720 return 0;
721}
722
723/* Disable IRQ wake on resume. */
724static int sun6i_rtc_resume(struct device *dev)
725{
726 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
727
728 if (device_may_wakeup(dev))
729 disable_irq_wake(chip->irq);
730
731 return 0;
732}
733#endif
734
735static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops,
736 sun6i_rtc_suspend, sun6i_rtc_resume);
737
738static void sun6i_rtc_bus_clk_cleanup(void *data)
739{
740 struct clk *bus_clk = data;
741
742 clk_disable_unprepare(bus_clk);
743}
744
745static int sun6i_rtc_probe(struct platform_device *pdev)
746{
747 struct sun6i_rtc_dev *chip = sun6i_rtc;
748 struct device *dev = &pdev->dev;
749 struct clk *bus_clk;
750 int ret;
751
752 bus_clk = devm_clk_get_optional(dev, "bus");
753 if (IS_ERR(bus_clk))
754 return PTR_ERR(bus_clk);
755
756 if (bus_clk) {
757 ret = clk_prepare_enable(bus_clk);
758 if (ret)
759 return ret;
760
761 ret = devm_add_action_or_reset(dev, sun6i_rtc_bus_clk_cleanup,
762 bus_clk);
763 if (ret)
764 return ret;
765 }
766
767 if (!chip) {
768 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
769 if (!chip)
770 return -ENOMEM;
771
772 spin_lock_init(&chip->lock);
773
774 chip->base = devm_platform_ioremap_resource(pdev, 0);
775 if (IS_ERR(chip->base))
776 return PTR_ERR(chip->base);
777
778 if (IS_REACHABLE(CONFIG_SUN6I_RTC_CCU)) {
779 ret = sun6i_rtc_ccu_probe(dev, chip->base);
780 if (ret)
781 return ret;
782 }
783 }
784
785 platform_set_drvdata(pdev, chip);
786
787 chip->flags = (unsigned long)of_device_get_match_data(&pdev->dev);
788
789 chip->irq = platform_get_irq(pdev, 0);
790 if (chip->irq < 0)
791 return chip->irq;
792
793 ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq,
794 0, dev_name(&pdev->dev), chip);
795 if (ret) {
796 dev_err(&pdev->dev, "Could not request IRQ\n");
797 return ret;
798 }
799
800 /* clear the alarm counter value */
801 writel(0, chip->base + SUN6I_ALRM_COUNTER);
802
803 /* disable counter alarm */
804 writel(0, chip->base + SUN6I_ALRM_EN);
805
806 /* disable counter alarm interrupt */
807 writel(0, chip->base + SUN6I_ALRM_IRQ_EN);
808
809 /* disable week alarm */
810 writel(0, chip->base + SUN6I_ALRM1_EN);
811
812 /* disable week alarm interrupt */
813 writel(0, chip->base + SUN6I_ALRM1_IRQ_EN);
814
815 /* clear counter alarm pending interrupts */
816 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
817 chip->base + SUN6I_ALRM_IRQ_STA);
818
819 /* clear week alarm pending interrupts */
820 writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND,
821 chip->base + SUN6I_ALRM1_IRQ_STA);
822
823 /* disable alarm wakeup */
824 writel(0, chip->base + SUN6I_ALARM_CONFIG);
825
826 clk_prepare_enable(chip->losc);
827
828 device_init_wakeup(&pdev->dev, 1);
829
830 chip->rtc = devm_rtc_allocate_device(&pdev->dev);
831 if (IS_ERR(chip->rtc))
832 return PTR_ERR(chip->rtc);
833
834 chip->rtc->ops = &sun6i_rtc_ops;
835 if (chip->flags & RTC_LINEAR_DAY)
836 chip->rtc->range_max = (65536 * SECS_PER_DAY) - 1;
837 else
838 chip->rtc->range_max = 2019686399LL; /* 2033-12-31 23:59:59 */
839
840 ret = devm_rtc_register_device(chip->rtc);
841 if (ret)
842 return ret;
843
844 sun6i_rtc_nvmem_cfg.priv = chip;
845 ret = devm_rtc_nvmem_register(chip->rtc, &sun6i_rtc_nvmem_cfg);
846 if (ret)
847 return ret;
848
849 return 0;
850}
851
852/*
853 * As far as RTC functionality goes, all models are the same. The
854 * datasheets claim that different models have different number of
855 * registers available for non-volatile storage, but experiments show
856 * that all SoCs have 16 registers available for this purpose.
857 */
858static const struct of_device_id sun6i_rtc_dt_ids[] = {
859 { .compatible = "allwinner,sun6i-a31-rtc" },
860 { .compatible = "allwinner,sun8i-a23-rtc" },
861 { .compatible = "allwinner,sun8i-h3-rtc" },
862 { .compatible = "allwinner,sun8i-r40-rtc" },
863 { .compatible = "allwinner,sun8i-v3-rtc" },
864 { .compatible = "allwinner,sun50i-h5-rtc" },
865 { .compatible = "allwinner,sun50i-h6-rtc" },
866 { .compatible = "allwinner,sun50i-h616-rtc",
867 .data = (void *)RTC_LINEAR_DAY },
868 { .compatible = "allwinner,sun50i-r329-rtc",
869 .data = (void *)RTC_LINEAR_DAY },
870 { /* sentinel */ },
871};
872MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
873
874static struct platform_driver sun6i_rtc_driver = {
875 .probe = sun6i_rtc_probe,
876 .driver = {
877 .name = "sun6i-rtc",
878 .of_match_table = sun6i_rtc_dt_ids,
879 .pm = &sun6i_rtc_pm_ops,
880 },
881};
882builtin_platform_driver(sun6i_rtc_driver);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * An RTC driver for Allwinner A31/A23
4 *
5 * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org>
6 *
7 * based on rtc-sunxi.c
8 *
9 * An RTC driver for Allwinner A10/A20
10 *
11 * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
12 */
13
14#include <linux/clk.h>
15#include <linux/clk-provider.h>
16#include <linux/clk/sunxi-ng.h>
17#include <linux/delay.h>
18#include <linux/err.h>
19#include <linux/fs.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/of_address.h>
27#include <linux/of_device.h>
28#include <linux/platform_device.h>
29#include <linux/rtc.h>
30#include <linux/slab.h>
31#include <linux/types.h>
32
33/* Control register */
34#define SUN6I_LOSC_CTRL 0x0000
35#define SUN6I_LOSC_CTRL_KEY (0x16aa << 16)
36#define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15)
37#define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9)
38#define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8)
39#define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7)
40#define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4)
41#define SUN6I_LOSC_CTRL_EXT_OSC BIT(0)
42#define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7)
43
44#define SUN6I_LOSC_CLK_PRESCAL 0x0008
45
46/* RTC */
47#define SUN6I_RTC_YMD 0x0010
48#define SUN6I_RTC_HMS 0x0014
49
50/* Alarm 0 (counter) */
51#define SUN6I_ALRM_COUNTER 0x0020
52/* This holds the remaining alarm seconds on older SoCs (current value) */
53#define SUN6I_ALRM_COUNTER_HMS 0x0024
54#define SUN6I_ALRM_EN 0x0028
55#define SUN6I_ALRM_EN_CNT_EN BIT(0)
56#define SUN6I_ALRM_IRQ_EN 0x002c
57#define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0)
58#define SUN6I_ALRM_IRQ_STA 0x0030
59#define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0)
60
61/* Alarm 1 (wall clock) */
62#define SUN6I_ALRM1_EN 0x0044
63#define SUN6I_ALRM1_IRQ_EN 0x0048
64#define SUN6I_ALRM1_IRQ_STA 0x004c
65#define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0)
66
67/* Alarm config */
68#define SUN6I_ALARM_CONFIG 0x0050
69#define SUN6I_ALARM_CONFIG_WAKEUP BIT(0)
70
71#define SUN6I_LOSC_OUT_GATING 0x0060
72#define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0
73
74/* General-purpose data */
75#define SUN6I_GP_DATA 0x0100
76#define SUN6I_GP_DATA_SIZE 0x20
77
78/*
79 * Get date values
80 */
81#define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f)
82#define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8)
83#define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16)
84#define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22)
85
86/*
87 * Get time values
88 */
89#define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f)
90#define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8)
91#define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16)
92
93/*
94 * Set date values
95 */
96#define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f)
97#define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00)
98#define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000)
99#define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000)
100
101/*
102 * Set time values
103 */
104#define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f)
105#define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00)
106#define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000)
107
108/*
109 * The year parameter passed to the driver is usually an offset relative to
110 * the year 1900. This macro is used to convert this offset to another one
111 * relative to the minimum year allowed by the hardware.
112 *
113 * The year range is 1970 - 2033. This range is selected to match Allwinner's
114 * driver, even though it is somewhat limited.
115 */
116#define SUN6I_YEAR_MIN 1970
117#define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900)
118
119#define SECS_PER_DAY (24 * 3600ULL)
120
121/*
122 * There are other differences between models, including:
123 *
124 * - number of GPIO pins that can be configured to hold a certain level
125 * - crypto-key related registers (H5, H6)
126 * - boot process related (super standby, secondary processor entry address)
127 * registers (R40, H6)
128 * - SYS power domain controls (R40)
129 * - DCXO controls (H6)
130 * - RC oscillator calibration (H6)
131 *
132 * These functions are not covered by this driver.
133 */
134struct sun6i_rtc_clk_data {
135 unsigned long rc_osc_rate;
136 unsigned int fixed_prescaler : 16;
137 unsigned int has_prescaler : 1;
138 unsigned int has_out_clk : 1;
139 unsigned int export_iosc : 1;
140 unsigned int has_losc_en : 1;
141 unsigned int has_auto_swt : 1;
142};
143
144#define RTC_LINEAR_DAY BIT(0)
145
146struct sun6i_rtc_dev {
147 struct rtc_device *rtc;
148 const struct sun6i_rtc_clk_data *data;
149 void __iomem *base;
150 int irq;
151 time64_t alarm;
152 unsigned long flags;
153
154 struct clk_hw hw;
155 struct clk_hw *int_osc;
156 struct clk *losc;
157 struct clk *ext_losc;
158
159 spinlock_t lock;
160};
161
162static struct sun6i_rtc_dev *sun6i_rtc;
163
164static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw,
165 unsigned long parent_rate)
166{
167 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
168 u32 val = 0;
169
170 val = readl(rtc->base + SUN6I_LOSC_CTRL);
171 if (val & SUN6I_LOSC_CTRL_EXT_OSC)
172 return parent_rate;
173
174 if (rtc->data->fixed_prescaler)
175 parent_rate /= rtc->data->fixed_prescaler;
176
177 if (rtc->data->has_prescaler) {
178 val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL);
179 val &= GENMASK(4, 0);
180 }
181
182 return parent_rate / (val + 1);
183}
184
185static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw)
186{
187 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
188
189 return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC;
190}
191
192static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index)
193{
194 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
195 unsigned long flags;
196 u32 val;
197
198 if (index > 1)
199 return -EINVAL;
200
201 spin_lock_irqsave(&rtc->lock, flags);
202 val = readl(rtc->base + SUN6I_LOSC_CTRL);
203 val &= ~SUN6I_LOSC_CTRL_EXT_OSC;
204 val |= SUN6I_LOSC_CTRL_KEY;
205 val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0;
206 if (rtc->data->has_losc_en) {
207 val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN;
208 val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0;
209 }
210 writel(val, rtc->base + SUN6I_LOSC_CTRL);
211 spin_unlock_irqrestore(&rtc->lock, flags);
212
213 return 0;
214}
215
216static const struct clk_ops sun6i_rtc_osc_ops = {
217 .recalc_rate = sun6i_rtc_osc_recalc_rate,
218
219 .get_parent = sun6i_rtc_osc_get_parent,
220 .set_parent = sun6i_rtc_osc_set_parent,
221};
222
223static void __init sun6i_rtc_clk_init(struct device_node *node,
224 const struct sun6i_rtc_clk_data *data)
225{
226 struct clk_hw_onecell_data *clk_data;
227 struct sun6i_rtc_dev *rtc;
228 struct clk_init_data init = {
229 .ops = &sun6i_rtc_osc_ops,
230 .name = "losc",
231 };
232 const char *iosc_name = "rtc-int-osc";
233 const char *clkout_name = "osc32k-out";
234 const char *parents[2];
235 u32 reg;
236
237 rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
238 if (!rtc)
239 return;
240
241 rtc->data = data;
242 clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL);
243 if (!clk_data) {
244 kfree(rtc);
245 return;
246 }
247
248 spin_lock_init(&rtc->lock);
249
250 rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node));
251 if (IS_ERR(rtc->base)) {
252 pr_crit("Can't map RTC registers");
253 goto err;
254 }
255
256 reg = SUN6I_LOSC_CTRL_KEY;
257 if (rtc->data->has_auto_swt) {
258 /* Bypass auto-switch to int osc, on ext losc failure */
259 reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS;
260 writel(reg, rtc->base + SUN6I_LOSC_CTRL);
261 }
262
263 /* Switch to the external, more precise, oscillator, if present */
264 if (of_get_property(node, "clocks", NULL)) {
265 reg |= SUN6I_LOSC_CTRL_EXT_OSC;
266 if (rtc->data->has_losc_en)
267 reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN;
268 }
269 writel(reg, rtc->base + SUN6I_LOSC_CTRL);
270
271 /* Yes, I know, this is ugly. */
272 sun6i_rtc = rtc;
273
274 /* Only read IOSC name from device tree if it is exported */
275 if (rtc->data->export_iosc)
276 of_property_read_string_index(node, "clock-output-names", 2,
277 &iosc_name);
278
279 rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL,
280 iosc_name,
281 NULL, 0,
282 rtc->data->rc_osc_rate,
283 300000000);
284 if (IS_ERR(rtc->int_osc)) {
285 pr_crit("Couldn't register the internal oscillator\n");
286 goto err;
287 }
288
289 parents[0] = clk_hw_get_name(rtc->int_osc);
290 /* If there is no external oscillator, this will be NULL and ... */
291 parents[1] = of_clk_get_parent_name(node, 0);
292
293 rtc->hw.init = &init;
294
295 init.parent_names = parents;
296 /* ... number of clock parents will be 1. */
297 init.num_parents = of_clk_get_parent_count(node) + 1;
298 of_property_read_string_index(node, "clock-output-names", 0,
299 &init.name);
300
301 rtc->losc = clk_register(NULL, &rtc->hw);
302 if (IS_ERR(rtc->losc)) {
303 pr_crit("Couldn't register the LOSC clock\n");
304 goto err_register;
305 }
306
307 of_property_read_string_index(node, "clock-output-names", 1,
308 &clkout_name);
309 rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name,
310 0, rtc->base + SUN6I_LOSC_OUT_GATING,
311 SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,
312 &rtc->lock);
313 if (IS_ERR(rtc->ext_losc)) {
314 pr_crit("Couldn't register the LOSC external gate\n");
315 goto err_register;
316 }
317
318 clk_data->num = 2;
319 clk_data->hws[0] = &rtc->hw;
320 clk_data->hws[1] = __clk_get_hw(rtc->ext_losc);
321 if (rtc->data->export_iosc) {
322 clk_data->hws[2] = rtc->int_osc;
323 clk_data->num = 3;
324 }
325 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
326 return;
327
328err_register:
329 clk_hw_unregister_fixed_rate(rtc->int_osc);
330err:
331 kfree(clk_data);
332}
333
334static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = {
335 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
336 .has_prescaler = 1,
337};
338
339static void __init sun6i_a31_rtc_clk_init(struct device_node *node)
340{
341 sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data);
342}
343CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc",
344 sun6i_a31_rtc_clk_init);
345
346static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = {
347 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
348 .has_prescaler = 1,
349 .has_out_clk = 1,
350};
351
352static void __init sun8i_a23_rtc_clk_init(struct device_node *node)
353{
354 sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data);
355}
356CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc",
357 sun8i_a23_rtc_clk_init);
358
359static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = {
360 .rc_osc_rate = 16000000,
361 .fixed_prescaler = 32,
362 .has_prescaler = 1,
363 .has_out_clk = 1,
364 .export_iosc = 1,
365};
366
367static void __init sun8i_h3_rtc_clk_init(struct device_node *node)
368{
369 sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data);
370}
371CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc",
372 sun8i_h3_rtc_clk_init);
373/* As far as we are concerned, clocks for H5 are the same as H3 */
374CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc",
375 sun8i_h3_rtc_clk_init);
376
377static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = {
378 .rc_osc_rate = 16000000,
379 .fixed_prescaler = 32,
380 .has_prescaler = 1,
381 .has_out_clk = 1,
382 .export_iosc = 1,
383 .has_losc_en = 1,
384 .has_auto_swt = 1,
385};
386
387static void __init sun50i_h6_rtc_clk_init(struct device_node *node)
388{
389 sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data);
390}
391CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",
392 sun50i_h6_rtc_clk_init);
393
394/*
395 * The R40 user manual is self-conflicting on whether the prescaler is
396 * fixed or configurable. The clock diagram shows it as fixed, but there
397 * is also a configurable divider in the RTC block.
398 */
399static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = {
400 .rc_osc_rate = 16000000,
401 .fixed_prescaler = 512,
402};
403static void __init sun8i_r40_rtc_clk_init(struct device_node *node)
404{
405 sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data);
406}
407CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc",
408 sun8i_r40_rtc_clk_init);
409
410static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = {
411 .rc_osc_rate = 32000,
412 .has_out_clk = 1,
413};
414
415static void __init sun8i_v3_rtc_clk_init(struct device_node *node)
416{
417 sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data);
418}
419CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc",
420 sun8i_v3_rtc_clk_init);
421
422static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id)
423{
424 struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id;
425 irqreturn_t ret = IRQ_NONE;
426 u32 val;
427
428 spin_lock(&chip->lock);
429 val = readl(chip->base + SUN6I_ALRM_IRQ_STA);
430
431 if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) {
432 val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND;
433 writel(val, chip->base + SUN6I_ALRM_IRQ_STA);
434
435 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
436
437 ret = IRQ_HANDLED;
438 }
439 spin_unlock(&chip->lock);
440
441 return ret;
442}
443
444static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip)
445{
446 u32 alrm_val = 0;
447 u32 alrm_irq_val = 0;
448 u32 alrm_wake_val = 0;
449 unsigned long flags;
450
451 if (to) {
452 alrm_val = SUN6I_ALRM_EN_CNT_EN;
453 alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN;
454 alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP;
455 } else {
456 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
457 chip->base + SUN6I_ALRM_IRQ_STA);
458 }
459
460 spin_lock_irqsave(&chip->lock, flags);
461 writel(alrm_val, chip->base + SUN6I_ALRM_EN);
462 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);
463 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);
464 spin_unlock_irqrestore(&chip->lock, flags);
465}
466
467static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
468{
469 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
470 u32 date, time;
471
472 /*
473 * read again in case it changes
474 */
475 do {
476 date = readl(chip->base + SUN6I_RTC_YMD);
477 time = readl(chip->base + SUN6I_RTC_HMS);
478 } while ((date != readl(chip->base + SUN6I_RTC_YMD)) ||
479 (time != readl(chip->base + SUN6I_RTC_HMS)));
480
481 if (chip->flags & RTC_LINEAR_DAY) {
482 /*
483 * Newer chips store a linear day number, the manual
484 * does not mandate any epoch base. The BSP driver uses
485 * the UNIX epoch, let's just copy that, as it's the
486 * easiest anyway.
487 */
488 rtc_time64_to_tm((date & 0xffff) * SECS_PER_DAY, rtc_tm);
489 } else {
490 rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
491 rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date) - 1;
492 rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);
493
494 /*
495 * switch from (data_year->min)-relative offset to
496 * a (1900)-relative one
497 */
498 rtc_tm->tm_year += SUN6I_YEAR_OFF;
499 }
500
501 rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time);
502 rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time);
503 rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time);
504
505 return 0;
506}
507
508static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
509{
510 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
511 unsigned long flags;
512 u32 alrm_st;
513 u32 alrm_en;
514
515 spin_lock_irqsave(&chip->lock, flags);
516 alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN);
517 alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA);
518 spin_unlock_irqrestore(&chip->lock, flags);
519
520 wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN);
521 wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN);
522 rtc_time64_to_tm(chip->alarm, &wkalrm->time);
523
524 return 0;
525}
526
527static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
528{
529 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
530 struct rtc_time *alrm_tm = &wkalrm->time;
531 struct rtc_time tm_now;
532 time64_t time_set;
533 u32 counter_val, counter_val_hms;
534 int ret;
535
536 time_set = rtc_tm_to_time64(alrm_tm);
537
538 if (chip->flags & RTC_LINEAR_DAY) {
539 /*
540 * The alarm registers hold the actual alarm time, encoded
541 * in the same way (linear day + HMS) as the current time.
542 */
543 counter_val_hms = SUN6I_TIME_SET_SEC_VALUE(alrm_tm->tm_sec) |
544 SUN6I_TIME_SET_MIN_VALUE(alrm_tm->tm_min) |
545 SUN6I_TIME_SET_HOUR_VALUE(alrm_tm->tm_hour);
546 /* The division will cut off the H:M:S part of alrm_tm. */
547 counter_val = div_u64(rtc_tm_to_time64(alrm_tm), SECS_PER_DAY);
548 } else {
549 /* The alarm register holds the number of seconds left. */
550 time64_t time_now;
551
552 ret = sun6i_rtc_gettime(dev, &tm_now);
553 if (ret < 0) {
554 dev_err(dev, "Error in getting time\n");
555 return -EINVAL;
556 }
557
558 time_now = rtc_tm_to_time64(&tm_now);
559 if (time_set <= time_now) {
560 dev_err(dev, "Date to set in the past\n");
561 return -EINVAL;
562 }
563 if ((time_set - time_now) > U32_MAX) {
564 dev_err(dev, "Date too far in the future\n");
565 return -EINVAL;
566 }
567
568 counter_val = time_set - time_now;
569 }
570
571 sun6i_rtc_setaie(0, chip);
572 writel(0, chip->base + SUN6I_ALRM_COUNTER);
573 if (chip->flags & RTC_LINEAR_DAY)
574 writel(0, chip->base + SUN6I_ALRM_COUNTER_HMS);
575 usleep_range(100, 300);
576
577 writel(counter_val, chip->base + SUN6I_ALRM_COUNTER);
578 if (chip->flags & RTC_LINEAR_DAY)
579 writel(counter_val_hms, chip->base + SUN6I_ALRM_COUNTER_HMS);
580 chip->alarm = time_set;
581
582 sun6i_rtc_setaie(wkalrm->enabled, chip);
583
584 return 0;
585}
586
587static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset,
588 unsigned int mask, unsigned int ms_timeout)
589{
590 const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
591 u32 reg;
592
593 do {
594 reg = readl(chip->base + offset);
595 reg &= mask;
596
597 if (!reg)
598 return 0;
599
600 } while (time_before(jiffies, timeout));
601
602 return -ETIMEDOUT;
603}
604
605static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
606{
607 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
608 u32 date = 0;
609 u32 time = 0;
610
611 time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) |
612 SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) |
613 SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
614
615 if (chip->flags & RTC_LINEAR_DAY) {
616 /* The division will cut off the H:M:S part of rtc_tm. */
617 date = div_u64(rtc_tm_to_time64(rtc_tm), SECS_PER_DAY);
618 } else {
619 rtc_tm->tm_year -= SUN6I_YEAR_OFF;
620 rtc_tm->tm_mon += 1;
621
622 date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
623 SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
624 SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
625
626 if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN))
627 date |= SUN6I_LEAP_SET_VALUE(1);
628 }
629
630 /* Check whether registers are writable */
631 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
632 SUN6I_LOSC_CTRL_ACC_MASK, 50)) {
633 dev_err(dev, "rtc is still busy.\n");
634 return -EBUSY;
635 }
636
637 writel(time, chip->base + SUN6I_RTC_HMS);
638
639 /*
640 * After writing the RTC HH-MM-SS register, the
641 * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
642 * be cleared until the real writing operation is finished
643 */
644
645 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
646 SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) {
647 dev_err(dev, "Failed to set rtc time.\n");
648 return -ETIMEDOUT;
649 }
650
651 writel(date, chip->base + SUN6I_RTC_YMD);
652
653 /*
654 * After writing the RTC YY-MM-DD register, the
655 * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
656 * be cleared until the real writing operation is finished
657 */
658
659 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
660 SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) {
661 dev_err(dev, "Failed to set rtc time.\n");
662 return -ETIMEDOUT;
663 }
664
665 return 0;
666}
667
668static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
669{
670 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
671
672 if (!enabled)
673 sun6i_rtc_setaie(enabled, chip);
674
675 return 0;
676}
677
678static const struct rtc_class_ops sun6i_rtc_ops = {
679 .read_time = sun6i_rtc_gettime,
680 .set_time = sun6i_rtc_settime,
681 .read_alarm = sun6i_rtc_getalarm,
682 .set_alarm = sun6i_rtc_setalarm,
683 .alarm_irq_enable = sun6i_rtc_alarm_irq_enable
684};
685
686static int sun6i_rtc_nvmem_read(void *priv, unsigned int offset, void *_val, size_t bytes)
687{
688 struct sun6i_rtc_dev *chip = priv;
689 u32 *val = _val;
690 int i;
691
692 for (i = 0; i < bytes / 4; ++i)
693 val[i] = readl(chip->base + SUN6I_GP_DATA + offset + 4 * i);
694
695 return 0;
696}
697
698static int sun6i_rtc_nvmem_write(void *priv, unsigned int offset, void *_val, size_t bytes)
699{
700 struct sun6i_rtc_dev *chip = priv;
701 u32 *val = _val;
702 int i;
703
704 for (i = 0; i < bytes / 4; ++i)
705 writel(val[i], chip->base + SUN6I_GP_DATA + offset + 4 * i);
706
707 return 0;
708}
709
710static struct nvmem_config sun6i_rtc_nvmem_cfg = {
711 .type = NVMEM_TYPE_BATTERY_BACKED,
712 .reg_read = sun6i_rtc_nvmem_read,
713 .reg_write = sun6i_rtc_nvmem_write,
714 .size = SUN6I_GP_DATA_SIZE,
715 .word_size = 4,
716 .stride = 4,
717};
718
719#ifdef CONFIG_PM_SLEEP
720/* Enable IRQ wake on suspend, to wake up from RTC. */
721static int sun6i_rtc_suspend(struct device *dev)
722{
723 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
724
725 if (device_may_wakeup(dev))
726 enable_irq_wake(chip->irq);
727
728 return 0;
729}
730
731/* Disable IRQ wake on resume. */
732static int sun6i_rtc_resume(struct device *dev)
733{
734 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
735
736 if (device_may_wakeup(dev))
737 disable_irq_wake(chip->irq);
738
739 return 0;
740}
741#endif
742
743static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops,
744 sun6i_rtc_suspend, sun6i_rtc_resume);
745
746static void sun6i_rtc_bus_clk_cleanup(void *data)
747{
748 struct clk *bus_clk = data;
749
750 clk_disable_unprepare(bus_clk);
751}
752
753static int sun6i_rtc_probe(struct platform_device *pdev)
754{
755 struct sun6i_rtc_dev *chip = sun6i_rtc;
756 struct device *dev = &pdev->dev;
757 struct clk *bus_clk;
758 int ret;
759
760 bus_clk = devm_clk_get_optional(dev, "bus");
761 if (IS_ERR(bus_clk))
762 return PTR_ERR(bus_clk);
763
764 if (bus_clk) {
765 ret = clk_prepare_enable(bus_clk);
766 if (ret)
767 return ret;
768
769 ret = devm_add_action_or_reset(dev, sun6i_rtc_bus_clk_cleanup,
770 bus_clk);
771 if (ret)
772 return ret;
773 }
774
775 if (!chip) {
776 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
777 if (!chip)
778 return -ENOMEM;
779
780 spin_lock_init(&chip->lock);
781
782 chip->base = devm_platform_ioremap_resource(pdev, 0);
783 if (IS_ERR(chip->base))
784 return PTR_ERR(chip->base);
785
786 if (IS_REACHABLE(CONFIG_SUN6I_RTC_CCU)) {
787 ret = sun6i_rtc_ccu_probe(dev, chip->base);
788 if (ret)
789 return ret;
790 }
791 }
792
793 platform_set_drvdata(pdev, chip);
794
795 chip->flags = (unsigned long)of_device_get_match_data(&pdev->dev);
796
797 chip->irq = platform_get_irq(pdev, 0);
798 if (chip->irq < 0)
799 return chip->irq;
800
801 ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq,
802 0, dev_name(&pdev->dev), chip);
803 if (ret) {
804 dev_err(&pdev->dev, "Could not request IRQ\n");
805 return ret;
806 }
807
808 /* clear the alarm counter value */
809 writel(0, chip->base + SUN6I_ALRM_COUNTER);
810
811 /* disable counter alarm */
812 writel(0, chip->base + SUN6I_ALRM_EN);
813
814 /* disable counter alarm interrupt */
815 writel(0, chip->base + SUN6I_ALRM_IRQ_EN);
816
817 /* disable week alarm */
818 writel(0, chip->base + SUN6I_ALRM1_EN);
819
820 /* disable week alarm interrupt */
821 writel(0, chip->base + SUN6I_ALRM1_IRQ_EN);
822
823 /* clear counter alarm pending interrupts */
824 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
825 chip->base + SUN6I_ALRM_IRQ_STA);
826
827 /* clear week alarm pending interrupts */
828 writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND,
829 chip->base + SUN6I_ALRM1_IRQ_STA);
830
831 /* disable alarm wakeup */
832 writel(0, chip->base + SUN6I_ALARM_CONFIG);
833
834 clk_prepare_enable(chip->losc);
835
836 device_init_wakeup(&pdev->dev, 1);
837
838 chip->rtc = devm_rtc_allocate_device(&pdev->dev);
839 if (IS_ERR(chip->rtc))
840 return PTR_ERR(chip->rtc);
841
842 chip->rtc->ops = &sun6i_rtc_ops;
843 if (chip->flags & RTC_LINEAR_DAY)
844 chip->rtc->range_max = (65536 * SECS_PER_DAY) - 1;
845 else
846 chip->rtc->range_max = 2019686399LL; /* 2033-12-31 23:59:59 */
847
848 ret = devm_rtc_register_device(chip->rtc);
849 if (ret)
850 return ret;
851
852 sun6i_rtc_nvmem_cfg.priv = chip;
853 ret = devm_rtc_nvmem_register(chip->rtc, &sun6i_rtc_nvmem_cfg);
854 if (ret)
855 return ret;
856
857 dev_info(&pdev->dev, "RTC enabled\n");
858
859 return 0;
860}
861
862/*
863 * As far as RTC functionality goes, all models are the same. The
864 * datasheets claim that different models have different number of
865 * registers available for non-volatile storage, but experiments show
866 * that all SoCs have 16 registers available for this purpose.
867 */
868static const struct of_device_id sun6i_rtc_dt_ids[] = {
869 { .compatible = "allwinner,sun6i-a31-rtc" },
870 { .compatible = "allwinner,sun8i-a23-rtc" },
871 { .compatible = "allwinner,sun8i-h3-rtc" },
872 { .compatible = "allwinner,sun8i-r40-rtc" },
873 { .compatible = "allwinner,sun8i-v3-rtc" },
874 { .compatible = "allwinner,sun50i-h5-rtc" },
875 { .compatible = "allwinner,sun50i-h6-rtc" },
876 { .compatible = "allwinner,sun50i-h616-rtc",
877 .data = (void *)RTC_LINEAR_DAY },
878 { .compatible = "allwinner,sun50i-r329-rtc",
879 .data = (void *)RTC_LINEAR_DAY },
880 { /* sentinel */ },
881};
882MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
883
884static struct platform_driver sun6i_rtc_driver = {
885 .probe = sun6i_rtc_probe,
886 .driver = {
887 .name = "sun6i-rtc",
888 .of_match_table = sun6i_rtc_dt_ids,
889 .pm = &sun6i_rtc_pm_ops,
890 },
891};
892builtin_platform_driver(sun6i_rtc_driver);