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v6.8
  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * pm8xxx RTC driver
  4 *
  5 * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
  6 * Copyright (c) 2023, Linaro Limited
  7 */
  8#include <linux/of.h>
  9#include <linux/module.h>
 10#include <linux/nvmem-consumer.h>
 11#include <linux/init.h>
 12#include <linux/rtc.h>
 13#include <linux/platform_device.h>
 14#include <linux/pm.h>
 15#include <linux/pm_wakeirq.h>
 16#include <linux/regmap.h>
 17#include <linux/slab.h>
 18#include <linux/spinlock.h>
 19
 20#include <asm/unaligned.h>
 
 
 
 
 21
 22/* RTC_CTRL register bit fields */
 23#define PM8xxx_RTC_ENABLE		BIT(7)
 24#define PM8xxx_RTC_ALARM_CLEAR		BIT(0)
 25#define PM8xxx_RTC_ALARM_ENABLE		BIT(7)
 26
 27#define NUM_8_BIT_RTC_REGS		0x4
 28
 29/**
 30 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
 31 * @ctrl:		address of control register
 32 * @write:		base address of write registers
 33 * @read:		base address of read registers
 34 * @alarm_ctrl:		address of alarm control register
 35 * @alarm_ctrl2:	address of alarm control2 register
 36 * @alarm_rw:		base address of alarm read-write registers
 37 * @alarm_en:		alarm enable mask
 38 */
 39struct pm8xxx_rtc_regs {
 40	unsigned int ctrl;
 41	unsigned int write;
 42	unsigned int read;
 43	unsigned int alarm_ctrl;
 44	unsigned int alarm_ctrl2;
 45	unsigned int alarm_rw;
 46	unsigned int alarm_en;
 47};
 48
 49/**
 50 * struct pm8xxx_rtc -  RTC driver internal structure
 51 * @rtc:		RTC device
 52 * @regmap:		regmap used to access registers
 53 * @allow_set_time:	whether the time can be set
 54 * @alarm_irq:		alarm irq number
 55 * @regs:		register description
 56 * @dev:		device structure
 57 * @nvmem_cell:		nvmem cell for offset
 58 * @offset:		offset from epoch in seconds
 59 */
 60struct pm8xxx_rtc {
 61	struct rtc_device *rtc;
 62	struct regmap *regmap;
 63	bool allow_set_time;
 64	int alarm_irq;
 65	const struct pm8xxx_rtc_regs *regs;
 66	struct device *dev;
 67	struct nvmem_cell *nvmem_cell;
 68	u32 offset;
 69};
 70
 71static int pm8xxx_rtc_read_nvmem_offset(struct pm8xxx_rtc *rtc_dd)
 72{
 73	size_t len;
 74	void *buf;
 75	int rc;
 76
 77	buf = nvmem_cell_read(rtc_dd->nvmem_cell, &len);
 78	if (IS_ERR(buf)) {
 79		rc = PTR_ERR(buf);
 80		dev_dbg(rtc_dd->dev, "failed to read nvmem offset: %d\n", rc);
 81		return rc;
 82	}
 83
 84	if (len != sizeof(u32)) {
 85		dev_dbg(rtc_dd->dev, "unexpected nvmem cell size %zu\n", len);
 86		kfree(buf);
 87		return -EINVAL;
 88	}
 89
 90	rtc_dd->offset = get_unaligned_le32(buf);
 91
 92	kfree(buf);
 93
 94	return 0;
 95}
 96
 97static int pm8xxx_rtc_write_nvmem_offset(struct pm8xxx_rtc *rtc_dd, u32 offset)
 98{
 99	u8 buf[sizeof(u32)];
100	int rc;
101
102	put_unaligned_le32(offset, buf);
103
104	rc = nvmem_cell_write(rtc_dd->nvmem_cell, buf, sizeof(buf));
105	if (rc < 0) {
106		dev_dbg(rtc_dd->dev, "failed to write nvmem offset: %d\n", rc);
107		return rc;
108	}
109
110	return 0;
111}
112
113static int pm8xxx_rtc_read_offset(struct pm8xxx_rtc *rtc_dd)
114{
115	if (!rtc_dd->nvmem_cell)
116		return 0;
117
118	return pm8xxx_rtc_read_nvmem_offset(rtc_dd);
119}
120
121static int pm8xxx_rtc_read_raw(struct pm8xxx_rtc *rtc_dd, u32 *secs)
122{
123	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
124	u8 value[NUM_8_BIT_RTC_REGS];
125	unsigned int reg;
126	int rc;
127
128	rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
129	if (rc)
130		return rc;
131
132	/*
133	 * Read the LSB again and check if there has been a carry over.
134	 * If there has, redo the read operation.
135	 */
136	rc = regmap_read(rtc_dd->regmap, regs->read, &reg);
137	if (rc < 0)
138		return rc;
139
140	if (reg < value[0]) {
141		rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value,
142				      sizeof(value));
143		if (rc)
144			return rc;
145	}
146
147	*secs = get_unaligned_le32(value);
148
149	return 0;
150}
151
152static int pm8xxx_rtc_update_offset(struct pm8xxx_rtc *rtc_dd, u32 secs)
153{
154	u32 raw_secs;
155	u32 offset;
156	int rc;
157
158	if (!rtc_dd->nvmem_cell)
159		return -ENODEV;
160
161	rc = pm8xxx_rtc_read_raw(rtc_dd, &raw_secs);
162	if (rc)
163		return rc;
164
165	offset = secs - raw_secs;
166
167	if (offset == rtc_dd->offset)
168		return 0;
169
170	rc = pm8xxx_rtc_write_nvmem_offset(rtc_dd, offset);
171	if (rc)
172		return rc;
173
174	rtc_dd->offset = offset;
175
176	return 0;
177}
178
179/*
180 * Steps to write the RTC registers.
181 * 1. Disable alarm if enabled.
182 * 2. Disable rtc if enabled.
183 * 3. Write 0x00 to LSB.
184 * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
185 * 5. Enable rtc if disabled in step 2.
186 * 6. Enable alarm if disabled in step 1.
187 */
188static int __pm8xxx_rtc_set_time(struct pm8xxx_rtc *rtc_dd, u32 secs)
189{
 
 
 
 
 
190	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
191	u8 value[NUM_8_BIT_RTC_REGS];
192	bool alarm_enabled;
193	int rc;
194
195	put_unaligned_le32(secs, value);
 
196
197	rc = regmap_update_bits_check(rtc_dd->regmap, regs->alarm_ctrl,
198				      regs->alarm_en, 0, &alarm_enabled);
 
 
 
 
 
 
 
 
 
 
199	if (rc)
200		return rc;
 
 
 
 
 
 
 
 
 
 
201
202	/* Disable RTC */
203	rc = regmap_update_bits(rtc_dd->regmap, regs->ctrl, PM8xxx_RTC_ENABLE, 0);
204	if (rc)
205		return rc;
 
 
 
 
 
 
 
 
 
 
206
207	/* Write 0 to Byte[0] */
208	rc = regmap_write(rtc_dd->regmap, regs->write, 0);
209	if (rc)
210		return rc;
 
 
211
212	/* Write Byte[1], Byte[2], Byte[3] */
213	rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
214			       &value[1], sizeof(value) - 1);
215	if (rc)
216		return rc;
 
 
217
218	/* Write Byte[0] */
219	rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
220	if (rc)
221		return rc;
 
 
222
223	/* Enable RTC */
224	rc = regmap_update_bits(rtc_dd->regmap, regs->ctrl, PM8xxx_RTC_ENABLE,
225				PM8xxx_RTC_ENABLE);
226	if (rc)
227		return rc;
 
 
 
 
228
229	if (alarm_enabled) {
230		rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
231					regs->alarm_en, regs->alarm_en);
232		if (rc)
233			return rc;
 
 
234	}
235
236	return 0;
 
 
 
237}
238
239static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
240{
241	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
242	u32 secs;
243	int rc;
 
 
 
 
 
244
245	secs = rtc_tm_to_time64(tm);
246
247	if (rtc_dd->allow_set_time)
248		rc = __pm8xxx_rtc_set_time(rtc_dd, secs);
249	else
250		rc = pm8xxx_rtc_update_offset(rtc_dd, secs);
251
252	if (rc)
253		return rc;
 
254
255	dev_dbg(dev, "set time: %ptRd %ptRt (%u + %u)\n", tm, tm,
256			secs - rtc_dd->offset, rtc_dd->offset);
257	return 0;
258}
 
 
 
 
 
259
260static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
261{
262	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
263	u32 secs;
264	int rc;
 
 
 
265
266	rc = pm8xxx_rtc_read_raw(rtc_dd, &secs);
267	if (rc)
268		return rc;
269
270	secs += rtc_dd->offset;
271	rtc_time64_to_tm(secs, tm);
272
273	dev_dbg(dev, "read time: %ptRd %ptRt (%u + %u)\n", tm, tm,
274			secs - rtc_dd->offset, rtc_dd->offset);
275	return 0;
276}
277
278static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
279{
 
 
 
 
280	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
281	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
282	u8 value[NUM_8_BIT_RTC_REGS];
283	u32 secs;
284	int rc;
285
286	secs = rtc_tm_to_time64(&alarm->time);
287	secs -= rtc_dd->offset;
288	put_unaligned_le32(secs, value);
289
290	rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
291				regs->alarm_en, 0);
292	if (rc)
293		return rc;
 
 
294
295	rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
296			       sizeof(value));
 
 
 
 
 
 
297	if (rc)
298		return rc;
299
300	if (alarm->enabled) {
301		rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
302					regs->alarm_en, regs->alarm_en);
303		if (rc)
304			return rc;
305	}
306
307	dev_dbg(dev, "set alarm: %ptRd %ptRt\n", &alarm->time, &alarm->time);
 
 
 
 
308
309	return 0;
 
 
 
 
310}
311
312static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
313{
 
 
 
 
314	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
315	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
316	u8 value[NUM_8_BIT_RTC_REGS];
317	unsigned int ctrl_reg;
318	u32 secs;
319	int rc;
320
321	rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
322			      sizeof(value));
323	if (rc)
 
324		return rc;
 
 
 
 
325
326	secs = get_unaligned_le32(value);
327	secs += rtc_dd->offset;
328	rtc_time64_to_tm(secs, &alarm->time);
329
330	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
331	if (rc)
 
332		return rc;
333
334	alarm->enabled = !!(ctrl_reg & PM8xxx_RTC_ALARM_ENABLE);
335
336	dev_dbg(dev, "read alarm: %ptRd %ptRt\n", &alarm->time, &alarm->time);
 
337
338	return 0;
339}
340
341static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
342{
 
 
343	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
344	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
 
345	u8 value[NUM_8_BIT_RTC_REGS] = {0};
346	unsigned int val;
347	int rc;
 
 
 
 
348
349	if (enable)
350		val = regs->alarm_en;
351	else
352		val = 0;
353
354	rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
355				regs->alarm_en, val);
356	if (rc)
357		return rc;
 
358
359	/* Clear alarm register */
360	if (!enable) {
361		rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
362				       sizeof(value));
363		if (rc)
364			return rc;
 
 
365	}
366
367	return 0;
 
 
368}
369
370static const struct rtc_class_ops pm8xxx_rtc_ops = {
371	.read_time	= pm8xxx_rtc_read_time,
372	.set_time	= pm8xxx_rtc_set_time,
373	.set_alarm	= pm8xxx_rtc_set_alarm,
374	.read_alarm	= pm8xxx_rtc_read_alarm,
375	.alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
376};
377
378static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
379{
380	struct pm8xxx_rtc *rtc_dd = dev_id;
381	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
 
382	int rc;
383
384	rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
385
386	/* Disable alarm */
387	rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
388				regs->alarm_en, 0);
389	if (rc)
390		return IRQ_NONE;
 
 
 
 
 
391
392	/* Clear alarm status */
393	rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl2,
394				PM8xxx_RTC_ALARM_CLEAR, 0);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
395	if (rc)
396		return IRQ_NONE;
 
397
 
398	return IRQ_HANDLED;
399}
400
401static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
402{
403	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
404
405	return regmap_update_bits(rtc_dd->regmap, regs->ctrl, PM8xxx_RTC_ENABLE,
406				  PM8xxx_RTC_ENABLE);
407}
408
409static const struct pm8xxx_rtc_regs pm8921_regs = {
410	.ctrl		= 0x11d,
411	.write		= 0x11f,
412	.read		= 0x123,
413	.alarm_rw	= 0x127,
414	.alarm_ctrl	= 0x11d,
415	.alarm_ctrl2	= 0x11e,
416	.alarm_en	= BIT(1),
417};
418
419static const struct pm8xxx_rtc_regs pm8058_regs = {
420	.ctrl		= 0x1e8,
421	.write		= 0x1ea,
422	.read		= 0x1ee,
423	.alarm_rw	= 0x1f2,
424	.alarm_ctrl	= 0x1e8,
425	.alarm_ctrl2	= 0x1e9,
426	.alarm_en	= BIT(1),
427};
428
429static const struct pm8xxx_rtc_regs pm8941_regs = {
430	.ctrl		= 0x6046,
431	.write		= 0x6040,
432	.read		= 0x6048,
433	.alarm_rw	= 0x6140,
434	.alarm_ctrl	= 0x6146,
435	.alarm_ctrl2	= 0x6148,
436	.alarm_en	= BIT(7),
437};
438
439static const struct pm8xxx_rtc_regs pmk8350_regs = {
440	.ctrl		= 0x6146,
441	.write		= 0x6140,
442	.read		= 0x6148,
443	.alarm_rw	= 0x6240,
444	.alarm_ctrl	= 0x6246,
445	.alarm_ctrl2	= 0x6248,
446	.alarm_en	= BIT(7),
447};
448
 
 
 
449static const struct of_device_id pm8xxx_id_table[] = {
450	{ .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
451	{ .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
452	{ .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
453	{ .compatible = "qcom,pmk8350-rtc", .data = &pmk8350_regs },
454	{ },
455};
456MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
457
458static int pm8xxx_rtc_probe(struct platform_device *pdev)
459{
460	const struct of_device_id *match;
461	struct pm8xxx_rtc *rtc_dd;
462	int rc;
 
 
463
464	match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
465	if (!match)
466		return -ENXIO;
467
468	rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
469	if (rtc_dd == NULL)
470		return -ENOMEM;
471
 
 
 
472	rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
473	if (!rtc_dd->regmap)
 
474		return -ENXIO;
 
475
476	rtc_dd->alarm_irq = platform_get_irq(pdev, 0);
477	if (rtc_dd->alarm_irq < 0)
478		return -ENXIO;
479
480	rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
481						      "allow-set-time");
482
483	rtc_dd->nvmem_cell = devm_nvmem_cell_get(&pdev->dev, "offset");
484	if (IS_ERR(rtc_dd->nvmem_cell)) {
485		rc = PTR_ERR(rtc_dd->nvmem_cell);
486		if (rc != -ENOENT)
487			return rc;
488		rtc_dd->nvmem_cell = NULL;
489	}
490
491	rtc_dd->regs = match->data;
492	rtc_dd->dev = &pdev->dev;
493
494	if (!rtc_dd->allow_set_time) {
495		rc = pm8xxx_rtc_read_offset(rtc_dd);
496		if (rc)
497			return rc;
498	}
499
500	rc = pm8xxx_rtc_enable(rtc_dd);
501	if (rc)
502		return rc;
503
504	platform_set_drvdata(pdev, rtc_dd);
505
506	device_init_wakeup(&pdev->dev, 1);
507
 
508	rtc_dd->rtc = devm_rtc_allocate_device(&pdev->dev);
509	if (IS_ERR(rtc_dd->rtc))
510		return PTR_ERR(rtc_dd->rtc);
511
512	rtc_dd->rtc->ops = &pm8xxx_rtc_ops;
513	rtc_dd->rtc->range_max = U32_MAX;
514
515	rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->alarm_irq,
 
516					  pm8xxx_alarm_trigger,
517					  IRQF_TRIGGER_RISING,
518					  "pm8xxx_rtc_alarm", rtc_dd);
519	if (rc < 0)
 
520		return rc;
 
521
522	rc = devm_rtc_register_device(rtc_dd->rtc);
523	if (rc)
524		return rc;
525
526	rc = dev_pm_set_wake_irq(&pdev->dev, rtc_dd->alarm_irq);
527	if (rc)
528		return rc;
529
530	return 0;
531}
532
533static void pm8xxx_remove(struct platform_device *pdev)
534{
535	dev_pm_clear_wake_irq(&pdev->dev);
 
536}
537
538static struct platform_driver pm8xxx_rtc_driver = {
539	.probe		= pm8xxx_rtc_probe,
540	.remove_new	= pm8xxx_remove,
541	.driver	= {
542		.name		= "rtc-pm8xxx",
543		.of_match_table	= pm8xxx_id_table,
544	},
545};
546
547module_platform_driver(pm8xxx_rtc_driver);
548
549MODULE_ALIAS("platform:rtc-pm8xxx");
550MODULE_DESCRIPTION("PMIC8xxx RTC driver");
551MODULE_LICENSE("GPL v2");
552MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");
553MODULE_AUTHOR("Johan Hovold <johan@kernel.org>");
v6.2
  1// SPDX-License-Identifier: GPL-2.0-only
  2/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
 
 
 
 
  3 */
  4#include <linux/of.h>
  5#include <linux/module.h>
 
  6#include <linux/init.h>
  7#include <linux/rtc.h>
  8#include <linux/platform_device.h>
  9#include <linux/pm.h>
 10#include <linux/pm_wakeirq.h>
 11#include <linux/regmap.h>
 12#include <linux/slab.h>
 13#include <linux/spinlock.h>
 14
 15/* RTC Register offsets from RTC CTRL REG */
 16#define PM8XXX_ALARM_CTRL_OFFSET	0x01
 17#define PM8XXX_RTC_WRITE_OFFSET		0x02
 18#define PM8XXX_RTC_READ_OFFSET		0x06
 19#define PM8XXX_ALARM_RW_OFFSET		0x0A
 20
 21/* RTC_CTRL register bit fields */
 22#define PM8xxx_RTC_ENABLE		BIT(7)
 23#define PM8xxx_RTC_ALARM_CLEAR		BIT(0)
 24#define PM8xxx_RTC_ALARM_ENABLE		BIT(7)
 25
 26#define NUM_8_BIT_RTC_REGS		0x4
 27
 28/**
 29 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
 30 * @ctrl: base address of control register
 31 * @write: base address of write register
 32 * @read: base address of read register
 33 * @alarm_ctrl: base address of alarm control register
 34 * @alarm_ctrl2: base address of alarm control2 register
 35 * @alarm_rw: base address of alarm read-write register
 36 * @alarm_en: alarm enable mask
 37 */
 38struct pm8xxx_rtc_regs {
 39	unsigned int ctrl;
 40	unsigned int write;
 41	unsigned int read;
 42	unsigned int alarm_ctrl;
 43	unsigned int alarm_ctrl2;
 44	unsigned int alarm_rw;
 45	unsigned int alarm_en;
 46};
 47
 48/**
 49 * struct pm8xxx_rtc -  rtc driver internal structure
 50 * @rtc:		rtc device for this driver.
 51 * @regmap:		regmap used to access RTC registers
 52 * @allow_set_time:	indicates whether writing to the RTC is allowed
 53 * @rtc_alarm_irq:	rtc alarm irq number.
 54 * @regs:		rtc registers description.
 55 * @rtc_dev:		device structure.
 56 * @ctrl_reg_lock:	spinlock protecting access to ctrl_reg.
 
 57 */
 58struct pm8xxx_rtc {
 59	struct rtc_device *rtc;
 60	struct regmap *regmap;
 61	bool allow_set_time;
 62	int rtc_alarm_irq;
 63	const struct pm8xxx_rtc_regs *regs;
 64	struct device *rtc_dev;
 65	spinlock_t ctrl_reg_lock;
 
 66};
 67
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 68/*
 69 * Steps to write the RTC registers.
 70 * 1. Disable alarm if enabled.
 71 * 2. Disable rtc if enabled.
 72 * 3. Write 0x00 to LSB.
 73 * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
 74 * 5. Enable rtc if disabled in step 2.
 75 * 6. Enable alarm if disabled in step 1.
 76 */
 77static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
 78{
 79	int rc, i;
 80	unsigned long secs, irq_flags;
 81	u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, rtc_disabled = 0;
 82	unsigned int ctrl_reg, rtc_ctrl_reg;
 83	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
 84	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
 
 
 
 85
 86	if (!rtc_dd->allow_set_time)
 87		return -ENODEV;
 88
 89	secs = rtc_tm_to_time64(tm);
 90
 91	dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
 92
 93	for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
 94		value[i] = secs & 0xFF;
 95		secs >>= 8;
 96	}
 97
 98	spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
 99
100	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
101	if (rc)
102		goto rtc_rw_fail;
103
104	if (ctrl_reg & regs->alarm_en) {
105		alarm_enabled = 1;
106		ctrl_reg &= ~regs->alarm_en;
107		rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
108		if (rc) {
109			dev_err(dev, "Write to RTC Alarm control register failed\n");
110			goto rtc_rw_fail;
111		}
112	}
113
114	/* Disable RTC H/w before writing on RTC register */
115	rc = regmap_read(rtc_dd->regmap, regs->ctrl, &rtc_ctrl_reg);
116	if (rc)
117		goto rtc_rw_fail;
118
119	if (rtc_ctrl_reg & PM8xxx_RTC_ENABLE) {
120		rtc_disabled = 1;
121		rtc_ctrl_reg &= ~PM8xxx_RTC_ENABLE;
122		rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
123		if (rc) {
124			dev_err(dev, "Write to RTC control register failed\n");
125			goto rtc_rw_fail;
126		}
127	}
128
129	/* Write 0 to Byte[0] */
130	rc = regmap_write(rtc_dd->regmap, regs->write, 0);
131	if (rc) {
132		dev_err(dev, "Write to RTC write data register failed\n");
133		goto rtc_rw_fail;
134	}
135
136	/* Write Byte[1], Byte[2], Byte[3] */
137	rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
138			       &value[1], sizeof(value) - 1);
139	if (rc) {
140		dev_err(dev, "Write to RTC write data register failed\n");
141		goto rtc_rw_fail;
142	}
143
144	/* Write Byte[0] */
145	rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
146	if (rc) {
147		dev_err(dev, "Write to RTC write data register failed\n");
148		goto rtc_rw_fail;
149	}
150
151	/* Enable RTC H/w after writing on RTC register */
152	if (rtc_disabled) {
153		rtc_ctrl_reg |= PM8xxx_RTC_ENABLE;
154		rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
155		if (rc) {
156			dev_err(dev, "Write to RTC control register failed\n");
157			goto rtc_rw_fail;
158		}
159	}
160
161	if (alarm_enabled) {
162		ctrl_reg |= regs->alarm_en;
163		rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
164		if (rc) {
165			dev_err(dev, "Write to RTC Alarm control register failed\n");
166			goto rtc_rw_fail;
167		}
168	}
169
170rtc_rw_fail:
171	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
172
173	return rc;
174}
175
176static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
177{
 
 
178	int rc;
179	u8 value[NUM_8_BIT_RTC_REGS];
180	unsigned long secs;
181	unsigned int reg;
182	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
183	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
184
185	rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
186	if (rc) {
187		dev_err(dev, "RTC read data register failed\n");
 
 
 
 
 
188		return rc;
189	}
190
191	/*
192	 * Read the LSB again and check if there has been a carry over.
193	 * If there is, redo the read operation.
194	 */
195	rc = regmap_read(rtc_dd->regmap, regs->read, &reg);
196	if (rc < 0) {
197		dev_err(dev, "RTC read data register failed\n");
198		return rc;
199	}
200
201	if (unlikely(reg < value[0])) {
202		rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
203				      value, sizeof(value));
204		if (rc) {
205			dev_err(dev, "RTC read data register failed\n");
206			return rc;
207		}
208	}
209
210	secs = value[0] | (value[1] << 8) | (value[2] << 16) |
211	       ((unsigned long)value[3] << 24);
 
212
 
213	rtc_time64_to_tm(secs, tm);
214
215	dev_dbg(dev, "secs = %lu, h:m:s == %ptRt, y-m-d = %ptRdr\n", secs, tm, tm);
216
217	return 0;
218}
219
220static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
221{
222	int rc, i;
223	u8 value[NUM_8_BIT_RTC_REGS];
224	unsigned int ctrl_reg;
225	unsigned long secs, irq_flags;
226	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
227	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
 
 
 
228
229	secs = rtc_tm_to_time64(&alarm->time);
 
 
230
231	for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
232		value[i] = secs & 0xFF;
233		secs >>= 8;
234	}
235
236	spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
237
238	rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
239			       sizeof(value));
240	if (rc) {
241		dev_err(dev, "Write to RTC ALARM register failed\n");
242		goto rtc_rw_fail;
243	}
244
245	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
246	if (rc)
247		goto rtc_rw_fail;
248
249	if (alarm->enabled)
250		ctrl_reg |= regs->alarm_en;
251	else
252		ctrl_reg &= ~regs->alarm_en;
 
 
253
254	rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
255	if (rc) {
256		dev_err(dev, "Write to RTC alarm control register failed\n");
257		goto rtc_rw_fail;
258	}
259
260	dev_dbg(dev, "Alarm Set for h:m:s=%ptRt, y-m-d=%ptRdr\n",
261		&alarm->time, &alarm->time);
262rtc_rw_fail:
263	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
264	return rc;
265}
266
267static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
268{
269	int rc;
270	unsigned int ctrl_reg;
271	u8 value[NUM_8_BIT_RTC_REGS];
272	unsigned long secs;
273	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
274	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
 
 
 
 
275
276	rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
277			      sizeof(value));
278	if (rc) {
279		dev_err(dev, "RTC alarm time read failed\n");
280		return rc;
281	}
282
283	secs = value[0] | (value[1] << 8) | (value[2] << 16) |
284	       ((unsigned long)value[3] << 24);
285
 
 
286	rtc_time64_to_tm(secs, &alarm->time);
287
288	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
289	if (rc) {
290		dev_err(dev, "Read from RTC alarm control register failed\n");
291		return rc;
292	}
293	alarm->enabled = !!(ctrl_reg & PM8xxx_RTC_ALARM_ENABLE);
294
295	dev_dbg(dev, "Alarm set for - h:m:s=%ptRt, y-m-d=%ptRdr\n",
296		&alarm->time, &alarm->time);
297
298	return 0;
299}
300
301static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
302{
303	int rc;
304	unsigned long irq_flags;
305	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
306	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
307	unsigned int ctrl_reg;
308	u8 value[NUM_8_BIT_RTC_REGS] = {0};
309
310	spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
311
312	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
313	if (rc)
314		goto rtc_rw_fail;
315
316	if (enable)
317		ctrl_reg |= regs->alarm_en;
318	else
319		ctrl_reg &= ~regs->alarm_en;
320
321	rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
322	if (rc) {
323		dev_err(dev, "Write to RTC control register failed\n");
324		goto rtc_rw_fail;
325	}
326
327	/* Clear Alarm register */
328	if (!enable) {
329		rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
330				       sizeof(value));
331		if (rc) {
332			dev_err(dev, "Clear RTC ALARM register failed\n");
333			goto rtc_rw_fail;
334		}
335	}
336
337rtc_rw_fail:
338	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
339	return rc;
340}
341
342static const struct rtc_class_ops pm8xxx_rtc_ops = {
343	.read_time	= pm8xxx_rtc_read_time,
344	.set_time	= pm8xxx_rtc_set_time,
345	.set_alarm	= pm8xxx_rtc_set_alarm,
346	.read_alarm	= pm8xxx_rtc_read_alarm,
347	.alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
348};
349
350static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
351{
352	struct pm8xxx_rtc *rtc_dd = dev_id;
353	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
354	unsigned int ctrl_reg;
355	int rc;
356
357	rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
358
359	spin_lock(&rtc_dd->ctrl_reg_lock);
360
361	/* Clear the alarm enable bit */
362	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
363	if (rc) {
364		spin_unlock(&rtc_dd->ctrl_reg_lock);
365		goto rtc_alarm_handled;
366	}
367
368	ctrl_reg &= ~regs->alarm_en;
369
370	rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
371	if (rc) {
372		spin_unlock(&rtc_dd->ctrl_reg_lock);
373		dev_err(rtc_dd->rtc_dev,
374			"Write to alarm control register failed\n");
375		goto rtc_alarm_handled;
376	}
377
378	spin_unlock(&rtc_dd->ctrl_reg_lock);
379
380	/* Clear RTC alarm register */
381	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
382	if (rc) {
383		dev_err(rtc_dd->rtc_dev,
384			"RTC Alarm control2 register read failed\n");
385		goto rtc_alarm_handled;
386	}
387
388	ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
389	rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
390	if (rc)
391		dev_err(rtc_dd->rtc_dev,
392			"Write to RTC Alarm control2 register failed\n");
393
394rtc_alarm_handled:
395	return IRQ_HANDLED;
396}
397
398static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
399{
400	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
401	unsigned int ctrl_reg;
402	int rc;
403
404	/* Check if the RTC is on, else turn it on */
405	rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
406	if (rc)
407		return rc;
408
409	if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
410		ctrl_reg |= PM8xxx_RTC_ENABLE;
411		rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
412		if (rc)
413			return rc;
414	}
415
416	return 0;
 
417}
418
419static const struct pm8xxx_rtc_regs pm8921_regs = {
420	.ctrl		= 0x11d,
421	.write		= 0x11f,
422	.read		= 0x123,
423	.alarm_rw	= 0x127,
424	.alarm_ctrl	= 0x11d,
425	.alarm_ctrl2	= 0x11e,
426	.alarm_en	= BIT(1),
427};
428
429static const struct pm8xxx_rtc_regs pm8058_regs = {
430	.ctrl		= 0x1e8,
431	.write		= 0x1ea,
432	.read		= 0x1ee,
433	.alarm_rw	= 0x1f2,
434	.alarm_ctrl	= 0x1e8,
435	.alarm_ctrl2	= 0x1e9,
436	.alarm_en	= BIT(1),
437};
438
439static const struct pm8xxx_rtc_regs pm8941_regs = {
440	.ctrl		= 0x6046,
441	.write		= 0x6040,
442	.read		= 0x6048,
443	.alarm_rw	= 0x6140,
444	.alarm_ctrl	= 0x6146,
445	.alarm_ctrl2	= 0x6148,
446	.alarm_en	= BIT(7),
447};
448
449static const struct pm8xxx_rtc_regs pmk8350_regs = {
450	.ctrl		= 0x6146,
451	.write		= 0x6140,
452	.read		= 0x6148,
453	.alarm_rw	= 0x6240,
454	.alarm_ctrl	= 0x6246,
455	.alarm_ctrl2	= 0x6248,
456	.alarm_en	= BIT(7),
457};
458
459/*
460 * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
461 */
462static const struct of_device_id pm8xxx_id_table[] = {
463	{ .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
464	{ .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
465	{ .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
466	{ .compatible = "qcom,pmk8350-rtc", .data = &pmk8350_regs },
467	{ },
468};
469MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
470
471static int pm8xxx_rtc_probe(struct platform_device *pdev)
472{
 
 
473	int rc;
474	struct pm8xxx_rtc *rtc_dd;
475	const struct of_device_id *match;
476
477	match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
478	if (!match)
479		return -ENXIO;
480
481	rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
482	if (rtc_dd == NULL)
483		return -ENOMEM;
484
485	/* Initialise spinlock to protect RTC control register */
486	spin_lock_init(&rtc_dd->ctrl_reg_lock);
487
488	rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
489	if (!rtc_dd->regmap) {
490		dev_err(&pdev->dev, "Parent regmap unavailable.\n");
491		return -ENXIO;
492	}
493
494	rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
495	if (rtc_dd->rtc_alarm_irq < 0)
496		return -ENXIO;
497
498	rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
499						      "allow-set-time");
500
 
 
 
 
 
 
 
 
501	rtc_dd->regs = match->data;
502	rtc_dd->rtc_dev = &pdev->dev;
 
 
 
 
 
 
503
504	rc = pm8xxx_rtc_enable(rtc_dd);
505	if (rc)
506		return rc;
507
508	platform_set_drvdata(pdev, rtc_dd);
509
510	device_init_wakeup(&pdev->dev, 1);
511
512	/* Register the RTC device */
513	rtc_dd->rtc = devm_rtc_allocate_device(&pdev->dev);
514	if (IS_ERR(rtc_dd->rtc))
515		return PTR_ERR(rtc_dd->rtc);
516
517	rtc_dd->rtc->ops = &pm8xxx_rtc_ops;
518	rtc_dd->rtc->range_max = U32_MAX;
519
520	/* Request the alarm IRQ */
521	rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
522					  pm8xxx_alarm_trigger,
523					  IRQF_TRIGGER_RISING,
524					  "pm8xxx_rtc_alarm", rtc_dd);
525	if (rc < 0) {
526		dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
527		return rc;
528	}
529
530	rc = devm_rtc_register_device(rtc_dd->rtc);
531	if (rc)
532		return rc;
533
534	rc = dev_pm_set_wake_irq(&pdev->dev, rtc_dd->rtc_alarm_irq);
535	if (rc)
536		return rc;
537
538	return 0;
539}
540
541static int pm8xxx_remove(struct platform_device *pdev)
542{
543	dev_pm_clear_wake_irq(&pdev->dev);
544	return 0;
545}
546
547static struct platform_driver pm8xxx_rtc_driver = {
548	.probe		= pm8xxx_rtc_probe,
549	.remove		= pm8xxx_remove,
550	.driver	= {
551		.name		= "rtc-pm8xxx",
552		.of_match_table	= pm8xxx_id_table,
553	},
554};
555
556module_platform_driver(pm8xxx_rtc_driver);
557
558MODULE_ALIAS("platform:rtc-pm8xxx");
559MODULE_DESCRIPTION("PMIC8xxx RTC driver");
560MODULE_LICENSE("GPL v2");
561MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");