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1/*
2 * Atmel AT91 SAM9 & SAMA5 SoCs reset code
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 * Copyright (C) BitBox Ltd 2010
6 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
7 * Copyright (C) 2014 Free Electrons
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/module.h>
17#include <linux/of_address.h>
18#include <linux/platform_device.h>
19#include <linux/reboot.h>
20#include <linux/reset-controller.h>
21#include <linux/power/power_on_reason.h>
22
23#include <soc/at91/at91sam9_ddrsdr.h>
24#include <soc/at91/at91sam9_sdramc.h>
25
26#include <dt-bindings/reset/sama7g5-reset.h>
27
28#define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */
29#define AT91_RSTC_PROCRST BIT(0) /* Processor Reset */
30#define AT91_RSTC_PERRST BIT(2) /* Peripheral Reset */
31#define AT91_RSTC_EXTRST BIT(3) /* External Reset */
32#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
33
34#define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */
35#define AT91_RSTC_URSTS BIT(0) /* User Reset Status */
36#define AT91_RSTC_RSTTYP GENMASK(10, 8) /* Reset Type */
37#define AT91_RSTC_NRSTL BIT(16) /* NRST Pin Level */
38#define AT91_RSTC_SRCMP BIT(17) /* Software Reset Command in Progress */
39
40#define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */
41#define AT91_RSTC_URSTEN BIT(0) /* User Reset Enable */
42#define AT91_RSTC_URSTASYNC BIT(2) /* User Reset Asynchronous Control */
43#define AT91_RSTC_URSTIEN BIT(4) /* User Reset Interrupt Enable */
44#define AT91_RSTC_ERSTL GENMASK(11, 8) /* External Reset Length */
45
46/**
47 * enum reset_type - reset types
48 * @RESET_TYPE_GENERAL: first power-up reset
49 * @RESET_TYPE_WAKEUP: return from backup mode
50 * @RESET_TYPE_WATCHDOG: watchdog fault
51 * @RESET_TYPE_SOFTWARE: processor reset required by software
52 * @RESET_TYPE_USER: NRST pin detected low
53 * @RESET_TYPE_CPU_FAIL: CPU clock failure detection
54 * @RESET_TYPE_XTAL_FAIL: 32KHz crystal failure dectection fault
55 * @RESET_TYPE_ULP2: ULP2 reset
56 */
57enum reset_type {
58 RESET_TYPE_GENERAL = 0,
59 RESET_TYPE_WAKEUP = 1,
60 RESET_TYPE_WATCHDOG = 2,
61 RESET_TYPE_SOFTWARE = 3,
62 RESET_TYPE_USER = 4,
63 RESET_TYPE_CPU_FAIL = 6,
64 RESET_TYPE_XTAL_FAIL = 7,
65 RESET_TYPE_ULP2 = 8,
66};
67
68/**
69 * struct at91_reset - AT91 reset specific data structure
70 * @rstc_base: base address for system reset
71 * @ramc_base: array with base addresses of RAM controllers
72 * @dev_base: base address for devices reset
73 * @sclk: slow clock
74 * @data: platform specific reset data
75 * @rcdev: reset controller device
76 * @lock: lock for devices reset register access
77 * @nb: reset notifier block
78 * @args: SoC specific system reset arguments
79 * @ramc_lpr: SDRAM Controller Low Power Register
80 */
81struct at91_reset {
82 void __iomem *rstc_base;
83 void __iomem *ramc_base[2];
84 void __iomem *dev_base;
85 struct clk *sclk;
86 const struct at91_reset_data *data;
87 struct reset_controller_dev rcdev;
88 spinlock_t lock;
89 struct notifier_block nb;
90 u32 args;
91 u32 ramc_lpr;
92};
93
94#define to_at91_reset(r) container_of(r, struct at91_reset, rcdev)
95
96/**
97 * struct at91_reset_data - AT91 reset data
98 * @reset_args: SoC specific system reset arguments
99 * @n_device_reset: number of device resets
100 * @device_reset_min_id: min id for device reset
101 * @device_reset_max_id: max id for device reset
102 */
103struct at91_reset_data {
104 u32 reset_args;
105 u32 n_device_reset;
106 u8 device_reset_min_id;
107 u8 device_reset_max_id;
108};
109
110/*
111* unless the SDRAM is cleanly shutdown before we hit the
112* reset register it can be left driving the data bus and
113* killing the chance of a subsequent boot from NAND
114*/
115static int at91_reset(struct notifier_block *this, unsigned long mode,
116 void *cmd)
117{
118 struct at91_reset *reset = container_of(this, struct at91_reset, nb);
119
120 asm volatile(
121 /* Align to cache lines */
122 ".balign 32\n\t"
123
124 /* Disable SDRAM0 accesses */
125 " tst %0, #0\n\t"
126 " beq 1f\n\t"
127 " str %3, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
128 /* Power down SDRAM0 */
129 " str %4, [%0, %6]\n\t"
130 /* Disable SDRAM1 accesses */
131 "1: tst %1, #0\n\t"
132 " beq 2f\n\t"
133 " strne %3, [%1, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
134 /* Power down SDRAM1 */
135 " strne %4, [%1, %6]\n\t"
136 /* Reset CPU */
137 "2: str %5, [%2, #" __stringify(AT91_RSTC_CR) "]\n\t"
138
139 " b .\n\t"
140 :
141 : "r" (reset->ramc_base[0]),
142 "r" (reset->ramc_base[1]),
143 "r" (reset->rstc_base),
144 "r" (1),
145 "r" cpu_to_le32(AT91_DDRSDRC_LPCB_POWER_DOWN),
146 "r" (reset->data->reset_args),
147 "r" (reset->ramc_lpr)
148 : "r4");
149
150 return NOTIFY_DONE;
151}
152
153static const char *at91_reset_reason(struct at91_reset *reset)
154{
155 u32 reg = readl(reset->rstc_base + AT91_RSTC_SR);
156 const char *reason;
157
158 switch ((reg & AT91_RSTC_RSTTYP) >> 8) {
159 case RESET_TYPE_GENERAL:
160 reason = POWER_ON_REASON_REGULAR;
161 break;
162 case RESET_TYPE_WAKEUP:
163 reason = POWER_ON_REASON_RTC;
164 break;
165 case RESET_TYPE_WATCHDOG:
166 reason = POWER_ON_REASON_WATCHDOG;
167 break;
168 case RESET_TYPE_SOFTWARE:
169 reason = POWER_ON_REASON_SOFTWARE;
170 break;
171 case RESET_TYPE_USER:
172 reason = POWER_ON_REASON_RST_BTN;
173 break;
174 case RESET_TYPE_CPU_FAIL:
175 reason = POWER_ON_REASON_CPU_CLK_FAIL;
176 break;
177 case RESET_TYPE_XTAL_FAIL:
178 reason = POWER_ON_REASON_XTAL_FAIL;
179 break;
180 case RESET_TYPE_ULP2:
181 reason = POWER_ON_REASON_BROWN_OUT;
182 break;
183 default:
184 reason = POWER_ON_REASON_UNKNOWN;
185 break;
186 }
187
188 return reason;
189}
190
191static ssize_t power_on_reason_show(struct device *dev,
192 struct device_attribute *attr, char *buf)
193{
194 struct platform_device *pdev = to_platform_device(dev);
195 struct at91_reset *reset = platform_get_drvdata(pdev);
196
197 return sprintf(buf, "%s\n", at91_reset_reason(reset));
198}
199static DEVICE_ATTR_RO(power_on_reason);
200
201static const struct of_device_id at91_ramc_of_match[] = {
202 {
203 .compatible = "atmel,at91sam9260-sdramc",
204 .data = (void *)AT91_SDRAMC_LPR,
205 },
206 {
207 .compatible = "atmel,at91sam9g45-ddramc",
208 .data = (void *)AT91_DDRSDRC_LPR,
209 },
210 { /* sentinel */ }
211};
212
213static const struct at91_reset_data sam9260 = {
214 .reset_args = AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST,
215};
216
217static const struct at91_reset_data samx7 = {
218 .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST,
219};
220
221static const struct at91_reset_data sama7g5 = {
222 .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST,
223 .n_device_reset = 3,
224 .device_reset_min_id = SAMA7G5_RESET_USB_PHY1,
225 .device_reset_max_id = SAMA7G5_RESET_USB_PHY3,
226};
227
228static const struct of_device_id at91_reset_of_match[] = {
229 {
230 .compatible = "atmel,at91sam9260-rstc",
231 .data = &sam9260,
232 },
233 {
234 .compatible = "atmel,at91sam9g45-rstc",
235 .data = &sam9260,
236 },
237 {
238 .compatible = "atmel,sama5d3-rstc",
239 .data = &sam9260,
240 },
241 {
242 .compatible = "atmel,samx7-rstc",
243 .data = &samx7,
244 },
245 {
246 .compatible = "microchip,sam9x60-rstc",
247 .data = &samx7,
248 },
249 {
250 .compatible = "microchip,sama7g5-rstc",
251 .data = &sama7g5,
252 },
253 { /* sentinel */ }
254};
255MODULE_DEVICE_TABLE(of, at91_reset_of_match);
256
257static int at91_reset_update(struct reset_controller_dev *rcdev,
258 unsigned long id, bool assert)
259{
260 struct at91_reset *reset = to_at91_reset(rcdev);
261 unsigned long flags;
262 u32 val;
263
264 spin_lock_irqsave(&reset->lock, flags);
265 val = readl_relaxed(reset->dev_base);
266 if (assert)
267 val |= BIT(id);
268 else
269 val &= ~BIT(id);
270 writel_relaxed(val, reset->dev_base);
271 spin_unlock_irqrestore(&reset->lock, flags);
272
273 return 0;
274}
275
276static int at91_reset_assert(struct reset_controller_dev *rcdev,
277 unsigned long id)
278{
279 return at91_reset_update(rcdev, id, true);
280}
281
282static int at91_reset_deassert(struct reset_controller_dev *rcdev,
283 unsigned long id)
284{
285 return at91_reset_update(rcdev, id, false);
286}
287
288static int at91_reset_dev_status(struct reset_controller_dev *rcdev,
289 unsigned long id)
290{
291 struct at91_reset *reset = to_at91_reset(rcdev);
292 u32 val;
293
294 val = readl_relaxed(reset->dev_base);
295
296 return !!(val & BIT(id));
297}
298
299static const struct reset_control_ops at91_reset_ops = {
300 .assert = at91_reset_assert,
301 .deassert = at91_reset_deassert,
302 .status = at91_reset_dev_status,
303};
304
305static int at91_reset_of_xlate(struct reset_controller_dev *rcdev,
306 const struct of_phandle_args *reset_spec)
307{
308 struct at91_reset *reset = to_at91_reset(rcdev);
309
310 if (!reset->data->n_device_reset ||
311 (reset_spec->args[0] < reset->data->device_reset_min_id ||
312 reset_spec->args[0] > reset->data->device_reset_max_id))
313 return -EINVAL;
314
315 return reset_spec->args[0];
316}
317
318static int at91_rcdev_init(struct at91_reset *reset,
319 struct platform_device *pdev)
320{
321 if (!reset->data->n_device_reset)
322 return 0;
323
324 reset->dev_base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 1,
325 NULL);
326 if (IS_ERR(reset->dev_base))
327 return -ENODEV;
328
329 spin_lock_init(&reset->lock);
330 reset->rcdev.ops = &at91_reset_ops;
331 reset->rcdev.owner = THIS_MODULE;
332 reset->rcdev.of_node = pdev->dev.of_node;
333 reset->rcdev.nr_resets = reset->data->n_device_reset;
334 reset->rcdev.of_reset_n_cells = 1;
335 reset->rcdev.of_xlate = at91_reset_of_xlate;
336
337 return devm_reset_controller_register(&pdev->dev, &reset->rcdev);
338}
339
340static int at91_reset_probe(struct platform_device *pdev)
341{
342 const struct of_device_id *match;
343 struct at91_reset *reset;
344 struct device_node *np;
345 int ret, idx = 0;
346
347 reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
348 if (!reset)
349 return -ENOMEM;
350
351 reset->rstc_base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
352 if (IS_ERR(reset->rstc_base)) {
353 dev_err(&pdev->dev, "Could not map reset controller address\n");
354 return -ENODEV;
355 }
356
357 if (!of_device_is_compatible(pdev->dev.of_node, "atmel,sama5d3-rstc")) {
358 /* we need to shutdown the ddr controller, so get ramc base */
359 for_each_matching_node_and_match(np, at91_ramc_of_match, &match) {
360 reset->ramc_lpr = (u32)match->data;
361 reset->ramc_base[idx] = devm_of_iomap(&pdev->dev, np, 0, NULL);
362 if (IS_ERR(reset->ramc_base[idx])) {
363 dev_err(&pdev->dev, "Could not map ram controller address\n");
364 of_node_put(np);
365 return -ENODEV;
366 }
367 idx++;
368 }
369 }
370
371 reset->data = device_get_match_data(&pdev->dev);
372 if (!reset->data)
373 return -ENODEV;
374
375 reset->nb.notifier_call = at91_reset;
376 reset->nb.priority = 192;
377
378 reset->sclk = devm_clk_get(&pdev->dev, NULL);
379 if (IS_ERR(reset->sclk))
380 return PTR_ERR(reset->sclk);
381
382 ret = clk_prepare_enable(reset->sclk);
383 if (ret) {
384 dev_err(&pdev->dev, "Could not enable slow clock\n");
385 return ret;
386 }
387
388 platform_set_drvdata(pdev, reset);
389
390 ret = at91_rcdev_init(reset, pdev);
391 if (ret)
392 goto disable_clk;
393
394 if (of_device_is_compatible(pdev->dev.of_node, "microchip,sam9x60-rstc")) {
395 u32 val = readl(reset->rstc_base + AT91_RSTC_MR);
396
397 writel(AT91_RSTC_KEY | AT91_RSTC_URSTASYNC | val,
398 reset->rstc_base + AT91_RSTC_MR);
399 }
400
401 ret = register_restart_handler(&reset->nb);
402 if (ret)
403 goto disable_clk;
404
405 ret = device_create_file(&pdev->dev, &dev_attr_power_on_reason);
406 if (ret) {
407 dev_err(&pdev->dev, "Could not create sysfs entry\n");
408 return ret;
409 }
410
411 dev_info(&pdev->dev, "Starting after %s\n", at91_reset_reason(reset));
412
413 return 0;
414
415disable_clk:
416 clk_disable_unprepare(reset->sclk);
417 return ret;
418}
419
420static void at91_reset_remove(struct platform_device *pdev)
421{
422 struct at91_reset *reset = platform_get_drvdata(pdev);
423
424 unregister_restart_handler(&reset->nb);
425 clk_disable_unprepare(reset->sclk);
426}
427
428static struct platform_driver at91_reset_driver = {
429 .probe = at91_reset_probe,
430 .remove_new = at91_reset_remove,
431 .driver = {
432 .name = "at91-reset",
433 .of_match_table = at91_reset_of_match,
434 },
435};
436module_platform_driver(at91_reset_driver);
437
438MODULE_AUTHOR("Atmel Corporation");
439MODULE_DESCRIPTION("Reset driver for Atmel SoCs");
440MODULE_LICENSE("GPL v2");
1/*
2 * Atmel AT91 SAM9 & SAMA5 SoCs reset code
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 * Copyright (C) BitBox Ltd 2010
6 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
7 * Copyright (C) 2014 Free Electrons
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/module.h>
17#include <linux/of_address.h>
18#include <linux/platform_device.h>
19#include <linux/reboot.h>
20#include <linux/reset-controller.h>
21
22#include <soc/at91/at91sam9_ddrsdr.h>
23#include <soc/at91/at91sam9_sdramc.h>
24
25#include <dt-bindings/reset/sama7g5-reset.h>
26
27#define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */
28#define AT91_RSTC_PROCRST BIT(0) /* Processor Reset */
29#define AT91_RSTC_PERRST BIT(2) /* Peripheral Reset */
30#define AT91_RSTC_EXTRST BIT(3) /* External Reset */
31#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
32
33#define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */
34#define AT91_RSTC_URSTS BIT(0) /* User Reset Status */
35#define AT91_RSTC_RSTTYP GENMASK(10, 8) /* Reset Type */
36#define AT91_RSTC_NRSTL BIT(16) /* NRST Pin Level */
37#define AT91_RSTC_SRCMP BIT(17) /* Software Reset Command in Progress */
38
39#define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */
40#define AT91_RSTC_URSTEN BIT(0) /* User Reset Enable */
41#define AT91_RSTC_URSTASYNC BIT(2) /* User Reset Asynchronous Control */
42#define AT91_RSTC_URSTIEN BIT(4) /* User Reset Interrupt Enable */
43#define AT91_RSTC_ERSTL GENMASK(11, 8) /* External Reset Length */
44
45/**
46 * enum reset_type - reset types
47 * @RESET_TYPE_GENERAL: first power-up reset
48 * @RESET_TYPE_WAKEUP: return from backup mode
49 * @RESET_TYPE_WATCHDOG: watchdog fault
50 * @RESET_TYPE_SOFTWARE: processor reset required by software
51 * @RESET_TYPE_USER: NRST pin detected low
52 * @RESET_TYPE_CPU_FAIL: CPU clock failure detection
53 * @RESET_TYPE_XTAL_FAIL: 32KHz crystal failure dectection fault
54 * @RESET_TYPE_ULP2: ULP2 reset
55 */
56enum reset_type {
57 RESET_TYPE_GENERAL = 0,
58 RESET_TYPE_WAKEUP = 1,
59 RESET_TYPE_WATCHDOG = 2,
60 RESET_TYPE_SOFTWARE = 3,
61 RESET_TYPE_USER = 4,
62 RESET_TYPE_CPU_FAIL = 6,
63 RESET_TYPE_XTAL_FAIL = 7,
64 RESET_TYPE_ULP2 = 8,
65};
66
67/**
68 * struct at91_reset - AT91 reset specific data structure
69 * @rstc_base: base address for system reset
70 * @ramc_base: array with base addresses of RAM controllers
71 * @dev_base: base address for devices reset
72 * @sclk: slow clock
73 * @data: platform specific reset data
74 * @rcdev: reset controller device
75 * @lock: lock for devices reset register access
76 * @nb: reset notifier block
77 * @args: SoC specific system reset arguments
78 * @ramc_lpr: SDRAM Controller Low Power Register
79 */
80struct at91_reset {
81 void __iomem *rstc_base;
82 void __iomem *ramc_base[2];
83 void __iomem *dev_base;
84 struct clk *sclk;
85 const struct at91_reset_data *data;
86 struct reset_controller_dev rcdev;
87 spinlock_t lock;
88 struct notifier_block nb;
89 u32 args;
90 u32 ramc_lpr;
91};
92
93#define to_at91_reset(r) container_of(r, struct at91_reset, rcdev)
94
95/**
96 * struct at91_reset_data - AT91 reset data
97 * @reset_args: SoC specific system reset arguments
98 * @n_device_reset: number of device resets
99 * @device_reset_min_id: min id for device reset
100 * @device_reset_max_id: max id for device reset
101 */
102struct at91_reset_data {
103 u32 reset_args;
104 u32 n_device_reset;
105 u8 device_reset_min_id;
106 u8 device_reset_max_id;
107};
108
109/*
110* unless the SDRAM is cleanly shutdown before we hit the
111* reset register it can be left driving the data bus and
112* killing the chance of a subsequent boot from NAND
113*/
114static int at91_reset(struct notifier_block *this, unsigned long mode,
115 void *cmd)
116{
117 struct at91_reset *reset = container_of(this, struct at91_reset, nb);
118
119 asm volatile(
120 /* Align to cache lines */
121 ".balign 32\n\t"
122
123 /* Disable SDRAM0 accesses */
124 " tst %0, #0\n\t"
125 " beq 1f\n\t"
126 " str %3, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
127 /* Power down SDRAM0 */
128 " str %4, [%0, %6]\n\t"
129 /* Disable SDRAM1 accesses */
130 "1: tst %1, #0\n\t"
131 " beq 2f\n\t"
132 " strne %3, [%1, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
133 /* Power down SDRAM1 */
134 " strne %4, [%1, %6]\n\t"
135 /* Reset CPU */
136 "2: str %5, [%2, #" __stringify(AT91_RSTC_CR) "]\n\t"
137
138 " b .\n\t"
139 :
140 : "r" (reset->ramc_base[0]),
141 "r" (reset->ramc_base[1]),
142 "r" (reset->rstc_base),
143 "r" (1),
144 "r" cpu_to_le32(AT91_DDRSDRC_LPCB_POWER_DOWN),
145 "r" (reset->data->reset_args),
146 "r" (reset->ramc_lpr)
147 : "r4");
148
149 return NOTIFY_DONE;
150}
151
152static void __init at91_reset_status(struct platform_device *pdev,
153 void __iomem *base)
154{
155 const char *reason;
156 u32 reg = readl(base + AT91_RSTC_SR);
157
158 switch ((reg & AT91_RSTC_RSTTYP) >> 8) {
159 case RESET_TYPE_GENERAL:
160 reason = "general reset";
161 break;
162 case RESET_TYPE_WAKEUP:
163 reason = "wakeup";
164 break;
165 case RESET_TYPE_WATCHDOG:
166 reason = "watchdog reset";
167 break;
168 case RESET_TYPE_SOFTWARE:
169 reason = "software reset";
170 break;
171 case RESET_TYPE_USER:
172 reason = "user reset";
173 break;
174 case RESET_TYPE_CPU_FAIL:
175 reason = "CPU clock failure detection";
176 break;
177 case RESET_TYPE_XTAL_FAIL:
178 reason = "32.768 kHz crystal failure detection";
179 break;
180 case RESET_TYPE_ULP2:
181 reason = "ULP2 reset";
182 break;
183 default:
184 reason = "unknown reset";
185 break;
186 }
187
188 dev_info(&pdev->dev, "Starting after %s\n", reason);
189}
190
191static const struct of_device_id at91_ramc_of_match[] = {
192 {
193 .compatible = "atmel,at91sam9260-sdramc",
194 .data = (void *)AT91_SDRAMC_LPR,
195 },
196 {
197 .compatible = "atmel,at91sam9g45-ddramc",
198 .data = (void *)AT91_DDRSDRC_LPR,
199 },
200 { /* sentinel */ }
201};
202
203static const struct at91_reset_data sam9260 = {
204 .reset_args = AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST,
205};
206
207static const struct at91_reset_data samx7 = {
208 .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST,
209};
210
211static const struct at91_reset_data sama7g5 = {
212 .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST,
213 .n_device_reset = 3,
214 .device_reset_min_id = SAMA7G5_RESET_USB_PHY1,
215 .device_reset_max_id = SAMA7G5_RESET_USB_PHY3,
216};
217
218static const struct of_device_id at91_reset_of_match[] = {
219 {
220 .compatible = "atmel,at91sam9260-rstc",
221 .data = &sam9260,
222 },
223 {
224 .compatible = "atmel,at91sam9g45-rstc",
225 .data = &sam9260,
226 },
227 {
228 .compatible = "atmel,sama5d3-rstc",
229 .data = &sam9260,
230 },
231 {
232 .compatible = "atmel,samx7-rstc",
233 .data = &samx7,
234 },
235 {
236 .compatible = "microchip,sam9x60-rstc",
237 .data = &samx7,
238 },
239 {
240 .compatible = "microchip,sama7g5-rstc",
241 .data = &sama7g5,
242 },
243 { /* sentinel */ }
244};
245MODULE_DEVICE_TABLE(of, at91_reset_of_match);
246
247static int at91_reset_update(struct reset_controller_dev *rcdev,
248 unsigned long id, bool assert)
249{
250 struct at91_reset *reset = to_at91_reset(rcdev);
251 unsigned long flags;
252 u32 val;
253
254 spin_lock_irqsave(&reset->lock, flags);
255 val = readl_relaxed(reset->dev_base);
256 if (assert)
257 val |= BIT(id);
258 else
259 val &= ~BIT(id);
260 writel_relaxed(val, reset->dev_base);
261 spin_unlock_irqrestore(&reset->lock, flags);
262
263 return 0;
264}
265
266static int at91_reset_assert(struct reset_controller_dev *rcdev,
267 unsigned long id)
268{
269 return at91_reset_update(rcdev, id, true);
270}
271
272static int at91_reset_deassert(struct reset_controller_dev *rcdev,
273 unsigned long id)
274{
275 return at91_reset_update(rcdev, id, false);
276}
277
278static int at91_reset_dev_status(struct reset_controller_dev *rcdev,
279 unsigned long id)
280{
281 struct at91_reset *reset = to_at91_reset(rcdev);
282 u32 val;
283
284 val = readl_relaxed(reset->dev_base);
285
286 return !!(val & BIT(id));
287}
288
289static const struct reset_control_ops at91_reset_ops = {
290 .assert = at91_reset_assert,
291 .deassert = at91_reset_deassert,
292 .status = at91_reset_dev_status,
293};
294
295static int at91_reset_of_xlate(struct reset_controller_dev *rcdev,
296 const struct of_phandle_args *reset_spec)
297{
298 struct at91_reset *reset = to_at91_reset(rcdev);
299
300 if (!reset->data->n_device_reset ||
301 (reset_spec->args[0] < reset->data->device_reset_min_id ||
302 reset_spec->args[0] > reset->data->device_reset_max_id))
303 return -EINVAL;
304
305 return reset_spec->args[0];
306}
307
308static int at91_rcdev_init(struct at91_reset *reset,
309 struct platform_device *pdev)
310{
311 if (!reset->data->n_device_reset)
312 return 0;
313
314 reset->dev_base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 1,
315 NULL);
316 if (IS_ERR(reset->dev_base))
317 return -ENODEV;
318
319 spin_lock_init(&reset->lock);
320 reset->rcdev.ops = &at91_reset_ops;
321 reset->rcdev.owner = THIS_MODULE;
322 reset->rcdev.of_node = pdev->dev.of_node;
323 reset->rcdev.nr_resets = reset->data->n_device_reset;
324 reset->rcdev.of_reset_n_cells = 1;
325 reset->rcdev.of_xlate = at91_reset_of_xlate;
326
327 return devm_reset_controller_register(&pdev->dev, &reset->rcdev);
328}
329
330static int __init at91_reset_probe(struct platform_device *pdev)
331{
332 const struct of_device_id *match;
333 struct at91_reset *reset;
334 struct device_node *np;
335 int ret, idx = 0;
336
337 reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
338 if (!reset)
339 return -ENOMEM;
340
341 reset->rstc_base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
342 if (IS_ERR(reset->rstc_base)) {
343 dev_err(&pdev->dev, "Could not map reset controller address\n");
344 return -ENODEV;
345 }
346
347 if (!of_device_is_compatible(pdev->dev.of_node, "atmel,sama5d3-rstc")) {
348 /* we need to shutdown the ddr controller, so get ramc base */
349 for_each_matching_node_and_match(np, at91_ramc_of_match, &match) {
350 reset->ramc_lpr = (u32)match->data;
351 reset->ramc_base[idx] = devm_of_iomap(&pdev->dev, np, 0, NULL);
352 if (IS_ERR(reset->ramc_base[idx])) {
353 dev_err(&pdev->dev, "Could not map ram controller address\n");
354 of_node_put(np);
355 return -ENODEV;
356 }
357 idx++;
358 }
359 }
360
361 reset->data = device_get_match_data(&pdev->dev);
362 if (!reset->data)
363 return -ENODEV;
364
365 reset->nb.notifier_call = at91_reset;
366 reset->nb.priority = 192;
367
368 reset->sclk = devm_clk_get(&pdev->dev, NULL);
369 if (IS_ERR(reset->sclk))
370 return PTR_ERR(reset->sclk);
371
372 ret = clk_prepare_enable(reset->sclk);
373 if (ret) {
374 dev_err(&pdev->dev, "Could not enable slow clock\n");
375 return ret;
376 }
377
378 platform_set_drvdata(pdev, reset);
379
380 ret = at91_rcdev_init(reset, pdev);
381 if (ret)
382 goto disable_clk;
383
384 if (of_device_is_compatible(pdev->dev.of_node, "microchip,sam9x60-rstc")) {
385 u32 val = readl(reset->rstc_base + AT91_RSTC_MR);
386
387 writel(AT91_RSTC_KEY | AT91_RSTC_URSTASYNC | val,
388 reset->rstc_base + AT91_RSTC_MR);
389 }
390
391 ret = register_restart_handler(&reset->nb);
392 if (ret)
393 goto disable_clk;
394
395 at91_reset_status(pdev, reset->rstc_base);
396
397 return 0;
398
399disable_clk:
400 clk_disable_unprepare(reset->sclk);
401 return ret;
402}
403
404static int __exit at91_reset_remove(struct platform_device *pdev)
405{
406 struct at91_reset *reset = platform_get_drvdata(pdev);
407
408 unregister_restart_handler(&reset->nb);
409 clk_disable_unprepare(reset->sclk);
410
411 return 0;
412}
413
414static struct platform_driver at91_reset_driver = {
415 .remove = __exit_p(at91_reset_remove),
416 .driver = {
417 .name = "at91-reset",
418 .of_match_table = at91_reset_of_match,
419 },
420};
421module_platform_driver_probe(at91_reset_driver, at91_reset_probe);
422
423MODULE_AUTHOR("Atmel Corporation");
424MODULE_DESCRIPTION("Reset driver for Atmel SoCs");
425MODULE_LICENSE("GPL v2");