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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
4 *
5 * Author: Ley Foon Tan <lftan@altera.com>
6 * Description: Altera PCIe host controller driver
7 */
8
9#include <linux/delay.h>
10#include <linux/interrupt.h>
11#include <linux/irqchip/chained_irq.h>
12#include <linux/irqdomain.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/of_pci.h>
17#include <linux/pci.h>
18#include <linux/platform_device.h>
19#include <linux/slab.h>
20
21#include "../pci.h"
22
23#define RP_TX_REG0 0x2000
24#define RP_TX_REG1 0x2004
25#define RP_TX_CNTRL 0x2008
26#define RP_TX_EOP 0x2
27#define RP_TX_SOP 0x1
28#define RP_RXCPL_STATUS 0x2010
29#define RP_RXCPL_EOP 0x2
30#define RP_RXCPL_SOP 0x1
31#define RP_RXCPL_REG0 0x2014
32#define RP_RXCPL_REG1 0x2018
33#define P2A_INT_STATUS 0x3060
34#define P2A_INT_STS_ALL 0xf
35#define P2A_INT_ENABLE 0x3070
36#define P2A_INT_ENA_ALL 0xf
37#define RP_LTSSM 0x3c64
38#define RP_LTSSM_MASK 0x1f
39#define LTSSM_L0 0xf
40
41#define S10_RP_TX_CNTRL 0x2004
42#define S10_RP_RXCPL_REG 0x2008
43#define S10_RP_RXCPL_STATUS 0x200C
44#define S10_RP_CFG_ADDR(pcie, reg) \
45 (((pcie)->hip_base) + (reg) + (1 << 20))
46#define S10_RP_SECONDARY(pcie) \
47 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
48
49/* TLP configuration type 0 and 1 */
50#define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
51#define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */
52#define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
53#define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
54#define TLP_PAYLOAD_SIZE 0x01
55#define TLP_READ_TAG 0x1d
56#define TLP_WRITE_TAG 0x10
57#define RP_DEVFN 0
58#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
59#define TLP_CFG_DW0(pcie, cfg) \
60 (((cfg) << 24) | \
61 TLP_PAYLOAD_SIZE)
62#define TLP_CFG_DW1(pcie, tag, be) \
63 (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
64#define TLP_CFG_DW2(bus, devfn, offset) \
65 (((bus) << 24) | ((devfn) << 16) | (offset))
66#define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
67#define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)
68#define TLP_HDR_SIZE 3
69#define TLP_LOOP 500
70
71#define LINK_UP_TIMEOUT HZ
72#define LINK_RETRAIN_TIMEOUT HZ
73
74#define DWORD_MASK 3
75
76#define S10_TLP_FMTTYPE_CFGRD0 0x05
77#define S10_TLP_FMTTYPE_CFGRD1 0x04
78#define S10_TLP_FMTTYPE_CFGWR0 0x45
79#define S10_TLP_FMTTYPE_CFGWR1 0x44
80
81enum altera_pcie_version {
82 ALTERA_PCIE_V1 = 0,
83 ALTERA_PCIE_V2,
84};
85
86struct altera_pcie {
87 struct platform_device *pdev;
88 void __iomem *cra_base;
89 void __iomem *hip_base;
90 int irq;
91 u8 root_bus_nr;
92 struct irq_domain *irq_domain;
93 struct resource bus_range;
94 const struct altera_pcie_data *pcie_data;
95};
96
97struct altera_pcie_ops {
98 int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
99 void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
100 u32 data, bool align);
101 bool (*get_link_status)(struct altera_pcie *pcie);
102 int (*rp_read_cfg)(struct altera_pcie *pcie, int where,
103 int size, u32 *value);
104 int (*rp_write_cfg)(struct altera_pcie *pcie, u8 busno,
105 int where, int size, u32 value);
106};
107
108struct altera_pcie_data {
109 const struct altera_pcie_ops *ops;
110 enum altera_pcie_version version;
111 u32 cap_offset; /* PCIe capability structure register offset */
112 u32 cfgrd0;
113 u32 cfgrd1;
114 u32 cfgwr0;
115 u32 cfgwr1;
116};
117
118struct tlp_rp_regpair_t {
119 u32 ctrl;
120 u32 reg0;
121 u32 reg1;
122};
123
124static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
125 const u32 reg)
126{
127 writel_relaxed(value, pcie->cra_base + reg);
128}
129
130static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
131{
132 return readl_relaxed(pcie->cra_base + reg);
133}
134
135static bool altera_pcie_link_up(struct altera_pcie *pcie)
136{
137 return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
138}
139
140static bool s10_altera_pcie_link_up(struct altera_pcie *pcie)
141{
142 void __iomem *addr = S10_RP_CFG_ADDR(pcie,
143 pcie->pcie_data->cap_offset +
144 PCI_EXP_LNKSTA);
145
146 return !!(readw(addr) & PCI_EXP_LNKSTA_DLLLA);
147}
148
149/*
150 * Altera PCIe port uses BAR0 of RC's configuration space as the translation
151 * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
152 * using these registers, so it can be reached by DMA from EP devices.
153 * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
154 * from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge
155 * should be hidden during enumeration to avoid the sizing and resource
156 * allocation by PCIe core.
157 */
158static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,
159 int offset)
160{
161 if (pci_is_root_bus(bus) && (devfn == 0) &&
162 (offset == PCI_BASE_ADDRESS_0))
163 return true;
164
165 return false;
166}
167
168static void tlp_write_tx(struct altera_pcie *pcie,
169 struct tlp_rp_regpair_t *tlp_rp_regdata)
170{
171 cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
172 cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
173 cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
174}
175
176static void s10_tlp_write_tx(struct altera_pcie *pcie, u32 reg0, u32 ctrl)
177{
178 cra_writel(pcie, reg0, RP_TX_REG0);
179 cra_writel(pcie, ctrl, S10_RP_TX_CNTRL);
180}
181
182static bool altera_pcie_valid_device(struct altera_pcie *pcie,
183 struct pci_bus *bus, int dev)
184{
185 /* If there is no link, then there is no device */
186 if (bus->number != pcie->root_bus_nr) {
187 if (!pcie->pcie_data->ops->get_link_status(pcie))
188 return false;
189 }
190
191 /* access only one slot on each root port */
192 if (bus->number == pcie->root_bus_nr && dev > 0)
193 return false;
194
195 return true;
196}
197
198static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
199{
200 int i;
201 bool sop = false;
202 u32 ctrl;
203 u32 reg0, reg1;
204 u32 comp_status = 1;
205
206 /*
207 * Minimum 2 loops to read TLP headers and 1 loop to read data
208 * payload.
209 */
210 for (i = 0; i < TLP_LOOP; i++) {
211 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
212 if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
213 reg0 = cra_readl(pcie, RP_RXCPL_REG0);
214 reg1 = cra_readl(pcie, RP_RXCPL_REG1);
215
216 if (ctrl & RP_RXCPL_SOP) {
217 sop = true;
218 comp_status = TLP_COMP_STATUS(reg1);
219 }
220
221 if (ctrl & RP_RXCPL_EOP) {
222 if (comp_status)
223 return PCIBIOS_DEVICE_NOT_FOUND;
224
225 if (value)
226 *value = reg0;
227
228 return PCIBIOS_SUCCESSFUL;
229 }
230 }
231 udelay(5);
232 }
233
234 return PCIBIOS_DEVICE_NOT_FOUND;
235}
236
237static int s10_tlp_read_packet(struct altera_pcie *pcie, u32 *value)
238{
239 u32 ctrl;
240 u32 comp_status;
241 u32 dw[4];
242 u32 count;
243 struct device *dev = &pcie->pdev->dev;
244
245 for (count = 0; count < TLP_LOOP; count++) {
246 ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS);
247 if (ctrl & RP_RXCPL_SOP) {
248 /* Read first DW */
249 dw[0] = cra_readl(pcie, S10_RP_RXCPL_REG);
250 break;
251 }
252
253 udelay(5);
254 }
255
256 /* SOP detection failed, return error */
257 if (count == TLP_LOOP)
258 return PCIBIOS_DEVICE_NOT_FOUND;
259
260 count = 1;
261
262 /* Poll for EOP */
263 while (count < ARRAY_SIZE(dw)) {
264 ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS);
265 dw[count++] = cra_readl(pcie, S10_RP_RXCPL_REG);
266 if (ctrl & RP_RXCPL_EOP) {
267 comp_status = TLP_COMP_STATUS(dw[1]);
268 if (comp_status)
269 return PCIBIOS_DEVICE_NOT_FOUND;
270
271 if (value && TLP_BYTE_COUNT(dw[1]) == sizeof(u32) &&
272 count == 4)
273 *value = dw[3];
274
275 return PCIBIOS_SUCCESSFUL;
276 }
277 }
278
279 dev_warn(dev, "Malformed TLP packet\n");
280
281 return PCIBIOS_DEVICE_NOT_FOUND;
282}
283
284static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
285 u32 data, bool align)
286{
287 struct tlp_rp_regpair_t tlp_rp_regdata;
288
289 tlp_rp_regdata.reg0 = headers[0];
290 tlp_rp_regdata.reg1 = headers[1];
291 tlp_rp_regdata.ctrl = RP_TX_SOP;
292 tlp_write_tx(pcie, &tlp_rp_regdata);
293
294 if (align) {
295 tlp_rp_regdata.reg0 = headers[2];
296 tlp_rp_regdata.reg1 = 0;
297 tlp_rp_regdata.ctrl = 0;
298 tlp_write_tx(pcie, &tlp_rp_regdata);
299
300 tlp_rp_regdata.reg0 = data;
301 tlp_rp_regdata.reg1 = 0;
302 } else {
303 tlp_rp_regdata.reg0 = headers[2];
304 tlp_rp_regdata.reg1 = data;
305 }
306
307 tlp_rp_regdata.ctrl = RP_TX_EOP;
308 tlp_write_tx(pcie, &tlp_rp_regdata);
309}
310
311static void s10_tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
312 u32 data, bool dummy)
313{
314 s10_tlp_write_tx(pcie, headers[0], RP_TX_SOP);
315 s10_tlp_write_tx(pcie, headers[1], 0);
316 s10_tlp_write_tx(pcie, headers[2], 0);
317 s10_tlp_write_tx(pcie, data, RP_TX_EOP);
318}
319
320static void get_tlp_header(struct altera_pcie *pcie, u8 bus, u32 devfn,
321 int where, u8 byte_en, bool read, u32 *headers)
322{
323 u8 cfg;
324 u8 cfg0 = read ? pcie->pcie_data->cfgrd0 : pcie->pcie_data->cfgwr0;
325 u8 cfg1 = read ? pcie->pcie_data->cfgrd1 : pcie->pcie_data->cfgwr1;
326 u8 tag = read ? TLP_READ_TAG : TLP_WRITE_TAG;
327
328 if (pcie->pcie_data->version == ALTERA_PCIE_V1)
329 cfg = (bus == pcie->root_bus_nr) ? cfg0 : cfg1;
330 else
331 cfg = (bus > S10_RP_SECONDARY(pcie)) ? cfg0 : cfg1;
332
333 headers[0] = TLP_CFG_DW0(pcie, cfg);
334 headers[1] = TLP_CFG_DW1(pcie, tag, byte_en);
335 headers[2] = TLP_CFG_DW2(bus, devfn, where);
336}
337
338static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
339 int where, u8 byte_en, u32 *value)
340{
341 u32 headers[TLP_HDR_SIZE];
342
343 get_tlp_header(pcie, bus, devfn, where, byte_en, true,
344 headers);
345
346 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 0, false);
347
348 return pcie->pcie_data->ops->tlp_read_pkt(pcie, value);
349}
350
351static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
352 int where, u8 byte_en, u32 value)
353{
354 u32 headers[TLP_HDR_SIZE];
355 int ret;
356
357 get_tlp_header(pcie, bus, devfn, where, byte_en, false,
358 headers);
359
360 /* check alignment to Qword */
361 if ((where & 0x7) == 0)
362 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers,
363 value, true);
364 else
365 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers,
366 value, false);
367
368 ret = pcie->pcie_data->ops->tlp_read_pkt(pcie, NULL);
369 if (ret != PCIBIOS_SUCCESSFUL)
370 return ret;
371
372 /*
373 * Monitor changes to PCI_PRIMARY_BUS register on root port
374 * and update local copy of root bus number accordingly.
375 */
376 if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
377 pcie->root_bus_nr = (u8)(value);
378
379 return PCIBIOS_SUCCESSFUL;
380}
381
382static int s10_rp_read_cfg(struct altera_pcie *pcie, int where,
383 int size, u32 *value)
384{
385 void __iomem *addr = S10_RP_CFG_ADDR(pcie, where);
386
387 switch (size) {
388 case 1:
389 *value = readb(addr);
390 break;
391 case 2:
392 *value = readw(addr);
393 break;
394 default:
395 *value = readl(addr);
396 break;
397 }
398
399 return PCIBIOS_SUCCESSFUL;
400}
401
402static int s10_rp_write_cfg(struct altera_pcie *pcie, u8 busno,
403 int where, int size, u32 value)
404{
405 void __iomem *addr = S10_RP_CFG_ADDR(pcie, where);
406
407 switch (size) {
408 case 1:
409 writeb(value, addr);
410 break;
411 case 2:
412 writew(value, addr);
413 break;
414 default:
415 writel(value, addr);
416 break;
417 }
418
419 /*
420 * Monitor changes to PCI_PRIMARY_BUS register on root port
421 * and update local copy of root bus number accordingly.
422 */
423 if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS)
424 pcie->root_bus_nr = value & 0xff;
425
426 return PCIBIOS_SUCCESSFUL;
427}
428
429static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,
430 unsigned int devfn, int where, int size,
431 u32 *value)
432{
433 int ret;
434 u32 data;
435 u8 byte_en;
436
437 if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_read_cfg)
438 return pcie->pcie_data->ops->rp_read_cfg(pcie, where,
439 size, value);
440
441 switch (size) {
442 case 1:
443 byte_en = 1 << (where & 3);
444 break;
445 case 2:
446 byte_en = 3 << (where & 3);
447 break;
448 default:
449 byte_en = 0xf;
450 break;
451 }
452
453 ret = tlp_cfg_dword_read(pcie, busno, devfn,
454 (where & ~DWORD_MASK), byte_en, &data);
455 if (ret != PCIBIOS_SUCCESSFUL)
456 return ret;
457
458 switch (size) {
459 case 1:
460 *value = (data >> (8 * (where & 0x3))) & 0xff;
461 break;
462 case 2:
463 *value = (data >> (8 * (where & 0x2))) & 0xffff;
464 break;
465 default:
466 *value = data;
467 break;
468 }
469
470 return PCIBIOS_SUCCESSFUL;
471}
472
473static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno,
474 unsigned int devfn, int where, int size,
475 u32 value)
476{
477 u32 data32;
478 u32 shift = 8 * (where & 3);
479 u8 byte_en;
480
481 if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_write_cfg)
482 return pcie->pcie_data->ops->rp_write_cfg(pcie, busno,
483 where, size, value);
484
485 switch (size) {
486 case 1:
487 data32 = (value & 0xff) << shift;
488 byte_en = 1 << (where & 3);
489 break;
490 case 2:
491 data32 = (value & 0xffff) << shift;
492 byte_en = 3 << (where & 3);
493 break;
494 default:
495 data32 = value;
496 byte_en = 0xf;
497 break;
498 }
499
500 return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK),
501 byte_en, data32);
502}
503
504static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
505 int where, int size, u32 *value)
506{
507 struct altera_pcie *pcie = bus->sysdata;
508
509 if (altera_pcie_hide_rc_bar(bus, devfn, where))
510 return PCIBIOS_BAD_REGISTER_NUMBER;
511
512 if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
513 return PCIBIOS_DEVICE_NOT_FOUND;
514
515 return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size,
516 value);
517}
518
519static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
520 int where, int size, u32 value)
521{
522 struct altera_pcie *pcie = bus->sysdata;
523
524 if (altera_pcie_hide_rc_bar(bus, devfn, where))
525 return PCIBIOS_BAD_REGISTER_NUMBER;
526
527 if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
528 return PCIBIOS_DEVICE_NOT_FOUND;
529
530 return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size,
531 value);
532}
533
534static struct pci_ops altera_pcie_ops = {
535 .read = altera_pcie_cfg_read,
536 .write = altera_pcie_cfg_write,
537};
538
539static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno,
540 unsigned int devfn, int offset, u16 *value)
541{
542 u32 data;
543 int ret;
544
545 ret = _altera_pcie_cfg_read(pcie, busno, devfn,
546 pcie->pcie_data->cap_offset + offset,
547 sizeof(*value),
548 &data);
549 *value = data;
550 return ret;
551}
552
553static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno,
554 unsigned int devfn, int offset, u16 value)
555{
556 return _altera_pcie_cfg_write(pcie, busno, devfn,
557 pcie->pcie_data->cap_offset + offset,
558 sizeof(value),
559 value);
560}
561
562static void altera_wait_link_retrain(struct altera_pcie *pcie)
563{
564 struct device *dev = &pcie->pdev->dev;
565 u16 reg16;
566 unsigned long start_jiffies;
567
568 /* Wait for link training end. */
569 start_jiffies = jiffies;
570 for (;;) {
571 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
572 PCI_EXP_LNKSTA, ®16);
573 if (!(reg16 & PCI_EXP_LNKSTA_LT))
574 break;
575
576 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
577 dev_err(dev, "link retrain timeout\n");
578 break;
579 }
580 udelay(100);
581 }
582
583 /* Wait for link is up */
584 start_jiffies = jiffies;
585 for (;;) {
586 if (pcie->pcie_data->ops->get_link_status(pcie))
587 break;
588
589 if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
590 dev_err(dev, "link up timeout\n");
591 break;
592 }
593 udelay(100);
594 }
595}
596
597static void altera_pcie_retrain(struct altera_pcie *pcie)
598{
599 u16 linkcap, linkstat, linkctl;
600
601 if (!pcie->pcie_data->ops->get_link_status(pcie))
602 return;
603
604 /*
605 * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
606 * current speed is 2.5 GB/s.
607 */
608 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP,
609 &linkcap);
610 if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
611 return;
612
613 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA,
614 &linkstat);
615 if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
616 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
617 PCI_EXP_LNKCTL, &linkctl);
618 linkctl |= PCI_EXP_LNKCTL_RL;
619 altera_write_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
620 PCI_EXP_LNKCTL, linkctl);
621
622 altera_wait_link_retrain(pcie);
623 }
624}
625
626static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
627 irq_hw_number_t hwirq)
628{
629 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
630 irq_set_chip_data(irq, domain->host_data);
631 return 0;
632}
633
634static const struct irq_domain_ops intx_domain_ops = {
635 .map = altera_pcie_intx_map,
636 .xlate = pci_irqd_intx_xlate,
637};
638
639static void altera_pcie_isr(struct irq_desc *desc)
640{
641 struct irq_chip *chip = irq_desc_get_chip(desc);
642 struct altera_pcie *pcie;
643 struct device *dev;
644 unsigned long status;
645 u32 bit;
646 int ret;
647
648 chained_irq_enter(chip, desc);
649 pcie = irq_desc_get_handler_data(desc);
650 dev = &pcie->pdev->dev;
651
652 while ((status = cra_readl(pcie, P2A_INT_STATUS)
653 & P2A_INT_STS_ALL) != 0) {
654 for_each_set_bit(bit, &status, PCI_NUM_INTX) {
655 /* clear interrupts */
656 cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
657
658 ret = generic_handle_domain_irq(pcie->irq_domain, bit);
659 if (ret)
660 dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n", bit);
661 }
662 }
663
664 chained_irq_exit(chip, desc);
665}
666
667static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
668{
669 struct device *dev = &pcie->pdev->dev;
670 struct device_node *node = dev->of_node;
671
672 /* Setup INTx */
673 pcie->irq_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
674 &intx_domain_ops, pcie);
675 if (!pcie->irq_domain) {
676 dev_err(dev, "Failed to get a INTx IRQ domain\n");
677 return -ENOMEM;
678 }
679
680 return 0;
681}
682
683static void altera_pcie_irq_teardown(struct altera_pcie *pcie)
684{
685 irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
686 irq_domain_remove(pcie->irq_domain);
687 irq_dispose_mapping(pcie->irq);
688}
689
690static int altera_pcie_parse_dt(struct altera_pcie *pcie)
691{
692 struct platform_device *pdev = pcie->pdev;
693
694 pcie->cra_base = devm_platform_ioremap_resource_byname(pdev, "Cra");
695 if (IS_ERR(pcie->cra_base))
696 return PTR_ERR(pcie->cra_base);
697
698 if (pcie->pcie_data->version == ALTERA_PCIE_V2) {
699 pcie->hip_base =
700 devm_platform_ioremap_resource_byname(pdev, "Hip");
701 if (IS_ERR(pcie->hip_base))
702 return PTR_ERR(pcie->hip_base);
703 }
704
705 /* setup IRQ */
706 pcie->irq = platform_get_irq(pdev, 0);
707 if (pcie->irq < 0)
708 return pcie->irq;
709
710 irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
711 return 0;
712}
713
714static void altera_pcie_host_init(struct altera_pcie *pcie)
715{
716 altera_pcie_retrain(pcie);
717}
718
719static const struct altera_pcie_ops altera_pcie_ops_1_0 = {
720 .tlp_read_pkt = tlp_read_packet,
721 .tlp_write_pkt = tlp_write_packet,
722 .get_link_status = altera_pcie_link_up,
723};
724
725static const struct altera_pcie_ops altera_pcie_ops_2_0 = {
726 .tlp_read_pkt = s10_tlp_read_packet,
727 .tlp_write_pkt = s10_tlp_write_packet,
728 .get_link_status = s10_altera_pcie_link_up,
729 .rp_read_cfg = s10_rp_read_cfg,
730 .rp_write_cfg = s10_rp_write_cfg,
731};
732
733static const struct altera_pcie_data altera_pcie_1_0_data = {
734 .ops = &altera_pcie_ops_1_0,
735 .cap_offset = 0x80,
736 .version = ALTERA_PCIE_V1,
737 .cfgrd0 = TLP_FMTTYPE_CFGRD0,
738 .cfgrd1 = TLP_FMTTYPE_CFGRD1,
739 .cfgwr0 = TLP_FMTTYPE_CFGWR0,
740 .cfgwr1 = TLP_FMTTYPE_CFGWR1,
741};
742
743static const struct altera_pcie_data altera_pcie_2_0_data = {
744 .ops = &altera_pcie_ops_2_0,
745 .version = ALTERA_PCIE_V2,
746 .cap_offset = 0x70,
747 .cfgrd0 = S10_TLP_FMTTYPE_CFGRD0,
748 .cfgrd1 = S10_TLP_FMTTYPE_CFGRD1,
749 .cfgwr0 = S10_TLP_FMTTYPE_CFGWR0,
750 .cfgwr1 = S10_TLP_FMTTYPE_CFGWR1,
751};
752
753static const struct of_device_id altera_pcie_of_match[] = {
754 {.compatible = "altr,pcie-root-port-1.0",
755 .data = &altera_pcie_1_0_data },
756 {.compatible = "altr,pcie-root-port-2.0",
757 .data = &altera_pcie_2_0_data },
758 {},
759};
760
761static int altera_pcie_probe(struct platform_device *pdev)
762{
763 struct device *dev = &pdev->dev;
764 struct altera_pcie *pcie;
765 struct pci_host_bridge *bridge;
766 int ret;
767 const struct altera_pcie_data *data;
768
769 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
770 if (!bridge)
771 return -ENOMEM;
772
773 pcie = pci_host_bridge_priv(bridge);
774 pcie->pdev = pdev;
775 platform_set_drvdata(pdev, pcie);
776
777 data = of_device_get_match_data(&pdev->dev);
778 if (!data)
779 return -ENODEV;
780
781 pcie->pcie_data = data;
782
783 ret = altera_pcie_parse_dt(pcie);
784 if (ret) {
785 dev_err(dev, "Parsing DT failed\n");
786 return ret;
787 }
788
789 ret = altera_pcie_init_irq_domain(pcie);
790 if (ret) {
791 dev_err(dev, "Failed creating IRQ Domain\n");
792 return ret;
793 }
794
795 /* clear all interrupts */
796 cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
797 /* enable all interrupts */
798 cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
799 altera_pcie_host_init(pcie);
800
801 bridge->sysdata = pcie;
802 bridge->busnr = pcie->root_bus_nr;
803 bridge->ops = &altera_pcie_ops;
804
805 return pci_host_probe(bridge);
806}
807
808static void altera_pcie_remove(struct platform_device *pdev)
809{
810 struct altera_pcie *pcie = platform_get_drvdata(pdev);
811 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
812
813 pci_stop_root_bus(bridge->bus);
814 pci_remove_root_bus(bridge->bus);
815 altera_pcie_irq_teardown(pcie);
816}
817
818static struct platform_driver altera_pcie_driver = {
819 .probe = altera_pcie_probe,
820 .remove_new = altera_pcie_remove,
821 .driver = {
822 .name = "altera-pcie",
823 .of_match_table = altera_pcie_of_match,
824 },
825};
826
827MODULE_DEVICE_TABLE(of, altera_pcie_of_match);
828module_platform_driver(altera_pcie_driver);
829MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
4 *
5 * Author: Ley Foon Tan <lftan@altera.com>
6 * Description: Altera PCIe host controller driver
7 */
8
9#include <linux/delay.h>
10#include <linux/interrupt.h>
11#include <linux/irqchip/chained_irq.h>
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/of_address.h>
15#include <linux/of_device.h>
16#include <linux/of_irq.h>
17#include <linux/of_pci.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21
22#include "../pci.h"
23
24#define RP_TX_REG0 0x2000
25#define RP_TX_REG1 0x2004
26#define RP_TX_CNTRL 0x2008
27#define RP_TX_EOP 0x2
28#define RP_TX_SOP 0x1
29#define RP_RXCPL_STATUS 0x2010
30#define RP_RXCPL_EOP 0x2
31#define RP_RXCPL_SOP 0x1
32#define RP_RXCPL_REG0 0x2014
33#define RP_RXCPL_REG1 0x2018
34#define P2A_INT_STATUS 0x3060
35#define P2A_INT_STS_ALL 0xf
36#define P2A_INT_ENABLE 0x3070
37#define P2A_INT_ENA_ALL 0xf
38#define RP_LTSSM 0x3c64
39#define RP_LTSSM_MASK 0x1f
40#define LTSSM_L0 0xf
41
42#define S10_RP_TX_CNTRL 0x2004
43#define S10_RP_RXCPL_REG 0x2008
44#define S10_RP_RXCPL_STATUS 0x200C
45#define S10_RP_CFG_ADDR(pcie, reg) \
46 (((pcie)->hip_base) + (reg) + (1 << 20))
47#define S10_RP_SECONDARY(pcie) \
48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
49
50/* TLP configuration type 0 and 1 */
51#define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
52#define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */
53#define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
54#define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
55#define TLP_PAYLOAD_SIZE 0x01
56#define TLP_READ_TAG 0x1d
57#define TLP_WRITE_TAG 0x10
58#define RP_DEVFN 0
59#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
60#define TLP_CFG_DW0(pcie, cfg) \
61 (((cfg) << 24) | \
62 TLP_PAYLOAD_SIZE)
63#define TLP_CFG_DW1(pcie, tag, be) \
64 (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
65#define TLP_CFG_DW2(bus, devfn, offset) \
66 (((bus) << 24) | ((devfn) << 16) | (offset))
67#define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
68#define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)
69#define TLP_HDR_SIZE 3
70#define TLP_LOOP 500
71
72#define LINK_UP_TIMEOUT HZ
73#define LINK_RETRAIN_TIMEOUT HZ
74
75#define DWORD_MASK 3
76
77#define S10_TLP_FMTTYPE_CFGRD0 0x05
78#define S10_TLP_FMTTYPE_CFGRD1 0x04
79#define S10_TLP_FMTTYPE_CFGWR0 0x45
80#define S10_TLP_FMTTYPE_CFGWR1 0x44
81
82enum altera_pcie_version {
83 ALTERA_PCIE_V1 = 0,
84 ALTERA_PCIE_V2,
85};
86
87struct altera_pcie {
88 struct platform_device *pdev;
89 void __iomem *cra_base;
90 void __iomem *hip_base;
91 int irq;
92 u8 root_bus_nr;
93 struct irq_domain *irq_domain;
94 struct resource bus_range;
95 const struct altera_pcie_data *pcie_data;
96};
97
98struct altera_pcie_ops {
99 int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
100 void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
101 u32 data, bool align);
102 bool (*get_link_status)(struct altera_pcie *pcie);
103 int (*rp_read_cfg)(struct altera_pcie *pcie, int where,
104 int size, u32 *value);
105 int (*rp_write_cfg)(struct altera_pcie *pcie, u8 busno,
106 int where, int size, u32 value);
107};
108
109struct altera_pcie_data {
110 const struct altera_pcie_ops *ops;
111 enum altera_pcie_version version;
112 u32 cap_offset; /* PCIe capability structure register offset */
113 u32 cfgrd0;
114 u32 cfgrd1;
115 u32 cfgwr0;
116 u32 cfgwr1;
117};
118
119struct tlp_rp_regpair_t {
120 u32 ctrl;
121 u32 reg0;
122 u32 reg1;
123};
124
125static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
126 const u32 reg)
127{
128 writel_relaxed(value, pcie->cra_base + reg);
129}
130
131static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
132{
133 return readl_relaxed(pcie->cra_base + reg);
134}
135
136static bool altera_pcie_link_up(struct altera_pcie *pcie)
137{
138 return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
139}
140
141static bool s10_altera_pcie_link_up(struct altera_pcie *pcie)
142{
143 void __iomem *addr = S10_RP_CFG_ADDR(pcie,
144 pcie->pcie_data->cap_offset +
145 PCI_EXP_LNKSTA);
146
147 return !!(readw(addr) & PCI_EXP_LNKSTA_DLLLA);
148}
149
150/*
151 * Altera PCIe port uses BAR0 of RC's configuration space as the translation
152 * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
153 * using these registers, so it can be reached by DMA from EP devices.
154 * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
155 * from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge
156 * should be hidden during enumeration to avoid the sizing and resource
157 * allocation by PCIe core.
158 */
159static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,
160 int offset)
161{
162 if (pci_is_root_bus(bus) && (devfn == 0) &&
163 (offset == PCI_BASE_ADDRESS_0))
164 return true;
165
166 return false;
167}
168
169static void tlp_write_tx(struct altera_pcie *pcie,
170 struct tlp_rp_regpair_t *tlp_rp_regdata)
171{
172 cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
173 cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
174 cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
175}
176
177static void s10_tlp_write_tx(struct altera_pcie *pcie, u32 reg0, u32 ctrl)
178{
179 cra_writel(pcie, reg0, RP_TX_REG0);
180 cra_writel(pcie, ctrl, S10_RP_TX_CNTRL);
181}
182
183static bool altera_pcie_valid_device(struct altera_pcie *pcie,
184 struct pci_bus *bus, int dev)
185{
186 /* If there is no link, then there is no device */
187 if (bus->number != pcie->root_bus_nr) {
188 if (!pcie->pcie_data->ops->get_link_status(pcie))
189 return false;
190 }
191
192 /* access only one slot on each root port */
193 if (bus->number == pcie->root_bus_nr && dev > 0)
194 return false;
195
196 return true;
197}
198
199static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
200{
201 int i;
202 bool sop = false;
203 u32 ctrl;
204 u32 reg0, reg1;
205 u32 comp_status = 1;
206
207 /*
208 * Minimum 2 loops to read TLP headers and 1 loop to read data
209 * payload.
210 */
211 for (i = 0; i < TLP_LOOP; i++) {
212 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
213 if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
214 reg0 = cra_readl(pcie, RP_RXCPL_REG0);
215 reg1 = cra_readl(pcie, RP_RXCPL_REG1);
216
217 if (ctrl & RP_RXCPL_SOP) {
218 sop = true;
219 comp_status = TLP_COMP_STATUS(reg1);
220 }
221
222 if (ctrl & RP_RXCPL_EOP) {
223 if (comp_status)
224 return PCIBIOS_DEVICE_NOT_FOUND;
225
226 if (value)
227 *value = reg0;
228
229 return PCIBIOS_SUCCESSFUL;
230 }
231 }
232 udelay(5);
233 }
234
235 return PCIBIOS_DEVICE_NOT_FOUND;
236}
237
238static int s10_tlp_read_packet(struct altera_pcie *pcie, u32 *value)
239{
240 u32 ctrl;
241 u32 comp_status;
242 u32 dw[4];
243 u32 count;
244 struct device *dev = &pcie->pdev->dev;
245
246 for (count = 0; count < TLP_LOOP; count++) {
247 ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS);
248 if (ctrl & RP_RXCPL_SOP) {
249 /* Read first DW */
250 dw[0] = cra_readl(pcie, S10_RP_RXCPL_REG);
251 break;
252 }
253
254 udelay(5);
255 }
256
257 /* SOP detection failed, return error */
258 if (count == TLP_LOOP)
259 return PCIBIOS_DEVICE_NOT_FOUND;
260
261 count = 1;
262
263 /* Poll for EOP */
264 while (count < ARRAY_SIZE(dw)) {
265 ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS);
266 dw[count++] = cra_readl(pcie, S10_RP_RXCPL_REG);
267 if (ctrl & RP_RXCPL_EOP) {
268 comp_status = TLP_COMP_STATUS(dw[1]);
269 if (comp_status)
270 return PCIBIOS_DEVICE_NOT_FOUND;
271
272 if (value && TLP_BYTE_COUNT(dw[1]) == sizeof(u32) &&
273 count == 4)
274 *value = dw[3];
275
276 return PCIBIOS_SUCCESSFUL;
277 }
278 }
279
280 dev_warn(dev, "Malformed TLP packet\n");
281
282 return PCIBIOS_DEVICE_NOT_FOUND;
283}
284
285static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
286 u32 data, bool align)
287{
288 struct tlp_rp_regpair_t tlp_rp_regdata;
289
290 tlp_rp_regdata.reg0 = headers[0];
291 tlp_rp_regdata.reg1 = headers[1];
292 tlp_rp_regdata.ctrl = RP_TX_SOP;
293 tlp_write_tx(pcie, &tlp_rp_regdata);
294
295 if (align) {
296 tlp_rp_regdata.reg0 = headers[2];
297 tlp_rp_regdata.reg1 = 0;
298 tlp_rp_regdata.ctrl = 0;
299 tlp_write_tx(pcie, &tlp_rp_regdata);
300
301 tlp_rp_regdata.reg0 = data;
302 tlp_rp_regdata.reg1 = 0;
303 } else {
304 tlp_rp_regdata.reg0 = headers[2];
305 tlp_rp_regdata.reg1 = data;
306 }
307
308 tlp_rp_regdata.ctrl = RP_TX_EOP;
309 tlp_write_tx(pcie, &tlp_rp_regdata);
310}
311
312static void s10_tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
313 u32 data, bool dummy)
314{
315 s10_tlp_write_tx(pcie, headers[0], RP_TX_SOP);
316 s10_tlp_write_tx(pcie, headers[1], 0);
317 s10_tlp_write_tx(pcie, headers[2], 0);
318 s10_tlp_write_tx(pcie, data, RP_TX_EOP);
319}
320
321static void get_tlp_header(struct altera_pcie *pcie, u8 bus, u32 devfn,
322 int where, u8 byte_en, bool read, u32 *headers)
323{
324 u8 cfg;
325 u8 cfg0 = read ? pcie->pcie_data->cfgrd0 : pcie->pcie_data->cfgwr0;
326 u8 cfg1 = read ? pcie->pcie_data->cfgrd1 : pcie->pcie_data->cfgwr1;
327 u8 tag = read ? TLP_READ_TAG : TLP_WRITE_TAG;
328
329 if (pcie->pcie_data->version == ALTERA_PCIE_V1)
330 cfg = (bus == pcie->root_bus_nr) ? cfg0 : cfg1;
331 else
332 cfg = (bus > S10_RP_SECONDARY(pcie)) ? cfg0 : cfg1;
333
334 headers[0] = TLP_CFG_DW0(pcie, cfg);
335 headers[1] = TLP_CFG_DW1(pcie, tag, byte_en);
336 headers[2] = TLP_CFG_DW2(bus, devfn, where);
337}
338
339static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
340 int where, u8 byte_en, u32 *value)
341{
342 u32 headers[TLP_HDR_SIZE];
343
344 get_tlp_header(pcie, bus, devfn, where, byte_en, true,
345 headers);
346
347 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 0, false);
348
349 return pcie->pcie_data->ops->tlp_read_pkt(pcie, value);
350}
351
352static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
353 int where, u8 byte_en, u32 value)
354{
355 u32 headers[TLP_HDR_SIZE];
356 int ret;
357
358 get_tlp_header(pcie, bus, devfn, where, byte_en, false,
359 headers);
360
361 /* check alignment to Qword */
362 if ((where & 0x7) == 0)
363 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers,
364 value, true);
365 else
366 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers,
367 value, false);
368
369 ret = pcie->pcie_data->ops->tlp_read_pkt(pcie, NULL);
370 if (ret != PCIBIOS_SUCCESSFUL)
371 return ret;
372
373 /*
374 * Monitor changes to PCI_PRIMARY_BUS register on root port
375 * and update local copy of root bus number accordingly.
376 */
377 if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
378 pcie->root_bus_nr = (u8)(value);
379
380 return PCIBIOS_SUCCESSFUL;
381}
382
383static int s10_rp_read_cfg(struct altera_pcie *pcie, int where,
384 int size, u32 *value)
385{
386 void __iomem *addr = S10_RP_CFG_ADDR(pcie, where);
387
388 switch (size) {
389 case 1:
390 *value = readb(addr);
391 break;
392 case 2:
393 *value = readw(addr);
394 break;
395 default:
396 *value = readl(addr);
397 break;
398 }
399
400 return PCIBIOS_SUCCESSFUL;
401}
402
403static int s10_rp_write_cfg(struct altera_pcie *pcie, u8 busno,
404 int where, int size, u32 value)
405{
406 void __iomem *addr = S10_RP_CFG_ADDR(pcie, where);
407
408 switch (size) {
409 case 1:
410 writeb(value, addr);
411 break;
412 case 2:
413 writew(value, addr);
414 break;
415 default:
416 writel(value, addr);
417 break;
418 }
419
420 /*
421 * Monitor changes to PCI_PRIMARY_BUS register on root port
422 * and update local copy of root bus number accordingly.
423 */
424 if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS)
425 pcie->root_bus_nr = value & 0xff;
426
427 return PCIBIOS_SUCCESSFUL;
428}
429
430static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,
431 unsigned int devfn, int where, int size,
432 u32 *value)
433{
434 int ret;
435 u32 data;
436 u8 byte_en;
437
438 if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_read_cfg)
439 return pcie->pcie_data->ops->rp_read_cfg(pcie, where,
440 size, value);
441
442 switch (size) {
443 case 1:
444 byte_en = 1 << (where & 3);
445 break;
446 case 2:
447 byte_en = 3 << (where & 3);
448 break;
449 default:
450 byte_en = 0xf;
451 break;
452 }
453
454 ret = tlp_cfg_dword_read(pcie, busno, devfn,
455 (where & ~DWORD_MASK), byte_en, &data);
456 if (ret != PCIBIOS_SUCCESSFUL)
457 return ret;
458
459 switch (size) {
460 case 1:
461 *value = (data >> (8 * (where & 0x3))) & 0xff;
462 break;
463 case 2:
464 *value = (data >> (8 * (where & 0x2))) & 0xffff;
465 break;
466 default:
467 *value = data;
468 break;
469 }
470
471 return PCIBIOS_SUCCESSFUL;
472}
473
474static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno,
475 unsigned int devfn, int where, int size,
476 u32 value)
477{
478 u32 data32;
479 u32 shift = 8 * (where & 3);
480 u8 byte_en;
481
482 if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_write_cfg)
483 return pcie->pcie_data->ops->rp_write_cfg(pcie, busno,
484 where, size, value);
485
486 switch (size) {
487 case 1:
488 data32 = (value & 0xff) << shift;
489 byte_en = 1 << (where & 3);
490 break;
491 case 2:
492 data32 = (value & 0xffff) << shift;
493 byte_en = 3 << (where & 3);
494 break;
495 default:
496 data32 = value;
497 byte_en = 0xf;
498 break;
499 }
500
501 return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK),
502 byte_en, data32);
503}
504
505static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
506 int where, int size, u32 *value)
507{
508 struct altera_pcie *pcie = bus->sysdata;
509
510 if (altera_pcie_hide_rc_bar(bus, devfn, where))
511 return PCIBIOS_BAD_REGISTER_NUMBER;
512
513 if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
514 return PCIBIOS_DEVICE_NOT_FOUND;
515
516 return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size,
517 value);
518}
519
520static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
521 int where, int size, u32 value)
522{
523 struct altera_pcie *pcie = bus->sysdata;
524
525 if (altera_pcie_hide_rc_bar(bus, devfn, where))
526 return PCIBIOS_BAD_REGISTER_NUMBER;
527
528 if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
529 return PCIBIOS_DEVICE_NOT_FOUND;
530
531 return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size,
532 value);
533}
534
535static struct pci_ops altera_pcie_ops = {
536 .read = altera_pcie_cfg_read,
537 .write = altera_pcie_cfg_write,
538};
539
540static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno,
541 unsigned int devfn, int offset, u16 *value)
542{
543 u32 data;
544 int ret;
545
546 ret = _altera_pcie_cfg_read(pcie, busno, devfn,
547 pcie->pcie_data->cap_offset + offset,
548 sizeof(*value),
549 &data);
550 *value = data;
551 return ret;
552}
553
554static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno,
555 unsigned int devfn, int offset, u16 value)
556{
557 return _altera_pcie_cfg_write(pcie, busno, devfn,
558 pcie->pcie_data->cap_offset + offset,
559 sizeof(value),
560 value);
561}
562
563static void altera_wait_link_retrain(struct altera_pcie *pcie)
564{
565 struct device *dev = &pcie->pdev->dev;
566 u16 reg16;
567 unsigned long start_jiffies;
568
569 /* Wait for link training end. */
570 start_jiffies = jiffies;
571 for (;;) {
572 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
573 PCI_EXP_LNKSTA, ®16);
574 if (!(reg16 & PCI_EXP_LNKSTA_LT))
575 break;
576
577 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
578 dev_err(dev, "link retrain timeout\n");
579 break;
580 }
581 udelay(100);
582 }
583
584 /* Wait for link is up */
585 start_jiffies = jiffies;
586 for (;;) {
587 if (pcie->pcie_data->ops->get_link_status(pcie))
588 break;
589
590 if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
591 dev_err(dev, "link up timeout\n");
592 break;
593 }
594 udelay(100);
595 }
596}
597
598static void altera_pcie_retrain(struct altera_pcie *pcie)
599{
600 u16 linkcap, linkstat, linkctl;
601
602 if (!pcie->pcie_data->ops->get_link_status(pcie))
603 return;
604
605 /*
606 * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
607 * current speed is 2.5 GB/s.
608 */
609 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP,
610 &linkcap);
611 if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
612 return;
613
614 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA,
615 &linkstat);
616 if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
617 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
618 PCI_EXP_LNKCTL, &linkctl);
619 linkctl |= PCI_EXP_LNKCTL_RL;
620 altera_write_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
621 PCI_EXP_LNKCTL, linkctl);
622
623 altera_wait_link_retrain(pcie);
624 }
625}
626
627static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
628 irq_hw_number_t hwirq)
629{
630 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
631 irq_set_chip_data(irq, domain->host_data);
632 return 0;
633}
634
635static const struct irq_domain_ops intx_domain_ops = {
636 .map = altera_pcie_intx_map,
637 .xlate = pci_irqd_intx_xlate,
638};
639
640static void altera_pcie_isr(struct irq_desc *desc)
641{
642 struct irq_chip *chip = irq_desc_get_chip(desc);
643 struct altera_pcie *pcie;
644 struct device *dev;
645 unsigned long status;
646 u32 bit;
647 int ret;
648
649 chained_irq_enter(chip, desc);
650 pcie = irq_desc_get_handler_data(desc);
651 dev = &pcie->pdev->dev;
652
653 while ((status = cra_readl(pcie, P2A_INT_STATUS)
654 & P2A_INT_STS_ALL) != 0) {
655 for_each_set_bit(bit, &status, PCI_NUM_INTX) {
656 /* clear interrupts */
657 cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
658
659 ret = generic_handle_domain_irq(pcie->irq_domain, bit);
660 if (ret)
661 dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n", bit);
662 }
663 }
664
665 chained_irq_exit(chip, desc);
666}
667
668static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
669{
670 struct device *dev = &pcie->pdev->dev;
671 struct device_node *node = dev->of_node;
672
673 /* Setup INTx */
674 pcie->irq_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
675 &intx_domain_ops, pcie);
676 if (!pcie->irq_domain) {
677 dev_err(dev, "Failed to get a INTx IRQ domain\n");
678 return -ENOMEM;
679 }
680
681 return 0;
682}
683
684static void altera_pcie_irq_teardown(struct altera_pcie *pcie)
685{
686 irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
687 irq_domain_remove(pcie->irq_domain);
688 irq_dispose_mapping(pcie->irq);
689}
690
691static int altera_pcie_parse_dt(struct altera_pcie *pcie)
692{
693 struct platform_device *pdev = pcie->pdev;
694
695 pcie->cra_base = devm_platform_ioremap_resource_byname(pdev, "Cra");
696 if (IS_ERR(pcie->cra_base))
697 return PTR_ERR(pcie->cra_base);
698
699 if (pcie->pcie_data->version == ALTERA_PCIE_V2) {
700 pcie->hip_base =
701 devm_platform_ioremap_resource_byname(pdev, "Hip");
702 if (IS_ERR(pcie->hip_base))
703 return PTR_ERR(pcie->hip_base);
704 }
705
706 /* setup IRQ */
707 pcie->irq = platform_get_irq(pdev, 0);
708 if (pcie->irq < 0)
709 return pcie->irq;
710
711 irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
712 return 0;
713}
714
715static void altera_pcie_host_init(struct altera_pcie *pcie)
716{
717 altera_pcie_retrain(pcie);
718}
719
720static const struct altera_pcie_ops altera_pcie_ops_1_0 = {
721 .tlp_read_pkt = tlp_read_packet,
722 .tlp_write_pkt = tlp_write_packet,
723 .get_link_status = altera_pcie_link_up,
724};
725
726static const struct altera_pcie_ops altera_pcie_ops_2_0 = {
727 .tlp_read_pkt = s10_tlp_read_packet,
728 .tlp_write_pkt = s10_tlp_write_packet,
729 .get_link_status = s10_altera_pcie_link_up,
730 .rp_read_cfg = s10_rp_read_cfg,
731 .rp_write_cfg = s10_rp_write_cfg,
732};
733
734static const struct altera_pcie_data altera_pcie_1_0_data = {
735 .ops = &altera_pcie_ops_1_0,
736 .cap_offset = 0x80,
737 .version = ALTERA_PCIE_V1,
738 .cfgrd0 = TLP_FMTTYPE_CFGRD0,
739 .cfgrd1 = TLP_FMTTYPE_CFGRD1,
740 .cfgwr0 = TLP_FMTTYPE_CFGWR0,
741 .cfgwr1 = TLP_FMTTYPE_CFGWR1,
742};
743
744static const struct altera_pcie_data altera_pcie_2_0_data = {
745 .ops = &altera_pcie_ops_2_0,
746 .version = ALTERA_PCIE_V2,
747 .cap_offset = 0x70,
748 .cfgrd0 = S10_TLP_FMTTYPE_CFGRD0,
749 .cfgrd1 = S10_TLP_FMTTYPE_CFGRD1,
750 .cfgwr0 = S10_TLP_FMTTYPE_CFGWR0,
751 .cfgwr1 = S10_TLP_FMTTYPE_CFGWR1,
752};
753
754static const struct of_device_id altera_pcie_of_match[] = {
755 {.compatible = "altr,pcie-root-port-1.0",
756 .data = &altera_pcie_1_0_data },
757 {.compatible = "altr,pcie-root-port-2.0",
758 .data = &altera_pcie_2_0_data },
759 {},
760};
761
762static int altera_pcie_probe(struct platform_device *pdev)
763{
764 struct device *dev = &pdev->dev;
765 struct altera_pcie *pcie;
766 struct pci_host_bridge *bridge;
767 int ret;
768 const struct altera_pcie_data *data;
769
770 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
771 if (!bridge)
772 return -ENOMEM;
773
774 pcie = pci_host_bridge_priv(bridge);
775 pcie->pdev = pdev;
776 platform_set_drvdata(pdev, pcie);
777
778 data = of_device_get_match_data(&pdev->dev);
779 if (!data)
780 return -ENODEV;
781
782 pcie->pcie_data = data;
783
784 ret = altera_pcie_parse_dt(pcie);
785 if (ret) {
786 dev_err(dev, "Parsing DT failed\n");
787 return ret;
788 }
789
790 ret = altera_pcie_init_irq_domain(pcie);
791 if (ret) {
792 dev_err(dev, "Failed creating IRQ Domain\n");
793 return ret;
794 }
795
796 /* clear all interrupts */
797 cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
798 /* enable all interrupts */
799 cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
800 altera_pcie_host_init(pcie);
801
802 bridge->sysdata = pcie;
803 bridge->busnr = pcie->root_bus_nr;
804 bridge->ops = &altera_pcie_ops;
805
806 return pci_host_probe(bridge);
807}
808
809static int altera_pcie_remove(struct platform_device *pdev)
810{
811 struct altera_pcie *pcie = platform_get_drvdata(pdev);
812 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
813
814 pci_stop_root_bus(bridge->bus);
815 pci_remove_root_bus(bridge->bus);
816 altera_pcie_irq_teardown(pcie);
817
818 return 0;
819}
820
821static struct platform_driver altera_pcie_driver = {
822 .probe = altera_pcie_probe,
823 .remove = altera_pcie_remove,
824 .driver = {
825 .name = "altera-pcie",
826 .of_match_table = altera_pcie_of_match,
827 },
828};
829
830MODULE_DEVICE_TABLE(of, altera_pcie_of_match);
831module_platform_driver(altera_pcie_driver);
832MODULE_LICENSE("GPL v2");