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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Synopsys DesignWare PCIe host controller driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
7 *
8 * Author: Jingoo Han <jg1.han@samsung.com>
9 */
10
11#include <linux/iopoll.h>
12#include <linux/irqchip/chained_irq.h>
13#include <linux/irqdomain.h>
14#include <linux/msi.h>
15#include <linux/of_address.h>
16#include <linux/of_pci.h>
17#include <linux/pci_regs.h>
18#include <linux/platform_device.h>
19
20#include "../../pci.h"
21#include "pcie-designware.h"
22
23static struct pci_ops dw_pcie_ops;
24static struct pci_ops dw_child_pcie_ops;
25
26static void dw_msi_ack_irq(struct irq_data *d)
27{
28 irq_chip_ack_parent(d);
29}
30
31static void dw_msi_mask_irq(struct irq_data *d)
32{
33 pci_msi_mask_irq(d);
34 irq_chip_mask_parent(d);
35}
36
37static void dw_msi_unmask_irq(struct irq_data *d)
38{
39 pci_msi_unmask_irq(d);
40 irq_chip_unmask_parent(d);
41}
42
43static struct irq_chip dw_pcie_msi_irq_chip = {
44 .name = "PCI-MSI",
45 .irq_ack = dw_msi_ack_irq,
46 .irq_mask = dw_msi_mask_irq,
47 .irq_unmask = dw_msi_unmask_irq,
48};
49
50static struct msi_domain_info dw_pcie_msi_domain_info = {
51 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
52 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
53 .chip = &dw_pcie_msi_irq_chip,
54};
55
56/* MSI int handler */
57irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
58{
59 int i, pos;
60 unsigned long val;
61 u32 status, num_ctrls;
62 irqreturn_t ret = IRQ_NONE;
63 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
64
65 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
66
67 for (i = 0; i < num_ctrls; i++) {
68 status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
69 (i * MSI_REG_CTRL_BLOCK_SIZE));
70 if (!status)
71 continue;
72
73 ret = IRQ_HANDLED;
74 val = status;
75 pos = 0;
76 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL,
77 pos)) != MAX_MSI_IRQS_PER_CTRL) {
78 generic_handle_domain_irq(pp->irq_domain,
79 (i * MAX_MSI_IRQS_PER_CTRL) +
80 pos);
81 pos++;
82 }
83 }
84
85 return ret;
86}
87
88/* Chained MSI interrupt service routine */
89static void dw_chained_msi_isr(struct irq_desc *desc)
90{
91 struct irq_chip *chip = irq_desc_get_chip(desc);
92 struct dw_pcie_rp *pp;
93
94 chained_irq_enter(chip, desc);
95
96 pp = irq_desc_get_handler_data(desc);
97 dw_handle_msi_irq(pp);
98
99 chained_irq_exit(chip, desc);
100}
101
102static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
103{
104 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
105 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
106 u64 msi_target;
107
108 msi_target = (u64)pp->msi_data;
109
110 msg->address_lo = lower_32_bits(msi_target);
111 msg->address_hi = upper_32_bits(msi_target);
112
113 msg->data = d->hwirq;
114
115 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
116 (int)d->hwirq, msg->address_hi, msg->address_lo);
117}
118
119static int dw_pci_msi_set_affinity(struct irq_data *d,
120 const struct cpumask *mask, bool force)
121{
122 return -EINVAL;
123}
124
125static void dw_pci_bottom_mask(struct irq_data *d)
126{
127 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
128 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
129 unsigned int res, bit, ctrl;
130 unsigned long flags;
131
132 raw_spin_lock_irqsave(&pp->lock, flags);
133
134 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
135 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
136 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
137
138 pp->irq_mask[ctrl] |= BIT(bit);
139 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
140
141 raw_spin_unlock_irqrestore(&pp->lock, flags);
142}
143
144static void dw_pci_bottom_unmask(struct irq_data *d)
145{
146 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
147 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
148 unsigned int res, bit, ctrl;
149 unsigned long flags;
150
151 raw_spin_lock_irqsave(&pp->lock, flags);
152
153 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
154 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
155 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
156
157 pp->irq_mask[ctrl] &= ~BIT(bit);
158 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
159
160 raw_spin_unlock_irqrestore(&pp->lock, flags);
161}
162
163static void dw_pci_bottom_ack(struct irq_data *d)
164{
165 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
166 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
167 unsigned int res, bit, ctrl;
168
169 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
170 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
171 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
172
173 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit));
174}
175
176static struct irq_chip dw_pci_msi_bottom_irq_chip = {
177 .name = "DWPCI-MSI",
178 .irq_ack = dw_pci_bottom_ack,
179 .irq_compose_msi_msg = dw_pci_setup_msi_msg,
180 .irq_set_affinity = dw_pci_msi_set_affinity,
181 .irq_mask = dw_pci_bottom_mask,
182 .irq_unmask = dw_pci_bottom_unmask,
183};
184
185static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
186 unsigned int virq, unsigned int nr_irqs,
187 void *args)
188{
189 struct dw_pcie_rp *pp = domain->host_data;
190 unsigned long flags;
191 u32 i;
192 int bit;
193
194 raw_spin_lock_irqsave(&pp->lock, flags);
195
196 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
197 order_base_2(nr_irqs));
198
199 raw_spin_unlock_irqrestore(&pp->lock, flags);
200
201 if (bit < 0)
202 return -ENOSPC;
203
204 for (i = 0; i < nr_irqs; i++)
205 irq_domain_set_info(domain, virq + i, bit + i,
206 pp->msi_irq_chip,
207 pp, handle_edge_irq,
208 NULL, NULL);
209
210 return 0;
211}
212
213static void dw_pcie_irq_domain_free(struct irq_domain *domain,
214 unsigned int virq, unsigned int nr_irqs)
215{
216 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
217 struct dw_pcie_rp *pp = domain->host_data;
218 unsigned long flags;
219
220 raw_spin_lock_irqsave(&pp->lock, flags);
221
222 bitmap_release_region(pp->msi_irq_in_use, d->hwirq,
223 order_base_2(nr_irqs));
224
225 raw_spin_unlock_irqrestore(&pp->lock, flags);
226}
227
228static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
229 .alloc = dw_pcie_irq_domain_alloc,
230 .free = dw_pcie_irq_domain_free,
231};
232
233int dw_pcie_allocate_domains(struct dw_pcie_rp *pp)
234{
235 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
236 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
237
238 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
239 &dw_pcie_msi_domain_ops, pp);
240 if (!pp->irq_domain) {
241 dev_err(pci->dev, "Failed to create IRQ domain\n");
242 return -ENOMEM;
243 }
244
245 irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS);
246
247 pp->msi_domain = pci_msi_create_irq_domain(fwnode,
248 &dw_pcie_msi_domain_info,
249 pp->irq_domain);
250 if (!pp->msi_domain) {
251 dev_err(pci->dev, "Failed to create MSI domain\n");
252 irq_domain_remove(pp->irq_domain);
253 return -ENOMEM;
254 }
255
256 return 0;
257}
258
259static void dw_pcie_free_msi(struct dw_pcie_rp *pp)
260{
261 u32 ctrl;
262
263 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
264 if (pp->msi_irq[ctrl] > 0)
265 irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
266 NULL, NULL);
267 }
268
269 irq_domain_remove(pp->msi_domain);
270 irq_domain_remove(pp->irq_domain);
271}
272
273static void dw_pcie_msi_init(struct dw_pcie_rp *pp)
274{
275 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
276 u64 msi_target = (u64)pp->msi_data;
277
278 if (!pci_msi_enabled() || !pp->has_msi_ctrl)
279 return;
280
281 /* Program the msi_data */
282 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));
283 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
284}
285
286static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp)
287{
288 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
289 struct device *dev = pci->dev;
290 struct platform_device *pdev = to_platform_device(dev);
291 u32 ctrl, max_vectors;
292 int irq;
293
294 /* Parse any "msiX" IRQs described in the devicetree */
295 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
296 char msi_name[] = "msiX";
297
298 msi_name[3] = '0' + ctrl;
299 irq = platform_get_irq_byname_optional(pdev, msi_name);
300 if (irq == -ENXIO)
301 break;
302 if (irq < 0)
303 return dev_err_probe(dev, irq,
304 "Failed to parse MSI IRQ '%s'\n",
305 msi_name);
306
307 pp->msi_irq[ctrl] = irq;
308 }
309
310 /* If no "msiX" IRQs, caller should fallback to "msi" IRQ */
311 if (ctrl == 0)
312 return -ENXIO;
313
314 max_vectors = ctrl * MAX_MSI_IRQS_PER_CTRL;
315 if (pp->num_vectors > max_vectors) {
316 dev_warn(dev, "Exceeding number of MSI vectors, limiting to %u\n",
317 max_vectors);
318 pp->num_vectors = max_vectors;
319 }
320 if (!pp->num_vectors)
321 pp->num_vectors = max_vectors;
322
323 return 0;
324}
325
326static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
327{
328 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
329 struct device *dev = pci->dev;
330 struct platform_device *pdev = to_platform_device(dev);
331 u64 *msi_vaddr;
332 int ret;
333 u32 ctrl, num_ctrls;
334
335 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++)
336 pp->irq_mask[ctrl] = ~0;
337
338 if (!pp->msi_irq[0]) {
339 ret = dw_pcie_parse_split_msi_irq(pp);
340 if (ret < 0 && ret != -ENXIO)
341 return ret;
342 }
343
344 if (!pp->num_vectors)
345 pp->num_vectors = MSI_DEF_NUM_VECTORS;
346 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
347
348 if (!pp->msi_irq[0]) {
349 pp->msi_irq[0] = platform_get_irq_byname_optional(pdev, "msi");
350 if (pp->msi_irq[0] < 0) {
351 pp->msi_irq[0] = platform_get_irq(pdev, 0);
352 if (pp->msi_irq[0] < 0)
353 return pp->msi_irq[0];
354 }
355 }
356
357 dev_dbg(dev, "Using %d MSI vectors\n", pp->num_vectors);
358
359 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
360
361 ret = dw_pcie_allocate_domains(pp);
362 if (ret)
363 return ret;
364
365 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
366 if (pp->msi_irq[ctrl] > 0)
367 irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
368 dw_chained_msi_isr, pp);
369 }
370
371 /*
372 * Even though the iMSI-RX Module supports 64-bit addresses some
373 * peripheral PCIe devices may lack 64-bit message support. In
374 * order not to miss MSI TLPs from those devices the MSI target
375 * address has to be within the lowest 4GB.
376 *
377 * Note until there is a better alternative found the reservation is
378 * done by allocating from the artificially limited DMA-coherent
379 * memory.
380 */
381 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
382 if (ret)
383 dev_warn(dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
384
385 msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data,
386 GFP_KERNEL);
387 if (!msi_vaddr) {
388 dev_err(dev, "Failed to alloc and map MSI data\n");
389 dw_pcie_free_msi(pp);
390 return -ENOMEM;
391 }
392
393 return 0;
394}
395
396int dw_pcie_host_init(struct dw_pcie_rp *pp)
397{
398 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
399 struct device *dev = pci->dev;
400 struct device_node *np = dev->of_node;
401 struct platform_device *pdev = to_platform_device(dev);
402 struct resource_entry *win;
403 struct pci_host_bridge *bridge;
404 struct resource *res;
405 int ret;
406
407 raw_spin_lock_init(&pp->lock);
408
409 ret = dw_pcie_get_resources(pci);
410 if (ret)
411 return ret;
412
413 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
414 if (res) {
415 pp->cfg0_size = resource_size(res);
416 pp->cfg0_base = res->start;
417
418 pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res);
419 if (IS_ERR(pp->va_cfg0_base))
420 return PTR_ERR(pp->va_cfg0_base);
421 } else {
422 dev_err(dev, "Missing *config* reg space\n");
423 return -ENODEV;
424 }
425
426 bridge = devm_pci_alloc_host_bridge(dev, 0);
427 if (!bridge)
428 return -ENOMEM;
429
430 pp->bridge = bridge;
431
432 /* Get the I/O range from DT */
433 win = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
434 if (win) {
435 pp->io_size = resource_size(win->res);
436 pp->io_bus_addr = win->res->start - win->offset;
437 pp->io_base = pci_pio_to_address(win->res->start);
438 }
439
440 /* Set default bus ops */
441 bridge->ops = &dw_pcie_ops;
442 bridge->child_ops = &dw_child_pcie_ops;
443
444 if (pp->ops->init) {
445 ret = pp->ops->init(pp);
446 if (ret)
447 return ret;
448 }
449
450 if (pci_msi_enabled()) {
451 pp->has_msi_ctrl = !(pp->ops->msi_init ||
452 of_property_read_bool(np, "msi-parent") ||
453 of_property_read_bool(np, "msi-map"));
454
455 /*
456 * For the has_msi_ctrl case the default assignment is handled
457 * in the dw_pcie_msi_host_init().
458 */
459 if (!pp->has_msi_ctrl && !pp->num_vectors) {
460 pp->num_vectors = MSI_DEF_NUM_VECTORS;
461 } else if (pp->num_vectors > MAX_MSI_IRQS) {
462 dev_err(dev, "Invalid number of vectors\n");
463 ret = -EINVAL;
464 goto err_deinit_host;
465 }
466
467 if (pp->ops->msi_init) {
468 ret = pp->ops->msi_init(pp);
469 if (ret < 0)
470 goto err_deinit_host;
471 } else if (pp->has_msi_ctrl) {
472 ret = dw_pcie_msi_host_init(pp);
473 if (ret < 0)
474 goto err_deinit_host;
475 }
476 }
477
478 dw_pcie_version_detect(pci);
479
480 dw_pcie_iatu_detect(pci);
481
482 ret = dw_pcie_edma_detect(pci);
483 if (ret)
484 goto err_free_msi;
485
486 ret = dw_pcie_setup_rc(pp);
487 if (ret)
488 goto err_remove_edma;
489
490 if (!dw_pcie_link_up(pci)) {
491 ret = dw_pcie_start_link(pci);
492 if (ret)
493 goto err_remove_edma;
494 }
495
496 /* Ignore errors, the link may come up later */
497 dw_pcie_wait_for_link(pci);
498
499 bridge->sysdata = pp;
500
501 ret = pci_host_probe(bridge);
502 if (ret)
503 goto err_stop_link;
504
505 if (pp->ops->post_init)
506 pp->ops->post_init(pp);
507
508 return 0;
509
510err_stop_link:
511 dw_pcie_stop_link(pci);
512
513err_remove_edma:
514 dw_pcie_edma_remove(pci);
515
516err_free_msi:
517 if (pp->has_msi_ctrl)
518 dw_pcie_free_msi(pp);
519
520err_deinit_host:
521 if (pp->ops->deinit)
522 pp->ops->deinit(pp);
523
524 return ret;
525}
526EXPORT_SYMBOL_GPL(dw_pcie_host_init);
527
528void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
529{
530 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
531
532 pci_stop_root_bus(pp->bridge->bus);
533 pci_remove_root_bus(pp->bridge->bus);
534
535 dw_pcie_stop_link(pci);
536
537 dw_pcie_edma_remove(pci);
538
539 if (pp->has_msi_ctrl)
540 dw_pcie_free_msi(pp);
541
542 if (pp->ops->deinit)
543 pp->ops->deinit(pp);
544}
545EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
546
547static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
548 unsigned int devfn, int where)
549{
550 struct dw_pcie_rp *pp = bus->sysdata;
551 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
552 int type, ret;
553 u32 busdev;
554
555 /*
556 * Checking whether the link is up here is a last line of defense
557 * against platforms that forward errors on the system bus as
558 * SError upon PCI configuration transactions issued when the link
559 * is down. This check is racy by definition and does not stop
560 * the system from triggering an SError if the link goes down
561 * after this check is performed.
562 */
563 if (!dw_pcie_link_up(pci))
564 return NULL;
565
566 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
567 PCIE_ATU_FUNC(PCI_FUNC(devfn));
568
569 if (pci_is_root_bus(bus->parent))
570 type = PCIE_ATU_TYPE_CFG0;
571 else
572 type = PCIE_ATU_TYPE_CFG1;
573
574 ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev,
575 pp->cfg0_size);
576 if (ret)
577 return NULL;
578
579 return pp->va_cfg0_base + where;
580}
581
582static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
583 int where, int size, u32 *val)
584{
585 struct dw_pcie_rp *pp = bus->sysdata;
586 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
587 int ret;
588
589 ret = pci_generic_config_read(bus, devfn, where, size, val);
590 if (ret != PCIBIOS_SUCCESSFUL)
591 return ret;
592
593 if (pp->cfg0_io_shared) {
594 ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
595 pp->io_base, pp->io_bus_addr,
596 pp->io_size);
597 if (ret)
598 return PCIBIOS_SET_FAILED;
599 }
600
601 return PCIBIOS_SUCCESSFUL;
602}
603
604static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
605 int where, int size, u32 val)
606{
607 struct dw_pcie_rp *pp = bus->sysdata;
608 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
609 int ret;
610
611 ret = pci_generic_config_write(bus, devfn, where, size, val);
612 if (ret != PCIBIOS_SUCCESSFUL)
613 return ret;
614
615 if (pp->cfg0_io_shared) {
616 ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
617 pp->io_base, pp->io_bus_addr,
618 pp->io_size);
619 if (ret)
620 return PCIBIOS_SET_FAILED;
621 }
622
623 return PCIBIOS_SUCCESSFUL;
624}
625
626static struct pci_ops dw_child_pcie_ops = {
627 .map_bus = dw_pcie_other_conf_map_bus,
628 .read = dw_pcie_rd_other_conf,
629 .write = dw_pcie_wr_other_conf,
630};
631
632void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
633{
634 struct dw_pcie_rp *pp = bus->sysdata;
635 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
636
637 if (PCI_SLOT(devfn) > 0)
638 return NULL;
639
640 return pci->dbi_base + where;
641}
642EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus);
643
644static struct pci_ops dw_pcie_ops = {
645 .map_bus = dw_pcie_own_conf_map_bus,
646 .read = pci_generic_config_read,
647 .write = pci_generic_config_write,
648};
649
650static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
651{
652 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
653 struct resource_entry *entry;
654 int i, ret;
655
656 /* Note the very first outbound ATU is used for CFG IOs */
657 if (!pci->num_ob_windows) {
658 dev_err(pci->dev, "No outbound iATU found\n");
659 return -EINVAL;
660 }
661
662 /*
663 * Ensure all out/inbound windows are disabled before proceeding with
664 * the MEM/IO (dma-)ranges setups.
665 */
666 for (i = 0; i < pci->num_ob_windows; i++)
667 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_OB, i);
668
669 for (i = 0; i < pci->num_ib_windows; i++)
670 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, i);
671
672 i = 0;
673 resource_list_for_each_entry(entry, &pp->bridge->windows) {
674 if (resource_type(entry->res) != IORESOURCE_MEM)
675 continue;
676
677 if (pci->num_ob_windows <= ++i)
678 break;
679
680 ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM,
681 entry->res->start,
682 entry->res->start - entry->offset,
683 resource_size(entry->res));
684 if (ret) {
685 dev_err(pci->dev, "Failed to set MEM range %pr\n",
686 entry->res);
687 return ret;
688 }
689 }
690
691 if (pp->io_size) {
692 if (pci->num_ob_windows > ++i) {
693 ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO,
694 pp->io_base,
695 pp->io_bus_addr,
696 pp->io_size);
697 if (ret) {
698 dev_err(pci->dev, "Failed to set IO range %pr\n",
699 entry->res);
700 return ret;
701 }
702 } else {
703 pp->cfg0_io_shared = true;
704 }
705 }
706
707 if (pci->num_ob_windows <= i)
708 dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n",
709 pci->num_ob_windows);
710
711 i = 0;
712 resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) {
713 if (resource_type(entry->res) != IORESOURCE_MEM)
714 continue;
715
716 if (pci->num_ib_windows <= i)
717 break;
718
719 ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM,
720 entry->res->start,
721 entry->res->start - entry->offset,
722 resource_size(entry->res));
723 if (ret) {
724 dev_err(pci->dev, "Failed to set DMA range %pr\n",
725 entry->res);
726 return ret;
727 }
728 }
729
730 if (pci->num_ib_windows <= i)
731 dev_warn(pci->dev, "Dma-ranges exceed inbound iATU size (%u)\n",
732 pci->num_ib_windows);
733
734 return 0;
735}
736
737int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
738{
739 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
740 u32 val, ctrl, num_ctrls;
741 int ret;
742
743 /*
744 * Enable DBI read-only registers for writing/updating configuration.
745 * Write permission gets disabled towards the end of this function.
746 */
747 dw_pcie_dbi_ro_wr_en(pci);
748
749 dw_pcie_setup(pci);
750
751 if (pp->has_msi_ctrl) {
752 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
753
754 /* Initialize IRQ Status array */
755 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
756 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
757 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
758 pp->irq_mask[ctrl]);
759 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
760 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
761 ~0);
762 }
763 }
764
765 dw_pcie_msi_init(pp);
766
767 /* Setup RC BARs */
768 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
769 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
770
771 /* Setup interrupt pins */
772 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
773 val &= 0xffff00ff;
774 val |= 0x00000100;
775 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
776
777 /* Setup bus numbers */
778 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
779 val &= 0xff000000;
780 val |= 0x00ff0100;
781 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
782
783 /* Setup command register */
784 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
785 val &= 0xffff0000;
786 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
787 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
788 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
789
790 /*
791 * If the platform provides its own child bus config accesses, it means
792 * the platform uses its own address translation component rather than
793 * ATU, so we should not program the ATU here.
794 */
795 if (pp->bridge->child_ops == &dw_child_pcie_ops) {
796 ret = dw_pcie_iatu_setup(pp);
797 if (ret)
798 return ret;
799 }
800
801 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
802
803 /* Program correct class for RC */
804 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
805
806 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
807 val |= PORT_LOGIC_SPEED_CHANGE;
808 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
809
810 dw_pcie_dbi_ro_wr_dis(pci);
811
812 return 0;
813}
814EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
815
816int dw_pcie_suspend_noirq(struct dw_pcie *pci)
817{
818 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
819 u32 val;
820 int ret;
821
822 /*
823 * If L1SS is supported, then do not put the link into L2 as some
824 * devices such as NVMe expect low resume latency.
825 */
826 if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1)
827 return 0;
828
829 if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT)
830 return 0;
831
832 if (!pci->pp.ops->pme_turn_off)
833 return 0;
834
835 pci->pp.ops->pme_turn_off(&pci->pp);
836
837 ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE,
838 PCIE_PME_TO_L2_TIMEOUT_US/10,
839 PCIE_PME_TO_L2_TIMEOUT_US, false, pci);
840 if (ret) {
841 dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val);
842 return ret;
843 }
844
845 if (pci->pp.ops->deinit)
846 pci->pp.ops->deinit(&pci->pp);
847
848 pci->suspended = true;
849
850 return ret;
851}
852EXPORT_SYMBOL_GPL(dw_pcie_suspend_noirq);
853
854int dw_pcie_resume_noirq(struct dw_pcie *pci)
855{
856 int ret;
857
858 if (!pci->suspended)
859 return 0;
860
861 pci->suspended = false;
862
863 if (pci->pp.ops->init) {
864 ret = pci->pp.ops->init(&pci->pp);
865 if (ret) {
866 dev_err(pci->dev, "Host init failed: %d\n", ret);
867 return ret;
868 }
869 }
870
871 dw_pcie_setup_rc(&pci->pp);
872
873 ret = dw_pcie_start_link(pci);
874 if (ret)
875 return ret;
876
877 ret = dw_pcie_wait_for_link(pci);
878 if (ret)
879 return ret;
880
881 return ret;
882}
883EXPORT_SYMBOL_GPL(dw_pcie_resume_noirq);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Synopsys DesignWare PCIe host controller driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
7 *
8 * Author: Jingoo Han <jg1.han@samsung.com>
9 */
10
11#include <linux/irqchip/chained_irq.h>
12#include <linux/irqdomain.h>
13#include <linux/msi.h>
14#include <linux/of_address.h>
15#include <linux/of_pci.h>
16#include <linux/pci_regs.h>
17#include <linux/platform_device.h>
18
19#include "pcie-designware.h"
20
21static struct pci_ops dw_pcie_ops;
22static struct pci_ops dw_child_pcie_ops;
23
24static void dw_msi_ack_irq(struct irq_data *d)
25{
26 irq_chip_ack_parent(d);
27}
28
29static void dw_msi_mask_irq(struct irq_data *d)
30{
31 pci_msi_mask_irq(d);
32 irq_chip_mask_parent(d);
33}
34
35static void dw_msi_unmask_irq(struct irq_data *d)
36{
37 pci_msi_unmask_irq(d);
38 irq_chip_unmask_parent(d);
39}
40
41static struct irq_chip dw_pcie_msi_irq_chip = {
42 .name = "PCI-MSI",
43 .irq_ack = dw_msi_ack_irq,
44 .irq_mask = dw_msi_mask_irq,
45 .irq_unmask = dw_msi_unmask_irq,
46};
47
48static struct msi_domain_info dw_pcie_msi_domain_info = {
49 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
50 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
51 .chip = &dw_pcie_msi_irq_chip,
52};
53
54/* MSI int handler */
55irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
56{
57 int i, pos;
58 unsigned long val;
59 u32 status, num_ctrls;
60 irqreturn_t ret = IRQ_NONE;
61 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
62
63 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
64
65 for (i = 0; i < num_ctrls; i++) {
66 status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
67 (i * MSI_REG_CTRL_BLOCK_SIZE));
68 if (!status)
69 continue;
70
71 ret = IRQ_HANDLED;
72 val = status;
73 pos = 0;
74 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL,
75 pos)) != MAX_MSI_IRQS_PER_CTRL) {
76 generic_handle_domain_irq(pp->irq_domain,
77 (i * MAX_MSI_IRQS_PER_CTRL) +
78 pos);
79 pos++;
80 }
81 }
82
83 return ret;
84}
85
86/* Chained MSI interrupt service routine */
87static void dw_chained_msi_isr(struct irq_desc *desc)
88{
89 struct irq_chip *chip = irq_desc_get_chip(desc);
90 struct dw_pcie_rp *pp;
91
92 chained_irq_enter(chip, desc);
93
94 pp = irq_desc_get_handler_data(desc);
95 dw_handle_msi_irq(pp);
96
97 chained_irq_exit(chip, desc);
98}
99
100static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
101{
102 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
103 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
104 u64 msi_target;
105
106 msi_target = (u64)pp->msi_data;
107
108 msg->address_lo = lower_32_bits(msi_target);
109 msg->address_hi = upper_32_bits(msi_target);
110
111 msg->data = d->hwirq;
112
113 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
114 (int)d->hwirq, msg->address_hi, msg->address_lo);
115}
116
117static int dw_pci_msi_set_affinity(struct irq_data *d,
118 const struct cpumask *mask, bool force)
119{
120 return -EINVAL;
121}
122
123static void dw_pci_bottom_mask(struct irq_data *d)
124{
125 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
126 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
127 unsigned int res, bit, ctrl;
128 unsigned long flags;
129
130 raw_spin_lock_irqsave(&pp->lock, flags);
131
132 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
133 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
134 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
135
136 pp->irq_mask[ctrl] |= BIT(bit);
137 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
138
139 raw_spin_unlock_irqrestore(&pp->lock, flags);
140}
141
142static void dw_pci_bottom_unmask(struct irq_data *d)
143{
144 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
145 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
146 unsigned int res, bit, ctrl;
147 unsigned long flags;
148
149 raw_spin_lock_irqsave(&pp->lock, flags);
150
151 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
152 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
153 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
154
155 pp->irq_mask[ctrl] &= ~BIT(bit);
156 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
157
158 raw_spin_unlock_irqrestore(&pp->lock, flags);
159}
160
161static void dw_pci_bottom_ack(struct irq_data *d)
162{
163 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
164 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
165 unsigned int res, bit, ctrl;
166
167 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
168 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
169 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
170
171 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit));
172}
173
174static struct irq_chip dw_pci_msi_bottom_irq_chip = {
175 .name = "DWPCI-MSI",
176 .irq_ack = dw_pci_bottom_ack,
177 .irq_compose_msi_msg = dw_pci_setup_msi_msg,
178 .irq_set_affinity = dw_pci_msi_set_affinity,
179 .irq_mask = dw_pci_bottom_mask,
180 .irq_unmask = dw_pci_bottom_unmask,
181};
182
183static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
184 unsigned int virq, unsigned int nr_irqs,
185 void *args)
186{
187 struct dw_pcie_rp *pp = domain->host_data;
188 unsigned long flags;
189 u32 i;
190 int bit;
191
192 raw_spin_lock_irqsave(&pp->lock, flags);
193
194 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
195 order_base_2(nr_irqs));
196
197 raw_spin_unlock_irqrestore(&pp->lock, flags);
198
199 if (bit < 0)
200 return -ENOSPC;
201
202 for (i = 0; i < nr_irqs; i++)
203 irq_domain_set_info(domain, virq + i, bit + i,
204 pp->msi_irq_chip,
205 pp, handle_edge_irq,
206 NULL, NULL);
207
208 return 0;
209}
210
211static void dw_pcie_irq_domain_free(struct irq_domain *domain,
212 unsigned int virq, unsigned int nr_irqs)
213{
214 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
215 struct dw_pcie_rp *pp = domain->host_data;
216 unsigned long flags;
217
218 raw_spin_lock_irqsave(&pp->lock, flags);
219
220 bitmap_release_region(pp->msi_irq_in_use, d->hwirq,
221 order_base_2(nr_irqs));
222
223 raw_spin_unlock_irqrestore(&pp->lock, flags);
224}
225
226static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
227 .alloc = dw_pcie_irq_domain_alloc,
228 .free = dw_pcie_irq_domain_free,
229};
230
231int dw_pcie_allocate_domains(struct dw_pcie_rp *pp)
232{
233 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
234 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
235
236 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
237 &dw_pcie_msi_domain_ops, pp);
238 if (!pp->irq_domain) {
239 dev_err(pci->dev, "Failed to create IRQ domain\n");
240 return -ENOMEM;
241 }
242
243 irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS);
244
245 pp->msi_domain = pci_msi_create_irq_domain(fwnode,
246 &dw_pcie_msi_domain_info,
247 pp->irq_domain);
248 if (!pp->msi_domain) {
249 dev_err(pci->dev, "Failed to create MSI domain\n");
250 irq_domain_remove(pp->irq_domain);
251 return -ENOMEM;
252 }
253
254 return 0;
255}
256
257static void dw_pcie_free_msi(struct dw_pcie_rp *pp)
258{
259 u32 ctrl;
260
261 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
262 if (pp->msi_irq[ctrl] > 0)
263 irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
264 NULL, NULL);
265 }
266
267 irq_domain_remove(pp->msi_domain);
268 irq_domain_remove(pp->irq_domain);
269}
270
271static void dw_pcie_msi_init(struct dw_pcie_rp *pp)
272{
273 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
274 u64 msi_target = (u64)pp->msi_data;
275
276 if (!pci_msi_enabled() || !pp->has_msi_ctrl)
277 return;
278
279 /* Program the msi_data */
280 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));
281 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
282}
283
284static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp)
285{
286 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
287 struct device *dev = pci->dev;
288 struct platform_device *pdev = to_platform_device(dev);
289 u32 ctrl, max_vectors;
290 int irq;
291
292 /* Parse any "msiX" IRQs described in the devicetree */
293 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
294 char msi_name[] = "msiX";
295
296 msi_name[3] = '0' + ctrl;
297 irq = platform_get_irq_byname_optional(pdev, msi_name);
298 if (irq == -ENXIO)
299 break;
300 if (irq < 0)
301 return dev_err_probe(dev, irq,
302 "Failed to parse MSI IRQ '%s'\n",
303 msi_name);
304
305 pp->msi_irq[ctrl] = irq;
306 }
307
308 /* If no "msiX" IRQs, caller should fallback to "msi" IRQ */
309 if (ctrl == 0)
310 return -ENXIO;
311
312 max_vectors = ctrl * MAX_MSI_IRQS_PER_CTRL;
313 if (pp->num_vectors > max_vectors) {
314 dev_warn(dev, "Exceeding number of MSI vectors, limiting to %u\n",
315 max_vectors);
316 pp->num_vectors = max_vectors;
317 }
318 if (!pp->num_vectors)
319 pp->num_vectors = max_vectors;
320
321 return 0;
322}
323
324static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
325{
326 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
327 struct device *dev = pci->dev;
328 struct platform_device *pdev = to_platform_device(dev);
329 u64 *msi_vaddr;
330 int ret;
331 u32 ctrl, num_ctrls;
332
333 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++)
334 pp->irq_mask[ctrl] = ~0;
335
336 if (!pp->msi_irq[0]) {
337 ret = dw_pcie_parse_split_msi_irq(pp);
338 if (ret < 0 && ret != -ENXIO)
339 return ret;
340 }
341
342 if (!pp->num_vectors)
343 pp->num_vectors = MSI_DEF_NUM_VECTORS;
344 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
345
346 if (!pp->msi_irq[0]) {
347 pp->msi_irq[0] = platform_get_irq_byname_optional(pdev, "msi");
348 if (pp->msi_irq[0] < 0) {
349 pp->msi_irq[0] = platform_get_irq(pdev, 0);
350 if (pp->msi_irq[0] < 0)
351 return pp->msi_irq[0];
352 }
353 }
354
355 dev_dbg(dev, "Using %d MSI vectors\n", pp->num_vectors);
356
357 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
358
359 ret = dw_pcie_allocate_domains(pp);
360 if (ret)
361 return ret;
362
363 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
364 if (pp->msi_irq[ctrl] > 0)
365 irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
366 dw_chained_msi_isr, pp);
367 }
368
369 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
370 if (ret)
371 dev_warn(dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
372
373 msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data,
374 GFP_KERNEL);
375 if (!msi_vaddr) {
376 dev_err(dev, "Failed to alloc and map MSI data\n");
377 dw_pcie_free_msi(pp);
378 return -ENOMEM;
379 }
380
381 return 0;
382}
383
384int dw_pcie_host_init(struct dw_pcie_rp *pp)
385{
386 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
387 struct device *dev = pci->dev;
388 struct device_node *np = dev->of_node;
389 struct platform_device *pdev = to_platform_device(dev);
390 struct resource_entry *win;
391 struct pci_host_bridge *bridge;
392 struct resource *res;
393 int ret;
394
395 raw_spin_lock_init(&pp->lock);
396
397 ret = dw_pcie_get_resources(pci);
398 if (ret)
399 return ret;
400
401 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
402 if (res) {
403 pp->cfg0_size = resource_size(res);
404 pp->cfg0_base = res->start;
405
406 pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res);
407 if (IS_ERR(pp->va_cfg0_base))
408 return PTR_ERR(pp->va_cfg0_base);
409 } else {
410 dev_err(dev, "Missing *config* reg space\n");
411 return -ENODEV;
412 }
413
414 bridge = devm_pci_alloc_host_bridge(dev, 0);
415 if (!bridge)
416 return -ENOMEM;
417
418 pp->bridge = bridge;
419
420 /* Get the I/O range from DT */
421 win = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
422 if (win) {
423 pp->io_size = resource_size(win->res);
424 pp->io_bus_addr = win->res->start - win->offset;
425 pp->io_base = pci_pio_to_address(win->res->start);
426 }
427
428 /* Set default bus ops */
429 bridge->ops = &dw_pcie_ops;
430 bridge->child_ops = &dw_child_pcie_ops;
431
432 if (pp->ops->host_init) {
433 ret = pp->ops->host_init(pp);
434 if (ret)
435 return ret;
436 }
437
438 if (pci_msi_enabled()) {
439 pp->has_msi_ctrl = !(pp->ops->msi_host_init ||
440 of_property_read_bool(np, "msi-parent") ||
441 of_property_read_bool(np, "msi-map"));
442
443 /*
444 * For the has_msi_ctrl case the default assignment is handled
445 * in the dw_pcie_msi_host_init().
446 */
447 if (!pp->has_msi_ctrl && !pp->num_vectors) {
448 pp->num_vectors = MSI_DEF_NUM_VECTORS;
449 } else if (pp->num_vectors > MAX_MSI_IRQS) {
450 dev_err(dev, "Invalid number of vectors\n");
451 ret = -EINVAL;
452 goto err_deinit_host;
453 }
454
455 if (pp->ops->msi_host_init) {
456 ret = pp->ops->msi_host_init(pp);
457 if (ret < 0)
458 goto err_deinit_host;
459 } else if (pp->has_msi_ctrl) {
460 ret = dw_pcie_msi_host_init(pp);
461 if (ret < 0)
462 goto err_deinit_host;
463 }
464 }
465
466 dw_pcie_version_detect(pci);
467
468 dw_pcie_iatu_detect(pci);
469
470 ret = dw_pcie_setup_rc(pp);
471 if (ret)
472 goto err_free_msi;
473
474 if (!dw_pcie_link_up(pci)) {
475 ret = dw_pcie_start_link(pci);
476 if (ret)
477 goto err_free_msi;
478 }
479
480 /* Ignore errors, the link may come up later */
481 dw_pcie_wait_for_link(pci);
482
483 bridge->sysdata = pp;
484
485 ret = pci_host_probe(bridge);
486 if (ret)
487 goto err_stop_link;
488
489 return 0;
490
491err_stop_link:
492 dw_pcie_stop_link(pci);
493
494err_free_msi:
495 if (pp->has_msi_ctrl)
496 dw_pcie_free_msi(pp);
497
498err_deinit_host:
499 if (pp->ops->host_deinit)
500 pp->ops->host_deinit(pp);
501
502 return ret;
503}
504EXPORT_SYMBOL_GPL(dw_pcie_host_init);
505
506void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
507{
508 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
509
510 pci_stop_root_bus(pp->bridge->bus);
511 pci_remove_root_bus(pp->bridge->bus);
512
513 dw_pcie_stop_link(pci);
514
515 if (pp->has_msi_ctrl)
516 dw_pcie_free_msi(pp);
517
518 if (pp->ops->host_deinit)
519 pp->ops->host_deinit(pp);
520}
521EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
522
523static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
524 unsigned int devfn, int where)
525{
526 struct dw_pcie_rp *pp = bus->sysdata;
527 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
528 int type, ret;
529 u32 busdev;
530
531 /*
532 * Checking whether the link is up here is a last line of defense
533 * against platforms that forward errors on the system bus as
534 * SError upon PCI configuration transactions issued when the link
535 * is down. This check is racy by definition and does not stop
536 * the system from triggering an SError if the link goes down
537 * after this check is performed.
538 */
539 if (!dw_pcie_link_up(pci))
540 return NULL;
541
542 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
543 PCIE_ATU_FUNC(PCI_FUNC(devfn));
544
545 if (pci_is_root_bus(bus->parent))
546 type = PCIE_ATU_TYPE_CFG0;
547 else
548 type = PCIE_ATU_TYPE_CFG1;
549
550 ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev,
551 pp->cfg0_size);
552 if (ret)
553 return NULL;
554
555 return pp->va_cfg0_base + where;
556}
557
558static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
559 int where, int size, u32 *val)
560{
561 struct dw_pcie_rp *pp = bus->sysdata;
562 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
563 int ret;
564
565 ret = pci_generic_config_read(bus, devfn, where, size, val);
566 if (ret != PCIBIOS_SUCCESSFUL)
567 return ret;
568
569 if (pp->cfg0_io_shared) {
570 ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
571 pp->io_base, pp->io_bus_addr,
572 pp->io_size);
573 if (ret)
574 return PCIBIOS_SET_FAILED;
575 }
576
577 return PCIBIOS_SUCCESSFUL;
578}
579
580static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
581 int where, int size, u32 val)
582{
583 struct dw_pcie_rp *pp = bus->sysdata;
584 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
585 int ret;
586
587 ret = pci_generic_config_write(bus, devfn, where, size, val);
588 if (ret != PCIBIOS_SUCCESSFUL)
589 return ret;
590
591 if (pp->cfg0_io_shared) {
592 ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
593 pp->io_base, pp->io_bus_addr,
594 pp->io_size);
595 if (ret)
596 return PCIBIOS_SET_FAILED;
597 }
598
599 return PCIBIOS_SUCCESSFUL;
600}
601
602static struct pci_ops dw_child_pcie_ops = {
603 .map_bus = dw_pcie_other_conf_map_bus,
604 .read = dw_pcie_rd_other_conf,
605 .write = dw_pcie_wr_other_conf,
606};
607
608void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
609{
610 struct dw_pcie_rp *pp = bus->sysdata;
611 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
612
613 if (PCI_SLOT(devfn) > 0)
614 return NULL;
615
616 return pci->dbi_base + where;
617}
618EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus);
619
620static struct pci_ops dw_pcie_ops = {
621 .map_bus = dw_pcie_own_conf_map_bus,
622 .read = pci_generic_config_read,
623 .write = pci_generic_config_write,
624};
625
626static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
627{
628 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
629 struct resource_entry *entry;
630 int i, ret;
631
632 /* Note the very first outbound ATU is used for CFG IOs */
633 if (!pci->num_ob_windows) {
634 dev_err(pci->dev, "No outbound iATU found\n");
635 return -EINVAL;
636 }
637
638 /*
639 * Ensure all out/inbound windows are disabled before proceeding with
640 * the MEM/IO (dma-)ranges setups.
641 */
642 for (i = 0; i < pci->num_ob_windows; i++)
643 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_OB, i);
644
645 for (i = 0; i < pci->num_ib_windows; i++)
646 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, i);
647
648 i = 0;
649 resource_list_for_each_entry(entry, &pp->bridge->windows) {
650 if (resource_type(entry->res) != IORESOURCE_MEM)
651 continue;
652
653 if (pci->num_ob_windows <= ++i)
654 break;
655
656 ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM,
657 entry->res->start,
658 entry->res->start - entry->offset,
659 resource_size(entry->res));
660 if (ret) {
661 dev_err(pci->dev, "Failed to set MEM range %pr\n",
662 entry->res);
663 return ret;
664 }
665 }
666
667 if (pp->io_size) {
668 if (pci->num_ob_windows > ++i) {
669 ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO,
670 pp->io_base,
671 pp->io_bus_addr,
672 pp->io_size);
673 if (ret) {
674 dev_err(pci->dev, "Failed to set IO range %pr\n",
675 entry->res);
676 return ret;
677 }
678 } else {
679 pp->cfg0_io_shared = true;
680 }
681 }
682
683 if (pci->num_ob_windows <= i)
684 dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n",
685 pci->num_ob_windows);
686
687 i = 0;
688 resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) {
689 if (resource_type(entry->res) != IORESOURCE_MEM)
690 continue;
691
692 if (pci->num_ib_windows <= i)
693 break;
694
695 ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM,
696 entry->res->start,
697 entry->res->start - entry->offset,
698 resource_size(entry->res));
699 if (ret) {
700 dev_err(pci->dev, "Failed to set DMA range %pr\n",
701 entry->res);
702 return ret;
703 }
704 }
705
706 if (pci->num_ib_windows <= i)
707 dev_warn(pci->dev, "Dma-ranges exceed inbound iATU size (%u)\n",
708 pci->num_ib_windows);
709
710 return 0;
711}
712
713int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
714{
715 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
716 u32 val, ctrl, num_ctrls;
717 int ret;
718
719 /*
720 * Enable DBI read-only registers for writing/updating configuration.
721 * Write permission gets disabled towards the end of this function.
722 */
723 dw_pcie_dbi_ro_wr_en(pci);
724
725 dw_pcie_setup(pci);
726
727 if (pp->has_msi_ctrl) {
728 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
729
730 /* Initialize IRQ Status array */
731 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
732 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
733 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
734 pp->irq_mask[ctrl]);
735 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
736 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
737 ~0);
738 }
739 }
740
741 dw_pcie_msi_init(pp);
742
743 /* Setup RC BARs */
744 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
745 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
746
747 /* Setup interrupt pins */
748 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
749 val &= 0xffff00ff;
750 val |= 0x00000100;
751 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
752
753 /* Setup bus numbers */
754 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
755 val &= 0xff000000;
756 val |= 0x00ff0100;
757 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
758
759 /* Setup command register */
760 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
761 val &= 0xffff0000;
762 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
763 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
764 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
765
766 /*
767 * If the platform provides its own child bus config accesses, it means
768 * the platform uses its own address translation component rather than
769 * ATU, so we should not program the ATU here.
770 */
771 if (pp->bridge->child_ops == &dw_child_pcie_ops) {
772 ret = dw_pcie_iatu_setup(pp);
773 if (ret)
774 return ret;
775 }
776
777 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
778
779 /* Program correct class for RC */
780 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
781
782 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
783 val |= PORT_LOGIC_SPEED_CHANGE;
784 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
785
786 dw_pcie_dbi_ro_wr_dis(pci);
787
788 return 0;
789}
790EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);