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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCIe host controller driver for Amlogic MESON SoCs
4 *
5 * Copyright (c) 2018 Amlogic, inc.
6 * Author: Yue Wang <yue.wang@amlogic.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/gpio/consumer.h>
12#include <linux/of_gpio.h>
13#include <linux/pci.h>
14#include <linux/platform_device.h>
15#include <linux/reset.h>
16#include <linux/resource.h>
17#include <linux/types.h>
18#include <linux/phy/phy.h>
19#include <linux/mod_devicetable.h>
20#include <linux/module.h>
21
22#include "pcie-designware.h"
23
24#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
25
26#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
27#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
28
29/* PCIe specific config registers */
30#define PCIE_CFG0 0x0
31#define APP_LTSSM_ENABLE BIT(7)
32
33#define PCIE_CFG_STATUS12 0x30
34#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6))
35#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16))
36#define IS_LTSSM_UP(x) ((((x) >> 10) & 0x1f) == 0x11)
37
38#define PCIE_CFG_STATUS17 0x44
39#define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1)
40
41#define WAIT_LINKUP_TIMEOUT 4000
42#define PORT_CLK_RATE 100000000UL
43#define MAX_PAYLOAD_SIZE 256
44#define MAX_READ_REQ_SIZE 256
45#define PCIE_RESET_DELAY 500
46#define PCIE_SHARED_RESET 1
47#define PCIE_NORMAL_RESET 0
48
49enum pcie_data_rate {
50 PCIE_GEN1,
51 PCIE_GEN2,
52 PCIE_GEN3,
53 PCIE_GEN4
54};
55
56struct meson_pcie_clk_res {
57 struct clk *clk;
58 struct clk *port_clk;
59 struct clk *general_clk;
60};
61
62struct meson_pcie_rc_reset {
63 struct reset_control *port;
64 struct reset_control *apb;
65};
66
67struct meson_pcie {
68 struct dw_pcie pci;
69 void __iomem *cfg_base;
70 struct meson_pcie_clk_res clk_res;
71 struct meson_pcie_rc_reset mrst;
72 struct gpio_desc *reset_gpio;
73 struct phy *phy;
74};
75
76static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
77 const char *id,
78 u32 reset_type)
79{
80 struct device *dev = mp->pci.dev;
81 struct reset_control *reset;
82
83 if (reset_type == PCIE_SHARED_RESET)
84 reset = devm_reset_control_get_shared(dev, id);
85 else
86 reset = devm_reset_control_get(dev, id);
87
88 return reset;
89}
90
91static int meson_pcie_get_resets(struct meson_pcie *mp)
92{
93 struct meson_pcie_rc_reset *mrst = &mp->mrst;
94
95 mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
96 if (IS_ERR(mrst->port))
97 return PTR_ERR(mrst->port);
98 reset_control_deassert(mrst->port);
99
100 mrst->apb = meson_pcie_get_reset(mp, "apb", PCIE_SHARED_RESET);
101 if (IS_ERR(mrst->apb))
102 return PTR_ERR(mrst->apb);
103 reset_control_deassert(mrst->apb);
104
105 return 0;
106}
107
108static int meson_pcie_get_mems(struct platform_device *pdev,
109 struct meson_pcie *mp)
110{
111 struct dw_pcie *pci = &mp->pci;
112
113 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi");
114 if (IS_ERR(pci->dbi_base))
115 return PTR_ERR(pci->dbi_base);
116
117 mp->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
118 if (IS_ERR(mp->cfg_base))
119 return PTR_ERR(mp->cfg_base);
120
121 return 0;
122}
123
124static int meson_pcie_power_on(struct meson_pcie *mp)
125{
126 int ret = 0;
127
128 ret = phy_init(mp->phy);
129 if (ret)
130 return ret;
131
132 ret = phy_power_on(mp->phy);
133 if (ret) {
134 phy_exit(mp->phy);
135 return ret;
136 }
137
138 return 0;
139}
140
141static void meson_pcie_power_off(struct meson_pcie *mp)
142{
143 phy_power_off(mp->phy);
144 phy_exit(mp->phy);
145}
146
147static int meson_pcie_reset(struct meson_pcie *mp)
148{
149 struct meson_pcie_rc_reset *mrst = &mp->mrst;
150 int ret = 0;
151
152 ret = phy_reset(mp->phy);
153 if (ret)
154 return ret;
155
156 reset_control_assert(mrst->port);
157 reset_control_assert(mrst->apb);
158 udelay(PCIE_RESET_DELAY);
159 reset_control_deassert(mrst->port);
160 reset_control_deassert(mrst->apb);
161 udelay(PCIE_RESET_DELAY);
162
163 return 0;
164}
165
166static inline void meson_pcie_disable_clock(void *data)
167{
168 struct clk *clk = data;
169
170 clk_disable_unprepare(clk);
171}
172
173static inline struct clk *meson_pcie_probe_clock(struct device *dev,
174 const char *id, u64 rate)
175{
176 struct clk *clk;
177 int ret;
178
179 clk = devm_clk_get(dev, id);
180 if (IS_ERR(clk))
181 return clk;
182
183 if (rate) {
184 ret = clk_set_rate(clk, rate);
185 if (ret) {
186 dev_err(dev, "set clk rate failed, ret = %d\n", ret);
187 return ERR_PTR(ret);
188 }
189 }
190
191 ret = clk_prepare_enable(clk);
192 if (ret) {
193 dev_err(dev, "couldn't enable clk\n");
194 return ERR_PTR(ret);
195 }
196
197 devm_add_action_or_reset(dev, meson_pcie_disable_clock, clk);
198
199 return clk;
200}
201
202static int meson_pcie_probe_clocks(struct meson_pcie *mp)
203{
204 struct device *dev = mp->pci.dev;
205 struct meson_pcie_clk_res *res = &mp->clk_res;
206
207 res->port_clk = meson_pcie_probe_clock(dev, "port", PORT_CLK_RATE);
208 if (IS_ERR(res->port_clk))
209 return PTR_ERR(res->port_clk);
210
211 res->general_clk = meson_pcie_probe_clock(dev, "general", 0);
212 if (IS_ERR(res->general_clk))
213 return PTR_ERR(res->general_clk);
214
215 res->clk = meson_pcie_probe_clock(dev, "pclk", 0);
216 if (IS_ERR(res->clk))
217 return PTR_ERR(res->clk);
218
219 return 0;
220}
221
222static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg)
223{
224 return readl(mp->cfg_base + reg);
225}
226
227static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg)
228{
229 writel(val, mp->cfg_base + reg);
230}
231
232static void meson_pcie_assert_reset(struct meson_pcie *mp)
233{
234 gpiod_set_value_cansleep(mp->reset_gpio, 1);
235 udelay(500);
236 gpiod_set_value_cansleep(mp->reset_gpio, 0);
237}
238
239static void meson_pcie_ltssm_enable(struct meson_pcie *mp)
240{
241 u32 val;
242
243 val = meson_cfg_readl(mp, PCIE_CFG0);
244 val |= APP_LTSSM_ENABLE;
245 meson_cfg_writel(mp, val, PCIE_CFG0);
246}
247
248static int meson_size_to_payload(struct meson_pcie *mp, int size)
249{
250 struct device *dev = mp->pci.dev;
251
252 /*
253 * dwc supports 2^(val+7) payload size, which val is 0~5 default to 1.
254 * So if input size is not 2^order alignment or less than 2^7 or bigger
255 * than 2^12, just set to default size 2^(1+7).
256 */
257 if (!is_power_of_2(size) || size < 128 || size > 4096) {
258 dev_warn(dev, "payload size %d, set to default 256\n", size);
259 return 1;
260 }
261
262 return fls(size) - 8;
263}
264
265static void meson_set_max_payload(struct meson_pcie *mp, int size)
266{
267 struct dw_pcie *pci = &mp->pci;
268 u32 val;
269 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
270 int max_payload_size = meson_size_to_payload(mp, size);
271
272 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
273 val &= ~PCI_EXP_DEVCTL_PAYLOAD;
274 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
275
276 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
277 val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
278 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
279}
280
281static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
282{
283 struct dw_pcie *pci = &mp->pci;
284 u32 val;
285 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
286 int max_rd_req_size = meson_size_to_payload(mp, size);
287
288 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
289 val &= ~PCI_EXP_DEVCTL_READRQ;
290 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
291
292 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
293 val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size);
294 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
295}
296
297static int meson_pcie_start_link(struct dw_pcie *pci)
298{
299 struct meson_pcie *mp = to_meson_pcie(pci);
300
301 meson_pcie_ltssm_enable(mp);
302 meson_pcie_assert_reset(mp);
303
304 return 0;
305}
306
307static int meson_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn,
308 int where, int size, u32 *val)
309{
310 int ret;
311
312 ret = pci_generic_config_read(bus, devfn, where, size, val);
313 if (ret != PCIBIOS_SUCCESSFUL)
314 return ret;
315
316 /*
317 * There is a bug in the MESON AXG PCIe controller whereby software
318 * cannot program the PCI_CLASS_DEVICE register, so we must fabricate
319 * the return value in the config accessors.
320 */
321 if ((where & ~3) == PCI_CLASS_REVISION) {
322 if (size <= 2)
323 *val = (*val & ((1 << (size * 8)) - 1)) << (8 * (where & 3));
324 *val &= ~0xffffff00;
325 *val |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
326 if (size <= 2)
327 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
328 }
329
330 return PCIBIOS_SUCCESSFUL;
331}
332
333static struct pci_ops meson_pci_ops = {
334 .map_bus = dw_pcie_own_conf_map_bus,
335 .read = meson_pcie_rd_own_conf,
336 .write = pci_generic_config_write,
337};
338
339static int meson_pcie_link_up(struct dw_pcie *pci)
340{
341 struct meson_pcie *mp = to_meson_pcie(pci);
342 struct device *dev = pci->dev;
343 u32 speed_okay = 0;
344 u32 cnt = 0;
345 u32 state12, state17, smlh_up, ltssm_up, rdlh_up;
346
347 do {
348 state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
349 state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17);
350 smlh_up = IS_SMLH_LINK_UP(state12);
351 rdlh_up = IS_RDLH_LINK_UP(state12);
352 ltssm_up = IS_LTSSM_UP(state12);
353
354 if (PM_CURRENT_STATE(state17) < PCIE_GEN3)
355 speed_okay = 1;
356
357 if (smlh_up)
358 dev_dbg(dev, "smlh_link_up is on\n");
359 if (rdlh_up)
360 dev_dbg(dev, "rdlh_link_up is on\n");
361 if (ltssm_up)
362 dev_dbg(dev, "ltssm_up is on\n");
363 if (speed_okay)
364 dev_dbg(dev, "speed_okay\n");
365
366 if (smlh_up && rdlh_up && ltssm_up && speed_okay)
367 return 1;
368
369 cnt++;
370
371 udelay(10);
372 } while (cnt < WAIT_LINKUP_TIMEOUT);
373
374 dev_err(dev, "error: wait linkup timeout\n");
375 return 0;
376}
377
378static int meson_pcie_host_init(struct dw_pcie_rp *pp)
379{
380 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
381 struct meson_pcie *mp = to_meson_pcie(pci);
382
383 pp->bridge->ops = &meson_pci_ops;
384
385 meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
386 meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
387
388 return 0;
389}
390
391static const struct dw_pcie_host_ops meson_pcie_host_ops = {
392 .init = meson_pcie_host_init,
393};
394
395static const struct dw_pcie_ops dw_pcie_ops = {
396 .link_up = meson_pcie_link_up,
397 .start_link = meson_pcie_start_link,
398};
399
400static int meson_pcie_probe(struct platform_device *pdev)
401{
402 struct device *dev = &pdev->dev;
403 struct dw_pcie *pci;
404 struct meson_pcie *mp;
405 int ret;
406
407 mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
408 if (!mp)
409 return -ENOMEM;
410
411 pci = &mp->pci;
412 pci->dev = dev;
413 pci->ops = &dw_pcie_ops;
414 pci->pp.ops = &meson_pcie_host_ops;
415 pci->num_lanes = 1;
416
417 mp->phy = devm_phy_get(dev, "pcie");
418 if (IS_ERR(mp->phy)) {
419 dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy));
420 return PTR_ERR(mp->phy);
421 }
422
423 mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
424 if (IS_ERR(mp->reset_gpio)) {
425 dev_err(dev, "get reset gpio failed\n");
426 return PTR_ERR(mp->reset_gpio);
427 }
428
429 ret = meson_pcie_get_resets(mp);
430 if (ret) {
431 dev_err(dev, "get reset resource failed, %d\n", ret);
432 return ret;
433 }
434
435 ret = meson_pcie_get_mems(pdev, mp);
436 if (ret) {
437 dev_err(dev, "get memory resource failed, %d\n", ret);
438 return ret;
439 }
440
441 ret = meson_pcie_power_on(mp);
442 if (ret) {
443 dev_err(dev, "phy power on failed, %d\n", ret);
444 return ret;
445 }
446
447 ret = meson_pcie_reset(mp);
448 if (ret) {
449 dev_err(dev, "reset failed, %d\n", ret);
450 goto err_phy;
451 }
452
453 ret = meson_pcie_probe_clocks(mp);
454 if (ret) {
455 dev_err(dev, "init clock resources failed, %d\n", ret);
456 goto err_phy;
457 }
458
459 platform_set_drvdata(pdev, mp);
460
461 ret = dw_pcie_host_init(&pci->pp);
462 if (ret < 0) {
463 dev_err(dev, "Add PCIe port failed, %d\n", ret);
464 goto err_phy;
465 }
466
467 return 0;
468
469err_phy:
470 meson_pcie_power_off(mp);
471 return ret;
472}
473
474static const struct of_device_id meson_pcie_of_match[] = {
475 {
476 .compatible = "amlogic,axg-pcie",
477 },
478 {
479 .compatible = "amlogic,g12a-pcie",
480 },
481 {},
482};
483MODULE_DEVICE_TABLE(of, meson_pcie_of_match);
484
485static struct platform_driver meson_pcie_driver = {
486 .probe = meson_pcie_probe,
487 .driver = {
488 .name = "meson-pcie",
489 .of_match_table = meson_pcie_of_match,
490 },
491};
492
493module_platform_driver(meson_pcie_driver);
494
495MODULE_AUTHOR("Yue Wang <yue.wang@amlogic.com>");
496MODULE_DESCRIPTION("Amlogic PCIe Controller driver");
497MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCIe host controller driver for Amlogic MESON SoCs
4 *
5 * Copyright (c) 2018 Amlogic, inc.
6 * Author: Yue Wang <yue.wang@amlogic.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/gpio/consumer.h>
12#include <linux/of_device.h>
13#include <linux/of_gpio.h>
14#include <linux/pci.h>
15#include <linux/platform_device.h>
16#include <linux/reset.h>
17#include <linux/resource.h>
18#include <linux/types.h>
19#include <linux/phy/phy.h>
20#include <linux/module.h>
21
22#include "pcie-designware.h"
23
24#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
25
26#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
27#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
28
29/* PCIe specific config registers */
30#define PCIE_CFG0 0x0
31#define APP_LTSSM_ENABLE BIT(7)
32
33#define PCIE_CFG_STATUS12 0x30
34#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6))
35#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16))
36#define IS_LTSSM_UP(x) ((((x) >> 10) & 0x1f) == 0x11)
37
38#define PCIE_CFG_STATUS17 0x44
39#define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1)
40
41#define WAIT_LINKUP_TIMEOUT 4000
42#define PORT_CLK_RATE 100000000UL
43#define MAX_PAYLOAD_SIZE 256
44#define MAX_READ_REQ_SIZE 256
45#define PCIE_RESET_DELAY 500
46#define PCIE_SHARED_RESET 1
47#define PCIE_NORMAL_RESET 0
48
49enum pcie_data_rate {
50 PCIE_GEN1,
51 PCIE_GEN2,
52 PCIE_GEN3,
53 PCIE_GEN4
54};
55
56struct meson_pcie_clk_res {
57 struct clk *clk;
58 struct clk *port_clk;
59 struct clk *general_clk;
60};
61
62struct meson_pcie_rc_reset {
63 struct reset_control *port;
64 struct reset_control *apb;
65};
66
67struct meson_pcie {
68 struct dw_pcie pci;
69 void __iomem *cfg_base;
70 struct meson_pcie_clk_res clk_res;
71 struct meson_pcie_rc_reset mrst;
72 struct gpio_desc *reset_gpio;
73 struct phy *phy;
74};
75
76static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
77 const char *id,
78 u32 reset_type)
79{
80 struct device *dev = mp->pci.dev;
81 struct reset_control *reset;
82
83 if (reset_type == PCIE_SHARED_RESET)
84 reset = devm_reset_control_get_shared(dev, id);
85 else
86 reset = devm_reset_control_get(dev, id);
87
88 return reset;
89}
90
91static int meson_pcie_get_resets(struct meson_pcie *mp)
92{
93 struct meson_pcie_rc_reset *mrst = &mp->mrst;
94
95 mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
96 if (IS_ERR(mrst->port))
97 return PTR_ERR(mrst->port);
98 reset_control_deassert(mrst->port);
99
100 mrst->apb = meson_pcie_get_reset(mp, "apb", PCIE_SHARED_RESET);
101 if (IS_ERR(mrst->apb))
102 return PTR_ERR(mrst->apb);
103 reset_control_deassert(mrst->apb);
104
105 return 0;
106}
107
108static int meson_pcie_get_mems(struct platform_device *pdev,
109 struct meson_pcie *mp)
110{
111 struct dw_pcie *pci = &mp->pci;
112
113 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi");
114 if (IS_ERR(pci->dbi_base))
115 return PTR_ERR(pci->dbi_base);
116
117 mp->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
118 if (IS_ERR(mp->cfg_base))
119 return PTR_ERR(mp->cfg_base);
120
121 return 0;
122}
123
124static int meson_pcie_power_on(struct meson_pcie *mp)
125{
126 int ret = 0;
127
128 ret = phy_init(mp->phy);
129 if (ret)
130 return ret;
131
132 ret = phy_power_on(mp->phy);
133 if (ret) {
134 phy_exit(mp->phy);
135 return ret;
136 }
137
138 return 0;
139}
140
141static void meson_pcie_power_off(struct meson_pcie *mp)
142{
143 phy_power_off(mp->phy);
144 phy_exit(mp->phy);
145}
146
147static int meson_pcie_reset(struct meson_pcie *mp)
148{
149 struct meson_pcie_rc_reset *mrst = &mp->mrst;
150 int ret = 0;
151
152 ret = phy_reset(mp->phy);
153 if (ret)
154 return ret;
155
156 reset_control_assert(mrst->port);
157 reset_control_assert(mrst->apb);
158 udelay(PCIE_RESET_DELAY);
159 reset_control_deassert(mrst->port);
160 reset_control_deassert(mrst->apb);
161 udelay(PCIE_RESET_DELAY);
162
163 return 0;
164}
165
166static inline struct clk *meson_pcie_probe_clock(struct device *dev,
167 const char *id, u64 rate)
168{
169 struct clk *clk;
170 int ret;
171
172 clk = devm_clk_get(dev, id);
173 if (IS_ERR(clk))
174 return clk;
175
176 if (rate) {
177 ret = clk_set_rate(clk, rate);
178 if (ret) {
179 dev_err(dev, "set clk rate failed, ret = %d\n", ret);
180 return ERR_PTR(ret);
181 }
182 }
183
184 ret = clk_prepare_enable(clk);
185 if (ret) {
186 dev_err(dev, "couldn't enable clk\n");
187 return ERR_PTR(ret);
188 }
189
190 devm_add_action_or_reset(dev,
191 (void (*) (void *))clk_disable_unprepare,
192 clk);
193
194 return clk;
195}
196
197static int meson_pcie_probe_clocks(struct meson_pcie *mp)
198{
199 struct device *dev = mp->pci.dev;
200 struct meson_pcie_clk_res *res = &mp->clk_res;
201
202 res->port_clk = meson_pcie_probe_clock(dev, "port", PORT_CLK_RATE);
203 if (IS_ERR(res->port_clk))
204 return PTR_ERR(res->port_clk);
205
206 res->general_clk = meson_pcie_probe_clock(dev, "general", 0);
207 if (IS_ERR(res->general_clk))
208 return PTR_ERR(res->general_clk);
209
210 res->clk = meson_pcie_probe_clock(dev, "pclk", 0);
211 if (IS_ERR(res->clk))
212 return PTR_ERR(res->clk);
213
214 return 0;
215}
216
217static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg)
218{
219 return readl(mp->cfg_base + reg);
220}
221
222static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg)
223{
224 writel(val, mp->cfg_base + reg);
225}
226
227static void meson_pcie_assert_reset(struct meson_pcie *mp)
228{
229 gpiod_set_value_cansleep(mp->reset_gpio, 1);
230 udelay(500);
231 gpiod_set_value_cansleep(mp->reset_gpio, 0);
232}
233
234static void meson_pcie_ltssm_enable(struct meson_pcie *mp)
235{
236 u32 val;
237
238 val = meson_cfg_readl(mp, PCIE_CFG0);
239 val |= APP_LTSSM_ENABLE;
240 meson_cfg_writel(mp, val, PCIE_CFG0);
241}
242
243static int meson_size_to_payload(struct meson_pcie *mp, int size)
244{
245 struct device *dev = mp->pci.dev;
246
247 /*
248 * dwc supports 2^(val+7) payload size, which val is 0~5 default to 1.
249 * So if input size is not 2^order alignment or less than 2^7 or bigger
250 * than 2^12, just set to default size 2^(1+7).
251 */
252 if (!is_power_of_2(size) || size < 128 || size > 4096) {
253 dev_warn(dev, "payload size %d, set to default 256\n", size);
254 return 1;
255 }
256
257 return fls(size) - 8;
258}
259
260static void meson_set_max_payload(struct meson_pcie *mp, int size)
261{
262 struct dw_pcie *pci = &mp->pci;
263 u32 val;
264 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
265 int max_payload_size = meson_size_to_payload(mp, size);
266
267 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
268 val &= ~PCI_EXP_DEVCTL_PAYLOAD;
269 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
270
271 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
272 val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
273 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
274}
275
276static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
277{
278 struct dw_pcie *pci = &mp->pci;
279 u32 val;
280 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
281 int max_rd_req_size = meson_size_to_payload(mp, size);
282
283 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
284 val &= ~PCI_EXP_DEVCTL_READRQ;
285 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
286
287 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
288 val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size);
289 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
290}
291
292static int meson_pcie_start_link(struct dw_pcie *pci)
293{
294 struct meson_pcie *mp = to_meson_pcie(pci);
295
296 meson_pcie_ltssm_enable(mp);
297 meson_pcie_assert_reset(mp);
298
299 return 0;
300}
301
302static int meson_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn,
303 int where, int size, u32 *val)
304{
305 int ret;
306
307 ret = pci_generic_config_read(bus, devfn, where, size, val);
308 if (ret != PCIBIOS_SUCCESSFUL)
309 return ret;
310
311 /*
312 * There is a bug in the MESON AXG PCIe controller whereby software
313 * cannot program the PCI_CLASS_DEVICE register, so we must fabricate
314 * the return value in the config accessors.
315 */
316 if ((where & ~3) == PCI_CLASS_REVISION) {
317 if (size <= 2)
318 *val = (*val & ((1 << (size * 8)) - 1)) << (8 * (where & 3));
319 *val &= ~0xffffff00;
320 *val |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
321 if (size <= 2)
322 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
323 }
324
325 return PCIBIOS_SUCCESSFUL;
326}
327
328static struct pci_ops meson_pci_ops = {
329 .map_bus = dw_pcie_own_conf_map_bus,
330 .read = meson_pcie_rd_own_conf,
331 .write = pci_generic_config_write,
332};
333
334static int meson_pcie_link_up(struct dw_pcie *pci)
335{
336 struct meson_pcie *mp = to_meson_pcie(pci);
337 struct device *dev = pci->dev;
338 u32 speed_okay = 0;
339 u32 cnt = 0;
340 u32 state12, state17, smlh_up, ltssm_up, rdlh_up;
341
342 do {
343 state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
344 state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17);
345 smlh_up = IS_SMLH_LINK_UP(state12);
346 rdlh_up = IS_RDLH_LINK_UP(state12);
347 ltssm_up = IS_LTSSM_UP(state12);
348
349 if (PM_CURRENT_STATE(state17) < PCIE_GEN3)
350 speed_okay = 1;
351
352 if (smlh_up)
353 dev_dbg(dev, "smlh_link_up is on\n");
354 if (rdlh_up)
355 dev_dbg(dev, "rdlh_link_up is on\n");
356 if (ltssm_up)
357 dev_dbg(dev, "ltssm_up is on\n");
358 if (speed_okay)
359 dev_dbg(dev, "speed_okay\n");
360
361 if (smlh_up && rdlh_up && ltssm_up && speed_okay)
362 return 1;
363
364 cnt++;
365
366 udelay(10);
367 } while (cnt < WAIT_LINKUP_TIMEOUT);
368
369 dev_err(dev, "error: wait linkup timeout\n");
370 return 0;
371}
372
373static int meson_pcie_host_init(struct dw_pcie_rp *pp)
374{
375 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
376 struct meson_pcie *mp = to_meson_pcie(pci);
377
378 pp->bridge->ops = &meson_pci_ops;
379
380 meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
381 meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
382
383 return 0;
384}
385
386static const struct dw_pcie_host_ops meson_pcie_host_ops = {
387 .host_init = meson_pcie_host_init,
388};
389
390static const struct dw_pcie_ops dw_pcie_ops = {
391 .link_up = meson_pcie_link_up,
392 .start_link = meson_pcie_start_link,
393};
394
395static int meson_pcie_probe(struct platform_device *pdev)
396{
397 struct device *dev = &pdev->dev;
398 struct dw_pcie *pci;
399 struct meson_pcie *mp;
400 int ret;
401
402 mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
403 if (!mp)
404 return -ENOMEM;
405
406 pci = &mp->pci;
407 pci->dev = dev;
408 pci->ops = &dw_pcie_ops;
409 pci->pp.ops = &meson_pcie_host_ops;
410 pci->num_lanes = 1;
411
412 mp->phy = devm_phy_get(dev, "pcie");
413 if (IS_ERR(mp->phy)) {
414 dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy));
415 return PTR_ERR(mp->phy);
416 }
417
418 mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
419 if (IS_ERR(mp->reset_gpio)) {
420 dev_err(dev, "get reset gpio failed\n");
421 return PTR_ERR(mp->reset_gpio);
422 }
423
424 ret = meson_pcie_get_resets(mp);
425 if (ret) {
426 dev_err(dev, "get reset resource failed, %d\n", ret);
427 return ret;
428 }
429
430 ret = meson_pcie_get_mems(pdev, mp);
431 if (ret) {
432 dev_err(dev, "get memory resource failed, %d\n", ret);
433 return ret;
434 }
435
436 ret = meson_pcie_power_on(mp);
437 if (ret) {
438 dev_err(dev, "phy power on failed, %d\n", ret);
439 return ret;
440 }
441
442 ret = meson_pcie_reset(mp);
443 if (ret) {
444 dev_err(dev, "reset failed, %d\n", ret);
445 goto err_phy;
446 }
447
448 ret = meson_pcie_probe_clocks(mp);
449 if (ret) {
450 dev_err(dev, "init clock resources failed, %d\n", ret);
451 goto err_phy;
452 }
453
454 platform_set_drvdata(pdev, mp);
455
456 ret = dw_pcie_host_init(&pci->pp);
457 if (ret < 0) {
458 dev_err(dev, "Add PCIe port failed, %d\n", ret);
459 goto err_phy;
460 }
461
462 return 0;
463
464err_phy:
465 meson_pcie_power_off(mp);
466 return ret;
467}
468
469static const struct of_device_id meson_pcie_of_match[] = {
470 {
471 .compatible = "amlogic,axg-pcie",
472 },
473 {
474 .compatible = "amlogic,g12a-pcie",
475 },
476 {},
477};
478MODULE_DEVICE_TABLE(of, meson_pcie_of_match);
479
480static struct platform_driver meson_pcie_driver = {
481 .probe = meson_pcie_probe,
482 .driver = {
483 .name = "meson-pcie",
484 .of_match_table = meson_pcie_of_match,
485 },
486};
487
488module_platform_driver(meson_pcie_driver);
489
490MODULE_AUTHOR("Yue Wang <yue.wang@amlogic.com>");
491MODULE_DESCRIPTION("Amlogic PCIe Controller driver");
492MODULE_LICENSE("GPL v2");