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1// SPDX-License-Identifier: ISC
2/* Copyright (C) 2020 MediaTek Inc.
3 *
4 */
5
6#include <linux/kernel.h>
7#include <linux/module.h>
8#include <linux/pci.h>
9
10#include "mt7921.h"
11#include "../mt76_connac2_mac.h"
12#include "../dma.h"
13#include "mcu.h"
14
15static const struct pci_device_id mt7921_pci_device_table[] = {
16 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961),
17 .driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM },
18 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922),
19 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM },
20 { PCI_DEVICE(PCI_VENDOR_ID_ITTIM, 0x7922),
21 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM },
22 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608),
23 .driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM },
24 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616),
25 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM },
26 { },
27};
28
29static bool mt7921_disable_aspm;
30module_param_named(disable_aspm, mt7921_disable_aspm, bool, 0644);
31MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support");
32
33static int mt7921e_init_reset(struct mt792x_dev *dev)
34{
35 return mt792x_wpdma_reset(dev, true);
36}
37
38static void mt7921e_unregister_device(struct mt792x_dev *dev)
39{
40 int i;
41 struct mt76_connac_pm *pm = &dev->pm;
42
43 cancel_work_sync(&dev->init_work);
44 mt76_unregister_device(&dev->mt76);
45 mt76_for_each_q_rx(&dev->mt76, i)
46 napi_disable(&dev->mt76.napi[i]);
47 cancel_delayed_work_sync(&pm->ps_work);
48 cancel_work_sync(&pm->wake_work);
49 cancel_work_sync(&dev->reset_work);
50
51 mt76_connac2_tx_token_put(&dev->mt76);
52 __mt792x_mcu_drv_pmctrl(dev);
53 mt792x_dma_cleanup(dev);
54 mt792x_wfsys_reset(dev);
55 skb_queue_purge(&dev->mt76.mcu.res_q);
56
57 tasklet_disable(&dev->mt76.irq_tasklet);
58}
59
60static u32 __mt7921_reg_addr(struct mt792x_dev *dev, u32 addr)
61{
62 static const struct mt76_connac_reg_map fixed_map[] = {
63 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
64 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
65 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
66 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
67 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
68 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
69 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
70 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
71 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
72 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
73 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
74 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */
75 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */
76 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
77 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */
78 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
79 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
80 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
81 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
82 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
83 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
84 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
85 { 0x820cc000, 0x0e000, 0x01000 }, /* WF_UMAC_TOP (PP) */
86 { 0x820cd000, 0x0f000, 0x01000 }, /* WF_MDP_TOP */
87 { 0x74030000, 0x10000, 0x10000 }, /* PCIE_MAC_IREG */
88 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
89 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
90 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
91 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
92 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
93 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
94 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
95 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
96 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
97 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
98 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
99 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
100 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
101 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
102 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
103 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
104 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
105 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
106 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
107 };
108 int i;
109
110 if (addr < 0x100000)
111 return addr;
112
113 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
114 u32 ofs;
115
116 if (addr < fixed_map[i].phys)
117 continue;
118
119 ofs = addr - fixed_map[i].phys;
120 if (ofs > fixed_map[i].size)
121 continue;
122
123 return fixed_map[i].maps + ofs;
124 }
125
126 if ((addr >= 0x18000000 && addr < 0x18c00000) ||
127 (addr >= 0x70000000 && addr < 0x78000000) ||
128 (addr >= 0x7c000000 && addr < 0x7c400000))
129 return mt7921_reg_map_l1(dev, addr);
130
131 dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n",
132 addr);
133
134 return 0;
135}
136
137static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset)
138{
139 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
140 u32 addr = __mt7921_reg_addr(dev, offset);
141
142 return dev->bus_ops->rr(mdev, addr);
143}
144
145static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val)
146{
147 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
148 u32 addr = __mt7921_reg_addr(dev, offset);
149
150 dev->bus_ops->wr(mdev, addr, val);
151}
152
153static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
154{
155 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
156 u32 addr = __mt7921_reg_addr(dev, offset);
157
158 return dev->bus_ops->rmw(mdev, addr, mask, val);
159}
160
161static int mt7921_dma_init(struct mt792x_dev *dev)
162{
163 int ret;
164
165 mt76_dma_attach(&dev->mt76);
166
167 ret = mt792x_dma_disable(dev, true);
168 if (ret)
169 return ret;
170
171 /* init tx queue */
172 ret = mt76_connac_init_tx_queues(dev->phy.mt76, MT7921_TXQ_BAND0,
173 MT7921_TX_RING_SIZE,
174 MT_TX_RING_BASE, NULL, 0);
175 if (ret)
176 return ret;
177
178 mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, 0x4);
179
180 /* command to WM */
181 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7921_TXQ_MCU_WM,
182 MT7921_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
183 if (ret)
184 return ret;
185
186 /* firmware download */
187 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7921_TXQ_FWDL,
188 MT7921_TX_FWDL_RING_SIZE, MT_TX_RING_BASE);
189 if (ret)
190 return ret;
191
192 /* event from WM before firmware download */
193 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
194 MT7921_RXQ_MCU_WM,
195 MT7921_RX_MCU_RING_SIZE,
196 MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE);
197 if (ret)
198 return ret;
199
200 /* Change mcu queue after firmware download */
201 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
202 MT7921_RXQ_MCU_WM,
203 MT7921_RX_MCU_WA_RING_SIZE,
204 MT_RX_BUF_SIZE, MT_WFDMA0(0x540));
205 if (ret)
206 return ret;
207
208 /* rx data */
209 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
210 MT7921_RXQ_BAND0, MT7921_RX_RING_SIZE,
211 MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE);
212 if (ret)
213 return ret;
214
215 ret = mt76_init_queues(dev, mt792x_poll_rx);
216 if (ret < 0)
217 return ret;
218
219 netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
220 mt792x_poll_tx);
221 napi_enable(&dev->mt76.tx_napi);
222
223 return mt792x_dma_enable(dev);
224}
225
226static int mt7921_pci_probe(struct pci_dev *pdev,
227 const struct pci_device_id *id)
228{
229 static const struct mt76_driver_ops drv_ops = {
230 /* txwi_size = txd size + txp size */
231 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_hw_txp),
232 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ |
233 MT_DRV_AMSDU_OFFLOAD,
234 .survey_flags = SURVEY_INFO_TIME_TX |
235 SURVEY_INFO_TIME_RX |
236 SURVEY_INFO_TIME_BSS_RX,
237 .token_size = MT7921_TOKEN_SIZE,
238 .tx_prepare_skb = mt7921e_tx_prepare_skb,
239 .tx_complete_skb = mt76_connac_tx_complete_skb,
240 .rx_check = mt7921_rx_check,
241 .rx_skb = mt7921_queue_rx_skb,
242 .rx_poll_complete = mt792x_rx_poll_complete,
243 .sta_add = mt7921_mac_sta_add,
244 .sta_assoc = mt7921_mac_sta_assoc,
245 .sta_remove = mt7921_mac_sta_remove,
246 .update_survey = mt792x_update_channel,
247 };
248 static const struct mt792x_hif_ops mt7921_pcie_ops = {
249 .init_reset = mt7921e_init_reset,
250 .reset = mt7921e_mac_reset,
251 .mcu_init = mt7921e_mcu_init,
252 .drv_own = mt792xe_mcu_drv_pmctrl,
253 .fw_own = mt792xe_mcu_fw_pmctrl,
254 };
255 static const struct mt792x_irq_map irq_map = {
256 .host_irq_enable = MT_WFDMA0_HOST_INT_ENA,
257 .tx = {
258 .all_complete_mask = MT_INT_TX_DONE_ALL,
259 .mcu_complete_mask = MT_INT_TX_DONE_MCU,
260 },
261 .rx = {
262 .data_complete_mask = MT_INT_RX_DONE_DATA,
263 .wm_complete_mask = MT_INT_RX_DONE_WM,
264 .wm2_complete_mask = MT_INT_RX_DONE_WM2,
265 },
266 };
267 struct ieee80211_ops *ops;
268 struct mt76_bus_ops *bus_ops;
269 struct mt792x_dev *dev;
270 struct mt76_dev *mdev;
271 u8 features;
272 int ret;
273 u16 cmd;
274
275 ret = pcim_enable_device(pdev);
276 if (ret)
277 return ret;
278
279 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
280 if (ret)
281 return ret;
282
283 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
284 if (!(cmd & PCI_COMMAND_MEMORY)) {
285 cmd |= PCI_COMMAND_MEMORY;
286 pci_write_config_word(pdev, PCI_COMMAND, cmd);
287 }
288 pci_set_master(pdev);
289
290 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
291 if (ret < 0)
292 return ret;
293
294 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
295 if (ret)
296 goto err_free_pci_vec;
297
298 if (mt7921_disable_aspm)
299 mt76_pci_disable_aspm(pdev);
300
301 ops = mt792x_get_mac80211_ops(&pdev->dev, &mt7921_ops,
302 (void *)id->driver_data, &features);
303 if (!ops) {
304 ret = -ENOMEM;
305 goto err_free_pci_vec;
306 }
307
308 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), ops, &drv_ops);
309 if (!mdev) {
310 ret = -ENOMEM;
311 goto err_free_pci_vec;
312 }
313
314 pci_set_drvdata(pdev, mdev);
315
316 dev = container_of(mdev, struct mt792x_dev, mt76);
317 dev->fw_features = features;
318 dev->hif_ops = &mt7921_pcie_ops;
319 dev->irq_map = &irq_map;
320 mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]);
321 tasklet_init(&mdev->irq_tasklet, mt792x_irq_tasklet, (unsigned long)dev);
322
323 dev->phy.dev = dev;
324 dev->phy.mt76 = &dev->mt76.phy;
325 dev->mt76.phy.priv = &dev->phy;
326 dev->bus_ops = dev->mt76.bus;
327 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
328 GFP_KERNEL);
329 if (!bus_ops) {
330 ret = -ENOMEM;
331 goto err_free_dev;
332 }
333
334 bus_ops->rr = mt7921_rr;
335 bus_ops->wr = mt7921_wr;
336 bus_ops->rmw = mt7921_rmw;
337 dev->mt76.bus = bus_ops;
338
339 ret = mt792xe_mcu_fw_pmctrl(dev);
340 if (ret)
341 goto err_free_dev;
342
343 ret = __mt792xe_mcu_drv_pmctrl(dev);
344 if (ret)
345 goto err_free_dev;
346
347 mdev->rev = (mt7921_l1_rr(dev, MT_HW_CHIPID) << 16) |
348 (mt7921_l1_rr(dev, MT_HW_REV) & 0xff);
349 dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
350
351 ret = mt792x_wfsys_reset(dev);
352 if (ret)
353 goto err_free_dev;
354
355 mt76_wr(dev, irq_map.host_irq_enable, 0);
356
357 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
358
359 ret = devm_request_irq(mdev->dev, pdev->irq, mt792x_irq_handler,
360 IRQF_SHARED, KBUILD_MODNAME, dev);
361 if (ret)
362 goto err_free_dev;
363
364 ret = mt7921_dma_init(dev);
365 if (ret)
366 goto err_free_irq;
367
368 ret = mt7921_register_device(dev);
369 if (ret)
370 goto err_free_irq;
371
372 return 0;
373
374err_free_irq:
375 devm_free_irq(&pdev->dev, pdev->irq, dev);
376err_free_dev:
377 mt76_free_device(&dev->mt76);
378err_free_pci_vec:
379 pci_free_irq_vectors(pdev);
380
381 return ret;
382}
383
384static void mt7921_pci_remove(struct pci_dev *pdev)
385{
386 struct mt76_dev *mdev = pci_get_drvdata(pdev);
387 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
388
389 mt7921e_unregister_device(dev);
390 devm_free_irq(&pdev->dev, pdev->irq, dev);
391 mt76_free_device(&dev->mt76);
392 pci_free_irq_vectors(pdev);
393}
394
395static int mt7921_pci_suspend(struct device *device)
396{
397 struct pci_dev *pdev = to_pci_dev(device);
398 struct mt76_dev *mdev = pci_get_drvdata(pdev);
399 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
400 struct mt76_connac_pm *pm = &dev->pm;
401 int i, err;
402
403 pm->suspended = true;
404 flush_work(&dev->reset_work);
405 cancel_delayed_work_sync(&pm->ps_work);
406 cancel_work_sync(&pm->wake_work);
407
408 err = mt792x_mcu_drv_pmctrl(dev);
409 if (err < 0)
410 goto restore_suspend;
411
412 err = mt76_connac_mcu_set_hif_suspend(mdev, true);
413 if (err)
414 goto restore_suspend;
415
416 /* always enable deep sleep during suspend to reduce
417 * power consumption
418 */
419 mt76_connac_mcu_set_deep_sleep(&dev->mt76, true);
420
421 napi_disable(&mdev->tx_napi);
422 mt76_worker_disable(&mdev->tx_worker);
423
424 mt76_for_each_q_rx(mdev, i) {
425 napi_disable(&mdev->napi[i]);
426 }
427
428 /* wait until dma is idle */
429 mt76_poll(dev, MT_WFDMA0_GLO_CFG,
430 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
431 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000);
432
433 /* put dma disabled */
434 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
435 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
436
437 /* disable interrupt */
438 mt76_wr(dev, dev->irq_map->host_irq_enable, 0);
439 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);
440 synchronize_irq(pdev->irq);
441 tasklet_kill(&mdev->irq_tasklet);
442
443 err = mt792x_mcu_fw_pmctrl(dev);
444 if (err)
445 goto restore_napi;
446
447 return 0;
448
449restore_napi:
450 mt76_for_each_q_rx(mdev, i) {
451 napi_enable(&mdev->napi[i]);
452 }
453 napi_enable(&mdev->tx_napi);
454
455 if (!pm->ds_enable)
456 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
457
458 mt76_connac_mcu_set_hif_suspend(mdev, false);
459
460restore_suspend:
461 pm->suspended = false;
462
463 if (err < 0)
464 mt792x_reset(&dev->mt76);
465
466 return err;
467}
468
469static int mt7921_pci_resume(struct device *device)
470{
471 struct pci_dev *pdev = to_pci_dev(device);
472 struct mt76_dev *mdev = pci_get_drvdata(pdev);
473 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
474 struct mt76_connac_pm *pm = &dev->pm;
475 int i, err;
476
477 err = mt792x_mcu_drv_pmctrl(dev);
478 if (err < 0)
479 goto failed;
480
481 mt792x_wpdma_reinit_cond(dev);
482
483 /* enable interrupt */
484 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
485 mt76_connac_irq_enable(&dev->mt76,
486 dev->irq_map->tx.all_complete_mask |
487 MT_INT_RX_DONE_ALL | MT_INT_MCU_CMD);
488 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);
489
490 /* put dma enabled */
491 mt76_set(dev, MT_WFDMA0_GLO_CFG,
492 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
493
494 mt76_worker_enable(&mdev->tx_worker);
495
496 local_bh_disable();
497 mt76_for_each_q_rx(mdev, i) {
498 napi_enable(&mdev->napi[i]);
499 napi_schedule(&mdev->napi[i]);
500 }
501 napi_enable(&mdev->tx_napi);
502 napi_schedule(&mdev->tx_napi);
503 local_bh_enable();
504
505 /* restore previous ds setting */
506 if (!pm->ds_enable)
507 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
508
509 err = mt76_connac_mcu_set_hif_suspend(mdev, false);
510
511 mt7921_regd_update(dev);
512
513failed:
514 pm->suspended = false;
515
516 if (err < 0)
517 mt792x_reset(&dev->mt76);
518
519 return err;
520}
521
522static void mt7921_pci_shutdown(struct pci_dev *pdev)
523{
524 mt7921_pci_remove(pdev);
525}
526
527static DEFINE_SIMPLE_DEV_PM_OPS(mt7921_pm_ops, mt7921_pci_suspend, mt7921_pci_resume);
528
529static struct pci_driver mt7921_pci_driver = {
530 .name = KBUILD_MODNAME,
531 .id_table = mt7921_pci_device_table,
532 .probe = mt7921_pci_probe,
533 .remove = mt7921_pci_remove,
534 .shutdown = mt7921_pci_shutdown,
535 .driver.pm = pm_sleep_ptr(&mt7921_pm_ops),
536};
537
538module_pci_driver(mt7921_pci_driver);
539
540MODULE_DEVICE_TABLE(pci, mt7921_pci_device_table);
541MODULE_FIRMWARE(MT7921_FIRMWARE_WM);
542MODULE_FIRMWARE(MT7921_ROM_PATCH);
543MODULE_FIRMWARE(MT7922_FIRMWARE_WM);
544MODULE_FIRMWARE(MT7922_ROM_PATCH);
545MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
546MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
547MODULE_DESCRIPTION("MediaTek MT7921E (PCIe) wireless driver");
548MODULE_LICENSE("Dual BSD/GPL");
1// SPDX-License-Identifier: ISC
2/* Copyright (C) 2020 MediaTek Inc.
3 *
4 */
5
6#include <linux/kernel.h>
7#include <linux/module.h>
8#include <linux/pci.h>
9
10#include "mt7921.h"
11#include "mac.h"
12#include "mcu.h"
13#include "../trace.h"
14
15static const struct pci_device_id mt7921_pci_device_table[] = {
16 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961),
17 .driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM },
18 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922),
19 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM },
20 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608),
21 .driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM },
22 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616),
23 .driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM },
24 { },
25};
26
27static bool mt7921_disable_aspm;
28module_param_named(disable_aspm, mt7921_disable_aspm, bool, 0644);
29MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support");
30
31static void
32mt7921_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
33{
34 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
35
36 if (q == MT_RXQ_MAIN)
37 mt7921_irq_enable(dev, MT_INT_RX_DONE_DATA);
38 else if (q == MT_RXQ_MCU_WA)
39 mt7921_irq_enable(dev, MT_INT_RX_DONE_WM2);
40 else
41 mt7921_irq_enable(dev, MT_INT_RX_DONE_WM);
42}
43
44static irqreturn_t mt7921_irq_handler(int irq, void *dev_instance)
45{
46 struct mt7921_dev *dev = dev_instance;
47
48 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
49
50 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
51 return IRQ_NONE;
52
53 tasklet_schedule(&dev->irq_tasklet);
54
55 return IRQ_HANDLED;
56}
57
58static void mt7921_irq_tasklet(unsigned long data)
59{
60 struct mt7921_dev *dev = (struct mt7921_dev *)data;
61 u32 intr, mask = 0;
62
63 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
64
65 intr = mt76_rr(dev, MT_WFDMA0_HOST_INT_STA);
66 intr &= dev->mt76.mmio.irqmask;
67 mt76_wr(dev, MT_WFDMA0_HOST_INT_STA, intr);
68
69 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
70
71 mask |= intr & MT_INT_RX_DONE_ALL;
72 if (intr & MT_INT_TX_DONE_MCU)
73 mask |= MT_INT_TX_DONE_MCU;
74
75 if (intr & MT_INT_MCU_CMD) {
76 u32 intr_sw;
77
78 intr_sw = mt76_rr(dev, MT_MCU_CMD);
79 /* ack MCU2HOST_SW_INT_STA */
80 mt76_wr(dev, MT_MCU_CMD, intr_sw);
81 if (intr_sw & MT_MCU_CMD_WAKE_RX_PCIE) {
82 mask |= MT_INT_RX_DONE_DATA;
83 intr |= MT_INT_RX_DONE_DATA;
84 }
85 }
86
87 mt76_set_irq_mask(&dev->mt76, MT_WFDMA0_HOST_INT_ENA, mask, 0);
88
89 if (intr & MT_INT_TX_DONE_ALL)
90 napi_schedule(&dev->mt76.tx_napi);
91
92 if (intr & MT_INT_RX_DONE_WM)
93 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]);
94
95 if (intr & MT_INT_RX_DONE_WM2)
96 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]);
97
98 if (intr & MT_INT_RX_DONE_DATA)
99 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]);
100}
101
102static int mt7921e_init_reset(struct mt7921_dev *dev)
103{
104 return mt7921_wpdma_reset(dev, true);
105}
106
107static void mt7921e_unregister_device(struct mt7921_dev *dev)
108{
109 int i;
110 struct mt76_connac_pm *pm = &dev->pm;
111
112 cancel_work_sync(&dev->init_work);
113 mt76_unregister_device(&dev->mt76);
114 mt76_for_each_q_rx(&dev->mt76, i)
115 napi_disable(&dev->mt76.napi[i]);
116 cancel_delayed_work_sync(&pm->ps_work);
117 cancel_work_sync(&pm->wake_work);
118
119 mt7921_tx_token_put(dev);
120 mt7921_mcu_drv_pmctrl(dev);
121 mt7921_dma_cleanup(dev);
122 mt7921_wfsys_reset(dev);
123 skb_queue_purge(&dev->mt76.mcu.res_q);
124
125 tasklet_disable(&dev->irq_tasklet);
126}
127
128static u32 __mt7921_reg_addr(struct mt7921_dev *dev, u32 addr)
129{
130 static const struct mt76_connac_reg_map fixed_map[] = {
131 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
132 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
133 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
134 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
135 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
136 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
137 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
138 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
139 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
140 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
141 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
142 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */
143 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */
144 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
145 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */
146 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
147 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
148 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
149 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
150 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
151 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
152 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
153 { 0x820cc000, 0x0e000, 0x01000 }, /* WF_UMAC_TOP (PP) */
154 { 0x820cd000, 0x0f000, 0x01000 }, /* WF_MDP_TOP */
155 { 0x74030000, 0x10000, 0x10000 }, /* PCIE_MAC_IREG */
156 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
157 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
158 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
159 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
160 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
161 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
162 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
163 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
164 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
165 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
166 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
167 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
168 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
169 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
170 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
171 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
172 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
173 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
174 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
175 };
176 int i;
177
178 if (addr < 0x100000)
179 return addr;
180
181 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
182 u32 ofs;
183
184 if (addr < fixed_map[i].phys)
185 continue;
186
187 ofs = addr - fixed_map[i].phys;
188 if (ofs > fixed_map[i].size)
189 continue;
190
191 return fixed_map[i].maps + ofs;
192 }
193
194 if ((addr >= 0x18000000 && addr < 0x18c00000) ||
195 (addr >= 0x70000000 && addr < 0x78000000) ||
196 (addr >= 0x7c000000 && addr < 0x7c400000))
197 return mt7921_reg_map_l1(dev, addr);
198
199 dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n",
200 addr);
201
202 return 0;
203}
204
205static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset)
206{
207 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
208 u32 addr = __mt7921_reg_addr(dev, offset);
209
210 return dev->bus_ops->rr(mdev, addr);
211}
212
213static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val)
214{
215 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
216 u32 addr = __mt7921_reg_addr(dev, offset);
217
218 dev->bus_ops->wr(mdev, addr, val);
219}
220
221static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
222{
223 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
224 u32 addr = __mt7921_reg_addr(dev, offset);
225
226 return dev->bus_ops->rmw(mdev, addr, mask, val);
227}
228
229static int mt7921_pci_probe(struct pci_dev *pdev,
230 const struct pci_device_id *id)
231{
232 static const struct mt76_driver_ops drv_ops = {
233 /* txwi_size = txd size + txp size */
234 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_hw_txp),
235 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ |
236 MT_DRV_AMSDU_OFFLOAD,
237 .survey_flags = SURVEY_INFO_TIME_TX |
238 SURVEY_INFO_TIME_RX |
239 SURVEY_INFO_TIME_BSS_RX,
240 .token_size = MT7921_TOKEN_SIZE,
241 .tx_prepare_skb = mt7921e_tx_prepare_skb,
242 .tx_complete_skb = mt76_connac_tx_complete_skb,
243 .rx_check = mt7921_rx_check,
244 .rx_skb = mt7921_queue_rx_skb,
245 .rx_poll_complete = mt7921_rx_poll_complete,
246 .sta_ps = mt7921_sta_ps,
247 .sta_add = mt7921_mac_sta_add,
248 .sta_assoc = mt7921_mac_sta_assoc,
249 .sta_remove = mt7921_mac_sta_remove,
250 .update_survey = mt7921_update_channel,
251 };
252 static const struct mt7921_hif_ops mt7921_pcie_ops = {
253 .init_reset = mt7921e_init_reset,
254 .reset = mt7921e_mac_reset,
255 .mcu_init = mt7921e_mcu_init,
256 .drv_own = mt7921e_mcu_drv_pmctrl,
257 .fw_own = mt7921e_mcu_fw_pmctrl,
258 };
259
260 struct ieee80211_ops *ops;
261 struct mt76_bus_ops *bus_ops;
262 struct mt7921_dev *dev;
263 struct mt76_dev *mdev;
264 u8 features;
265 int ret;
266
267 ret = pcim_enable_device(pdev);
268 if (ret)
269 return ret;
270
271 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
272 if (ret)
273 return ret;
274
275 pci_set_master(pdev);
276
277 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
278 if (ret < 0)
279 return ret;
280
281 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
282 if (ret)
283 goto err_free_pci_vec;
284
285 if (mt7921_disable_aspm)
286 mt76_pci_disable_aspm(pdev);
287
288 features = mt7921_check_offload_capability(&pdev->dev, (const char *)
289 id->driver_data);
290 ops = devm_kmemdup(&pdev->dev, &mt7921_ops, sizeof(mt7921_ops),
291 GFP_KERNEL);
292 if (!ops) {
293 ret = -ENOMEM;
294 goto err_free_pci_vec;
295 }
296
297 if (!(features & MT7921_FW_CAP_CNM)) {
298 ops->remain_on_channel = NULL;
299 ops->cancel_remain_on_channel = NULL;
300 ops->add_chanctx = NULL;
301 ops->remove_chanctx = NULL;
302 ops->change_chanctx = NULL;
303 ops->assign_vif_chanctx = NULL;
304 ops->unassign_vif_chanctx = NULL;
305 ops->mgd_prepare_tx = NULL;
306 ops->mgd_complete_tx = NULL;
307 }
308
309 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), ops, &drv_ops);
310 if (!mdev) {
311 ret = -ENOMEM;
312 goto err_free_pci_vec;
313 }
314
315 pci_set_drvdata(pdev, mdev);
316
317 dev = container_of(mdev, struct mt7921_dev, mt76);
318 dev->fw_features = features;
319 dev->hif_ops = &mt7921_pcie_ops;
320 mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]);
321 tasklet_init(&dev->irq_tasklet, mt7921_irq_tasklet, (unsigned long)dev);
322
323 dev->phy.dev = dev;
324 dev->phy.mt76 = &dev->mt76.phy;
325 dev->mt76.phy.priv = &dev->phy;
326 dev->bus_ops = dev->mt76.bus;
327 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
328 GFP_KERNEL);
329 if (!bus_ops) {
330 ret = -ENOMEM;
331 goto err_free_dev;
332 }
333
334 bus_ops->rr = mt7921_rr;
335 bus_ops->wr = mt7921_wr;
336 bus_ops->rmw = mt7921_rmw;
337 dev->mt76.bus = bus_ops;
338
339 ret = __mt7921e_mcu_drv_pmctrl(dev);
340 if (ret)
341 goto err_free_dev;
342
343 mdev->rev = (mt7921_l1_rr(dev, MT_HW_CHIPID) << 16) |
344 (mt7921_l1_rr(dev, MT_HW_REV) & 0xff);
345 dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
346
347 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
348
349 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
350
351 ret = devm_request_irq(mdev->dev, pdev->irq, mt7921_irq_handler,
352 IRQF_SHARED, KBUILD_MODNAME, dev);
353 if (ret)
354 goto err_free_dev;
355
356 ret = mt7921_dma_init(dev);
357 if (ret)
358 goto err_free_irq;
359
360 ret = mt7921_register_device(dev);
361 if (ret)
362 goto err_free_irq;
363
364 return 0;
365
366err_free_irq:
367 devm_free_irq(&pdev->dev, pdev->irq, dev);
368err_free_dev:
369 mt76_free_device(&dev->mt76);
370err_free_pci_vec:
371 pci_free_irq_vectors(pdev);
372
373 return ret;
374}
375
376static void mt7921_pci_remove(struct pci_dev *pdev)
377{
378 struct mt76_dev *mdev = pci_get_drvdata(pdev);
379 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
380
381 mt7921e_unregister_device(dev);
382 devm_free_irq(&pdev->dev, pdev->irq, dev);
383 mt76_free_device(&dev->mt76);
384 pci_free_irq_vectors(pdev);
385}
386
387static int mt7921_pci_suspend(struct device *device)
388{
389 struct pci_dev *pdev = to_pci_dev(device);
390 struct mt76_dev *mdev = pci_get_drvdata(pdev);
391 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
392 struct mt76_connac_pm *pm = &dev->pm;
393 int i, err;
394
395 pm->suspended = true;
396 flush_work(&dev->reset_work);
397 cancel_delayed_work_sync(&pm->ps_work);
398 cancel_work_sync(&pm->wake_work);
399
400 err = mt7921_mcu_drv_pmctrl(dev);
401 if (err < 0)
402 goto restore_suspend;
403
404 err = mt76_connac_mcu_set_hif_suspend(mdev, true);
405 if (err)
406 goto restore_suspend;
407
408 /* always enable deep sleep during suspend to reduce
409 * power consumption
410 */
411 mt76_connac_mcu_set_deep_sleep(&dev->mt76, true);
412
413 napi_disable(&mdev->tx_napi);
414 mt76_worker_disable(&mdev->tx_worker);
415
416 mt76_for_each_q_rx(mdev, i) {
417 napi_disable(&mdev->napi[i]);
418 }
419
420 /* wait until dma is idle */
421 mt76_poll(dev, MT_WFDMA0_GLO_CFG,
422 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
423 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000);
424
425 /* put dma disabled */
426 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
427 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
428
429 /* disable interrupt */
430 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
431 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);
432 synchronize_irq(pdev->irq);
433 tasklet_kill(&dev->irq_tasklet);
434
435 err = mt7921_mcu_fw_pmctrl(dev);
436 if (err)
437 goto restore_napi;
438
439 return 0;
440
441restore_napi:
442 mt76_for_each_q_rx(mdev, i) {
443 napi_enable(&mdev->napi[i]);
444 }
445 napi_enable(&mdev->tx_napi);
446
447 if (!pm->ds_enable)
448 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
449
450 mt76_connac_mcu_set_hif_suspend(mdev, false);
451
452restore_suspend:
453 pm->suspended = false;
454
455 if (err < 0)
456 mt7921_reset(&dev->mt76);
457
458 return err;
459}
460
461static int mt7921_pci_resume(struct device *device)
462{
463 struct pci_dev *pdev = to_pci_dev(device);
464 struct mt76_dev *mdev = pci_get_drvdata(pdev);
465 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
466 struct mt76_connac_pm *pm = &dev->pm;
467 int i, err;
468
469 err = mt7921_mcu_drv_pmctrl(dev);
470 if (err < 0)
471 goto failed;
472
473 mt7921_wpdma_reinit_cond(dev);
474
475 /* enable interrupt */
476 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
477 mt7921_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
478 MT_INT_MCU_CMD);
479 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);
480
481 /* put dma enabled */
482 mt76_set(dev, MT_WFDMA0_GLO_CFG,
483 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
484
485 mt76_worker_enable(&mdev->tx_worker);
486
487 local_bh_disable();
488 mt76_for_each_q_rx(mdev, i) {
489 napi_enable(&mdev->napi[i]);
490 napi_schedule(&mdev->napi[i]);
491 }
492 napi_enable(&mdev->tx_napi);
493 napi_schedule(&mdev->tx_napi);
494 local_bh_enable();
495
496 /* restore previous ds setting */
497 if (!pm->ds_enable)
498 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
499
500 err = mt76_connac_mcu_set_hif_suspend(mdev, false);
501failed:
502 pm->suspended = false;
503
504 if (err < 0)
505 mt7921_reset(&dev->mt76);
506
507 return err;
508}
509
510static void mt7921_pci_shutdown(struct pci_dev *pdev)
511{
512 struct mt76_dev *mdev = pci_get_drvdata(pdev);
513 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
514 struct mt76_connac_pm *pm = &dev->pm;
515
516 cancel_delayed_work_sync(&pm->ps_work);
517 cancel_work_sync(&pm->wake_work);
518
519 /* chip cleanup before reboot */
520 mt7921_mcu_drv_pmctrl(dev);
521 mt7921_dma_cleanup(dev);
522 mt7921_wfsys_reset(dev);
523}
524
525static DEFINE_SIMPLE_DEV_PM_OPS(mt7921_pm_ops, mt7921_pci_suspend, mt7921_pci_resume);
526
527static struct pci_driver mt7921_pci_driver = {
528 .name = KBUILD_MODNAME,
529 .id_table = mt7921_pci_device_table,
530 .probe = mt7921_pci_probe,
531 .remove = mt7921_pci_remove,
532 .shutdown = mt7921_pci_shutdown,
533 .driver.pm = pm_sleep_ptr(&mt7921_pm_ops),
534};
535
536module_pci_driver(mt7921_pci_driver);
537
538MODULE_DEVICE_TABLE(pci, mt7921_pci_device_table);
539MODULE_FIRMWARE(MT7921_FIRMWARE_WM);
540MODULE_FIRMWARE(MT7921_ROM_PATCH);
541MODULE_FIRMWARE(MT7922_FIRMWARE_WM);
542MODULE_FIRMWARE(MT7922_ROM_PATCH);
543MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
544MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
545MODULE_LICENSE("Dual BSD/GPL");