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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for Aquantia PHY
4 *
5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com>
6 *
7 * Copyright 2015 Freescale Semiconductor, Inc.
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/delay.h>
13#include <linux/bitfield.h>
14#include <linux/phy.h>
15
16#include "aquantia.h"
17
18#define PHY_ID_AQ1202 0x03a1b445
19#define PHY_ID_AQ2104 0x03a1b460
20#define PHY_ID_AQR105 0x03a1b4a2
21#define PHY_ID_AQR106 0x03a1b4d0
22#define PHY_ID_AQR107 0x03a1b4e0
23#define PHY_ID_AQCS109 0x03a1b5c2
24#define PHY_ID_AQR405 0x03a1b4b0
25#define PHY_ID_AQR112 0x03a1b662
26#define PHY_ID_AQR412 0x03a1b712
27#define PHY_ID_AQR113C 0x31c31c12
28
29#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
30#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
31#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
32#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1
33#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2
34#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3
35#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4
36#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
37#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7
38#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
39
40#define MDIO_AN_VEND_PROV 0xc400
41#define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
42#define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
43#define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11)
44#define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10)
45#define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4)
46#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)
47#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
48
49#define MDIO_AN_TX_VEND_STATUS1 0xc800
50#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)
51#define MDIO_AN_TX_VEND_STATUS1_10BASET 0
52#define MDIO_AN_TX_VEND_STATUS1_100BASETX 1
53#define MDIO_AN_TX_VEND_STATUS1_1000BASET 2
54#define MDIO_AN_TX_VEND_STATUS1_10GBASET 3
55#define MDIO_AN_TX_VEND_STATUS1_2500BASET 4
56#define MDIO_AN_TX_VEND_STATUS1_5000BASET 5
57#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0)
58
59#define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00
60#define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1)
61
62#define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01
63#define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0)
64
65#define MDIO_AN_TX_VEND_INT_MASK2 0xd401
66#define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
67
68#define MDIO_AN_RX_LP_STAT1 0xe820
69#define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15)
70#define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14)
71#define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13)
72#define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12)
73#define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2)
74
75#define MDIO_AN_RX_LP_STAT4 0xe823
76#define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8)
77#define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0)
78
79#define MDIO_AN_RX_VEND_STAT3 0xe832
80#define MDIO_AN_RX_VEND_STAT3_AFR BIT(0)
81
82/* MDIO_MMD_C22EXT */
83#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
84#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
85#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
86#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
87#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
88#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
89#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
90#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
91#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
92#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
93
94/* Vendor specific 1, MDIO_MMD_VEND1 */
95#define VEND1_GLOBAL_FW_ID 0x0020
96#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
97#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
98
99#define VEND1_GLOBAL_GEN_STAT2 0xc831
100#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
101
102/* The following registers all have similar layouts; first the registers... */
103#define VEND1_GLOBAL_CFG_10M 0x0310
104#define VEND1_GLOBAL_CFG_100M 0x031b
105#define VEND1_GLOBAL_CFG_1G 0x031c
106#define VEND1_GLOBAL_CFG_2_5G 0x031d
107#define VEND1_GLOBAL_CFG_5G 0x031e
108#define VEND1_GLOBAL_CFG_10G 0x031f
109/* ...and now the fields */
110#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
111#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
112#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
113#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
114
115#define VEND1_GLOBAL_RSVD_STAT1 0xc885
116#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
117#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
118
119#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
120#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
121#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
122
123#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
124#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
125
126#define VEND1_GLOBAL_INT_STD_MASK 0xff00
127#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
128#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
129#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
130#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
131#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
132#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
133#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
134#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
135#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
136#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
137#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
138
139#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
140#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
141#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
142#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
143#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
144#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
145#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
146#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
147#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
148
149/* Sleep and timeout for checking if the Processor-Intensive
150 * MDIO operation is finished
151 */
152#define AQR107_OP_IN_PROG_SLEEP 1000
153#define AQR107_OP_IN_PROG_TIMEOUT 100000
154
155struct aqr107_hw_stat {
156 const char *name;
157 int reg;
158 int size;
159};
160
161#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
162static const struct aqr107_hw_stat aqr107_hw_stats[] = {
163 SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
164 SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
165 SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8),
166 SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26),
167 SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26),
168 SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8),
169 SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8),
170 SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
171 SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
172 SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
173};
174#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
175
176struct aqr107_priv {
177 u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
178};
179
180static int aqr107_get_sset_count(struct phy_device *phydev)
181{
182 return AQR107_SGMII_STAT_SZ;
183}
184
185static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
186{
187 int i;
188
189 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)
190 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name,
191 ETH_GSTRING_LEN);
192}
193
194static u64 aqr107_get_stat(struct phy_device *phydev, int index)
195{
196 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index;
197 int len_l = min(stat->size, 16);
198 int len_h = stat->size - len_l;
199 u64 ret;
200 int val;
201
202 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
203 if (val < 0)
204 return U64_MAX;
205
206 ret = val & GENMASK(len_l - 1, 0);
207 if (len_h) {
208 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
209 if (val < 0)
210 return U64_MAX;
211
212 ret += (val & GENMASK(len_h - 1, 0)) << 16;
213 }
214
215 return ret;
216}
217
218static void aqr107_get_stats(struct phy_device *phydev,
219 struct ethtool_stats *stats, u64 *data)
220{
221 struct aqr107_priv *priv = phydev->priv;
222 u64 val;
223 int i;
224
225 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {
226 val = aqr107_get_stat(phydev, i);
227 if (val == U64_MAX)
228 phydev_err(phydev, "Reading HW Statistics failed for %s\n",
229 aqr107_hw_stats[i].name);
230 else
231 priv->sgmii_stats[i] += val;
232
233 data[i] = priv->sgmii_stats[i];
234 }
235}
236
237static int aqr_config_aneg(struct phy_device *phydev)
238{
239 bool changed = false;
240 u16 reg;
241 int ret;
242
243 if (phydev->autoneg == AUTONEG_DISABLE)
244 return genphy_c45_pma_setup_forced(phydev);
245
246 ret = genphy_c45_an_config_aneg(phydev);
247 if (ret < 0)
248 return ret;
249 if (ret > 0)
250 changed = true;
251
252 /* Clause 45 has no standardized support for 1000BaseT, therefore
253 * use vendor registers for this mode.
254 */
255 reg = 0;
256 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
257 phydev->advertising))
258 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
259
260 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
261 phydev->advertising))
262 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
263
264 /* Handle the case when the 2.5G and 5G speeds are not advertised */
265 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
266 phydev->advertising))
267 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL;
268
269 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
270 phydev->advertising))
271 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL;
272
273 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
274 MDIO_AN_VEND_PROV_1000BASET_HALF |
275 MDIO_AN_VEND_PROV_1000BASET_FULL |
276 MDIO_AN_VEND_PROV_2500BASET_FULL |
277 MDIO_AN_VEND_PROV_5000BASET_FULL, reg);
278 if (ret < 0)
279 return ret;
280 if (ret > 0)
281 changed = true;
282
283 return genphy_c45_check_and_restart_aneg(phydev, changed);
284}
285
286static int aqr_config_intr(struct phy_device *phydev)
287{
288 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
289 int err;
290
291 if (en) {
292 /* Clear any pending interrupts before enabling them */
293 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
294 if (err < 0)
295 return err;
296 }
297
298 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
299 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);
300 if (err < 0)
301 return err;
302
303 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
304 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);
305 if (err < 0)
306 return err;
307
308 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
309 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
310 VEND1_GLOBAL_INT_VEND_MASK_AN : 0);
311 if (err < 0)
312 return err;
313
314 if (!en) {
315 /* Clear any pending interrupts after we have disabled them */
316 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
317 if (err < 0)
318 return err;
319 }
320
321 return 0;
322}
323
324static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev)
325{
326 int irq_status;
327
328 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN,
329 MDIO_AN_TX_VEND_INT_STATUS2);
330 if (irq_status < 0) {
331 phy_error(phydev);
332 return IRQ_NONE;
333 }
334
335 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK))
336 return IRQ_NONE;
337
338 phy_trigger_machine(phydev);
339
340 return IRQ_HANDLED;
341}
342
343static int aqr_read_status(struct phy_device *phydev)
344{
345 int val;
346
347 if (phydev->autoneg == AUTONEG_ENABLE) {
348 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
349 if (val < 0)
350 return val;
351
352 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
353 phydev->lp_advertising,
354 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
355 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
356 phydev->lp_advertising,
357 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
358 }
359
360 return genphy_c45_read_status(phydev);
361}
362
363static int aqr107_read_rate(struct phy_device *phydev)
364{
365 u32 config_reg;
366 int val;
367
368 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
369 if (val < 0)
370 return val;
371
372 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
373 phydev->duplex = DUPLEX_FULL;
374 else
375 phydev->duplex = DUPLEX_HALF;
376
377 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
378 case MDIO_AN_TX_VEND_STATUS1_10BASET:
379 phydev->speed = SPEED_10;
380 config_reg = VEND1_GLOBAL_CFG_10M;
381 break;
382 case MDIO_AN_TX_VEND_STATUS1_100BASETX:
383 phydev->speed = SPEED_100;
384 config_reg = VEND1_GLOBAL_CFG_100M;
385 break;
386 case MDIO_AN_TX_VEND_STATUS1_1000BASET:
387 phydev->speed = SPEED_1000;
388 config_reg = VEND1_GLOBAL_CFG_1G;
389 break;
390 case MDIO_AN_TX_VEND_STATUS1_2500BASET:
391 phydev->speed = SPEED_2500;
392 config_reg = VEND1_GLOBAL_CFG_2_5G;
393 break;
394 case MDIO_AN_TX_VEND_STATUS1_5000BASET:
395 phydev->speed = SPEED_5000;
396 config_reg = VEND1_GLOBAL_CFG_5G;
397 break;
398 case MDIO_AN_TX_VEND_STATUS1_10GBASET:
399 phydev->speed = SPEED_10000;
400 config_reg = VEND1_GLOBAL_CFG_10G;
401 break;
402 default:
403 phydev->speed = SPEED_UNKNOWN;
404 return 0;
405 }
406
407 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);
408 if (val < 0)
409 return val;
410
411 if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) ==
412 VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)
413 phydev->rate_matching = RATE_MATCH_PAUSE;
414 else
415 phydev->rate_matching = RATE_MATCH_NONE;
416
417 return 0;
418}
419
420static int aqr107_read_status(struct phy_device *phydev)
421{
422 int val, ret;
423
424 ret = aqr_read_status(phydev);
425 if (ret)
426 return ret;
427
428 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
429 return 0;
430
431 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
432 if (val < 0)
433 return val;
434
435 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
436 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
437 phydev->interface = PHY_INTERFACE_MODE_10GKR;
438 break;
439 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX:
440 phydev->interface = PHY_INTERFACE_MODE_1000BASEKX;
441 break;
442 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
443 phydev->interface = PHY_INTERFACE_MODE_10GBASER;
444 break;
445 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
446 phydev->interface = PHY_INTERFACE_MODE_USXGMII;
447 break;
448 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI:
449 phydev->interface = PHY_INTERFACE_MODE_XAUI;
450 break;
451 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
452 phydev->interface = PHY_INTERFACE_MODE_SGMII;
453 break;
454 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI:
455 phydev->interface = PHY_INTERFACE_MODE_RXAUI;
456 break;
457 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
458 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
459 break;
460 default:
461 phydev->interface = PHY_INTERFACE_MODE_NA;
462 break;
463 }
464
465 /* Read possibly downshifted rate from vendor register */
466 return aqr107_read_rate(phydev);
467}
468
469static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
470{
471 int val, cnt, enable;
472
473 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
474 if (val < 0)
475 return val;
476
477 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
478 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
479
480 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
481
482 return 0;
483}
484
485static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
486{
487 int val = 0;
488
489 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
490 return -E2BIG;
491
492 if (cnt != DOWNSHIFT_DEV_DISABLE) {
493 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
494 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
495 }
496
497 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
498 MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
499 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
500}
501
502static int aqr107_get_tunable(struct phy_device *phydev,
503 struct ethtool_tunable *tuna, void *data)
504{
505 switch (tuna->id) {
506 case ETHTOOL_PHY_DOWNSHIFT:
507 return aqr107_get_downshift(phydev, data);
508 default:
509 return -EOPNOTSUPP;
510 }
511}
512
513static int aqr107_set_tunable(struct phy_device *phydev,
514 struct ethtool_tunable *tuna, const void *data)
515{
516 switch (tuna->id) {
517 case ETHTOOL_PHY_DOWNSHIFT:
518 return aqr107_set_downshift(phydev, *(const u8 *)data);
519 default:
520 return -EOPNOTSUPP;
521 }
522}
523
524/* If we configure settings whilst firmware is still initializing the chip,
525 * then these settings may be overwritten. Therefore make sure chip
526 * initialization has completed. Use presence of the firmware ID as
527 * indicator for initialization having completed.
528 * The chip also provides a "reset completed" bit, but it's cleared after
529 * read. Therefore function would time out if called again.
530 */
531static int aqr107_wait_reset_complete(struct phy_device *phydev)
532{
533 int val;
534
535 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
536 VEND1_GLOBAL_FW_ID, val, val != 0,
537 20000, 2000000, false);
538}
539
540static void aqr107_chip_info(struct phy_device *phydev)
541{
542 u8 fw_major, fw_minor, build_id, prov_id;
543 int val;
544
545 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
546 if (val < 0)
547 return;
548
549 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val);
550 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val);
551
552 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
553 if (val < 0)
554 return;
555
556 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
557 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
558
559 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
560 fw_major, fw_minor, build_id, prov_id);
561}
562
563static int aqr107_config_init(struct phy_device *phydev)
564{
565 int ret;
566
567 /* Check that the PHY interface type is compatible */
568 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
569 phydev->interface != PHY_INTERFACE_MODE_1000BASEKX &&
570 phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
571 phydev->interface != PHY_INTERFACE_MODE_XGMII &&
572 phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
573 phydev->interface != PHY_INTERFACE_MODE_10GKR &&
574 phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
575 phydev->interface != PHY_INTERFACE_MODE_XAUI &&
576 phydev->interface != PHY_INTERFACE_MODE_RXAUI)
577 return -ENODEV;
578
579 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
580 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
581
582 ret = aqr107_wait_reset_complete(phydev);
583 if (!ret)
584 aqr107_chip_info(phydev);
585
586 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
587}
588
589static int aqcs109_config_init(struct phy_device *phydev)
590{
591 int ret;
592
593 /* Check that the PHY interface type is compatible */
594 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
595 phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
596 return -ENODEV;
597
598 ret = aqr107_wait_reset_complete(phydev);
599 if (!ret)
600 aqr107_chip_info(phydev);
601
602 /* AQCS109 belongs to a chip family partially supporting 10G and 5G.
603 * PMA speed ability bits are the same for all members of the family,
604 * AQCS109 however supports speeds up to 2.5G only.
605 */
606 phy_set_max_speed(phydev, SPEED_2500);
607
608 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
609}
610
611static void aqr107_link_change_notify(struct phy_device *phydev)
612{
613 u8 fw_major, fw_minor;
614 bool downshift, short_reach, afr;
615 int mode, val;
616
617 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
618 return;
619
620 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
621 /* call failed or link partner is no Aquantia PHY */
622 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
623 return;
624
625 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
626 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
627
628 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
629 if (val < 0)
630 return;
631
632 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
633 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
634
635 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
636 if (val < 0)
637 return;
638
639 afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
640
641 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
642 fw_major, fw_minor,
643 short_reach ? ", short reach mode" : "",
644 downshift ? ", fast-retrain downshift advertised" : "",
645 afr ? ", fast reframe advertised" : "");
646
647 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
648 if (val < 0)
649 return;
650
651 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
652 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
653 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
654}
655
656static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
657{
658 int val, err;
659
660 /* The datasheet notes to wait at least 1ms after issuing a
661 * processor intensive operation before checking.
662 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout
663 * because that just determines the maximum time slept, not the minimum.
664 */
665 usleep_range(1000, 5000);
666
667 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
668 VEND1_GLOBAL_GEN_STAT2, val,
669 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG),
670 AQR107_OP_IN_PROG_SLEEP,
671 AQR107_OP_IN_PROG_TIMEOUT, false);
672 if (err) {
673 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");
674 return err;
675 }
676
677 return 0;
678}
679
680static int aqr107_get_rate_matching(struct phy_device *phydev,
681 phy_interface_t iface)
682{
683 if (iface == PHY_INTERFACE_MODE_10GBASER ||
684 iface == PHY_INTERFACE_MODE_2500BASEX ||
685 iface == PHY_INTERFACE_MODE_NA)
686 return RATE_MATCH_PAUSE;
687 return RATE_MATCH_NONE;
688}
689
690static int aqr107_suspend(struct phy_device *phydev)
691{
692 int err;
693
694 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
695 MDIO_CTRL1_LPOWER);
696 if (err)
697 return err;
698
699 return aqr107_wait_processor_intensive_op(phydev);
700}
701
702static int aqr107_resume(struct phy_device *phydev)
703{
704 int err;
705
706 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
707 MDIO_CTRL1_LPOWER);
708 if (err)
709 return err;
710
711 return aqr107_wait_processor_intensive_op(phydev);
712}
713
714static int aqr107_probe(struct phy_device *phydev)
715{
716 phydev->priv = devm_kzalloc(&phydev->mdio.dev,
717 sizeof(struct aqr107_priv), GFP_KERNEL);
718 if (!phydev->priv)
719 return -ENOMEM;
720
721 return aqr_hwmon_probe(phydev);
722}
723
724static struct phy_driver aqr_driver[] = {
725{
726 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
727 .name = "Aquantia AQ1202",
728 .config_aneg = aqr_config_aneg,
729 .config_intr = aqr_config_intr,
730 .handle_interrupt = aqr_handle_interrupt,
731 .read_status = aqr_read_status,
732},
733{
734 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
735 .name = "Aquantia AQ2104",
736 .config_aneg = aqr_config_aneg,
737 .config_intr = aqr_config_intr,
738 .handle_interrupt = aqr_handle_interrupt,
739 .read_status = aqr_read_status,
740},
741{
742 PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
743 .name = "Aquantia AQR105",
744 .config_aneg = aqr_config_aneg,
745 .config_intr = aqr_config_intr,
746 .handle_interrupt = aqr_handle_interrupt,
747 .read_status = aqr_read_status,
748 .suspend = aqr107_suspend,
749 .resume = aqr107_resume,
750},
751{
752 PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
753 .name = "Aquantia AQR106",
754 .config_aneg = aqr_config_aneg,
755 .config_intr = aqr_config_intr,
756 .handle_interrupt = aqr_handle_interrupt,
757 .read_status = aqr_read_status,
758},
759{
760 PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
761 .name = "Aquantia AQR107",
762 .probe = aqr107_probe,
763 .get_rate_matching = aqr107_get_rate_matching,
764 .config_init = aqr107_config_init,
765 .config_aneg = aqr_config_aneg,
766 .config_intr = aqr_config_intr,
767 .handle_interrupt = aqr_handle_interrupt,
768 .read_status = aqr107_read_status,
769 .get_tunable = aqr107_get_tunable,
770 .set_tunable = aqr107_set_tunable,
771 .suspend = aqr107_suspend,
772 .resume = aqr107_resume,
773 .get_sset_count = aqr107_get_sset_count,
774 .get_strings = aqr107_get_strings,
775 .get_stats = aqr107_get_stats,
776 .link_change_notify = aqr107_link_change_notify,
777},
778{
779 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
780 .name = "Aquantia AQCS109",
781 .probe = aqr107_probe,
782 .get_rate_matching = aqr107_get_rate_matching,
783 .config_init = aqcs109_config_init,
784 .config_aneg = aqr_config_aneg,
785 .config_intr = aqr_config_intr,
786 .handle_interrupt = aqr_handle_interrupt,
787 .read_status = aqr107_read_status,
788 .get_tunable = aqr107_get_tunable,
789 .set_tunable = aqr107_set_tunable,
790 .suspend = aqr107_suspend,
791 .resume = aqr107_resume,
792 .get_sset_count = aqr107_get_sset_count,
793 .get_strings = aqr107_get_strings,
794 .get_stats = aqr107_get_stats,
795 .link_change_notify = aqr107_link_change_notify,
796},
797{
798 PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
799 .name = "Aquantia AQR405",
800 .config_aneg = aqr_config_aneg,
801 .config_intr = aqr_config_intr,
802 .handle_interrupt = aqr_handle_interrupt,
803 .read_status = aqr_read_status,
804},
805{
806 PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
807 .name = "Aquantia AQR112",
808 .probe = aqr107_probe,
809 .config_aneg = aqr_config_aneg,
810 .config_intr = aqr_config_intr,
811 .handle_interrupt = aqr_handle_interrupt,
812 .get_tunable = aqr107_get_tunable,
813 .set_tunable = aqr107_set_tunable,
814 .suspend = aqr107_suspend,
815 .resume = aqr107_resume,
816 .read_status = aqr107_read_status,
817 .get_rate_matching = aqr107_get_rate_matching,
818 .get_sset_count = aqr107_get_sset_count,
819 .get_strings = aqr107_get_strings,
820 .get_stats = aqr107_get_stats,
821 .link_change_notify = aqr107_link_change_notify,
822},
823{
824 PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
825 .name = "Aquantia AQR412",
826 .probe = aqr107_probe,
827 .config_aneg = aqr_config_aneg,
828 .config_intr = aqr_config_intr,
829 .handle_interrupt = aqr_handle_interrupt,
830 .get_tunable = aqr107_get_tunable,
831 .set_tunable = aqr107_set_tunable,
832 .suspend = aqr107_suspend,
833 .resume = aqr107_resume,
834 .read_status = aqr107_read_status,
835 .get_rate_matching = aqr107_get_rate_matching,
836 .get_sset_count = aqr107_get_sset_count,
837 .get_strings = aqr107_get_strings,
838 .get_stats = aqr107_get_stats,
839 .link_change_notify = aqr107_link_change_notify,
840},
841{
842 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
843 .name = "Aquantia AQR113C",
844 .probe = aqr107_probe,
845 .get_rate_matching = aqr107_get_rate_matching,
846 .config_init = aqr107_config_init,
847 .config_aneg = aqr_config_aneg,
848 .config_intr = aqr_config_intr,
849 .handle_interrupt = aqr_handle_interrupt,
850 .read_status = aqr107_read_status,
851 .get_tunable = aqr107_get_tunable,
852 .set_tunable = aqr107_set_tunable,
853 .suspend = aqr107_suspend,
854 .resume = aqr107_resume,
855 .get_sset_count = aqr107_get_sset_count,
856 .get_strings = aqr107_get_strings,
857 .get_stats = aqr107_get_stats,
858 .link_change_notify = aqr107_link_change_notify,
859},
860};
861
862module_phy_driver(aqr_driver);
863
864static struct mdio_device_id __maybe_unused aqr_tbl[] = {
865 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
866 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
867 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
868 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
869 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
870 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
871 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
872 { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
873 { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
874 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
875 { }
876};
877
878MODULE_DEVICE_TABLE(mdio, aqr_tbl);
879
880MODULE_DESCRIPTION("Aquantia PHY driver");
881MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
882MODULE_LICENSE("GPL v2");