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1// SPDX-License-Identifier: GPL-2.0-only
2/*******************************************************************************
3 DWMAC Management Counters
4
5 Copyright (C) 2011 STMicroelectronics Ltd
6
7
8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9*******************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/io.h>
13#include "hwif.h"
14#include "mmc.h"
15
16/* MAC Management Counters register offset */
17
18#define MMC_CNTRL 0x00 /* MMC Control */
19#define MMC_RX_INTR 0x04 /* MMC RX Interrupt */
20#define MMC_TX_INTR 0x08 /* MMC TX Interrupt */
21#define MMC_RX_INTR_MASK 0x0c /* MMC Interrupt Mask */
22#define MMC_TX_INTR_MASK 0x10 /* MMC Interrupt Mask */
23#define MMC_DEFAULT_MASK 0xffffffff
24
25/* MMC TX counter registers */
26
27/* Note:
28 * _GB register stands for good and bad frames
29 * _G is for good only.
30 */
31#define MMC_TX_OCTETCOUNT_GB 0x14
32#define MMC_TX_FRAMECOUNT_GB 0x18
33#define MMC_TX_BROADCASTFRAME_G 0x1c
34#define MMC_TX_MULTICASTFRAME_G 0x20
35#define MMC_TX_64_OCTETS_GB 0x24
36#define MMC_TX_65_TO_127_OCTETS_GB 0x28
37#define MMC_TX_128_TO_255_OCTETS_GB 0x2c
38#define MMC_TX_256_TO_511_OCTETS_GB 0x30
39#define MMC_TX_512_TO_1023_OCTETS_GB 0x34
40#define MMC_TX_1024_TO_MAX_OCTETS_GB 0x38
41#define MMC_TX_UNICAST_GB 0x3c
42#define MMC_TX_MULTICAST_GB 0x40
43#define MMC_TX_BROADCAST_GB 0x44
44#define MMC_TX_UNDERFLOW_ERROR 0x48
45#define MMC_TX_SINGLECOL_G 0x4c
46#define MMC_TX_MULTICOL_G 0x50
47#define MMC_TX_DEFERRED 0x54
48#define MMC_TX_LATECOL 0x58
49#define MMC_TX_EXESSCOL 0x5c
50#define MMC_TX_CARRIER_ERROR 0x60
51#define MMC_TX_OCTETCOUNT_G 0x64
52#define MMC_TX_FRAMECOUNT_G 0x68
53#define MMC_TX_EXCESSDEF 0x6c
54#define MMC_TX_PAUSE_FRAME 0x70
55#define MMC_TX_VLAN_FRAME_G 0x74
56
57/* MMC RX counter registers */
58#define MMC_RX_FRAMECOUNT_GB 0x80
59#define MMC_RX_OCTETCOUNT_GB 0x84
60#define MMC_RX_OCTETCOUNT_G 0x88
61#define MMC_RX_BROADCASTFRAME_G 0x8c
62#define MMC_RX_MULTICASTFRAME_G 0x90
63#define MMC_RX_CRC_ERROR 0x94
64#define MMC_RX_ALIGN_ERROR 0x98
65#define MMC_RX_RUN_ERROR 0x9C
66#define MMC_RX_JABBER_ERROR 0xA0
67#define MMC_RX_UNDERSIZE_G 0xA4
68#define MMC_RX_OVERSIZE_G 0xA8
69#define MMC_RX_64_OCTETS_GB 0xAC
70#define MMC_RX_65_TO_127_OCTETS_GB 0xb0
71#define MMC_RX_128_TO_255_OCTETS_GB 0xb4
72#define MMC_RX_256_TO_511_OCTETS_GB 0xb8
73#define MMC_RX_512_TO_1023_OCTETS_GB 0xbc
74#define MMC_RX_1024_TO_MAX_OCTETS_GB 0xc0
75#define MMC_RX_UNICAST_G 0xc4
76#define MMC_RX_LENGTH_ERROR 0xc8
77#define MMC_RX_AUTOFRANGETYPE 0xcc
78#define MMC_RX_PAUSE_FRAMES 0xd0
79#define MMC_RX_FIFO_OVERFLOW 0xd4
80#define MMC_RX_VLAN_FRAMES_GB 0xd8
81#define MMC_RX_WATCHDOG_ERROR 0xdc
82/* IPC*/
83#define MMC_RX_IPC_INTR_MASK 0x100
84#define MMC_RX_IPC_INTR 0x108
85/* IPv4*/
86#define MMC_RX_IPV4_GD 0x110
87#define MMC_RX_IPV4_HDERR 0x114
88#define MMC_RX_IPV4_NOPAY 0x118
89#define MMC_RX_IPV4_FRAG 0x11C
90#define MMC_RX_IPV4_UDSBL 0x120
91
92#define MMC_RX_IPV4_GD_OCTETS 0x150
93#define MMC_RX_IPV4_HDERR_OCTETS 0x154
94#define MMC_RX_IPV4_NOPAY_OCTETS 0x158
95#define MMC_RX_IPV4_FRAG_OCTETS 0x15c
96#define MMC_RX_IPV4_UDSBL_OCTETS 0x160
97
98/* IPV6*/
99#define MMC_RX_IPV6_GD_OCTETS 0x164
100#define MMC_RX_IPV6_HDERR_OCTETS 0x168
101#define MMC_RX_IPV6_NOPAY_OCTETS 0x16c
102
103#define MMC_RX_IPV6_GD 0x124
104#define MMC_RX_IPV6_HDERR 0x128
105#define MMC_RX_IPV6_NOPAY 0x12c
106
107/* Protocols*/
108#define MMC_RX_UDP_GD 0x130
109#define MMC_RX_UDP_ERR 0x134
110#define MMC_RX_TCP_GD 0x138
111#define MMC_RX_TCP_ERR 0x13c
112#define MMC_RX_ICMP_GD 0x140
113#define MMC_RX_ICMP_ERR 0x144
114
115#define MMC_RX_UDP_GD_OCTETS 0x170
116#define MMC_RX_UDP_ERR_OCTETS 0x174
117#define MMC_RX_TCP_GD_OCTETS 0x178
118#define MMC_RX_TCP_ERR_OCTETS 0x17c
119#define MMC_RX_ICMP_GD_OCTETS 0x180
120#define MMC_RX_ICMP_ERR_OCTETS 0x184
121
122#define MMC_TX_FPE_FRAG 0x1a8
123#define MMC_TX_HOLD_REQ 0x1ac
124#define MMC_RX_PKT_ASSEMBLY_ERR 0x1c8
125#define MMC_RX_PKT_SMD_ERR 0x1cc
126#define MMC_RX_PKT_ASSEMBLY_OK 0x1d0
127#define MMC_RX_FPE_FRAG 0x1d4
128
129/* XGMAC MMC Registers */
130#define MMC_XGMAC_TX_OCTET_GB 0x14
131#define MMC_XGMAC_TX_PKT_GB 0x1c
132#define MMC_XGMAC_TX_BROAD_PKT_G 0x24
133#define MMC_XGMAC_TX_MULTI_PKT_G 0x2c
134#define MMC_XGMAC_TX_64OCT_GB 0x34
135#define MMC_XGMAC_TX_65OCT_GB 0x3c
136#define MMC_XGMAC_TX_128OCT_GB 0x44
137#define MMC_XGMAC_TX_256OCT_GB 0x4c
138#define MMC_XGMAC_TX_512OCT_GB 0x54
139#define MMC_XGMAC_TX_1024OCT_GB 0x5c
140#define MMC_XGMAC_TX_UNI_PKT_GB 0x64
141#define MMC_XGMAC_TX_MULTI_PKT_GB 0x6c
142#define MMC_XGMAC_TX_BROAD_PKT_GB 0x74
143#define MMC_XGMAC_TX_UNDER 0x7c
144#define MMC_XGMAC_TX_OCTET_G 0x84
145#define MMC_XGMAC_TX_PKT_G 0x8c
146#define MMC_XGMAC_TX_PAUSE 0x94
147#define MMC_XGMAC_TX_VLAN_PKT_G 0x9c
148#define MMC_XGMAC_TX_LPI_USEC 0xa4
149#define MMC_XGMAC_TX_LPI_TRAN 0xa8
150
151#define MMC_XGMAC_RX_PKT_GB 0x100
152#define MMC_XGMAC_RX_OCTET_GB 0x108
153#define MMC_XGMAC_RX_OCTET_G 0x110
154#define MMC_XGMAC_RX_BROAD_PKT_G 0x118
155#define MMC_XGMAC_RX_MULTI_PKT_G 0x120
156#define MMC_XGMAC_RX_CRC_ERR 0x128
157#define MMC_XGMAC_RX_RUNT_ERR 0x130
158#define MMC_XGMAC_RX_JABBER_ERR 0x134
159#define MMC_XGMAC_RX_UNDER 0x138
160#define MMC_XGMAC_RX_OVER 0x13c
161#define MMC_XGMAC_RX_64OCT_GB 0x140
162#define MMC_XGMAC_RX_65OCT_GB 0x148
163#define MMC_XGMAC_RX_128OCT_GB 0x150
164#define MMC_XGMAC_RX_256OCT_GB 0x158
165#define MMC_XGMAC_RX_512OCT_GB 0x160
166#define MMC_XGMAC_RX_1024OCT_GB 0x168
167#define MMC_XGMAC_RX_UNI_PKT_G 0x170
168#define MMC_XGMAC_RX_LENGTH_ERR 0x178
169#define MMC_XGMAC_RX_RANGE 0x180
170#define MMC_XGMAC_RX_PAUSE 0x188
171#define MMC_XGMAC_RX_FIFOOVER_PKT 0x190
172#define MMC_XGMAC_RX_VLAN_PKT_GB 0x198
173#define MMC_XGMAC_RX_WATCHDOG_ERR 0x1a0
174#define MMC_XGMAC_RX_LPI_USEC 0x1a4
175#define MMC_XGMAC_RX_LPI_TRAN 0x1a8
176#define MMC_XGMAC_RX_DISCARD_PKT_GB 0x1ac
177#define MMC_XGMAC_RX_DISCARD_OCT_GB 0x1b4
178#define MMC_XGMAC_RX_ALIGN_ERR_PKT 0x1bc
179
180#define MMC_XGMAC_SGF_PASS_PKT 0x1f0
181#define MMC_XGMAC_SGF_FAIL_PKT 0x1f4
182#define MMC_XGMAC_TX_FPE_INTR_MASK 0x204
183#define MMC_XGMAC_TX_FPE_FRAG 0x208
184#define MMC_XGMAC_TX_HOLD_REQ 0x20c
185#define MMC_XGMAC_TX_GATE_OVERRUN 0x210
186#define MMC_XGMAC_RX_FPE_INTR_MASK 0x224
187#define MMC_XGMAC_RX_PKT_ASSEMBLY_ERR 0x228
188#define MMC_XGMAC_RX_PKT_SMD_ERR 0x22c
189#define MMC_XGMAC_RX_PKT_ASSEMBLY_OK 0x230
190#define MMC_XGMAC_RX_FPE_FRAG 0x234
191#define MMC_XGMAC_RX_IPC_INTR_MASK 0x25c
192
193#define MMC_XGMAC_RX_IPV4_GD 0x264
194#define MMC_XGMAC_RX_IPV4_HDERR 0x26c
195#define MMC_XGMAC_RX_IPV4_NOPAY 0x274
196#define MMC_XGMAC_RX_IPV4_FRAG 0x27c
197#define MMC_XGMAC_RX_IPV4_UDSBL 0x284
198
199#define MMC_XGMAC_RX_IPV6_GD 0x28c
200#define MMC_XGMAC_RX_IPV6_HDERR 0x294
201#define MMC_XGMAC_RX_IPV6_NOPAY 0x29c
202
203#define MMC_XGMAC_RX_UDP_GD 0x2a4
204#define MMC_XGMAC_RX_UDP_ERR 0x2ac
205#define MMC_XGMAC_RX_TCP_GD 0x2b4
206#define MMC_XGMAC_RX_TCP_ERR 0x2bc
207#define MMC_XGMAC_RX_ICMP_GD 0x2c4
208#define MMC_XGMAC_RX_ICMP_ERR 0x2cc
209
210#define MMC_XGMAC_RX_IPV4_GD_OCTETS 0x2d4
211#define MMC_XGMAC_RX_IPV4_HDERR_OCTETS 0x2dc
212#define MMC_XGMAC_RX_IPV4_NOPAY_OCTETS 0x2e4
213#define MMC_XGMAC_RX_IPV4_FRAG_OCTETS 0x2ec
214#define MMC_XGMAC_RX_IPV4_UDSBL_OCTETS 0x2f4
215
216#define MMC_XGMAC_RX_IPV6_GD_OCTETS 0x2fc
217#define MMC_XGMAC_RX_IPV6_HDERR_OCTETS 0x304
218#define MMC_XGMAC_RX_IPV6_NOPAY_OCTETS 0x30c
219
220#define MMC_XGMAC_RX_UDP_GD_OCTETS 0x314
221#define MMC_XGMAC_RX_UDP_ERR_OCTETS 0x31c
222#define MMC_XGMAC_RX_TCP_GD_OCTETS 0x324
223#define MMC_XGMAC_RX_TCP_ERR_OCTETS 0x32c
224#define MMC_XGMAC_RX_ICMP_GD_OCTETS 0x334
225#define MMC_XGMAC_RX_ICMP_ERR_OCTETS 0x33c
226
227static void dwmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)
228{
229 u32 value = readl(mmcaddr + MMC_CNTRL);
230
231 value |= (mode & 0x3F);
232
233 writel(value, mmcaddr + MMC_CNTRL);
234
235 pr_debug("stmmac: MMC ctrl register (offset 0x%x): 0x%08x\n",
236 MMC_CNTRL, value);
237}
238
239/* To mask all interrupts.*/
240static void dwmac_mmc_intr_all_mask(void __iomem *mmcaddr)
241{
242 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_INTR_MASK);
243 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_TX_INTR_MASK);
244 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_IPC_INTR_MASK);
245}
246
247/* This reads the MAC core counters (if actaully supported).
248 * by default the MMC core is programmed to reset each
249 * counter after a read. So all the field of the mmc struct
250 * have to be incremented.
251 */
252static void dwmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)
253{
254 mmc->mmc_tx_octetcount_gb += readl(mmcaddr + MMC_TX_OCTETCOUNT_GB);
255 mmc->mmc_tx_framecount_gb += readl(mmcaddr + MMC_TX_FRAMECOUNT_GB);
256 mmc->mmc_tx_broadcastframe_g += readl(mmcaddr +
257 MMC_TX_BROADCASTFRAME_G);
258 mmc->mmc_tx_multicastframe_g += readl(mmcaddr +
259 MMC_TX_MULTICASTFRAME_G);
260 mmc->mmc_tx_64_octets_gb += readl(mmcaddr + MMC_TX_64_OCTETS_GB);
261 mmc->mmc_tx_65_to_127_octets_gb +=
262 readl(mmcaddr + MMC_TX_65_TO_127_OCTETS_GB);
263 mmc->mmc_tx_128_to_255_octets_gb +=
264 readl(mmcaddr + MMC_TX_128_TO_255_OCTETS_GB);
265 mmc->mmc_tx_256_to_511_octets_gb +=
266 readl(mmcaddr + MMC_TX_256_TO_511_OCTETS_GB);
267 mmc->mmc_tx_512_to_1023_octets_gb +=
268 readl(mmcaddr + MMC_TX_512_TO_1023_OCTETS_GB);
269 mmc->mmc_tx_1024_to_max_octets_gb +=
270 readl(mmcaddr + MMC_TX_1024_TO_MAX_OCTETS_GB);
271 mmc->mmc_tx_unicast_gb += readl(mmcaddr + MMC_TX_UNICAST_GB);
272 mmc->mmc_tx_multicast_gb += readl(mmcaddr + MMC_TX_MULTICAST_GB);
273 mmc->mmc_tx_broadcast_gb += readl(mmcaddr + MMC_TX_BROADCAST_GB);
274 mmc->mmc_tx_underflow_error += readl(mmcaddr + MMC_TX_UNDERFLOW_ERROR);
275 mmc->mmc_tx_singlecol_g += readl(mmcaddr + MMC_TX_SINGLECOL_G);
276 mmc->mmc_tx_multicol_g += readl(mmcaddr + MMC_TX_MULTICOL_G);
277 mmc->mmc_tx_deferred += readl(mmcaddr + MMC_TX_DEFERRED);
278 mmc->mmc_tx_latecol += readl(mmcaddr + MMC_TX_LATECOL);
279 mmc->mmc_tx_exesscol += readl(mmcaddr + MMC_TX_EXESSCOL);
280 mmc->mmc_tx_carrier_error += readl(mmcaddr + MMC_TX_CARRIER_ERROR);
281 mmc->mmc_tx_octetcount_g += readl(mmcaddr + MMC_TX_OCTETCOUNT_G);
282 mmc->mmc_tx_framecount_g += readl(mmcaddr + MMC_TX_FRAMECOUNT_G);
283 mmc->mmc_tx_excessdef += readl(mmcaddr + MMC_TX_EXCESSDEF);
284 mmc->mmc_tx_pause_frame += readl(mmcaddr + MMC_TX_PAUSE_FRAME);
285 mmc->mmc_tx_vlan_frame_g += readl(mmcaddr + MMC_TX_VLAN_FRAME_G);
286
287 /* MMC RX counter registers */
288 mmc->mmc_rx_framecount_gb += readl(mmcaddr + MMC_RX_FRAMECOUNT_GB);
289 mmc->mmc_rx_octetcount_gb += readl(mmcaddr + MMC_RX_OCTETCOUNT_GB);
290 mmc->mmc_rx_octetcount_g += readl(mmcaddr + MMC_RX_OCTETCOUNT_G);
291 mmc->mmc_rx_broadcastframe_g += readl(mmcaddr +
292 MMC_RX_BROADCASTFRAME_G);
293 mmc->mmc_rx_multicastframe_g += readl(mmcaddr +
294 MMC_RX_MULTICASTFRAME_G);
295 mmc->mmc_rx_crc_error += readl(mmcaddr + MMC_RX_CRC_ERROR);
296 mmc->mmc_rx_align_error += readl(mmcaddr + MMC_RX_ALIGN_ERROR);
297 mmc->mmc_rx_run_error += readl(mmcaddr + MMC_RX_RUN_ERROR);
298 mmc->mmc_rx_jabber_error += readl(mmcaddr + MMC_RX_JABBER_ERROR);
299 mmc->mmc_rx_undersize_g += readl(mmcaddr + MMC_RX_UNDERSIZE_G);
300 mmc->mmc_rx_oversize_g += readl(mmcaddr + MMC_RX_OVERSIZE_G);
301 mmc->mmc_rx_64_octets_gb += readl(mmcaddr + MMC_RX_64_OCTETS_GB);
302 mmc->mmc_rx_65_to_127_octets_gb +=
303 readl(mmcaddr + MMC_RX_65_TO_127_OCTETS_GB);
304 mmc->mmc_rx_128_to_255_octets_gb +=
305 readl(mmcaddr + MMC_RX_128_TO_255_OCTETS_GB);
306 mmc->mmc_rx_256_to_511_octets_gb +=
307 readl(mmcaddr + MMC_RX_256_TO_511_OCTETS_GB);
308 mmc->mmc_rx_512_to_1023_octets_gb +=
309 readl(mmcaddr + MMC_RX_512_TO_1023_OCTETS_GB);
310 mmc->mmc_rx_1024_to_max_octets_gb +=
311 readl(mmcaddr + MMC_RX_1024_TO_MAX_OCTETS_GB);
312 mmc->mmc_rx_unicast_g += readl(mmcaddr + MMC_RX_UNICAST_G);
313 mmc->mmc_rx_length_error += readl(mmcaddr + MMC_RX_LENGTH_ERROR);
314 mmc->mmc_rx_autofrangetype += readl(mmcaddr + MMC_RX_AUTOFRANGETYPE);
315 mmc->mmc_rx_pause_frames += readl(mmcaddr + MMC_RX_PAUSE_FRAMES);
316 mmc->mmc_rx_fifo_overflow += readl(mmcaddr + MMC_RX_FIFO_OVERFLOW);
317 mmc->mmc_rx_vlan_frames_gb += readl(mmcaddr + MMC_RX_VLAN_FRAMES_GB);
318 mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_RX_WATCHDOG_ERROR);
319 /* IPC */
320 mmc->mmc_rx_ipc_intr_mask += readl(mmcaddr + MMC_RX_IPC_INTR_MASK);
321 mmc->mmc_rx_ipc_intr += readl(mmcaddr + MMC_RX_IPC_INTR);
322 /* IPv4 */
323 mmc->mmc_rx_ipv4_gd += readl(mmcaddr + MMC_RX_IPV4_GD);
324 mmc->mmc_rx_ipv4_hderr += readl(mmcaddr + MMC_RX_IPV4_HDERR);
325 mmc->mmc_rx_ipv4_nopay += readl(mmcaddr + MMC_RX_IPV4_NOPAY);
326 mmc->mmc_rx_ipv4_frag += readl(mmcaddr + MMC_RX_IPV4_FRAG);
327 mmc->mmc_rx_ipv4_udsbl += readl(mmcaddr + MMC_RX_IPV4_UDSBL);
328
329 mmc->mmc_rx_ipv4_gd_octets += readl(mmcaddr + MMC_RX_IPV4_GD_OCTETS);
330 mmc->mmc_rx_ipv4_hderr_octets +=
331 readl(mmcaddr + MMC_RX_IPV4_HDERR_OCTETS);
332 mmc->mmc_rx_ipv4_nopay_octets +=
333 readl(mmcaddr + MMC_RX_IPV4_NOPAY_OCTETS);
334 mmc->mmc_rx_ipv4_frag_octets += readl(mmcaddr +
335 MMC_RX_IPV4_FRAG_OCTETS);
336 mmc->mmc_rx_ipv4_udsbl_octets +=
337 readl(mmcaddr + MMC_RX_IPV4_UDSBL_OCTETS);
338
339 /* IPV6 */
340 mmc->mmc_rx_ipv6_gd_octets += readl(mmcaddr + MMC_RX_IPV6_GD_OCTETS);
341 mmc->mmc_rx_ipv6_hderr_octets +=
342 readl(mmcaddr + MMC_RX_IPV6_HDERR_OCTETS);
343 mmc->mmc_rx_ipv6_nopay_octets +=
344 readl(mmcaddr + MMC_RX_IPV6_NOPAY_OCTETS);
345
346 mmc->mmc_rx_ipv6_gd += readl(mmcaddr + MMC_RX_IPV6_GD);
347 mmc->mmc_rx_ipv6_hderr += readl(mmcaddr + MMC_RX_IPV6_HDERR);
348 mmc->mmc_rx_ipv6_nopay += readl(mmcaddr + MMC_RX_IPV6_NOPAY);
349
350 /* Protocols */
351 mmc->mmc_rx_udp_gd += readl(mmcaddr + MMC_RX_UDP_GD);
352 mmc->mmc_rx_udp_err += readl(mmcaddr + MMC_RX_UDP_ERR);
353 mmc->mmc_rx_tcp_gd += readl(mmcaddr + MMC_RX_TCP_GD);
354 mmc->mmc_rx_tcp_err += readl(mmcaddr + MMC_RX_TCP_ERR);
355 mmc->mmc_rx_icmp_gd += readl(mmcaddr + MMC_RX_ICMP_GD);
356 mmc->mmc_rx_icmp_err += readl(mmcaddr + MMC_RX_ICMP_ERR);
357
358 mmc->mmc_rx_udp_gd_octets += readl(mmcaddr + MMC_RX_UDP_GD_OCTETS);
359 mmc->mmc_rx_udp_err_octets += readl(mmcaddr + MMC_RX_UDP_ERR_OCTETS);
360 mmc->mmc_rx_tcp_gd_octets += readl(mmcaddr + MMC_RX_TCP_GD_OCTETS);
361 mmc->mmc_rx_tcp_err_octets += readl(mmcaddr + MMC_RX_TCP_ERR_OCTETS);
362 mmc->mmc_rx_icmp_gd_octets += readl(mmcaddr + MMC_RX_ICMP_GD_OCTETS);
363 mmc->mmc_rx_icmp_err_octets += readl(mmcaddr + MMC_RX_ICMP_ERR_OCTETS);
364
365 mmc->mmc_tx_fpe_fragment_cntr += readl(mmcaddr + MMC_TX_FPE_FRAG);
366 mmc->mmc_tx_hold_req_cntr += readl(mmcaddr + MMC_TX_HOLD_REQ);
367 mmc->mmc_rx_packet_assembly_err_cntr +=
368 readl(mmcaddr + MMC_RX_PKT_ASSEMBLY_ERR);
369 mmc->mmc_rx_packet_smd_err_cntr += readl(mmcaddr + MMC_RX_PKT_SMD_ERR);
370 mmc->mmc_rx_packet_assembly_ok_cntr +=
371 readl(mmcaddr + MMC_RX_PKT_ASSEMBLY_OK);
372 mmc->mmc_rx_fpe_fragment_cntr += readl(mmcaddr + MMC_RX_FPE_FRAG);
373}
374
375const struct stmmac_mmc_ops dwmac_mmc_ops = {
376 .ctrl = dwmac_mmc_ctrl,
377 .intr_all_mask = dwmac_mmc_intr_all_mask,
378 .read = dwmac_mmc_read,
379};
380
381static void dwxgmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)
382{
383 u32 value = readl(mmcaddr + MMC_CNTRL);
384
385 value |= (mode & 0x3F);
386
387 writel(value, mmcaddr + MMC_CNTRL);
388}
389
390static void dwxgmac_mmc_intr_all_mask(void __iomem *mmcaddr)
391{
392 writel(0x0, mmcaddr + MMC_RX_INTR_MASK);
393 writel(0x0, mmcaddr + MMC_TX_INTR_MASK);
394 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_TX_FPE_INTR_MASK);
395 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_RX_FPE_INTR_MASK);
396 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_RX_IPC_INTR_MASK);
397}
398
399static void dwxgmac_read_mmc_reg(void __iomem *addr, u32 reg, u32 *dest)
400{
401 u64 tmp = 0;
402
403 tmp += readl(addr + reg);
404 tmp += ((u64 )readl(addr + reg + 0x4)) << 32;
405 if (tmp > GENMASK(31, 0))
406 *dest = ~0x0;
407 else
408 *dest = *dest + tmp;
409}
410
411/* This reads the MAC core counters (if actaully supported).
412 * by default the MMC core is programmed to reset each
413 * counter after a read. So all the field of the mmc struct
414 * have to be incremented.
415 */
416static void dwxgmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)
417{
418 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_OCTET_GB,
419 &mmc->mmc_tx_octetcount_gb);
420 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PKT_GB,
421 &mmc->mmc_tx_framecount_gb);
422 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_BROAD_PKT_G,
423 &mmc->mmc_tx_broadcastframe_g);
424 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_MULTI_PKT_G,
425 &mmc->mmc_tx_multicastframe_g);
426 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_64OCT_GB,
427 &mmc->mmc_tx_64_octets_gb);
428 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_65OCT_GB,
429 &mmc->mmc_tx_65_to_127_octets_gb);
430 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_128OCT_GB,
431 &mmc->mmc_tx_128_to_255_octets_gb);
432 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_256OCT_GB,
433 &mmc->mmc_tx_256_to_511_octets_gb);
434 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_512OCT_GB,
435 &mmc->mmc_tx_512_to_1023_octets_gb);
436 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_1024OCT_GB,
437 &mmc->mmc_tx_1024_to_max_octets_gb);
438 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_UNI_PKT_GB,
439 &mmc->mmc_tx_unicast_gb);
440 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_MULTI_PKT_GB,
441 &mmc->mmc_tx_multicast_gb);
442 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_BROAD_PKT_GB,
443 &mmc->mmc_tx_broadcast_gb);
444 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_UNDER,
445 &mmc->mmc_tx_underflow_error);
446 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_OCTET_G,
447 &mmc->mmc_tx_octetcount_g);
448 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PKT_G,
449 &mmc->mmc_tx_framecount_g);
450 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PAUSE,
451 &mmc->mmc_tx_pause_frame);
452 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_VLAN_PKT_G,
453 &mmc->mmc_tx_vlan_frame_g);
454 mmc->mmc_tx_lpi_usec += readl(mmcaddr + MMC_XGMAC_TX_LPI_USEC);
455 mmc->mmc_tx_lpi_tran += readl(mmcaddr + MMC_XGMAC_TX_LPI_TRAN);
456
457 /* MMC RX counter registers */
458 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_PKT_GB,
459 &mmc->mmc_rx_framecount_gb);
460 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_OCTET_GB,
461 &mmc->mmc_rx_octetcount_gb);
462 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_OCTET_G,
463 &mmc->mmc_rx_octetcount_g);
464 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_BROAD_PKT_G,
465 &mmc->mmc_rx_broadcastframe_g);
466 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_MULTI_PKT_G,
467 &mmc->mmc_rx_multicastframe_g);
468 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_CRC_ERR,
469 &mmc->mmc_rx_crc_error);
470 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_CRC_ERR,
471 &mmc->mmc_rx_crc_error);
472 mmc->mmc_rx_run_error += readl(mmcaddr + MMC_XGMAC_RX_RUNT_ERR);
473 mmc->mmc_rx_jabber_error += readl(mmcaddr + MMC_XGMAC_RX_JABBER_ERR);
474 mmc->mmc_rx_undersize_g += readl(mmcaddr + MMC_XGMAC_RX_UNDER);
475 mmc->mmc_rx_oversize_g += readl(mmcaddr + MMC_XGMAC_RX_OVER);
476 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_64OCT_GB,
477 &mmc->mmc_rx_64_octets_gb);
478 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_65OCT_GB,
479 &mmc->mmc_rx_65_to_127_octets_gb);
480 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_128OCT_GB,
481 &mmc->mmc_rx_128_to_255_octets_gb);
482 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_256OCT_GB,
483 &mmc->mmc_rx_256_to_511_octets_gb);
484 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_512OCT_GB,
485 &mmc->mmc_rx_512_to_1023_octets_gb);
486 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_1024OCT_GB,
487 &mmc->mmc_rx_1024_to_max_octets_gb);
488 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UNI_PKT_G,
489 &mmc->mmc_rx_unicast_g);
490 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_LENGTH_ERR,
491 &mmc->mmc_rx_length_error);
492 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_RANGE,
493 &mmc->mmc_rx_autofrangetype);
494 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_PAUSE,
495 &mmc->mmc_rx_pause_frames);
496 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_FIFOOVER_PKT,
497 &mmc->mmc_rx_fifo_overflow);
498 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_VLAN_PKT_GB,
499 &mmc->mmc_rx_vlan_frames_gb);
500 mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_XGMAC_RX_WATCHDOG_ERR);
501 mmc->mmc_rx_lpi_usec += readl(mmcaddr + MMC_XGMAC_RX_LPI_USEC);
502 mmc->mmc_rx_lpi_tran += readl(mmcaddr + MMC_XGMAC_RX_LPI_TRAN);
503 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_DISCARD_PKT_GB,
504 &mmc->mmc_rx_discard_frames_gb);
505 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_DISCARD_OCT_GB,
506 &mmc->mmc_rx_discard_octets_gb);
507 mmc->mmc_rx_align_err_frames +=
508 readl(mmcaddr + MMC_XGMAC_RX_ALIGN_ERR_PKT);
509
510 mmc->mmc_sgf_pass_fragment_cntr +=
511 readl(mmcaddr + MMC_XGMAC_SGF_PASS_PKT);
512 mmc->mmc_sgf_fail_fragment_cntr +=
513 readl(mmcaddr + MMC_XGMAC_SGF_FAIL_PKT);
514 mmc->mmc_tx_fpe_fragment_cntr += readl(mmcaddr + MMC_XGMAC_TX_FPE_FRAG);
515 mmc->mmc_tx_hold_req_cntr += readl(mmcaddr + MMC_XGMAC_TX_HOLD_REQ);
516 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_GATE_OVERRUN,
517 &mmc->mmc_tx_gate_overrun_cntr);
518 mmc->mmc_rx_packet_assembly_err_cntr +=
519 readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_ERR);
520 mmc->mmc_rx_packet_smd_err_cntr +=
521 readl(mmcaddr + MMC_XGMAC_RX_PKT_SMD_ERR);
522 mmc->mmc_rx_packet_assembly_ok_cntr +=
523 readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_OK);
524 mmc->mmc_rx_fpe_fragment_cntr +=
525 readl(mmcaddr + MMC_XGMAC_RX_FPE_FRAG);
526
527 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_GD,
528 &mmc->mmc_rx_ipv4_gd);
529 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_HDERR,
530 &mmc->mmc_rx_ipv4_hderr);
531 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_NOPAY,
532 &mmc->mmc_rx_ipv4_nopay);
533 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_FRAG,
534 &mmc->mmc_rx_ipv4_frag);
535 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_UDSBL,
536 &mmc->mmc_rx_ipv4_udsbl);
537
538 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_GD,
539 &mmc->mmc_rx_ipv6_gd);
540 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_HDERR,
541 &mmc->mmc_rx_ipv6_hderr);
542 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_NOPAY,
543 &mmc->mmc_rx_ipv6_nopay);
544
545 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UDP_GD,
546 &mmc->mmc_rx_udp_gd);
547 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UDP_ERR,
548 &mmc->mmc_rx_udp_err);
549 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_TCP_GD,
550 &mmc->mmc_rx_tcp_gd);
551 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_TCP_ERR,
552 &mmc->mmc_rx_tcp_err);
553 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_ICMP_GD,
554 &mmc->mmc_rx_icmp_gd);
555 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_ICMP_ERR,
556 &mmc->mmc_rx_icmp_err);
557
558 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_GD_OCTETS,
559 &mmc->mmc_rx_ipv4_gd_octets);
560 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_HDERR_OCTETS,
561 &mmc->mmc_rx_ipv4_hderr_octets);
562 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_NOPAY_OCTETS,
563 &mmc->mmc_rx_ipv4_nopay_octets);
564 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_FRAG_OCTETS,
565 &mmc->mmc_rx_ipv4_frag_octets);
566 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_UDSBL_OCTETS,
567 &mmc->mmc_rx_ipv4_udsbl_octets);
568
569 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_GD_OCTETS,
570 &mmc->mmc_rx_ipv6_gd_octets);
571 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_HDERR_OCTETS,
572 &mmc->mmc_rx_ipv6_hderr_octets);
573 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_NOPAY_OCTETS,
574 &mmc->mmc_rx_ipv6_nopay_octets);
575
576 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UDP_GD_OCTETS,
577 &mmc->mmc_rx_udp_gd_octets);
578 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UDP_ERR_OCTETS,
579 &mmc->mmc_rx_udp_err_octets);
580 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_TCP_GD_OCTETS,
581 &mmc->mmc_rx_tcp_gd_octets);
582 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_TCP_ERR_OCTETS,
583 &mmc->mmc_rx_tcp_err_octets);
584 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_ICMP_GD_OCTETS,
585 &mmc->mmc_rx_icmp_gd_octets);
586 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_ICMP_ERR_OCTETS,
587 &mmc->mmc_rx_icmp_err_octets);
588}
589
590const struct stmmac_mmc_ops dwxgmac_mmc_ops = {
591 .ctrl = dwxgmac_mmc_ctrl,
592 .intr_all_mask = dwxgmac_mmc_intr_all_mask,
593 .read = dwxgmac_mmc_read,
594};
1// SPDX-License-Identifier: GPL-2.0-only
2/*******************************************************************************
3 DWMAC Management Counters
4
5 Copyright (C) 2011 STMicroelectronics Ltd
6
7
8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9*******************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/io.h>
13#include "hwif.h"
14#include "mmc.h"
15
16/* MAC Management Counters register offset */
17
18#define MMC_CNTRL 0x00 /* MMC Control */
19#define MMC_RX_INTR 0x04 /* MMC RX Interrupt */
20#define MMC_TX_INTR 0x08 /* MMC TX Interrupt */
21#define MMC_RX_INTR_MASK 0x0c /* MMC Interrupt Mask */
22#define MMC_TX_INTR_MASK 0x10 /* MMC Interrupt Mask */
23#define MMC_DEFAULT_MASK 0xffffffff
24
25/* MMC TX counter registers */
26
27/* Note:
28 * _GB register stands for good and bad frames
29 * _G is for good only.
30 */
31#define MMC_TX_OCTETCOUNT_GB 0x14
32#define MMC_TX_FRAMECOUNT_GB 0x18
33#define MMC_TX_BROADCASTFRAME_G 0x1c
34#define MMC_TX_MULTICASTFRAME_G 0x20
35#define MMC_TX_64_OCTETS_GB 0x24
36#define MMC_TX_65_TO_127_OCTETS_GB 0x28
37#define MMC_TX_128_TO_255_OCTETS_GB 0x2c
38#define MMC_TX_256_TO_511_OCTETS_GB 0x30
39#define MMC_TX_512_TO_1023_OCTETS_GB 0x34
40#define MMC_TX_1024_TO_MAX_OCTETS_GB 0x38
41#define MMC_TX_UNICAST_GB 0x3c
42#define MMC_TX_MULTICAST_GB 0x40
43#define MMC_TX_BROADCAST_GB 0x44
44#define MMC_TX_UNDERFLOW_ERROR 0x48
45#define MMC_TX_SINGLECOL_G 0x4c
46#define MMC_TX_MULTICOL_G 0x50
47#define MMC_TX_DEFERRED 0x54
48#define MMC_TX_LATECOL 0x58
49#define MMC_TX_EXESSCOL 0x5c
50#define MMC_TX_CARRIER_ERROR 0x60
51#define MMC_TX_OCTETCOUNT_G 0x64
52#define MMC_TX_FRAMECOUNT_G 0x68
53#define MMC_TX_EXCESSDEF 0x6c
54#define MMC_TX_PAUSE_FRAME 0x70
55#define MMC_TX_VLAN_FRAME_G 0x74
56
57/* MMC RX counter registers */
58#define MMC_RX_FRAMECOUNT_GB 0x80
59#define MMC_RX_OCTETCOUNT_GB 0x84
60#define MMC_RX_OCTETCOUNT_G 0x88
61#define MMC_RX_BROADCASTFRAME_G 0x8c
62#define MMC_RX_MULTICASTFRAME_G 0x90
63#define MMC_RX_CRC_ERROR 0x94
64#define MMC_RX_ALIGN_ERROR 0x98
65#define MMC_RX_RUN_ERROR 0x9C
66#define MMC_RX_JABBER_ERROR 0xA0
67#define MMC_RX_UNDERSIZE_G 0xA4
68#define MMC_RX_OVERSIZE_G 0xA8
69#define MMC_RX_64_OCTETS_GB 0xAC
70#define MMC_RX_65_TO_127_OCTETS_GB 0xb0
71#define MMC_RX_128_TO_255_OCTETS_GB 0xb4
72#define MMC_RX_256_TO_511_OCTETS_GB 0xb8
73#define MMC_RX_512_TO_1023_OCTETS_GB 0xbc
74#define MMC_RX_1024_TO_MAX_OCTETS_GB 0xc0
75#define MMC_RX_UNICAST_G 0xc4
76#define MMC_RX_LENGTH_ERROR 0xc8
77#define MMC_RX_AUTOFRANGETYPE 0xcc
78#define MMC_RX_PAUSE_FRAMES 0xd0
79#define MMC_RX_FIFO_OVERFLOW 0xd4
80#define MMC_RX_VLAN_FRAMES_GB 0xd8
81#define MMC_RX_WATCHDOG_ERROR 0xdc
82/* IPC*/
83#define MMC_RX_IPC_INTR_MASK 0x100
84#define MMC_RX_IPC_INTR 0x108
85/* IPv4*/
86#define MMC_RX_IPV4_GD 0x110
87#define MMC_RX_IPV4_HDERR 0x114
88#define MMC_RX_IPV4_NOPAY 0x118
89#define MMC_RX_IPV4_FRAG 0x11C
90#define MMC_RX_IPV4_UDSBL 0x120
91
92#define MMC_RX_IPV4_GD_OCTETS 0x150
93#define MMC_RX_IPV4_HDERR_OCTETS 0x154
94#define MMC_RX_IPV4_NOPAY_OCTETS 0x158
95#define MMC_RX_IPV4_FRAG_OCTETS 0x15c
96#define MMC_RX_IPV4_UDSBL_OCTETS 0x160
97
98/* IPV6*/
99#define MMC_RX_IPV6_GD_OCTETS 0x164
100#define MMC_RX_IPV6_HDERR_OCTETS 0x168
101#define MMC_RX_IPV6_NOPAY_OCTETS 0x16c
102
103#define MMC_RX_IPV6_GD 0x124
104#define MMC_RX_IPV6_HDERR 0x128
105#define MMC_RX_IPV6_NOPAY 0x12c
106
107/* Protocols*/
108#define MMC_RX_UDP_GD 0x130
109#define MMC_RX_UDP_ERR 0x134
110#define MMC_RX_TCP_GD 0x138
111#define MMC_RX_TCP_ERR 0x13c
112#define MMC_RX_ICMP_GD 0x140
113#define MMC_RX_ICMP_ERR 0x144
114
115#define MMC_RX_UDP_GD_OCTETS 0x170
116#define MMC_RX_UDP_ERR_OCTETS 0x174
117#define MMC_RX_TCP_GD_OCTETS 0x178
118#define MMC_RX_TCP_ERR_OCTETS 0x17c
119#define MMC_RX_ICMP_GD_OCTETS 0x180
120#define MMC_RX_ICMP_ERR_OCTETS 0x184
121
122#define MMC_TX_FPE_FRAG 0x1a8
123#define MMC_TX_HOLD_REQ 0x1ac
124#define MMC_RX_PKT_ASSEMBLY_ERR 0x1c8
125#define MMC_RX_PKT_SMD_ERR 0x1cc
126#define MMC_RX_PKT_ASSEMBLY_OK 0x1d0
127#define MMC_RX_FPE_FRAG 0x1d4
128
129/* XGMAC MMC Registers */
130#define MMC_XGMAC_TX_OCTET_GB 0x14
131#define MMC_XGMAC_TX_PKT_GB 0x1c
132#define MMC_XGMAC_TX_BROAD_PKT_G 0x24
133#define MMC_XGMAC_TX_MULTI_PKT_G 0x2c
134#define MMC_XGMAC_TX_64OCT_GB 0x34
135#define MMC_XGMAC_TX_65OCT_GB 0x3c
136#define MMC_XGMAC_TX_128OCT_GB 0x44
137#define MMC_XGMAC_TX_256OCT_GB 0x4c
138#define MMC_XGMAC_TX_512OCT_GB 0x54
139#define MMC_XGMAC_TX_1024OCT_GB 0x5c
140#define MMC_XGMAC_TX_UNI_PKT_GB 0x64
141#define MMC_XGMAC_TX_MULTI_PKT_GB 0x6c
142#define MMC_XGMAC_TX_BROAD_PKT_GB 0x74
143#define MMC_XGMAC_TX_UNDER 0x7c
144#define MMC_XGMAC_TX_OCTET_G 0x84
145#define MMC_XGMAC_TX_PKT_G 0x8c
146#define MMC_XGMAC_TX_PAUSE 0x94
147#define MMC_XGMAC_TX_VLAN_PKT_G 0x9c
148#define MMC_XGMAC_TX_LPI_USEC 0xa4
149#define MMC_XGMAC_TX_LPI_TRAN 0xa8
150
151#define MMC_XGMAC_RX_PKT_GB 0x100
152#define MMC_XGMAC_RX_OCTET_GB 0x108
153#define MMC_XGMAC_RX_OCTET_G 0x110
154#define MMC_XGMAC_RX_BROAD_PKT_G 0x118
155#define MMC_XGMAC_RX_MULTI_PKT_G 0x120
156#define MMC_XGMAC_RX_CRC_ERR 0x128
157#define MMC_XGMAC_RX_RUNT_ERR 0x130
158#define MMC_XGMAC_RX_JABBER_ERR 0x134
159#define MMC_XGMAC_RX_UNDER 0x138
160#define MMC_XGMAC_RX_OVER 0x13c
161#define MMC_XGMAC_RX_64OCT_GB 0x140
162#define MMC_XGMAC_RX_65OCT_GB 0x148
163#define MMC_XGMAC_RX_128OCT_GB 0x150
164#define MMC_XGMAC_RX_256OCT_GB 0x158
165#define MMC_XGMAC_RX_512OCT_GB 0x160
166#define MMC_XGMAC_RX_1024OCT_GB 0x168
167#define MMC_XGMAC_RX_UNI_PKT_G 0x170
168#define MMC_XGMAC_RX_LENGTH_ERR 0x178
169#define MMC_XGMAC_RX_RANGE 0x180
170#define MMC_XGMAC_RX_PAUSE 0x188
171#define MMC_XGMAC_RX_FIFOOVER_PKT 0x190
172#define MMC_XGMAC_RX_VLAN_PKT_GB 0x198
173#define MMC_XGMAC_RX_WATCHDOG_ERR 0x1a0
174#define MMC_XGMAC_RX_LPI_USEC 0x1a4
175#define MMC_XGMAC_RX_LPI_TRAN 0x1a8
176#define MMC_XGMAC_RX_DISCARD_PKT_GB 0x1ac
177#define MMC_XGMAC_RX_DISCARD_OCT_GB 0x1b4
178#define MMC_XGMAC_RX_ALIGN_ERR_PKT 0x1bc
179
180#define MMC_XGMAC_TX_FPE_FRAG 0x208
181#define MMC_XGMAC_TX_HOLD_REQ 0x20c
182#define MMC_XGMAC_RX_PKT_ASSEMBLY_ERR 0x228
183#define MMC_XGMAC_RX_PKT_SMD_ERR 0x22c
184#define MMC_XGMAC_RX_PKT_ASSEMBLY_OK 0x230
185#define MMC_XGMAC_RX_FPE_FRAG 0x234
186#define MMC_XGMAC_RX_IPC_INTR_MASK 0x25c
187
188static void dwmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)
189{
190 u32 value = readl(mmcaddr + MMC_CNTRL);
191
192 value |= (mode & 0x3F);
193
194 writel(value, mmcaddr + MMC_CNTRL);
195
196 pr_debug("stmmac: MMC ctrl register (offset 0x%x): 0x%08x\n",
197 MMC_CNTRL, value);
198}
199
200/* To mask all interrupts.*/
201static void dwmac_mmc_intr_all_mask(void __iomem *mmcaddr)
202{
203 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_INTR_MASK);
204 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_TX_INTR_MASK);
205 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_IPC_INTR_MASK);
206}
207
208/* This reads the MAC core counters (if actaully supported).
209 * by default the MMC core is programmed to reset each
210 * counter after a read. So all the field of the mmc struct
211 * have to be incremented.
212 */
213static void dwmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)
214{
215 mmc->mmc_tx_octetcount_gb += readl(mmcaddr + MMC_TX_OCTETCOUNT_GB);
216 mmc->mmc_tx_framecount_gb += readl(mmcaddr + MMC_TX_FRAMECOUNT_GB);
217 mmc->mmc_tx_broadcastframe_g += readl(mmcaddr +
218 MMC_TX_BROADCASTFRAME_G);
219 mmc->mmc_tx_multicastframe_g += readl(mmcaddr +
220 MMC_TX_MULTICASTFRAME_G);
221 mmc->mmc_tx_64_octets_gb += readl(mmcaddr + MMC_TX_64_OCTETS_GB);
222 mmc->mmc_tx_65_to_127_octets_gb +=
223 readl(mmcaddr + MMC_TX_65_TO_127_OCTETS_GB);
224 mmc->mmc_tx_128_to_255_octets_gb +=
225 readl(mmcaddr + MMC_TX_128_TO_255_OCTETS_GB);
226 mmc->mmc_tx_256_to_511_octets_gb +=
227 readl(mmcaddr + MMC_TX_256_TO_511_OCTETS_GB);
228 mmc->mmc_tx_512_to_1023_octets_gb +=
229 readl(mmcaddr + MMC_TX_512_TO_1023_OCTETS_GB);
230 mmc->mmc_tx_1024_to_max_octets_gb +=
231 readl(mmcaddr + MMC_TX_1024_TO_MAX_OCTETS_GB);
232 mmc->mmc_tx_unicast_gb += readl(mmcaddr + MMC_TX_UNICAST_GB);
233 mmc->mmc_tx_multicast_gb += readl(mmcaddr + MMC_TX_MULTICAST_GB);
234 mmc->mmc_tx_broadcast_gb += readl(mmcaddr + MMC_TX_BROADCAST_GB);
235 mmc->mmc_tx_underflow_error += readl(mmcaddr + MMC_TX_UNDERFLOW_ERROR);
236 mmc->mmc_tx_singlecol_g += readl(mmcaddr + MMC_TX_SINGLECOL_G);
237 mmc->mmc_tx_multicol_g += readl(mmcaddr + MMC_TX_MULTICOL_G);
238 mmc->mmc_tx_deferred += readl(mmcaddr + MMC_TX_DEFERRED);
239 mmc->mmc_tx_latecol += readl(mmcaddr + MMC_TX_LATECOL);
240 mmc->mmc_tx_exesscol += readl(mmcaddr + MMC_TX_EXESSCOL);
241 mmc->mmc_tx_carrier_error += readl(mmcaddr + MMC_TX_CARRIER_ERROR);
242 mmc->mmc_tx_octetcount_g += readl(mmcaddr + MMC_TX_OCTETCOUNT_G);
243 mmc->mmc_tx_framecount_g += readl(mmcaddr + MMC_TX_FRAMECOUNT_G);
244 mmc->mmc_tx_excessdef += readl(mmcaddr + MMC_TX_EXCESSDEF);
245 mmc->mmc_tx_pause_frame += readl(mmcaddr + MMC_TX_PAUSE_FRAME);
246 mmc->mmc_tx_vlan_frame_g += readl(mmcaddr + MMC_TX_VLAN_FRAME_G);
247
248 /* MMC RX counter registers */
249 mmc->mmc_rx_framecount_gb += readl(mmcaddr + MMC_RX_FRAMECOUNT_GB);
250 mmc->mmc_rx_octetcount_gb += readl(mmcaddr + MMC_RX_OCTETCOUNT_GB);
251 mmc->mmc_rx_octetcount_g += readl(mmcaddr + MMC_RX_OCTETCOUNT_G);
252 mmc->mmc_rx_broadcastframe_g += readl(mmcaddr +
253 MMC_RX_BROADCASTFRAME_G);
254 mmc->mmc_rx_multicastframe_g += readl(mmcaddr +
255 MMC_RX_MULTICASTFRAME_G);
256 mmc->mmc_rx_crc_error += readl(mmcaddr + MMC_RX_CRC_ERROR);
257 mmc->mmc_rx_align_error += readl(mmcaddr + MMC_RX_ALIGN_ERROR);
258 mmc->mmc_rx_run_error += readl(mmcaddr + MMC_RX_RUN_ERROR);
259 mmc->mmc_rx_jabber_error += readl(mmcaddr + MMC_RX_JABBER_ERROR);
260 mmc->mmc_rx_undersize_g += readl(mmcaddr + MMC_RX_UNDERSIZE_G);
261 mmc->mmc_rx_oversize_g += readl(mmcaddr + MMC_RX_OVERSIZE_G);
262 mmc->mmc_rx_64_octets_gb += readl(mmcaddr + MMC_RX_64_OCTETS_GB);
263 mmc->mmc_rx_65_to_127_octets_gb +=
264 readl(mmcaddr + MMC_RX_65_TO_127_OCTETS_GB);
265 mmc->mmc_rx_128_to_255_octets_gb +=
266 readl(mmcaddr + MMC_RX_128_TO_255_OCTETS_GB);
267 mmc->mmc_rx_256_to_511_octets_gb +=
268 readl(mmcaddr + MMC_RX_256_TO_511_OCTETS_GB);
269 mmc->mmc_rx_512_to_1023_octets_gb +=
270 readl(mmcaddr + MMC_RX_512_TO_1023_OCTETS_GB);
271 mmc->mmc_rx_1024_to_max_octets_gb +=
272 readl(mmcaddr + MMC_RX_1024_TO_MAX_OCTETS_GB);
273 mmc->mmc_rx_unicast_g += readl(mmcaddr + MMC_RX_UNICAST_G);
274 mmc->mmc_rx_length_error += readl(mmcaddr + MMC_RX_LENGTH_ERROR);
275 mmc->mmc_rx_autofrangetype += readl(mmcaddr + MMC_RX_AUTOFRANGETYPE);
276 mmc->mmc_rx_pause_frames += readl(mmcaddr + MMC_RX_PAUSE_FRAMES);
277 mmc->mmc_rx_fifo_overflow += readl(mmcaddr + MMC_RX_FIFO_OVERFLOW);
278 mmc->mmc_rx_vlan_frames_gb += readl(mmcaddr + MMC_RX_VLAN_FRAMES_GB);
279 mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_RX_WATCHDOG_ERROR);
280 /* IPC */
281 mmc->mmc_rx_ipc_intr_mask += readl(mmcaddr + MMC_RX_IPC_INTR_MASK);
282 mmc->mmc_rx_ipc_intr += readl(mmcaddr + MMC_RX_IPC_INTR);
283 /* IPv4 */
284 mmc->mmc_rx_ipv4_gd += readl(mmcaddr + MMC_RX_IPV4_GD);
285 mmc->mmc_rx_ipv4_hderr += readl(mmcaddr + MMC_RX_IPV4_HDERR);
286 mmc->mmc_rx_ipv4_nopay += readl(mmcaddr + MMC_RX_IPV4_NOPAY);
287 mmc->mmc_rx_ipv4_frag += readl(mmcaddr + MMC_RX_IPV4_FRAG);
288 mmc->mmc_rx_ipv4_udsbl += readl(mmcaddr + MMC_RX_IPV4_UDSBL);
289
290 mmc->mmc_rx_ipv4_gd_octets += readl(mmcaddr + MMC_RX_IPV4_GD_OCTETS);
291 mmc->mmc_rx_ipv4_hderr_octets +=
292 readl(mmcaddr + MMC_RX_IPV4_HDERR_OCTETS);
293 mmc->mmc_rx_ipv4_nopay_octets +=
294 readl(mmcaddr + MMC_RX_IPV4_NOPAY_OCTETS);
295 mmc->mmc_rx_ipv4_frag_octets += readl(mmcaddr +
296 MMC_RX_IPV4_FRAG_OCTETS);
297 mmc->mmc_rx_ipv4_udsbl_octets +=
298 readl(mmcaddr + MMC_RX_IPV4_UDSBL_OCTETS);
299
300 /* IPV6 */
301 mmc->mmc_rx_ipv6_gd_octets += readl(mmcaddr + MMC_RX_IPV6_GD_OCTETS);
302 mmc->mmc_rx_ipv6_hderr_octets +=
303 readl(mmcaddr + MMC_RX_IPV6_HDERR_OCTETS);
304 mmc->mmc_rx_ipv6_nopay_octets +=
305 readl(mmcaddr + MMC_RX_IPV6_NOPAY_OCTETS);
306
307 mmc->mmc_rx_ipv6_gd += readl(mmcaddr + MMC_RX_IPV6_GD);
308 mmc->mmc_rx_ipv6_hderr += readl(mmcaddr + MMC_RX_IPV6_HDERR);
309 mmc->mmc_rx_ipv6_nopay += readl(mmcaddr + MMC_RX_IPV6_NOPAY);
310
311 /* Protocols */
312 mmc->mmc_rx_udp_gd += readl(mmcaddr + MMC_RX_UDP_GD);
313 mmc->mmc_rx_udp_err += readl(mmcaddr + MMC_RX_UDP_ERR);
314 mmc->mmc_rx_tcp_gd += readl(mmcaddr + MMC_RX_TCP_GD);
315 mmc->mmc_rx_tcp_err += readl(mmcaddr + MMC_RX_TCP_ERR);
316 mmc->mmc_rx_icmp_gd += readl(mmcaddr + MMC_RX_ICMP_GD);
317 mmc->mmc_rx_icmp_err += readl(mmcaddr + MMC_RX_ICMP_ERR);
318
319 mmc->mmc_rx_udp_gd_octets += readl(mmcaddr + MMC_RX_UDP_GD_OCTETS);
320 mmc->mmc_rx_udp_err_octets += readl(mmcaddr + MMC_RX_UDP_ERR_OCTETS);
321 mmc->mmc_rx_tcp_gd_octets += readl(mmcaddr + MMC_RX_TCP_GD_OCTETS);
322 mmc->mmc_rx_tcp_err_octets += readl(mmcaddr + MMC_RX_TCP_ERR_OCTETS);
323 mmc->mmc_rx_icmp_gd_octets += readl(mmcaddr + MMC_RX_ICMP_GD_OCTETS);
324 mmc->mmc_rx_icmp_err_octets += readl(mmcaddr + MMC_RX_ICMP_ERR_OCTETS);
325
326 mmc->mmc_tx_fpe_fragment_cntr += readl(mmcaddr + MMC_TX_FPE_FRAG);
327 mmc->mmc_tx_hold_req_cntr += readl(mmcaddr + MMC_TX_HOLD_REQ);
328 mmc->mmc_rx_packet_assembly_err_cntr +=
329 readl(mmcaddr + MMC_RX_PKT_ASSEMBLY_ERR);
330 mmc->mmc_rx_packet_smd_err_cntr += readl(mmcaddr + MMC_RX_PKT_SMD_ERR);
331 mmc->mmc_rx_packet_assembly_ok_cntr +=
332 readl(mmcaddr + MMC_RX_PKT_ASSEMBLY_OK);
333 mmc->mmc_rx_fpe_fragment_cntr += readl(mmcaddr + MMC_RX_FPE_FRAG);
334}
335
336const struct stmmac_mmc_ops dwmac_mmc_ops = {
337 .ctrl = dwmac_mmc_ctrl,
338 .intr_all_mask = dwmac_mmc_intr_all_mask,
339 .read = dwmac_mmc_read,
340};
341
342static void dwxgmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)
343{
344 u32 value = readl(mmcaddr + MMC_CNTRL);
345
346 value |= (mode & 0x3F);
347
348 writel(value, mmcaddr + MMC_CNTRL);
349}
350
351static void dwxgmac_mmc_intr_all_mask(void __iomem *mmcaddr)
352{
353 writel(0x0, mmcaddr + MMC_RX_INTR_MASK);
354 writel(0x0, mmcaddr + MMC_TX_INTR_MASK);
355 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_RX_IPC_INTR_MASK);
356}
357
358static void dwxgmac_read_mmc_reg(void __iomem *addr, u32 reg, u32 *dest)
359{
360 u64 tmp = 0;
361
362 tmp += readl(addr + reg);
363 tmp += ((u64 )readl(addr + reg + 0x4)) << 32;
364 if (tmp > GENMASK(31, 0))
365 *dest = ~0x0;
366 else
367 *dest = *dest + tmp;
368}
369
370/* This reads the MAC core counters (if actaully supported).
371 * by default the MMC core is programmed to reset each
372 * counter after a read. So all the field of the mmc struct
373 * have to be incremented.
374 */
375static void dwxgmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)
376{
377 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_OCTET_GB,
378 &mmc->mmc_tx_octetcount_gb);
379 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PKT_GB,
380 &mmc->mmc_tx_framecount_gb);
381 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_BROAD_PKT_G,
382 &mmc->mmc_tx_broadcastframe_g);
383 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_MULTI_PKT_G,
384 &mmc->mmc_tx_multicastframe_g);
385 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_64OCT_GB,
386 &mmc->mmc_tx_64_octets_gb);
387 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_65OCT_GB,
388 &mmc->mmc_tx_65_to_127_octets_gb);
389 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_128OCT_GB,
390 &mmc->mmc_tx_128_to_255_octets_gb);
391 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_256OCT_GB,
392 &mmc->mmc_tx_256_to_511_octets_gb);
393 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_512OCT_GB,
394 &mmc->mmc_tx_512_to_1023_octets_gb);
395 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_1024OCT_GB,
396 &mmc->mmc_tx_1024_to_max_octets_gb);
397 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_UNI_PKT_GB,
398 &mmc->mmc_tx_unicast_gb);
399 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_MULTI_PKT_GB,
400 &mmc->mmc_tx_multicast_gb);
401 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_BROAD_PKT_GB,
402 &mmc->mmc_tx_broadcast_gb);
403 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_UNDER,
404 &mmc->mmc_tx_underflow_error);
405 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_OCTET_G,
406 &mmc->mmc_tx_octetcount_g);
407 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PKT_G,
408 &mmc->mmc_tx_framecount_g);
409 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PAUSE,
410 &mmc->mmc_tx_pause_frame);
411 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_VLAN_PKT_G,
412 &mmc->mmc_tx_vlan_frame_g);
413
414 /* MMC RX counter registers */
415 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_PKT_GB,
416 &mmc->mmc_rx_framecount_gb);
417 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_OCTET_GB,
418 &mmc->mmc_rx_octetcount_gb);
419 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_OCTET_G,
420 &mmc->mmc_rx_octetcount_g);
421 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_BROAD_PKT_G,
422 &mmc->mmc_rx_broadcastframe_g);
423 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_MULTI_PKT_G,
424 &mmc->mmc_rx_multicastframe_g);
425 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_CRC_ERR,
426 &mmc->mmc_rx_crc_error);
427 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_CRC_ERR,
428 &mmc->mmc_rx_crc_error);
429 mmc->mmc_rx_run_error += readl(mmcaddr + MMC_XGMAC_RX_RUNT_ERR);
430 mmc->mmc_rx_jabber_error += readl(mmcaddr + MMC_XGMAC_RX_JABBER_ERR);
431 mmc->mmc_rx_undersize_g += readl(mmcaddr + MMC_XGMAC_RX_UNDER);
432 mmc->mmc_rx_oversize_g += readl(mmcaddr + MMC_XGMAC_RX_OVER);
433 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_64OCT_GB,
434 &mmc->mmc_rx_64_octets_gb);
435 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_65OCT_GB,
436 &mmc->mmc_rx_65_to_127_octets_gb);
437 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_128OCT_GB,
438 &mmc->mmc_rx_128_to_255_octets_gb);
439 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_256OCT_GB,
440 &mmc->mmc_rx_256_to_511_octets_gb);
441 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_512OCT_GB,
442 &mmc->mmc_rx_512_to_1023_octets_gb);
443 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_1024OCT_GB,
444 &mmc->mmc_rx_1024_to_max_octets_gb);
445 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UNI_PKT_G,
446 &mmc->mmc_rx_unicast_g);
447 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_LENGTH_ERR,
448 &mmc->mmc_rx_length_error);
449 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_RANGE,
450 &mmc->mmc_rx_autofrangetype);
451 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_PAUSE,
452 &mmc->mmc_rx_pause_frames);
453 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_FIFOOVER_PKT,
454 &mmc->mmc_rx_fifo_overflow);
455 dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_VLAN_PKT_GB,
456 &mmc->mmc_rx_vlan_frames_gb);
457 mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_XGMAC_RX_WATCHDOG_ERR);
458
459 mmc->mmc_tx_fpe_fragment_cntr += readl(mmcaddr + MMC_XGMAC_TX_FPE_FRAG);
460 mmc->mmc_tx_hold_req_cntr += readl(mmcaddr + MMC_XGMAC_TX_HOLD_REQ);
461 mmc->mmc_rx_packet_assembly_err_cntr +=
462 readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_ERR);
463 mmc->mmc_rx_packet_smd_err_cntr +=
464 readl(mmcaddr + MMC_XGMAC_RX_PKT_SMD_ERR);
465 mmc->mmc_rx_packet_assembly_ok_cntr +=
466 readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_OK);
467 mmc->mmc_rx_fpe_fragment_cntr +=
468 readl(mmcaddr + MMC_XGMAC_RX_FPE_FRAG);
469}
470
471const struct stmmac_mmc_ops dwxgmac_mmc_ops = {
472 .ctrl = dwxgmac_mmc_ctrl,
473 .intr_all_mask = dwxgmac_mmc_intr_all_mask,
474 .read = dwxgmac_mmc_read,
475};