1/* SPDX-License-Identifier: GPL-2.0 */
 2/* Renesas R-Car Gen4 gPTP device driver
 3 *
 4 * Copyright (C) 2022 Renesas Electronics Corporation
 5 */
 6
 7#ifndef __RCAR_GEN4_PTP_H__
 8#define __RCAR_GEN4_PTP_H__
 9
10#include <linux/ptp_clock_kernel.h>
11
 
 
12#define RCAR_GEN4_GPTP_OFFSET_S4	0x00018000
13
 
14enum rcar_gen4_ptp_reg_layout {
15	RCAR_GEN4_PTP_REG_LAYOUT
16};
17
18/* driver's definitions */
19#define RCAR_GEN4_RXTSTAMP_ENABLED		BIT(0)
20#define RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT	BIT(1)
21#define RCAR_GEN4_RXTSTAMP_TYPE_ALL		(RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT | BIT(2))
22#define RCAR_GEN4_RXTSTAMP_TYPE			RCAR_GEN4_RXTSTAMP_TYPE_ALL
23
24#define RCAR_GEN4_TXTSTAMP_ENABLED		BIT(0)
25
26#define PTPRO				0
27
28enum rcar_gen4_ptp_reg {
29	PTPTMEC		= PTPRO + 0x0010,
30	PTPTMDC		= PTPRO + 0x0014,
31	PTPTIVC0	= PTPRO + 0x0020,
32	PTPTOVC00	= PTPRO + 0x0030,
33	PTPTOVC10	= PTPRO + 0x0034,
34	PTPTOVC20	= PTPRO + 0x0038,
35	PTPGPTPTM00	= PTPRO + 0x0050,
36	PTPGPTPTM10	= PTPRO + 0x0054,
37	PTPGPTPTM20	= PTPRO + 0x0058,
38};
39
40struct rcar_gen4_ptp_reg_offset {
41	u16 enable;
42	u16 disable;
43	u16 increment;
44	u16 config_t0;
45	u16 config_t1;
46	u16 config_t2;
47	u16 monitor_t0;
48	u16 monitor_t1;
49	u16 monitor_t2;
50};
51
52struct rcar_gen4_ptp_private {
53	void __iomem *addr;
54	struct ptp_clock *clock;
55	struct ptp_clock_info info;
56	const struct rcar_gen4_ptp_reg_offset *offs;
57	spinlock_t lock;	/* For multiple registers access */
58	u32 tstamp_tx_ctrl;
59	u32 tstamp_rx_ctrl;
60	s64 default_addend;
61	bool initialized;
62};
63
64int rcar_gen4_ptp_register(struct rcar_gen4_ptp_private *ptp_priv,
65			   enum rcar_gen4_ptp_reg_layout layout, u32 rate);
66int rcar_gen4_ptp_unregister(struct rcar_gen4_ptp_private *ptp_priv);
67struct rcar_gen4_ptp_private *rcar_gen4_ptp_alloc(struct platform_device *pdev);
68
69#endif	/* #ifndef __RCAR_GEN4_PTP_H__ */

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/* Renesas R-Car Gen4 gPTP device driver
 3 *
 4 * Copyright (C) 2022 Renesas Electronics Corporation
 5 */
 6
 7#ifndef __RCAR_GEN4_PTP_H__
 8#define __RCAR_GEN4_PTP_H__
 9
10#include <linux/ptp_clock_kernel.h>
11
12#define PTPTIVC_INIT			0x19000000	/* 320MHz */
13#define RCAR_GEN4_PTP_CLOCK_S4		PTPTIVC_INIT
14#define RCAR_GEN4_GPTP_OFFSET_S4	0x00018000
15
16/* for rcar_gen4_ptp_init */
17enum rcar_gen4_ptp_reg_layout {
18	RCAR_GEN4_PTP_REG_LAYOUT_S4
19};
20
21/* driver's definitions */
22#define RCAR_GEN4_RXTSTAMP_ENABLED		BIT(0)
23#define RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT	BIT(1)
24#define RCAR_GEN4_RXTSTAMP_TYPE_ALL		(RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT | BIT(2))
25#define RCAR_GEN4_RXTSTAMP_TYPE			RCAR_GEN4_RXTSTAMP_TYPE_ALL
26
27#define RCAR_GEN4_TXTSTAMP_ENABLED		BIT(0)
28
29#define PTPRO				0
30
31enum rcar_gen4_ptp_reg_s4 {
32	PTPTMEC		= PTPRO + 0x0010,
33	PTPTMDC		= PTPRO + 0x0014,
34	PTPTIVC0	= PTPRO + 0x0020,
35	PTPTOVC00	= PTPRO + 0x0030,
36	PTPTOVC10	= PTPRO + 0x0034,
37	PTPTOVC20	= PTPRO + 0x0038,
38	PTPGPTPTM00	= PTPRO + 0x0050,
39	PTPGPTPTM10	= PTPRO + 0x0054,
40	PTPGPTPTM20	= PTPRO + 0x0058,
41};
42
43struct rcar_gen4_ptp_reg_offset {
44	u16 enable;
45	u16 disable;
46	u16 increment;
47	u16 config_t0;
48	u16 config_t1;
49	u16 config_t2;
50	u16 monitor_t0;
51	u16 monitor_t1;
52	u16 monitor_t2;
53};
54
55struct rcar_gen4_ptp_private {
56	void __iomem *addr;
57	struct ptp_clock *clock;
58	struct ptp_clock_info info;
59	const struct rcar_gen4_ptp_reg_offset *offs;
60	spinlock_t lock;	/* For multiple registers access */
61	u32 tstamp_tx_ctrl;
62	u32 tstamp_rx_ctrl;
63	s64 default_addend;
64	bool initialized;
65};
66
67int rcar_gen4_ptp_register(struct rcar_gen4_ptp_private *ptp_priv,
68			   enum rcar_gen4_ptp_reg_layout layout, u32 clock);
69int rcar_gen4_ptp_unregister(struct rcar_gen4_ptp_private *ptp_priv);
70struct rcar_gen4_ptp_private *rcar_gen4_ptp_alloc(struct platform_device *pdev);
71
72#endif	/* #ifndef __RCAR_GEN4_PTP_H__ */