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1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7#include <linux/dsa/ocelot.h>
8#include <linux/if_bridge.h>
9#include <linux/iopoll.h>
10#include <linux/phy/phy.h>
11#include <net/pkt_sched.h>
12#include <soc/mscc/ocelot_hsio.h>
13#include <soc/mscc/ocelot_vcap.h>
14#include "ocelot.h"
15#include "ocelot_vcap.h"
16
17#define TABLE_UPDATE_SLEEP_US 10
18#define TABLE_UPDATE_TIMEOUT_US 100000
19#define MEM_INIT_SLEEP_US 1000
20#define MEM_INIT_TIMEOUT_US 100000
21
22#define OCELOT_RSV_VLAN_RANGE_START 4000
23
24struct ocelot_mact_entry {
25 u8 mac[ETH_ALEN];
26 u16 vid;
27 enum macaccess_entry_type type;
28};
29
30/* Caller must hold &ocelot->mact_lock */
31static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
32{
33 return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
34}
35
36/* Caller must hold &ocelot->mact_lock */
37static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
38{
39 u32 val;
40
41 return readx_poll_timeout(ocelot_mact_read_macaccess,
42 ocelot, val,
43 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) ==
44 MACACCESS_CMD_IDLE,
45 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
46}
47
48/* Caller must hold &ocelot->mact_lock */
49static void ocelot_mact_select(struct ocelot *ocelot,
50 const unsigned char mac[ETH_ALEN],
51 unsigned int vid)
52{
53 u32 macl = 0, mach = 0;
54
55 /* Set the MAC address to handle and the vlan associated in a format
56 * understood by the hardware.
57 */
58 mach |= vid << 16;
59 mach |= mac[0] << 8;
60 mach |= mac[1] << 0;
61 macl |= mac[2] << 24;
62 macl |= mac[3] << 16;
63 macl |= mac[4] << 8;
64 macl |= mac[5] << 0;
65
66 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
67 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
68
69}
70
71static int __ocelot_mact_learn(struct ocelot *ocelot, int port,
72 const unsigned char mac[ETH_ALEN],
73 unsigned int vid, enum macaccess_entry_type type)
74{
75 u32 cmd = ANA_TABLES_MACACCESS_VALID |
76 ANA_TABLES_MACACCESS_DEST_IDX(port) |
77 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
78 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN);
79 unsigned int mc_ports;
80 int err;
81
82 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */
83 if (type == ENTRYTYPE_MACv4)
84 mc_ports = (mac[1] << 8) | mac[2];
85 else if (type == ENTRYTYPE_MACv6)
86 mc_ports = (mac[0] << 8) | mac[1];
87 else
88 mc_ports = 0;
89
90 if (mc_ports & BIT(ocelot->num_phys_ports))
91 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY;
92
93 ocelot_mact_select(ocelot, mac, vid);
94
95 /* Issue a write command */
96 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS);
97
98 err = ocelot_mact_wait_for_completion(ocelot);
99
100 return err;
101}
102
103int ocelot_mact_learn(struct ocelot *ocelot, int port,
104 const unsigned char mac[ETH_ALEN],
105 unsigned int vid, enum macaccess_entry_type type)
106{
107 int ret;
108
109 mutex_lock(&ocelot->mact_lock);
110 ret = __ocelot_mact_learn(ocelot, port, mac, vid, type);
111 mutex_unlock(&ocelot->mact_lock);
112
113 return ret;
114}
115EXPORT_SYMBOL(ocelot_mact_learn);
116
117int ocelot_mact_forget(struct ocelot *ocelot,
118 const unsigned char mac[ETH_ALEN], unsigned int vid)
119{
120 int err;
121
122 mutex_lock(&ocelot->mact_lock);
123
124 ocelot_mact_select(ocelot, mac, vid);
125
126 /* Issue a forget command */
127 ocelot_write(ocelot,
128 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
129 ANA_TABLES_MACACCESS);
130
131 err = ocelot_mact_wait_for_completion(ocelot);
132
133 mutex_unlock(&ocelot->mact_lock);
134
135 return err;
136}
137EXPORT_SYMBOL(ocelot_mact_forget);
138
139int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx,
140 const unsigned char mac[ETH_ALEN],
141 unsigned int vid, enum macaccess_entry_type *type)
142{
143 int val;
144
145 mutex_lock(&ocelot->mact_lock);
146
147 ocelot_mact_select(ocelot, mac, vid);
148
149 /* Issue a read command with MACACCESS_VALID=1. */
150 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID |
151 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
152 ANA_TABLES_MACACCESS);
153
154 if (ocelot_mact_wait_for_completion(ocelot)) {
155 mutex_unlock(&ocelot->mact_lock);
156 return -ETIMEDOUT;
157 }
158
159 /* Read back the entry flags */
160 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
161
162 mutex_unlock(&ocelot->mact_lock);
163
164 if (!(val & ANA_TABLES_MACACCESS_VALID))
165 return -ENOENT;
166
167 *dst_idx = ANA_TABLES_MACACCESS_DEST_IDX_X(val);
168 *type = ANA_TABLES_MACACCESS_ENTRYTYPE_X(val);
169
170 return 0;
171}
172EXPORT_SYMBOL(ocelot_mact_lookup);
173
174int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx,
175 const unsigned char mac[ETH_ALEN],
176 unsigned int vid,
177 enum macaccess_entry_type type,
178 int sfid, int ssid)
179{
180 int ret;
181
182 mutex_lock(&ocelot->mact_lock);
183
184 ocelot_write(ocelot,
185 (sfid < 0 ? 0 : ANA_TABLES_STREAMDATA_SFID_VALID) |
186 ANA_TABLES_STREAMDATA_SFID(sfid) |
187 (ssid < 0 ? 0 : ANA_TABLES_STREAMDATA_SSID_VALID) |
188 ANA_TABLES_STREAMDATA_SSID(ssid),
189 ANA_TABLES_STREAMDATA);
190
191 ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type);
192
193 mutex_unlock(&ocelot->mact_lock);
194
195 return ret;
196}
197EXPORT_SYMBOL(ocelot_mact_learn_streamdata);
198
199static void ocelot_mact_init(struct ocelot *ocelot)
200{
201 /* Configure the learning mode entries attributes:
202 * - Do not copy the frame to the CPU extraction queues.
203 * - Use the vlan and mac_cpoy for dmac lookup.
204 */
205 ocelot_rmw(ocelot, 0,
206 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
207 | ANA_AGENCTRL_LEARN_FWD_KILL
208 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
209 ANA_AGENCTRL);
210
211 /* Clear the MAC table. We are not concurrent with anyone, so
212 * holding &ocelot->mact_lock is pointless.
213 */
214 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
215}
216
217void ocelot_pll5_init(struct ocelot *ocelot)
218{
219 /* Configure PLL5. This will need a proper CCF driver
220 * The values are coming from the VTSS API for Ocelot
221 */
222 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4,
223 HSIO_PLL5G_CFG4_IB_CTRL(0x7600) |
224 HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8));
225 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0,
226 HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) |
227 HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) |
228 HSIO_PLL5G_CFG0_ENA_BIAS |
229 HSIO_PLL5G_CFG0_ENA_VCO_BUF |
230 HSIO_PLL5G_CFG0_ENA_CP1 |
231 HSIO_PLL5G_CFG0_SELCPI(2) |
232 HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) |
233 HSIO_PLL5G_CFG0_SELBGV820(4) |
234 HSIO_PLL5G_CFG0_DIV4 |
235 HSIO_PLL5G_CFG0_ENA_CLKTREE |
236 HSIO_PLL5G_CFG0_ENA_LANE);
237 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2,
238 HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET |
239 HSIO_PLL5G_CFG2_EN_RESET_OVERRUN |
240 HSIO_PLL5G_CFG2_GAIN_TEST(0x8) |
241 HSIO_PLL5G_CFG2_ENA_AMPCTRL |
242 HSIO_PLL5G_CFG2_PWD_AMPCTRL_N |
243 HSIO_PLL5G_CFG2_AMPC_SEL(0x10));
244}
245EXPORT_SYMBOL(ocelot_pll5_init);
246
247static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
248{
249 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
250 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
251 ANA_PORT_VCAP_S2_CFG, port);
252
253 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA,
254 ANA_PORT_VCAP_CFG, port);
255
256 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN,
257 REW_PORT_CFG_ES0_EN,
258 REW_PORT_CFG, port);
259}
260
261static int ocelot_single_vlan_aware_bridge(struct ocelot *ocelot,
262 struct netlink_ext_ack *extack)
263{
264 struct net_device *bridge = NULL;
265 int port;
266
267 for (port = 0; port < ocelot->num_phys_ports; port++) {
268 struct ocelot_port *ocelot_port = ocelot->ports[port];
269
270 if (!ocelot_port || !ocelot_port->bridge ||
271 !br_vlan_enabled(ocelot_port->bridge))
272 continue;
273
274 if (!bridge) {
275 bridge = ocelot_port->bridge;
276 continue;
277 }
278
279 if (bridge == ocelot_port->bridge)
280 continue;
281
282 NL_SET_ERR_MSG_MOD(extack,
283 "Only one VLAN-aware bridge is supported");
284 return -EBUSY;
285 }
286
287 return 0;
288}
289
290static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
291{
292 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
293}
294
295static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
296{
297 u32 val;
298
299 return readx_poll_timeout(ocelot_vlant_read_vlanaccess,
300 ocelot,
301 val,
302 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) ==
303 ANA_TABLES_VLANACCESS_CMD_IDLE,
304 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
305}
306
307static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
308{
309 /* Select the VID to configure */
310 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
311 ANA_TABLES_VLANTIDX);
312 /* Set the vlan port members mask and issue a write command */
313 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
314 ANA_TABLES_VLANACCESS_CMD_WRITE,
315 ANA_TABLES_VLANACCESS);
316
317 return ocelot_vlant_wait_for_completion(ocelot);
318}
319
320static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port)
321{
322 struct ocelot_bridge_vlan *vlan;
323 int num_untagged = 0;
324
325 list_for_each_entry(vlan, &ocelot->vlans, list) {
326 if (!(vlan->portmask & BIT(port)))
327 continue;
328
329 /* Ignore the VLAN added by ocelot_add_vlan_unaware_pvid(),
330 * because this is never active in hardware at the same time as
331 * the bridge VLANs, which only matter in VLAN-aware mode.
332 */
333 if (vlan->vid >= OCELOT_RSV_VLAN_RANGE_START)
334 continue;
335
336 if (vlan->untagged & BIT(port))
337 num_untagged++;
338 }
339
340 return num_untagged;
341}
342
343static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port)
344{
345 struct ocelot_bridge_vlan *vlan;
346 int num_tagged = 0;
347
348 list_for_each_entry(vlan, &ocelot->vlans, list) {
349 if (!(vlan->portmask & BIT(port)))
350 continue;
351
352 if (!(vlan->untagged & BIT(port)))
353 num_tagged++;
354 }
355
356 return num_tagged;
357}
358
359/* We use native VLAN when we have to mix egress-tagged VLANs with exactly
360 * _one_ egress-untagged VLAN (_the_ native VLAN)
361 */
362static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port)
363{
364 return ocelot_port_num_tagged_vlans(ocelot, port) &&
365 ocelot_port_num_untagged_vlans(ocelot, port) == 1;
366}
367
368static struct ocelot_bridge_vlan *
369ocelot_port_find_native_vlan(struct ocelot *ocelot, int port)
370{
371 struct ocelot_bridge_vlan *vlan;
372
373 list_for_each_entry(vlan, &ocelot->vlans, list)
374 if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port))
375 return vlan;
376
377 return NULL;
378}
379
380/* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable,
381 * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness
382 * state of the port.
383 */
384static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port)
385{
386 struct ocelot_port *ocelot_port = ocelot->ports[port];
387 enum ocelot_port_tag_config tag_cfg;
388 bool uses_native_vlan = false;
389
390 if (ocelot_port->vlan_aware) {
391 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port);
392
393 if (uses_native_vlan)
394 tag_cfg = OCELOT_PORT_TAG_NATIVE;
395 else if (ocelot_port_num_untagged_vlans(ocelot, port))
396 tag_cfg = OCELOT_PORT_TAG_DISABLED;
397 else
398 tag_cfg = OCELOT_PORT_TAG_TRUNK;
399 } else {
400 tag_cfg = OCELOT_PORT_TAG_DISABLED;
401 }
402
403 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg),
404 REW_TAG_CFG_TAG_CFG_M,
405 REW_TAG_CFG, port);
406
407 if (uses_native_vlan) {
408 struct ocelot_bridge_vlan *native_vlan;
409
410 /* Not having a native VLAN is impossible, because
411 * ocelot_port_num_untagged_vlans has returned 1.
412 * So there is no use in checking for NULL here.
413 */
414 native_vlan = ocelot_port_find_native_vlan(ocelot, port);
415
416 ocelot_rmw_gix(ocelot,
417 REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid),
418 REW_PORT_VLAN_CFG_PORT_VID_M,
419 REW_PORT_VLAN_CFG, port);
420 }
421}
422
423int ocelot_bridge_num_find(struct ocelot *ocelot,
424 const struct net_device *bridge)
425{
426 int port;
427
428 for (port = 0; port < ocelot->num_phys_ports; port++) {
429 struct ocelot_port *ocelot_port = ocelot->ports[port];
430
431 if (ocelot_port && ocelot_port->bridge == bridge)
432 return ocelot_port->bridge_num;
433 }
434
435 return -1;
436}
437EXPORT_SYMBOL_GPL(ocelot_bridge_num_find);
438
439static u16 ocelot_vlan_unaware_pvid(struct ocelot *ocelot,
440 const struct net_device *bridge)
441{
442 int bridge_num;
443
444 /* Standalone ports use VID 0 */
445 if (!bridge)
446 return 0;
447
448 bridge_num = ocelot_bridge_num_find(ocelot, bridge);
449 if (WARN_ON(bridge_num < 0))
450 return 0;
451
452 /* VLAN-unaware bridges use a reserved VID going from 4095 downwards */
453 return VLAN_N_VID - bridge_num - 1;
454}
455
456/* Default vlan to clasify for untagged frames (may be zero) */
457static void ocelot_port_set_pvid(struct ocelot *ocelot, int port,
458 const struct ocelot_bridge_vlan *pvid_vlan)
459{
460 struct ocelot_port *ocelot_port = ocelot->ports[port];
461 u16 pvid = ocelot_vlan_unaware_pvid(ocelot, ocelot_port->bridge);
462 u32 val = 0;
463
464 ocelot_port->pvid_vlan = pvid_vlan;
465
466 if (ocelot_port->vlan_aware && pvid_vlan)
467 pvid = pvid_vlan->vid;
468
469 ocelot_rmw_gix(ocelot,
470 ANA_PORT_VLAN_CFG_VLAN_VID(pvid),
471 ANA_PORT_VLAN_CFG_VLAN_VID_M,
472 ANA_PORT_VLAN_CFG, port);
473
474 /* If there's no pvid, we should drop not only untagged traffic (which
475 * happens automatically), but also 802.1p traffic which gets
476 * classified to VLAN 0, but that is always in our RX filter, so it
477 * would get accepted were it not for this setting.
478 */
479 if (!pvid_vlan && ocelot_port->vlan_aware)
480 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
481 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
482
483 ocelot_rmw_gix(ocelot, val,
484 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
485 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA,
486 ANA_PORT_DROP_CFG, port);
487}
488
489static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot,
490 u16 vid)
491{
492 struct ocelot_bridge_vlan *vlan;
493
494 list_for_each_entry(vlan, &ocelot->vlans, list)
495 if (vlan->vid == vid)
496 return vlan;
497
498 return NULL;
499}
500
501static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid,
502 bool untagged)
503{
504 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
505 unsigned long portmask;
506 int err;
507
508 if (vlan) {
509 portmask = vlan->portmask | BIT(port);
510
511 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
512 if (err)
513 return err;
514
515 vlan->portmask = portmask;
516 /* Bridge VLANs can be overwritten with a different
517 * egress-tagging setting, so make sure to override an untagged
518 * with a tagged VID if that's going on.
519 */
520 if (untagged)
521 vlan->untagged |= BIT(port);
522 else
523 vlan->untagged &= ~BIT(port);
524
525 return 0;
526 }
527
528 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
529 if (!vlan)
530 return -ENOMEM;
531
532 portmask = BIT(port);
533
534 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
535 if (err) {
536 kfree(vlan);
537 return err;
538 }
539
540 vlan->vid = vid;
541 vlan->portmask = portmask;
542 if (untagged)
543 vlan->untagged = BIT(port);
544 INIT_LIST_HEAD(&vlan->list);
545 list_add_tail(&vlan->list, &ocelot->vlans);
546
547 return 0;
548}
549
550static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid)
551{
552 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
553 unsigned long portmask;
554 int err;
555
556 if (!vlan)
557 return 0;
558
559 portmask = vlan->portmask & ~BIT(port);
560
561 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
562 if (err)
563 return err;
564
565 vlan->portmask = portmask;
566 if (vlan->portmask)
567 return 0;
568
569 list_del(&vlan->list);
570 kfree(vlan);
571
572 return 0;
573}
574
575static int ocelot_add_vlan_unaware_pvid(struct ocelot *ocelot, int port,
576 const struct net_device *bridge)
577{
578 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
579
580 return ocelot_vlan_member_add(ocelot, port, vid, true);
581}
582
583static int ocelot_del_vlan_unaware_pvid(struct ocelot *ocelot, int port,
584 const struct net_device *bridge)
585{
586 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
587
588 return ocelot_vlan_member_del(ocelot, port, vid);
589}
590
591int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
592 bool vlan_aware, struct netlink_ext_ack *extack)
593{
594 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1];
595 struct ocelot_port *ocelot_port = ocelot->ports[port];
596 struct ocelot_vcap_filter *filter;
597 int err = 0;
598 u32 val;
599
600 list_for_each_entry(filter, &block->rules, list) {
601 if (filter->ingress_port_mask & BIT(port) &&
602 filter->action.vid_replace_ena) {
603 NL_SET_ERR_MSG_MOD(extack,
604 "Cannot change VLAN state with vlan modify rules active");
605 return -EBUSY;
606 }
607 }
608
609 err = ocelot_single_vlan_aware_bridge(ocelot, extack);
610 if (err)
611 return err;
612
613 if (vlan_aware)
614 err = ocelot_del_vlan_unaware_pvid(ocelot, port,
615 ocelot_port->bridge);
616 else if (ocelot_port->bridge)
617 err = ocelot_add_vlan_unaware_pvid(ocelot, port,
618 ocelot_port->bridge);
619 if (err)
620 return err;
621
622 ocelot_port->vlan_aware = vlan_aware;
623
624 if (vlan_aware)
625 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
626 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
627 else
628 val = 0;
629 ocelot_rmw_gix(ocelot, val,
630 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
631 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
632 ANA_PORT_VLAN_CFG, port);
633
634 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan);
635 ocelot_port_manage_port_tag(ocelot, port);
636
637 return 0;
638}
639EXPORT_SYMBOL(ocelot_port_vlan_filtering);
640
641int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
642 bool untagged, struct netlink_ext_ack *extack)
643{
644 if (untagged) {
645 /* We are adding an egress-tagged VLAN */
646 if (ocelot_port_uses_native_vlan(ocelot, port)) {
647 NL_SET_ERR_MSG_MOD(extack,
648 "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN");
649 return -EBUSY;
650 }
651 } else {
652 /* We are adding an egress-tagged VLAN */
653 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) {
654 NL_SET_ERR_MSG_MOD(extack,
655 "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs");
656 return -EBUSY;
657 }
658 }
659
660 if (vid > OCELOT_RSV_VLAN_RANGE_START) {
661 NL_SET_ERR_MSG_MOD(extack,
662 "VLAN range 4000-4095 reserved for VLAN-unaware bridging");
663 return -EBUSY;
664 }
665
666 return 0;
667}
668EXPORT_SYMBOL(ocelot_vlan_prepare);
669
670int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
671 bool untagged)
672{
673 int err;
674
675 /* Ignore VID 0 added to our RX filter by the 8021q module, since
676 * that collides with OCELOT_STANDALONE_PVID and changes it from
677 * egress-untagged to egress-tagged.
678 */
679 if (!vid)
680 return 0;
681
682 err = ocelot_vlan_member_add(ocelot, port, vid, untagged);
683 if (err)
684 return err;
685
686 /* Default ingress vlan classification */
687 if (pvid)
688 ocelot_port_set_pvid(ocelot, port,
689 ocelot_bridge_vlan_find(ocelot, vid));
690
691 /* Untagged egress vlan clasification */
692 ocelot_port_manage_port_tag(ocelot, port);
693
694 return 0;
695}
696EXPORT_SYMBOL(ocelot_vlan_add);
697
698int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
699{
700 struct ocelot_port *ocelot_port = ocelot->ports[port];
701 bool del_pvid = false;
702 int err;
703
704 if (!vid)
705 return 0;
706
707 if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid)
708 del_pvid = true;
709
710 err = ocelot_vlan_member_del(ocelot, port, vid);
711 if (err)
712 return err;
713
714 /* Ingress */
715 if (del_pvid)
716 ocelot_port_set_pvid(ocelot, port, NULL);
717
718 /* Egress */
719 ocelot_port_manage_port_tag(ocelot, port);
720
721 return 0;
722}
723EXPORT_SYMBOL(ocelot_vlan_del);
724
725static void ocelot_vlan_init(struct ocelot *ocelot)
726{
727 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0);
728 u16 port, vid;
729
730 /* Clear VLAN table, by default all ports are members of all VLANs */
731 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
732 ANA_TABLES_VLANACCESS);
733 ocelot_vlant_wait_for_completion(ocelot);
734
735 /* Configure the port VLAN memberships */
736 for (vid = 1; vid < VLAN_N_VID; vid++)
737 ocelot_vlant_set_mask(ocelot, vid, 0);
738
739 /* We need VID 0 to get traffic on standalone ports.
740 * It is added automatically if the 8021q module is loaded, but we
741 * can't rely on that since it might not be.
742 */
743 ocelot_vlant_set_mask(ocelot, OCELOT_STANDALONE_PVID, all_ports);
744
745 /* Set vlan ingress filter mask to all ports but the CPU port by
746 * default.
747 */
748 ocelot_write(ocelot, all_ports, ANA_VLANMASK);
749
750 for (port = 0; port < ocelot->num_phys_ports; port++) {
751 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
752 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
753 }
754}
755
756static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port)
757{
758 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port);
759}
760
761static int ocelot_port_flush(struct ocelot *ocelot, int port)
762{
763 unsigned int pause_ena;
764 int err, val;
765
766 /* Disable dequeuing from the egress queues */
767 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS,
768 QSYS_PORT_MODE_DEQUEUE_DIS,
769 QSYS_PORT_MODE, port);
770
771 /* Disable flow control */
772 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena);
773 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0);
774
775 /* Disable priority flow control */
776 ocelot_fields_write(ocelot, port,
777 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0);
778
779 /* Wait at least the time it takes to receive a frame of maximum length
780 * at the port.
781 * Worst-case delays for 10 kilobyte jumbo frames are:
782 * 8 ms on a 10M port
783 * 800 μs on a 100M port
784 * 80 μs on a 1G port
785 * 32 μs on a 2.5G port
786 */
787 usleep_range(8000, 10000);
788
789 /* Disable half duplex backpressure. */
790 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE,
791 SYS_FRONT_PORT_MODE, port);
792
793 /* Flush the queues associated with the port. */
794 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA,
795 REW_PORT_CFG, port);
796
797 /* Enable dequeuing from the egress queues. */
798 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE,
799 port);
800
801 /* Wait until flushing is complete. */
802 err = read_poll_timeout(ocelot_read_eq_avail, val, !val,
803 100, 2000000, false, ocelot, port);
804
805 /* Clear flushing again. */
806 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port);
807
808 /* Re-enable flow control */
809 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena);
810
811 return err;
812}
813
814int ocelot_port_configure_serdes(struct ocelot *ocelot, int port,
815 struct device_node *portnp)
816{
817 struct ocelot_port *ocelot_port = ocelot->ports[port];
818 struct device *dev = ocelot->dev;
819 int err;
820
821 /* Ensure clock signals and speed are set on all QSGMII links */
822 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_QSGMII)
823 ocelot_port_rmwl(ocelot_port, 0,
824 DEV_CLOCK_CFG_MAC_TX_RST |
825 DEV_CLOCK_CFG_MAC_RX_RST,
826 DEV_CLOCK_CFG);
827
828 if (ocelot_port->phy_mode != PHY_INTERFACE_MODE_INTERNAL) {
829 struct phy *serdes = of_phy_get(portnp, NULL);
830
831 if (IS_ERR(serdes)) {
832 err = PTR_ERR(serdes);
833 dev_err_probe(dev, err,
834 "missing SerDes phys for port %d\n",
835 port);
836 return err;
837 }
838
839 err = phy_set_mode_ext(serdes, PHY_MODE_ETHERNET,
840 ocelot_port->phy_mode);
841 of_phy_put(serdes);
842 if (err) {
843 dev_err(dev, "Could not SerDes mode on port %d: %pe\n",
844 port, ERR_PTR(err));
845 return err;
846 }
847 }
848
849 return 0;
850}
851EXPORT_SYMBOL_GPL(ocelot_port_configure_serdes);
852
853void ocelot_phylink_mac_config(struct ocelot *ocelot, int port,
854 unsigned int link_an_mode,
855 const struct phylink_link_state *state)
856{
857 struct ocelot_port *ocelot_port = ocelot->ports[port];
858
859 /* Disable HDX fast control */
860 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS,
861 DEV_PORT_MISC);
862
863 /* SGMII only for now */
864 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA,
865 PCS1G_MODE_CFG);
866 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
867
868 /* Enable PCS */
869 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
870
871 /* No aneg on SGMII */
872 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG);
873
874 /* No loopback */
875 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG);
876}
877EXPORT_SYMBOL_GPL(ocelot_phylink_mac_config);
878
879void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port,
880 unsigned int link_an_mode,
881 phy_interface_t interface,
882 unsigned long quirks)
883{
884 struct ocelot_port *ocelot_port = ocelot->ports[port];
885 int err;
886
887 ocelot_port->speed = SPEED_UNKNOWN;
888
889 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA,
890 DEV_MAC_ENA_CFG);
891
892 if (ocelot->ops->cut_through_fwd) {
893 mutex_lock(&ocelot->fwd_domain_lock);
894 ocelot->ops->cut_through_fwd(ocelot);
895 mutex_unlock(&ocelot->fwd_domain_lock);
896 }
897
898 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);
899
900 err = ocelot_port_flush(ocelot, port);
901 if (err)
902 dev_err(ocelot->dev, "failed to flush port %d: %d\n",
903 port, err);
904
905 /* Put the port in reset. */
906 if (interface != PHY_INTERFACE_MODE_QSGMII ||
907 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP))
908 ocelot_port_rmwl(ocelot_port,
909 DEV_CLOCK_CFG_MAC_TX_RST |
910 DEV_CLOCK_CFG_MAC_RX_RST,
911 DEV_CLOCK_CFG_MAC_TX_RST |
912 DEV_CLOCK_CFG_MAC_RX_RST,
913 DEV_CLOCK_CFG);
914}
915EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down);
916
917void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port,
918 struct phy_device *phydev,
919 unsigned int link_an_mode,
920 phy_interface_t interface,
921 int speed, int duplex,
922 bool tx_pause, bool rx_pause,
923 unsigned long quirks)
924{
925 struct ocelot_port *ocelot_port = ocelot->ports[port];
926 int mac_speed, mode = 0;
927 u32 mac_fc_cfg;
928
929 ocelot_port->speed = speed;
930
931 /* The MAC might be integrated in systems where the MAC speed is fixed
932 * and it's the PCS who is performing the rate adaptation, so we have
933 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG
934 * (which is also its default value).
935 */
936 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) ||
937 speed == SPEED_1000) {
938 mac_speed = OCELOT_SPEED_1000;
939 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
940 } else if (speed == SPEED_2500) {
941 mac_speed = OCELOT_SPEED_2500;
942 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
943 } else if (speed == SPEED_100) {
944 mac_speed = OCELOT_SPEED_100;
945 } else {
946 mac_speed = OCELOT_SPEED_10;
947 }
948
949 if (duplex == DUPLEX_FULL)
950 mode |= DEV_MAC_MODE_CFG_FDX_ENA;
951
952 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG);
953
954 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and
955 * PORT_RST bits in DEV_CLOCK_CFG.
956 */
957 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed),
958 DEV_CLOCK_CFG);
959
960 switch (speed) {
961 case SPEED_10:
962 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10);
963 break;
964 case SPEED_100:
965 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100);
966 break;
967 case SPEED_1000:
968 case SPEED_2500:
969 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000);
970 break;
971 default:
972 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n",
973 port, speed);
974 return;
975 }
976
977 if (rx_pause)
978 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA;
979
980 if (tx_pause)
981 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA |
982 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
983 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
984 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA;
985
986 /* Flow control. Link speed is only used here to evaluate the time
987 * specification in incoming pause frames.
988 */
989 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port);
990
991 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
992
993 /* Don't attempt to send PAUSE frames on the NPI port, it's broken */
994 if (port != ocelot->npi)
995 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA,
996 tx_pause);
997
998 /* Undo the effects of ocelot_phylink_mac_link_down:
999 * enable MAC module
1000 */
1001 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
1002 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
1003
1004 /* If the port supports cut-through forwarding, update the masks before
1005 * enabling forwarding on the port.
1006 */
1007 if (ocelot->ops->cut_through_fwd) {
1008 mutex_lock(&ocelot->fwd_domain_lock);
1009 /* Workaround for hardware bug - FP doesn't work
1010 * at all link speeds for all PHY modes. The function
1011 * below also calls ocelot->ops->cut_through_fwd(),
1012 * so we don't need to do it twice.
1013 */
1014 ocelot_port_update_active_preemptible_tcs(ocelot, port);
1015 mutex_unlock(&ocelot->fwd_domain_lock);
1016 }
1017
1018 /* Core: Enable port for frame transfer */
1019 ocelot_fields_write(ocelot, port,
1020 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
1021}
1022EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up);
1023
1024static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
1025 u32 *rval)
1026{
1027 u32 bytes_valid, val;
1028
1029 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1030 if (val == XTR_NOT_READY) {
1031 if (ifh)
1032 return -EIO;
1033
1034 do {
1035 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1036 } while (val == XTR_NOT_READY);
1037 }
1038
1039 switch (val) {
1040 case XTR_ABORT:
1041 return -EIO;
1042 case XTR_EOF_0:
1043 case XTR_EOF_1:
1044 case XTR_EOF_2:
1045 case XTR_EOF_3:
1046 case XTR_PRUNED:
1047 bytes_valid = XTR_VALID_BYTES(val);
1048 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1049 if (val == XTR_ESCAPE)
1050 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1051 else
1052 *rval = val;
1053
1054 return bytes_valid;
1055 case XTR_ESCAPE:
1056 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1057
1058 return 4;
1059 default:
1060 *rval = val;
1061
1062 return 4;
1063 }
1064}
1065
1066static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh)
1067{
1068 int i, err = 0;
1069
1070 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) {
1071 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]);
1072 if (err != 4)
1073 return (err < 0) ? err : -EIO;
1074 }
1075
1076 return 0;
1077}
1078
1079void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb,
1080 u64 timestamp)
1081{
1082 struct skb_shared_hwtstamps *shhwtstamps;
1083 u64 tod_in_ns, full_ts_in_ns;
1084 struct timespec64 ts;
1085
1086 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1087
1088 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec);
1089 if ((tod_in_ns & 0xffffffff) < timestamp)
1090 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) |
1091 timestamp;
1092 else
1093 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) |
1094 timestamp;
1095
1096 shhwtstamps = skb_hwtstamps(skb);
1097 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
1098 shhwtstamps->hwtstamp = full_ts_in_ns;
1099}
1100EXPORT_SYMBOL(ocelot_ptp_rx_timestamp);
1101
1102int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb)
1103{
1104 u64 timestamp, src_port, len;
1105 u32 xfh[OCELOT_TAG_LEN / 4];
1106 struct net_device *dev;
1107 struct sk_buff *skb;
1108 int sz, buf_len;
1109 u32 val, *buf;
1110 int err;
1111
1112 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh);
1113 if (err)
1114 return err;
1115
1116 ocelot_xfh_get_src_port(xfh, &src_port);
1117 ocelot_xfh_get_len(xfh, &len);
1118 ocelot_xfh_get_rew_val(xfh, ×tamp);
1119
1120 if (WARN_ON(src_port >= ocelot->num_phys_ports))
1121 return -EINVAL;
1122
1123 dev = ocelot->ops->port_to_netdev(ocelot, src_port);
1124 if (!dev)
1125 return -EINVAL;
1126
1127 skb = netdev_alloc_skb(dev, len);
1128 if (unlikely(!skb)) {
1129 netdev_err(dev, "Unable to allocate sk_buff\n");
1130 return -ENOMEM;
1131 }
1132
1133 buf_len = len - ETH_FCS_LEN;
1134 buf = (u32 *)skb_put(skb, buf_len);
1135
1136 len = 0;
1137 do {
1138 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1139 if (sz < 0) {
1140 err = sz;
1141 goto out_free_skb;
1142 }
1143 *buf++ = val;
1144 len += sz;
1145 } while (len < buf_len);
1146
1147 /* Read the FCS */
1148 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1149 if (sz < 0) {
1150 err = sz;
1151 goto out_free_skb;
1152 }
1153
1154 /* Update the statistics if part of the FCS was read before */
1155 len -= ETH_FCS_LEN - sz;
1156
1157 if (unlikely(dev->features & NETIF_F_RXFCS)) {
1158 buf = (u32 *)skb_put(skb, ETH_FCS_LEN);
1159 *buf = val;
1160 }
1161
1162 if (ocelot->ptp)
1163 ocelot_ptp_rx_timestamp(ocelot, skb, timestamp);
1164
1165 /* Everything we see on an interface that is in the HW bridge
1166 * has already been forwarded.
1167 */
1168 if (ocelot->ports[src_port]->bridge)
1169 skb->offload_fwd_mark = 1;
1170
1171 skb->protocol = eth_type_trans(skb, dev);
1172
1173 *nskb = skb;
1174
1175 return 0;
1176
1177out_free_skb:
1178 kfree_skb(skb);
1179 return err;
1180}
1181EXPORT_SYMBOL(ocelot_xtr_poll_frame);
1182
1183bool ocelot_can_inject(struct ocelot *ocelot, int grp)
1184{
1185 u32 val = ocelot_read(ocelot, QS_INJ_STATUS);
1186
1187 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))))
1188 return false;
1189 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))
1190 return false;
1191
1192 return true;
1193}
1194EXPORT_SYMBOL(ocelot_can_inject);
1195
1196void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag)
1197{
1198 ocelot_ifh_set_bypass(ifh, 1);
1199 ocelot_ifh_set_dest(ifh, BIT_ULL(port));
1200 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C);
1201 if (vlan_tag)
1202 ocelot_ifh_set_vlan_tci(ifh, vlan_tag);
1203 if (rew_op)
1204 ocelot_ifh_set_rew_op(ifh, rew_op);
1205}
1206EXPORT_SYMBOL(ocelot_ifh_port_set);
1207
1208void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
1209 u32 rew_op, struct sk_buff *skb)
1210{
1211 u32 ifh[OCELOT_TAG_LEN / 4] = {0};
1212 unsigned int i, count, last;
1213
1214 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1215 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
1216
1217 ocelot_ifh_port_set(ifh, port, rew_op, skb_vlan_tag_get(skb));
1218
1219 for (i = 0; i < OCELOT_TAG_LEN / 4; i++)
1220 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp);
1221
1222 count = DIV_ROUND_UP(skb->len, 4);
1223 last = skb->len % 4;
1224 for (i = 0; i < count; i++)
1225 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
1226
1227 /* Add padding */
1228 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
1229 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1230 i++;
1231 }
1232
1233 /* Indicate EOF and valid bytes in last word */
1234 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1235 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
1236 QS_INJ_CTRL_EOF,
1237 QS_INJ_CTRL, grp);
1238
1239 /* Add dummy CRC */
1240 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1241 skb_tx_timestamp(skb);
1242
1243 skb->dev->stats.tx_packets++;
1244 skb->dev->stats.tx_bytes += skb->len;
1245}
1246EXPORT_SYMBOL(ocelot_port_inject_frame);
1247
1248void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp)
1249{
1250 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
1251 ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1252}
1253EXPORT_SYMBOL(ocelot_drain_cpu_queue);
1254
1255int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr,
1256 u16 vid, const struct net_device *bridge)
1257{
1258 if (!vid)
1259 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1260
1261 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED);
1262}
1263EXPORT_SYMBOL(ocelot_fdb_add);
1264
1265int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr,
1266 u16 vid, const struct net_device *bridge)
1267{
1268 if (!vid)
1269 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1270
1271 return ocelot_mact_forget(ocelot, addr, vid);
1272}
1273EXPORT_SYMBOL(ocelot_fdb_del);
1274
1275/* Caller must hold &ocelot->mact_lock */
1276static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col,
1277 struct ocelot_mact_entry *entry)
1278{
1279 u32 val, dst, macl, mach;
1280 char mac[ETH_ALEN];
1281
1282 /* Set row and column to read from */
1283 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
1284 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
1285
1286 /* Issue a read command */
1287 ocelot_write(ocelot,
1288 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
1289 ANA_TABLES_MACACCESS);
1290
1291 if (ocelot_mact_wait_for_completion(ocelot))
1292 return -ETIMEDOUT;
1293
1294 /* Read the entry flags */
1295 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
1296 if (!(val & ANA_TABLES_MACACCESS_VALID))
1297 return -EINVAL;
1298
1299 /* If the entry read has another port configured as its destination,
1300 * do not report it.
1301 */
1302 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
1303 if (dst != port)
1304 return -EINVAL;
1305
1306 /* Get the entry's MAC address and VLAN id */
1307 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
1308 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
1309
1310 mac[0] = (mach >> 8) & 0xff;
1311 mac[1] = (mach >> 0) & 0xff;
1312 mac[2] = (macl >> 24) & 0xff;
1313 mac[3] = (macl >> 16) & 0xff;
1314 mac[4] = (macl >> 8) & 0xff;
1315 mac[5] = (macl >> 0) & 0xff;
1316
1317 entry->vid = (mach >> 16) & 0xfff;
1318 ether_addr_copy(entry->mac, mac);
1319
1320 return 0;
1321}
1322
1323int ocelot_mact_flush(struct ocelot *ocelot, int port)
1324{
1325 int err;
1326
1327 mutex_lock(&ocelot->mact_lock);
1328
1329 /* Program ageing filter for a single port */
1330 ocelot_write(ocelot, ANA_ANAGEFIL_PID_EN | ANA_ANAGEFIL_PID_VAL(port),
1331 ANA_ANAGEFIL);
1332
1333 /* Flushing dynamic FDB entries requires two successive age scans */
1334 ocelot_write(ocelot,
1335 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE),
1336 ANA_TABLES_MACACCESS);
1337
1338 err = ocelot_mact_wait_for_completion(ocelot);
1339 if (err) {
1340 mutex_unlock(&ocelot->mact_lock);
1341 return err;
1342 }
1343
1344 /* And second... */
1345 ocelot_write(ocelot,
1346 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE),
1347 ANA_TABLES_MACACCESS);
1348
1349 err = ocelot_mact_wait_for_completion(ocelot);
1350
1351 /* Restore ageing filter */
1352 ocelot_write(ocelot, 0, ANA_ANAGEFIL);
1353
1354 mutex_unlock(&ocelot->mact_lock);
1355
1356 return err;
1357}
1358EXPORT_SYMBOL_GPL(ocelot_mact_flush);
1359
1360int ocelot_fdb_dump(struct ocelot *ocelot, int port,
1361 dsa_fdb_dump_cb_t *cb, void *data)
1362{
1363 int err = 0;
1364 int i, j;
1365
1366 /* We could take the lock just around ocelot_mact_read, but doing so
1367 * thousands of times in a row seems rather pointless and inefficient.
1368 */
1369 mutex_lock(&ocelot->mact_lock);
1370
1371 /* Loop through all the mac tables entries. */
1372 for (i = 0; i < ocelot->num_mact_rows; i++) {
1373 for (j = 0; j < 4; j++) {
1374 struct ocelot_mact_entry entry;
1375 bool is_static;
1376
1377 err = ocelot_mact_read(ocelot, port, i, j, &entry);
1378 /* If the entry is invalid (wrong port, invalid...),
1379 * skip it.
1380 */
1381 if (err == -EINVAL)
1382 continue;
1383 else if (err)
1384 break;
1385
1386 is_static = (entry.type == ENTRYTYPE_LOCKED);
1387
1388 /* Hide the reserved VLANs used for
1389 * VLAN-unaware bridging.
1390 */
1391 if (entry.vid > OCELOT_RSV_VLAN_RANGE_START)
1392 entry.vid = 0;
1393
1394 err = cb(entry.mac, entry.vid, is_static, data);
1395 if (err)
1396 break;
1397 }
1398 }
1399
1400 mutex_unlock(&ocelot->mact_lock);
1401
1402 return err;
1403}
1404EXPORT_SYMBOL(ocelot_fdb_dump);
1405
1406int ocelot_trap_add(struct ocelot *ocelot, int port,
1407 unsigned long cookie, bool take_ts,
1408 void (*populate)(struct ocelot_vcap_filter *f))
1409{
1410 struct ocelot_vcap_block *block_vcap_is2;
1411 struct ocelot_vcap_filter *trap;
1412 bool new = false;
1413 int err;
1414
1415 block_vcap_is2 = &ocelot->block[VCAP_IS2];
1416
1417 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie,
1418 false);
1419 if (!trap) {
1420 trap = kzalloc(sizeof(*trap), GFP_KERNEL);
1421 if (!trap)
1422 return -ENOMEM;
1423
1424 populate(trap);
1425 trap->prio = 1;
1426 trap->id.cookie = cookie;
1427 trap->id.tc_offload = false;
1428 trap->block_id = VCAP_IS2;
1429 trap->type = OCELOT_VCAP_FILTER_OFFLOAD;
1430 trap->lookup = 0;
1431 trap->action.cpu_copy_ena = true;
1432 trap->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY;
1433 trap->action.port_mask = 0;
1434 trap->take_ts = take_ts;
1435 trap->is_trap = true;
1436 new = true;
1437 }
1438
1439 trap->ingress_port_mask |= BIT(port);
1440
1441 if (new)
1442 err = ocelot_vcap_filter_add(ocelot, trap, NULL);
1443 else
1444 err = ocelot_vcap_filter_replace(ocelot, trap);
1445 if (err) {
1446 trap->ingress_port_mask &= ~BIT(port);
1447 if (!trap->ingress_port_mask)
1448 kfree(trap);
1449 return err;
1450 }
1451
1452 return 0;
1453}
1454
1455int ocelot_trap_del(struct ocelot *ocelot, int port, unsigned long cookie)
1456{
1457 struct ocelot_vcap_block *block_vcap_is2;
1458 struct ocelot_vcap_filter *trap;
1459
1460 block_vcap_is2 = &ocelot->block[VCAP_IS2];
1461
1462 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie,
1463 false);
1464 if (!trap)
1465 return 0;
1466
1467 trap->ingress_port_mask &= ~BIT(port);
1468 if (!trap->ingress_port_mask)
1469 return ocelot_vcap_filter_del(ocelot, trap);
1470
1471 return ocelot_vcap_filter_replace(ocelot, trap);
1472}
1473
1474static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond)
1475{
1476 u32 mask = 0;
1477 int port;
1478
1479 lockdep_assert_held(&ocelot->fwd_domain_lock);
1480
1481 for (port = 0; port < ocelot->num_phys_ports; port++) {
1482 struct ocelot_port *ocelot_port = ocelot->ports[port];
1483
1484 if (!ocelot_port)
1485 continue;
1486
1487 if (ocelot_port->bond == bond)
1488 mask |= BIT(port);
1489 }
1490
1491 return mask;
1492}
1493
1494/* The logical port number of a LAG is equal to the lowest numbered physical
1495 * port ID present in that LAG. It may change if that port ever leaves the LAG.
1496 */
1497int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond)
1498{
1499 int bond_mask = ocelot_get_bond_mask(ocelot, bond);
1500
1501 if (!bond_mask)
1502 return -ENOENT;
1503
1504 return __ffs(bond_mask);
1505}
1506EXPORT_SYMBOL_GPL(ocelot_bond_get_id);
1507
1508/* Returns the mask of user ports assigned to this DSA tag_8021q CPU port.
1509 * Note that when CPU ports are in a LAG, the user ports are assigned to the
1510 * 'primary' CPU port, the one whose physical port number gives the logical
1511 * port number of the LAG.
1512 *
1513 * We leave PGID_SRC poorly configured for the 'secondary' CPU port in the LAG
1514 * (to which no user port is assigned), but it appears that forwarding from
1515 * this secondary CPU port looks at the PGID_SRC associated with the logical
1516 * port ID that it's assigned to, which *is* configured properly.
1517 */
1518static u32 ocelot_dsa_8021q_cpu_assigned_ports(struct ocelot *ocelot,
1519 struct ocelot_port *cpu)
1520{
1521 u32 mask = 0;
1522 int port;
1523
1524 for (port = 0; port < ocelot->num_phys_ports; port++) {
1525 struct ocelot_port *ocelot_port = ocelot->ports[port];
1526
1527 if (!ocelot_port)
1528 continue;
1529
1530 if (ocelot_port->dsa_8021q_cpu == cpu)
1531 mask |= BIT(port);
1532 }
1533
1534 if (cpu->bond)
1535 mask &= ~ocelot_get_bond_mask(ocelot, cpu->bond);
1536
1537 return mask;
1538}
1539
1540/* Returns the DSA tag_8021q CPU port that the given port is assigned to,
1541 * or the bit mask of CPU ports if said CPU port is in a LAG.
1542 */
1543u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port)
1544{
1545 struct ocelot_port *ocelot_port = ocelot->ports[port];
1546 struct ocelot_port *cpu_port = ocelot_port->dsa_8021q_cpu;
1547
1548 if (!cpu_port)
1549 return 0;
1550
1551 if (cpu_port->bond)
1552 return ocelot_get_bond_mask(ocelot, cpu_port->bond);
1553
1554 return BIT(cpu_port->index);
1555}
1556EXPORT_SYMBOL_GPL(ocelot_port_assigned_dsa_8021q_cpu_mask);
1557
1558u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port)
1559{
1560 struct ocelot_port *ocelot_port = ocelot->ports[src_port];
1561 const struct net_device *bridge;
1562 u32 mask = 0;
1563 int port;
1564
1565 if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING)
1566 return 0;
1567
1568 bridge = ocelot_port->bridge;
1569 if (!bridge)
1570 return 0;
1571
1572 for (port = 0; port < ocelot->num_phys_ports; port++) {
1573 ocelot_port = ocelot->ports[port];
1574
1575 if (!ocelot_port)
1576 continue;
1577
1578 if (ocelot_port->stp_state == BR_STATE_FORWARDING &&
1579 ocelot_port->bridge == bridge)
1580 mask |= BIT(port);
1581 }
1582
1583 return mask;
1584}
1585EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask);
1586
1587static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining)
1588{
1589 int port;
1590
1591 lockdep_assert_held(&ocelot->fwd_domain_lock);
1592
1593 /* If cut-through forwarding is supported, update the masks before a
1594 * port joins the forwarding domain, to avoid potential underruns if it
1595 * has the highest speed from the new domain.
1596 */
1597 if (joining && ocelot->ops->cut_through_fwd)
1598 ocelot->ops->cut_through_fwd(ocelot);
1599
1600 /* Apply FWD mask. The loop is needed to add/remove the current port as
1601 * a source for the other ports.
1602 */
1603 for (port = 0; port < ocelot->num_phys_ports; port++) {
1604 struct ocelot_port *ocelot_port = ocelot->ports[port];
1605 unsigned long mask;
1606
1607 if (!ocelot_port) {
1608 /* Unused ports can't send anywhere */
1609 mask = 0;
1610 } else if (ocelot_port->is_dsa_8021q_cpu) {
1611 /* The DSA tag_8021q CPU ports need to be able to
1612 * forward packets to all ports assigned to them.
1613 */
1614 mask = ocelot_dsa_8021q_cpu_assigned_ports(ocelot,
1615 ocelot_port);
1616 } else if (ocelot_port->bridge) {
1617 struct net_device *bond = ocelot_port->bond;
1618
1619 mask = ocelot_get_bridge_fwd_mask(ocelot, port);
1620 mask &= ~BIT(port);
1621
1622 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
1623 port);
1624
1625 if (bond)
1626 mask &= ~ocelot_get_bond_mask(ocelot, bond);
1627 } else {
1628 /* Standalone ports forward only to DSA tag_8021q CPU
1629 * ports (if those exist), or to the hardware CPU port
1630 * module otherwise.
1631 */
1632 mask = ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
1633 port);
1634 }
1635
1636 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port);
1637 }
1638
1639 /* If cut-through forwarding is supported and a port is leaving, there
1640 * is a chance that cut-through was disabled on the other ports due to
1641 * the port which is leaving (it has a higher link speed). We need to
1642 * update the cut-through masks of the remaining ports no earlier than
1643 * after the port has left, to prevent underruns from happening between
1644 * the cut-through update and the forwarding domain update.
1645 */
1646 if (!joining && ocelot->ops->cut_through_fwd)
1647 ocelot->ops->cut_through_fwd(ocelot);
1648}
1649
1650/* Update PGID_CPU which is the destination port mask used for whitelisting
1651 * unicast addresses filtered towards the host. In the normal and NPI modes,
1652 * this points to the analyzer entry for the CPU port module, while in DSA
1653 * tag_8021q mode, it is a bit mask of all active CPU ports.
1654 * PGID_SRC will take care of forwarding a packet from one user port to
1655 * no more than a single CPU port.
1656 */
1657static void ocelot_update_pgid_cpu(struct ocelot *ocelot)
1658{
1659 int pgid_cpu = 0;
1660 int port;
1661
1662 for (port = 0; port < ocelot->num_phys_ports; port++) {
1663 struct ocelot_port *ocelot_port = ocelot->ports[port];
1664
1665 if (!ocelot_port || !ocelot_port->is_dsa_8021q_cpu)
1666 continue;
1667
1668 pgid_cpu |= BIT(port);
1669 }
1670
1671 if (!pgid_cpu)
1672 pgid_cpu = BIT(ocelot->num_phys_ports);
1673
1674 ocelot_write_rix(ocelot, pgid_cpu, ANA_PGID_PGID, PGID_CPU);
1675}
1676
1677void ocelot_port_setup_dsa_8021q_cpu(struct ocelot *ocelot, int cpu)
1678{
1679 struct ocelot_port *cpu_port = ocelot->ports[cpu];
1680 u16 vid;
1681
1682 mutex_lock(&ocelot->fwd_domain_lock);
1683
1684 cpu_port->is_dsa_8021q_cpu = true;
1685
1686 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
1687 ocelot_vlan_member_add(ocelot, cpu, vid, true);
1688
1689 ocelot_update_pgid_cpu(ocelot);
1690
1691 mutex_unlock(&ocelot->fwd_domain_lock);
1692}
1693EXPORT_SYMBOL_GPL(ocelot_port_setup_dsa_8021q_cpu);
1694
1695void ocelot_port_teardown_dsa_8021q_cpu(struct ocelot *ocelot, int cpu)
1696{
1697 struct ocelot_port *cpu_port = ocelot->ports[cpu];
1698 u16 vid;
1699
1700 mutex_lock(&ocelot->fwd_domain_lock);
1701
1702 cpu_port->is_dsa_8021q_cpu = false;
1703
1704 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
1705 ocelot_vlan_member_del(ocelot, cpu_port->index, vid);
1706
1707 ocelot_update_pgid_cpu(ocelot);
1708
1709 mutex_unlock(&ocelot->fwd_domain_lock);
1710}
1711EXPORT_SYMBOL_GPL(ocelot_port_teardown_dsa_8021q_cpu);
1712
1713void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port,
1714 int cpu)
1715{
1716 struct ocelot_port *cpu_port = ocelot->ports[cpu];
1717
1718 mutex_lock(&ocelot->fwd_domain_lock);
1719
1720 ocelot->ports[port]->dsa_8021q_cpu = cpu_port;
1721 ocelot_apply_bridge_fwd_mask(ocelot, true);
1722
1723 mutex_unlock(&ocelot->fwd_domain_lock);
1724}
1725EXPORT_SYMBOL_GPL(ocelot_port_assign_dsa_8021q_cpu);
1726
1727void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port)
1728{
1729 mutex_lock(&ocelot->fwd_domain_lock);
1730
1731 ocelot->ports[port]->dsa_8021q_cpu = NULL;
1732 ocelot_apply_bridge_fwd_mask(ocelot, true);
1733
1734 mutex_unlock(&ocelot->fwd_domain_lock);
1735}
1736EXPORT_SYMBOL_GPL(ocelot_port_unassign_dsa_8021q_cpu);
1737
1738void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
1739{
1740 struct ocelot_port *ocelot_port = ocelot->ports[port];
1741 u32 learn_ena = 0;
1742
1743 mutex_lock(&ocelot->fwd_domain_lock);
1744
1745 ocelot_port->stp_state = state;
1746
1747 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) &&
1748 ocelot_port->learn_ena)
1749 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA;
1750
1751 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA,
1752 ANA_PORT_PORT_CFG, port);
1753
1754 ocelot_apply_bridge_fwd_mask(ocelot, state == BR_STATE_FORWARDING);
1755
1756 mutex_unlock(&ocelot->fwd_domain_lock);
1757}
1758EXPORT_SYMBOL(ocelot_bridge_stp_state_set);
1759
1760void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
1761{
1762 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000);
1763
1764 /* Setting AGE_PERIOD to zero effectively disables automatic aging,
1765 * which is clearly not what our intention is. So avoid that.
1766 */
1767 if (!age_period)
1768 age_period = 1;
1769
1770 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE);
1771}
1772EXPORT_SYMBOL(ocelot_set_ageing_time);
1773
1774static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
1775 const unsigned char *addr,
1776 u16 vid)
1777{
1778 struct ocelot_multicast *mc;
1779
1780 list_for_each_entry(mc, &ocelot->multicast, list) {
1781 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
1782 return mc;
1783 }
1784
1785 return NULL;
1786}
1787
1788static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr)
1789{
1790 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e)
1791 return ENTRYTYPE_MACv4;
1792 if (addr[0] == 0x33 && addr[1] == 0x33)
1793 return ENTRYTYPE_MACv6;
1794 return ENTRYTYPE_LOCKED;
1795}
1796
1797static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index,
1798 unsigned long ports)
1799{
1800 struct ocelot_pgid *pgid;
1801
1802 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL);
1803 if (!pgid)
1804 return ERR_PTR(-ENOMEM);
1805
1806 pgid->ports = ports;
1807 pgid->index = index;
1808 refcount_set(&pgid->refcount, 1);
1809 list_add_tail(&pgid->list, &ocelot->pgids);
1810
1811 return pgid;
1812}
1813
1814static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid)
1815{
1816 if (!refcount_dec_and_test(&pgid->refcount))
1817 return;
1818
1819 list_del(&pgid->list);
1820 kfree(pgid);
1821}
1822
1823static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot,
1824 const struct ocelot_multicast *mc)
1825{
1826 struct ocelot_pgid *pgid;
1827 int index;
1828
1829 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and
1830 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the
1831 * destination mask table (PGID), the destination set is programmed as
1832 * part of the entry MAC address.", and the DEST_IDX is set to 0.
1833 */
1834 if (mc->entry_type == ENTRYTYPE_MACv4 ||
1835 mc->entry_type == ENTRYTYPE_MACv6)
1836 return ocelot_pgid_alloc(ocelot, 0, mc->ports);
1837
1838 list_for_each_entry(pgid, &ocelot->pgids, list) {
1839 /* When searching for a nonreserved multicast PGID, ignore the
1840 * dummy PGID of zero that we have for MACv4/MACv6 entries
1841 */
1842 if (pgid->index && pgid->ports == mc->ports) {
1843 refcount_inc(&pgid->refcount);
1844 return pgid;
1845 }
1846 }
1847
1848 /* Search for a free index in the nonreserved multicast PGID area */
1849 for_each_nonreserved_multicast_dest_pgid(ocelot, index) {
1850 bool used = false;
1851
1852 list_for_each_entry(pgid, &ocelot->pgids, list) {
1853 if (pgid->index == index) {
1854 used = true;
1855 break;
1856 }
1857 }
1858
1859 if (!used)
1860 return ocelot_pgid_alloc(ocelot, index, mc->ports);
1861 }
1862
1863 return ERR_PTR(-ENOSPC);
1864}
1865
1866static void ocelot_encode_ports_to_mdb(unsigned char *addr,
1867 struct ocelot_multicast *mc)
1868{
1869 ether_addr_copy(addr, mc->addr);
1870
1871 if (mc->entry_type == ENTRYTYPE_MACv4) {
1872 addr[0] = 0;
1873 addr[1] = mc->ports >> 8;
1874 addr[2] = mc->ports & 0xff;
1875 } else if (mc->entry_type == ENTRYTYPE_MACv6) {
1876 addr[0] = mc->ports >> 8;
1877 addr[1] = mc->ports & 0xff;
1878 }
1879}
1880
1881int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
1882 const struct switchdev_obj_port_mdb *mdb,
1883 const struct net_device *bridge)
1884{
1885 unsigned char addr[ETH_ALEN];
1886 struct ocelot_multicast *mc;
1887 struct ocelot_pgid *pgid;
1888 u16 vid = mdb->vid;
1889
1890 if (!vid)
1891 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1892
1893 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1894 if (!mc) {
1895 /* New entry */
1896 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
1897 if (!mc)
1898 return -ENOMEM;
1899
1900 mc->entry_type = ocelot_classify_mdb(mdb->addr);
1901 ether_addr_copy(mc->addr, mdb->addr);
1902 mc->vid = vid;
1903
1904 list_add_tail(&mc->list, &ocelot->multicast);
1905 } else {
1906 /* Existing entry. Clean up the current port mask from
1907 * hardware now, because we'll be modifying it.
1908 */
1909 ocelot_pgid_free(ocelot, mc->pgid);
1910 ocelot_encode_ports_to_mdb(addr, mc);
1911 ocelot_mact_forget(ocelot, addr, vid);
1912 }
1913
1914 mc->ports |= BIT(port);
1915
1916 pgid = ocelot_mdb_get_pgid(ocelot, mc);
1917 if (IS_ERR(pgid)) {
1918 dev_err(ocelot->dev,
1919 "Cannot allocate PGID for mdb %pM vid %d\n",
1920 mc->addr, mc->vid);
1921 devm_kfree(ocelot->dev, mc);
1922 return PTR_ERR(pgid);
1923 }
1924 mc->pgid = pgid;
1925
1926 ocelot_encode_ports_to_mdb(addr, mc);
1927
1928 if (mc->entry_type != ENTRYTYPE_MACv4 &&
1929 mc->entry_type != ENTRYTYPE_MACv6)
1930 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
1931 pgid->index);
1932
1933 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
1934 mc->entry_type);
1935}
1936EXPORT_SYMBOL(ocelot_port_mdb_add);
1937
1938int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
1939 const struct switchdev_obj_port_mdb *mdb,
1940 const struct net_device *bridge)
1941{
1942 unsigned char addr[ETH_ALEN];
1943 struct ocelot_multicast *mc;
1944 struct ocelot_pgid *pgid;
1945 u16 vid = mdb->vid;
1946
1947 if (!vid)
1948 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1949
1950 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1951 if (!mc)
1952 return -ENOENT;
1953
1954 ocelot_encode_ports_to_mdb(addr, mc);
1955 ocelot_mact_forget(ocelot, addr, vid);
1956
1957 ocelot_pgid_free(ocelot, mc->pgid);
1958 mc->ports &= ~BIT(port);
1959 if (!mc->ports) {
1960 list_del(&mc->list);
1961 devm_kfree(ocelot->dev, mc);
1962 return 0;
1963 }
1964
1965 /* We have a PGID with fewer ports now */
1966 pgid = ocelot_mdb_get_pgid(ocelot, mc);
1967 if (IS_ERR(pgid))
1968 return PTR_ERR(pgid);
1969 mc->pgid = pgid;
1970
1971 ocelot_encode_ports_to_mdb(addr, mc);
1972
1973 if (mc->entry_type != ENTRYTYPE_MACv4 &&
1974 mc->entry_type != ENTRYTYPE_MACv6)
1975 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
1976 pgid->index);
1977
1978 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
1979 mc->entry_type);
1980}
1981EXPORT_SYMBOL(ocelot_port_mdb_del);
1982
1983int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
1984 struct net_device *bridge, int bridge_num,
1985 struct netlink_ext_ack *extack)
1986{
1987 struct ocelot_port *ocelot_port = ocelot->ports[port];
1988 int err;
1989
1990 err = ocelot_single_vlan_aware_bridge(ocelot, extack);
1991 if (err)
1992 return err;
1993
1994 mutex_lock(&ocelot->fwd_domain_lock);
1995
1996 ocelot_port->bridge = bridge;
1997 ocelot_port->bridge_num = bridge_num;
1998
1999 ocelot_apply_bridge_fwd_mask(ocelot, true);
2000
2001 mutex_unlock(&ocelot->fwd_domain_lock);
2002
2003 if (br_vlan_enabled(bridge))
2004 return 0;
2005
2006 return ocelot_add_vlan_unaware_pvid(ocelot, port, bridge);
2007}
2008EXPORT_SYMBOL(ocelot_port_bridge_join);
2009
2010void ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
2011 struct net_device *bridge)
2012{
2013 struct ocelot_port *ocelot_port = ocelot->ports[port];
2014
2015 mutex_lock(&ocelot->fwd_domain_lock);
2016
2017 if (!br_vlan_enabled(bridge))
2018 ocelot_del_vlan_unaware_pvid(ocelot, port, bridge);
2019
2020 ocelot_port->bridge = NULL;
2021 ocelot_port->bridge_num = -1;
2022
2023 ocelot_port_set_pvid(ocelot, port, NULL);
2024 ocelot_port_manage_port_tag(ocelot, port);
2025 ocelot_apply_bridge_fwd_mask(ocelot, false);
2026
2027 mutex_unlock(&ocelot->fwd_domain_lock);
2028}
2029EXPORT_SYMBOL(ocelot_port_bridge_leave);
2030
2031static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
2032{
2033 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0);
2034 int i, port, lag;
2035
2036 /* Reset destination and aggregation PGIDS */
2037 for_each_unicast_dest_pgid(ocelot, port)
2038 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
2039
2040 for_each_aggr_pgid(ocelot, i)
2041 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
2042 ANA_PGID_PGID, i);
2043
2044 /* The visited ports bitmask holds the list of ports offloading any
2045 * bonding interface. Initially we mark all these ports as unvisited,
2046 * then every time we visit a port in this bitmask, we know that it is
2047 * the lowest numbered port, i.e. the one whose logical ID == physical
2048 * port ID == LAG ID. So we mark as visited all further ports in the
2049 * bitmask that are offloading the same bonding interface. This way,
2050 * we set up the aggregation PGIDs only once per bonding interface.
2051 */
2052 for (port = 0; port < ocelot->num_phys_ports; port++) {
2053 struct ocelot_port *ocelot_port = ocelot->ports[port];
2054
2055 if (!ocelot_port || !ocelot_port->bond)
2056 continue;
2057
2058 visited &= ~BIT(port);
2059 }
2060
2061 /* Now, set PGIDs for each active LAG */
2062 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
2063 struct net_device *bond = ocelot->ports[lag]->bond;
2064 int num_active_ports = 0;
2065 unsigned long bond_mask;
2066 u8 aggr_idx[16];
2067
2068 if (!bond || (visited & BIT(lag)))
2069 continue;
2070
2071 bond_mask = ocelot_get_bond_mask(ocelot, bond);
2072
2073 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
2074 struct ocelot_port *ocelot_port = ocelot->ports[port];
2075
2076 // Destination mask
2077 ocelot_write_rix(ocelot, bond_mask,
2078 ANA_PGID_PGID, port);
2079
2080 if (ocelot_port->lag_tx_active)
2081 aggr_idx[num_active_ports++] = port;
2082 }
2083
2084 for_each_aggr_pgid(ocelot, i) {
2085 u32 ac;
2086
2087 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
2088 ac &= ~bond_mask;
2089 /* Don't do division by zero if there was no active
2090 * port. Just make all aggregation codes zero.
2091 */
2092 if (num_active_ports)
2093 ac |= BIT(aggr_idx[i % num_active_ports]);
2094 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
2095 }
2096
2097 /* Mark all ports in the same LAG as visited to avoid applying
2098 * the same config again.
2099 */
2100 for (port = lag; port < ocelot->num_phys_ports; port++) {
2101 struct ocelot_port *ocelot_port = ocelot->ports[port];
2102
2103 if (!ocelot_port)
2104 continue;
2105
2106 if (ocelot_port->bond == bond)
2107 visited |= BIT(port);
2108 }
2109 }
2110}
2111
2112/* When offloading a bonding interface, the switch ports configured under the
2113 * same bond must have the same logical port ID, equal to the physical port ID
2114 * of the lowest numbered physical port in that bond. Otherwise, in standalone/
2115 * bridged mode, each port has a logical port ID equal to its physical port ID.
2116 */
2117static void ocelot_setup_logical_port_ids(struct ocelot *ocelot)
2118{
2119 int port;
2120
2121 for (port = 0; port < ocelot->num_phys_ports; port++) {
2122 struct ocelot_port *ocelot_port = ocelot->ports[port];
2123 struct net_device *bond;
2124
2125 if (!ocelot_port)
2126 continue;
2127
2128 bond = ocelot_port->bond;
2129 if (bond) {
2130 int lag = ocelot_bond_get_id(ocelot, bond);
2131
2132 ocelot_rmw_gix(ocelot,
2133 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
2134 ANA_PORT_PORT_CFG_PORTID_VAL_M,
2135 ANA_PORT_PORT_CFG, port);
2136 } else {
2137 ocelot_rmw_gix(ocelot,
2138 ANA_PORT_PORT_CFG_PORTID_VAL(port),
2139 ANA_PORT_PORT_CFG_PORTID_VAL_M,
2140 ANA_PORT_PORT_CFG, port);
2141 }
2142 }
2143}
2144
2145static int ocelot_migrate_mc(struct ocelot *ocelot, struct ocelot_multicast *mc,
2146 unsigned long from_mask, unsigned long to_mask)
2147{
2148 unsigned char addr[ETH_ALEN];
2149 struct ocelot_pgid *pgid;
2150 u16 vid = mc->vid;
2151
2152 dev_dbg(ocelot->dev,
2153 "Migrating multicast %pM vid %d from port mask 0x%lx to 0x%lx\n",
2154 mc->addr, mc->vid, from_mask, to_mask);
2155
2156 /* First clean up the current port mask from hardware, because
2157 * we'll be modifying it.
2158 */
2159 ocelot_pgid_free(ocelot, mc->pgid);
2160 ocelot_encode_ports_to_mdb(addr, mc);
2161 ocelot_mact_forget(ocelot, addr, vid);
2162
2163 mc->ports &= ~from_mask;
2164 mc->ports |= to_mask;
2165
2166 pgid = ocelot_mdb_get_pgid(ocelot, mc);
2167 if (IS_ERR(pgid)) {
2168 dev_err(ocelot->dev,
2169 "Cannot allocate PGID for mdb %pM vid %d\n",
2170 mc->addr, mc->vid);
2171 devm_kfree(ocelot->dev, mc);
2172 return PTR_ERR(pgid);
2173 }
2174 mc->pgid = pgid;
2175
2176 ocelot_encode_ports_to_mdb(addr, mc);
2177
2178 if (mc->entry_type != ENTRYTYPE_MACv4 &&
2179 mc->entry_type != ENTRYTYPE_MACv6)
2180 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2181 pgid->index);
2182
2183 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2184 mc->entry_type);
2185}
2186
2187int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask,
2188 unsigned long to_mask)
2189{
2190 struct ocelot_multicast *mc;
2191 int err;
2192
2193 list_for_each_entry(mc, &ocelot->multicast, list) {
2194 if (!(mc->ports & from_mask))
2195 continue;
2196
2197 err = ocelot_migrate_mc(ocelot, mc, from_mask, to_mask);
2198 if (err)
2199 return err;
2200 }
2201
2202 return 0;
2203}
2204EXPORT_SYMBOL_GPL(ocelot_migrate_mdbs);
2205
2206/* Documentation for PORTID_VAL says:
2207 * Logical port number for front port. If port is not a member of a LLAG,
2208 * then PORTID must be set to the physical port number.
2209 * If port is a member of a LLAG, then PORTID must be set to the common
2210 * PORTID_VAL used for all member ports of the LLAG.
2211 * The value must not exceed the number of physical ports on the device.
2212 *
2213 * This means we have little choice but to migrate FDB entries pointing towards
2214 * a logical port when that changes.
2215 */
2216static void ocelot_migrate_lag_fdbs(struct ocelot *ocelot,
2217 struct net_device *bond,
2218 int lag)
2219{
2220 struct ocelot_lag_fdb *fdb;
2221 int err;
2222
2223 lockdep_assert_held(&ocelot->fwd_domain_lock);
2224
2225 list_for_each_entry(fdb, &ocelot->lag_fdbs, list) {
2226 if (fdb->bond != bond)
2227 continue;
2228
2229 err = ocelot_mact_forget(ocelot, fdb->addr, fdb->vid);
2230 if (err) {
2231 dev_err(ocelot->dev,
2232 "failed to delete LAG %s FDB %pM vid %d: %pe\n",
2233 bond->name, fdb->addr, fdb->vid, ERR_PTR(err));
2234 }
2235
2236 err = ocelot_mact_learn(ocelot, lag, fdb->addr, fdb->vid,
2237 ENTRYTYPE_LOCKED);
2238 if (err) {
2239 dev_err(ocelot->dev,
2240 "failed to migrate LAG %s FDB %pM vid %d: %pe\n",
2241 bond->name, fdb->addr, fdb->vid, ERR_PTR(err));
2242 }
2243 }
2244}
2245
2246int ocelot_port_lag_join(struct ocelot *ocelot, int port,
2247 struct net_device *bond,
2248 struct netdev_lag_upper_info *info,
2249 struct netlink_ext_ack *extack)
2250{
2251 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
2252 NL_SET_ERR_MSG_MOD(extack,
2253 "Can only offload LAG using hash TX type");
2254 return -EOPNOTSUPP;
2255 }
2256
2257 mutex_lock(&ocelot->fwd_domain_lock);
2258
2259 ocelot->ports[port]->bond = bond;
2260
2261 ocelot_setup_logical_port_ids(ocelot);
2262 ocelot_apply_bridge_fwd_mask(ocelot, true);
2263 ocelot_set_aggr_pgids(ocelot);
2264
2265 mutex_unlock(&ocelot->fwd_domain_lock);
2266
2267 return 0;
2268}
2269EXPORT_SYMBOL(ocelot_port_lag_join);
2270
2271void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
2272 struct net_device *bond)
2273{
2274 int old_lag_id, new_lag_id;
2275
2276 mutex_lock(&ocelot->fwd_domain_lock);
2277
2278 old_lag_id = ocelot_bond_get_id(ocelot, bond);
2279
2280 ocelot->ports[port]->bond = NULL;
2281
2282 ocelot_setup_logical_port_ids(ocelot);
2283 ocelot_apply_bridge_fwd_mask(ocelot, false);
2284 ocelot_set_aggr_pgids(ocelot);
2285
2286 new_lag_id = ocelot_bond_get_id(ocelot, bond);
2287
2288 if (new_lag_id >= 0 && old_lag_id != new_lag_id)
2289 ocelot_migrate_lag_fdbs(ocelot, bond, new_lag_id);
2290
2291 mutex_unlock(&ocelot->fwd_domain_lock);
2292}
2293EXPORT_SYMBOL(ocelot_port_lag_leave);
2294
2295void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active)
2296{
2297 struct ocelot_port *ocelot_port = ocelot->ports[port];
2298
2299 mutex_lock(&ocelot->fwd_domain_lock);
2300
2301 ocelot_port->lag_tx_active = lag_tx_active;
2302
2303 /* Rebalance the LAGs */
2304 ocelot_set_aggr_pgids(ocelot);
2305
2306 mutex_unlock(&ocelot->fwd_domain_lock);
2307}
2308EXPORT_SYMBOL(ocelot_port_lag_change);
2309
2310int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond,
2311 const unsigned char *addr, u16 vid,
2312 const struct net_device *bridge)
2313{
2314 struct ocelot_lag_fdb *fdb;
2315 int lag, err;
2316
2317 fdb = kzalloc(sizeof(*fdb), GFP_KERNEL);
2318 if (!fdb)
2319 return -ENOMEM;
2320
2321 mutex_lock(&ocelot->fwd_domain_lock);
2322
2323 if (!vid)
2324 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2325
2326 ether_addr_copy(fdb->addr, addr);
2327 fdb->vid = vid;
2328 fdb->bond = bond;
2329
2330 lag = ocelot_bond_get_id(ocelot, bond);
2331
2332 err = ocelot_mact_learn(ocelot, lag, addr, vid, ENTRYTYPE_LOCKED);
2333 if (err) {
2334 mutex_unlock(&ocelot->fwd_domain_lock);
2335 kfree(fdb);
2336 return err;
2337 }
2338
2339 list_add_tail(&fdb->list, &ocelot->lag_fdbs);
2340 mutex_unlock(&ocelot->fwd_domain_lock);
2341
2342 return 0;
2343}
2344EXPORT_SYMBOL_GPL(ocelot_lag_fdb_add);
2345
2346int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond,
2347 const unsigned char *addr, u16 vid,
2348 const struct net_device *bridge)
2349{
2350 struct ocelot_lag_fdb *fdb, *tmp;
2351
2352 mutex_lock(&ocelot->fwd_domain_lock);
2353
2354 if (!vid)
2355 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2356
2357 list_for_each_entry_safe(fdb, tmp, &ocelot->lag_fdbs, list) {
2358 if (!ether_addr_equal(fdb->addr, addr) || fdb->vid != vid ||
2359 fdb->bond != bond)
2360 continue;
2361
2362 ocelot_mact_forget(ocelot, addr, vid);
2363 list_del(&fdb->list);
2364 mutex_unlock(&ocelot->fwd_domain_lock);
2365 kfree(fdb);
2366
2367 return 0;
2368 }
2369
2370 mutex_unlock(&ocelot->fwd_domain_lock);
2371
2372 return -ENOENT;
2373}
2374EXPORT_SYMBOL_GPL(ocelot_lag_fdb_del);
2375
2376/* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
2377 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
2378 * In the special case that it's the NPI port that we're configuring, the
2379 * length of the tag and optional prefix needs to be accounted for privately,
2380 * in order to be able to sustain communication at the requested @sdu.
2381 */
2382void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu)
2383{
2384 struct ocelot_port *ocelot_port = ocelot->ports[port];
2385 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN;
2386 int pause_start, pause_stop;
2387 int atop, atop_tot;
2388
2389 if (port == ocelot->npi) {
2390 maxlen += OCELOT_TAG_LEN;
2391
2392 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2393 maxlen += OCELOT_SHORT_PREFIX_LEN;
2394 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2395 maxlen += OCELOT_LONG_PREFIX_LEN;
2396 }
2397
2398 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG);
2399
2400 /* Set Pause watermark hysteresis */
2401 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ;
2402 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ;
2403 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START,
2404 pause_start);
2405 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP,
2406 pause_stop);
2407
2408 /* Tail dropping watermarks */
2409 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) /
2410 OCELOT_BUFFER_CELL_SZ;
2411 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ;
2412 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port);
2413 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG);
2414}
2415EXPORT_SYMBOL(ocelot_port_set_maxlen);
2416
2417int ocelot_get_max_mtu(struct ocelot *ocelot, int port)
2418{
2419 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN;
2420
2421 if (port == ocelot->npi) {
2422 max_mtu -= OCELOT_TAG_LEN;
2423
2424 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2425 max_mtu -= OCELOT_SHORT_PREFIX_LEN;
2426 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2427 max_mtu -= OCELOT_LONG_PREFIX_LEN;
2428 }
2429
2430 return max_mtu;
2431}
2432EXPORT_SYMBOL(ocelot_get_max_mtu);
2433
2434static void ocelot_port_set_learning(struct ocelot *ocelot, int port,
2435 bool enabled)
2436{
2437 struct ocelot_port *ocelot_port = ocelot->ports[port];
2438 u32 val = 0;
2439
2440 if (enabled)
2441 val = ANA_PORT_PORT_CFG_LEARN_ENA;
2442
2443 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA,
2444 ANA_PORT_PORT_CFG, port);
2445
2446 ocelot_port->learn_ena = enabled;
2447}
2448
2449static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port,
2450 bool enabled)
2451{
2452 u32 val = 0;
2453
2454 if (enabled)
2455 val = BIT(port);
2456
2457 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC);
2458}
2459
2460static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port,
2461 bool enabled)
2462{
2463 u32 val = 0;
2464
2465 if (enabled)
2466 val = BIT(port);
2467
2468 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC);
2469 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV4);
2470 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV6);
2471}
2472
2473static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port,
2474 bool enabled)
2475{
2476 u32 val = 0;
2477
2478 if (enabled)
2479 val = BIT(port);
2480
2481 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC);
2482}
2483
2484int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
2485 struct switchdev_brport_flags flags)
2486{
2487 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
2488 BR_BCAST_FLOOD))
2489 return -EINVAL;
2490
2491 return 0;
2492}
2493EXPORT_SYMBOL(ocelot_port_pre_bridge_flags);
2494
2495void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
2496 struct switchdev_brport_flags flags)
2497{
2498 if (flags.mask & BR_LEARNING)
2499 ocelot_port_set_learning(ocelot, port,
2500 !!(flags.val & BR_LEARNING));
2501
2502 if (flags.mask & BR_FLOOD)
2503 ocelot_port_set_ucast_flood(ocelot, port,
2504 !!(flags.val & BR_FLOOD));
2505
2506 if (flags.mask & BR_MCAST_FLOOD)
2507 ocelot_port_set_mcast_flood(ocelot, port,
2508 !!(flags.val & BR_MCAST_FLOOD));
2509
2510 if (flags.mask & BR_BCAST_FLOOD)
2511 ocelot_port_set_bcast_flood(ocelot, port,
2512 !!(flags.val & BR_BCAST_FLOOD));
2513}
2514EXPORT_SYMBOL(ocelot_port_bridge_flags);
2515
2516int ocelot_port_get_default_prio(struct ocelot *ocelot, int port)
2517{
2518 int val = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port);
2519
2520 return ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(val);
2521}
2522EXPORT_SYMBOL_GPL(ocelot_port_get_default_prio);
2523
2524int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio)
2525{
2526 if (prio >= OCELOT_NUM_TC)
2527 return -ERANGE;
2528
2529 ocelot_rmw_gix(ocelot,
2530 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(prio),
2531 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M,
2532 ANA_PORT_QOS_CFG,
2533 port);
2534
2535 return 0;
2536}
2537EXPORT_SYMBOL_GPL(ocelot_port_set_default_prio);
2538
2539int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp)
2540{
2541 int qos_cfg = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port);
2542 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2543
2544 /* Return error if DSCP prioritization isn't enabled */
2545 if (!(qos_cfg & ANA_PORT_QOS_CFG_QOS_DSCP_ENA))
2546 return -EOPNOTSUPP;
2547
2548 if (qos_cfg & ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA) {
2549 dscp = ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(dscp_cfg);
2550 /* Re-read ANA_DSCP_CFG for the translated DSCP */
2551 dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2552 }
2553
2554 /* If the DSCP value is not trusted, the QoS classification falls back
2555 * to VLAN PCP or port-based default.
2556 */
2557 if (!(dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA))
2558 return -EOPNOTSUPP;
2559
2560 return ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg);
2561}
2562EXPORT_SYMBOL_GPL(ocelot_port_get_dscp_prio);
2563
2564int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio)
2565{
2566 int mask, val;
2567
2568 if (prio >= OCELOT_NUM_TC)
2569 return -ERANGE;
2570
2571 /* There is at least one app table priority (this one), so we need to
2572 * make sure DSCP prioritization is enabled on the port.
2573 * Also make sure DSCP translation is disabled
2574 * (dcbnl doesn't support it).
2575 */
2576 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA |
2577 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA;
2578
2579 ocelot_rmw_gix(ocelot, ANA_PORT_QOS_CFG_QOS_DSCP_ENA, mask,
2580 ANA_PORT_QOS_CFG, port);
2581
2582 /* Trust this DSCP value and map it to the given QoS class */
2583 val = ANA_DSCP_CFG_DSCP_TRUST_ENA | ANA_DSCP_CFG_QOS_DSCP_VAL(prio);
2584
2585 ocelot_write_rix(ocelot, val, ANA_DSCP_CFG, dscp);
2586
2587 return 0;
2588}
2589EXPORT_SYMBOL_GPL(ocelot_port_add_dscp_prio);
2590
2591int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio)
2592{
2593 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2594 int mask, i;
2595
2596 /* During a "dcb app replace" command, the new app table entry will be
2597 * added first, then the old one will be deleted. But the hardware only
2598 * supports one QoS class per DSCP value (duh), so if we blindly delete
2599 * the app table entry for this DSCP value, we end up deleting the
2600 * entry with the new priority. Avoid that by checking whether user
2601 * space wants to delete the priority which is currently configured, or
2602 * something else which is no longer current.
2603 */
2604 if (ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg) != prio)
2605 return 0;
2606
2607 /* Untrust this DSCP value */
2608 ocelot_write_rix(ocelot, 0, ANA_DSCP_CFG, dscp);
2609
2610 for (i = 0; i < 64; i++) {
2611 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, i);
2612
2613 /* There are still app table entries on the port, so we need to
2614 * keep DSCP enabled, nothing to do.
2615 */
2616 if (dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA)
2617 return 0;
2618 }
2619
2620 /* Disable DSCP QoS classification if there isn't any trusted
2621 * DSCP value left.
2622 */
2623 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA |
2624 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA;
2625
2626 ocelot_rmw_gix(ocelot, 0, mask, ANA_PORT_QOS_CFG, port);
2627
2628 return 0;
2629}
2630EXPORT_SYMBOL_GPL(ocelot_port_del_dscp_prio);
2631
2632struct ocelot_mirror *ocelot_mirror_get(struct ocelot *ocelot, int to,
2633 struct netlink_ext_ack *extack)
2634{
2635 struct ocelot_mirror *m = ocelot->mirror;
2636
2637 if (m) {
2638 if (m->to != to) {
2639 NL_SET_ERR_MSG_MOD(extack,
2640 "Mirroring already configured towards different egress port");
2641 return ERR_PTR(-EBUSY);
2642 }
2643
2644 refcount_inc(&m->refcount);
2645 return m;
2646 }
2647
2648 m = kzalloc(sizeof(*m), GFP_KERNEL);
2649 if (!m)
2650 return ERR_PTR(-ENOMEM);
2651
2652 m->to = to;
2653 refcount_set(&m->refcount, 1);
2654 ocelot->mirror = m;
2655
2656 /* Program the mirror port to hardware */
2657 ocelot_write(ocelot, BIT(to), ANA_MIRRORPORTS);
2658
2659 return m;
2660}
2661
2662void ocelot_mirror_put(struct ocelot *ocelot)
2663{
2664 struct ocelot_mirror *m = ocelot->mirror;
2665
2666 if (!refcount_dec_and_test(&m->refcount))
2667 return;
2668
2669 ocelot_write(ocelot, 0, ANA_MIRRORPORTS);
2670 ocelot->mirror = NULL;
2671 kfree(m);
2672}
2673
2674int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to,
2675 bool ingress, struct netlink_ext_ack *extack)
2676{
2677 struct ocelot_mirror *m = ocelot_mirror_get(ocelot, to, extack);
2678
2679 if (IS_ERR(m))
2680 return PTR_ERR(m);
2681
2682 if (ingress) {
2683 ocelot_rmw_gix(ocelot, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2684 ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2685 ANA_PORT_PORT_CFG, from);
2686 } else {
2687 ocelot_rmw(ocelot, BIT(from), BIT(from),
2688 ANA_EMIRRORPORTS);
2689 }
2690
2691 return 0;
2692}
2693EXPORT_SYMBOL_GPL(ocelot_port_mirror_add);
2694
2695void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress)
2696{
2697 if (ingress) {
2698 ocelot_rmw_gix(ocelot, 0, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2699 ANA_PORT_PORT_CFG, from);
2700 } else {
2701 ocelot_rmw(ocelot, 0, BIT(from), ANA_EMIRRORPORTS);
2702 }
2703
2704 ocelot_mirror_put(ocelot);
2705}
2706EXPORT_SYMBOL_GPL(ocelot_port_mirror_del);
2707
2708static void ocelot_port_reset_mqprio(struct ocelot *ocelot, int port)
2709{
2710 struct net_device *dev = ocelot->ops->port_to_netdev(ocelot, port);
2711
2712 netdev_reset_tc(dev);
2713 ocelot_port_change_fp(ocelot, port, 0);
2714}
2715
2716int ocelot_port_mqprio(struct ocelot *ocelot, int port,
2717 struct tc_mqprio_qopt_offload *mqprio)
2718{
2719 struct net_device *dev = ocelot->ops->port_to_netdev(ocelot, port);
2720 struct netlink_ext_ack *extack = mqprio->extack;
2721 struct tc_mqprio_qopt *qopt = &mqprio->qopt;
2722 int num_tc = qopt->num_tc;
2723 int tc, err;
2724
2725 if (!num_tc) {
2726 ocelot_port_reset_mqprio(ocelot, port);
2727 return 0;
2728 }
2729
2730 err = netdev_set_num_tc(dev, num_tc);
2731 if (err)
2732 return err;
2733
2734 for (tc = 0; tc < num_tc; tc++) {
2735 if (qopt->count[tc] != 1) {
2736 NL_SET_ERR_MSG_MOD(extack,
2737 "Only one TXQ per TC supported");
2738 return -EINVAL;
2739 }
2740
2741 err = netdev_set_tc_queue(dev, tc, 1, qopt->offset[tc]);
2742 if (err)
2743 goto err_reset_tc;
2744 }
2745
2746 err = netif_set_real_num_tx_queues(dev, num_tc);
2747 if (err)
2748 goto err_reset_tc;
2749
2750 ocelot_port_change_fp(ocelot, port, mqprio->preemptible_tcs);
2751
2752 return 0;
2753
2754err_reset_tc:
2755 ocelot_port_reset_mqprio(ocelot, port);
2756 return err;
2757}
2758EXPORT_SYMBOL_GPL(ocelot_port_mqprio);
2759
2760void ocelot_init_port(struct ocelot *ocelot, int port)
2761{
2762 struct ocelot_port *ocelot_port = ocelot->ports[port];
2763
2764 skb_queue_head_init(&ocelot_port->tx_skbs);
2765
2766 /* Basic L2 initialization */
2767
2768 /* Set MAC IFG Gaps
2769 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
2770 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
2771 */
2772 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
2773 DEV_MAC_IFG_CFG);
2774
2775 /* Load seed (0) and set MAC HDX late collision */
2776 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
2777 DEV_MAC_HDX_CFG_SEED_LOAD,
2778 DEV_MAC_HDX_CFG);
2779 mdelay(1);
2780 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
2781 DEV_MAC_HDX_CFG);
2782
2783 /* Set Max Length and maximum tags allowed */
2784 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN);
2785 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
2786 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
2787 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA |
2788 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
2789 DEV_MAC_TAGS_CFG);
2790
2791 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
2792 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
2793 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
2794
2795 /* Enable transmission of pause frames */
2796 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1);
2797
2798 /* Drop frames with multicast source address */
2799 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2800 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2801 ANA_PORT_DROP_CFG, port);
2802
2803 /* Set default VLAN and tag type to 8021Q. */
2804 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
2805 REW_PORT_VLAN_CFG_PORT_TPID_M,
2806 REW_PORT_VLAN_CFG, port);
2807
2808 /* Disable source address learning for standalone mode */
2809 ocelot_port_set_learning(ocelot, port, false);
2810
2811 /* Set the port's initial logical port ID value, enable receiving
2812 * frames on it, and configure the MAC address learning type to
2813 * automatic.
2814 */
2815 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
2816 ANA_PORT_PORT_CFG_RECV_ENA |
2817 ANA_PORT_PORT_CFG_PORTID_VAL(port),
2818 ANA_PORT_PORT_CFG, port);
2819
2820 /* Enable vcap lookups */
2821 ocelot_vcap_enable(ocelot, port);
2822}
2823EXPORT_SYMBOL(ocelot_init_port);
2824
2825/* Configure and enable the CPU port module, which is a set of queues
2826 * accessible through register MMIO, frame DMA or Ethernet (in case
2827 * NPI mode is used).
2828 */
2829static void ocelot_cpu_port_init(struct ocelot *ocelot)
2830{
2831 int cpu = ocelot->num_phys_ports;
2832
2833 /* The unicast destination PGID for the CPU port module is unused */
2834 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
2835 /* Instead set up a multicast destination PGID for traffic copied to
2836 * the CPU. Whitelisted MAC addresses like the port netdevice MAC
2837 * addresses will be copied to the CPU via this PGID.
2838 */
2839 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
2840 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
2841 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
2842 ANA_PORT_PORT_CFG, cpu);
2843
2844 /* Enable CPU port module */
2845 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
2846 /* CPU port Injection/Extraction configuration */
2847 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR,
2848 OCELOT_TAG_PREFIX_NONE);
2849 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR,
2850 OCELOT_TAG_PREFIX_NONE);
2851
2852 /* Configure the CPU port to be VLAN aware */
2853 ocelot_write_gix(ocelot,
2854 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_STANDALONE_PVID) |
2855 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
2856 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
2857 ANA_PORT_VLAN_CFG, cpu);
2858}
2859
2860static void ocelot_detect_features(struct ocelot *ocelot)
2861{
2862 int mmgt, eq_ctrl;
2863
2864 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds
2865 * the number of 240-byte free memory words (aka 4-cell chunks) and not
2866 * 192 bytes as the documentation incorrectly says.
2867 */
2868 mmgt = ocelot_read(ocelot, SYS_MMGT);
2869 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt);
2870
2871 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL);
2872 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl);
2873}
2874
2875static int ocelot_mem_init_status(struct ocelot *ocelot)
2876{
2877 unsigned int val;
2878 int err;
2879
2880 err = regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],
2881 &val);
2882
2883 return err ?: val;
2884}
2885
2886int ocelot_reset(struct ocelot *ocelot)
2887{
2888 int err;
2889 u32 val;
2890
2891 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1);
2892 if (err)
2893 return err;
2894
2895 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
2896 if (err)
2897 return err;
2898
2899 /* MEM_INIT is a self-clearing bit. Wait for it to be cleared (should be
2900 * 100us) before enabling the switch core.
2901 */
2902 err = readx_poll_timeout(ocelot_mem_init_status, ocelot, val, !val,
2903 MEM_INIT_SLEEP_US, MEM_INIT_TIMEOUT_US);
2904 if (err)
2905 return err;
2906
2907 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
2908 if (err)
2909 return err;
2910
2911 return regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
2912}
2913EXPORT_SYMBOL(ocelot_reset);
2914
2915int ocelot_init(struct ocelot *ocelot)
2916{
2917 int i, ret;
2918 u32 port;
2919
2920 if (ocelot->ops->reset) {
2921 ret = ocelot->ops->reset(ocelot);
2922 if (ret) {
2923 dev_err(ocelot->dev, "Switch reset failed\n");
2924 return ret;
2925 }
2926 }
2927
2928 mutex_init(&ocelot->mact_lock);
2929 mutex_init(&ocelot->fwd_domain_lock);
2930 spin_lock_init(&ocelot->ptp_clock_lock);
2931 spin_lock_init(&ocelot->ts_id_lock);
2932
2933 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0);
2934 if (!ocelot->owq)
2935 return -ENOMEM;
2936
2937 ret = ocelot_stats_init(ocelot);
2938 if (ret)
2939 goto err_stats_init;
2940
2941 INIT_LIST_HEAD(&ocelot->multicast);
2942 INIT_LIST_HEAD(&ocelot->pgids);
2943 INIT_LIST_HEAD(&ocelot->vlans);
2944 INIT_LIST_HEAD(&ocelot->lag_fdbs);
2945 ocelot_detect_features(ocelot);
2946 ocelot_mact_init(ocelot);
2947 ocelot_vlan_init(ocelot);
2948 ocelot_vcap_init(ocelot);
2949 ocelot_cpu_port_init(ocelot);
2950
2951 if (ocelot->ops->psfp_init)
2952 ocelot->ops->psfp_init(ocelot);
2953
2954 if (ocelot->mm_supported) {
2955 ret = ocelot_mm_init(ocelot);
2956 if (ret)
2957 goto err_mm_init;
2958 }
2959
2960 for (port = 0; port < ocelot->num_phys_ports; port++) {
2961 /* Clear all counters (5 groups) */
2962 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
2963 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
2964 SYS_STAT_CFG);
2965 }
2966
2967 /* Only use S-Tag */
2968 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
2969
2970 /* Aggregation mode */
2971 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
2972 ANA_AGGR_CFG_AC_DMAC_ENA |
2973 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
2974 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA |
2975 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA |
2976 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA,
2977 ANA_AGGR_CFG);
2978
2979 /* Set MAC age time to default value. The entry is aged after
2980 * 2*AGE_PERIOD
2981 */
2982 ocelot_write(ocelot,
2983 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
2984 ANA_AUTOAGE);
2985
2986 /* Disable learning for frames discarded by VLAN ingress filtering */
2987 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
2988
2989 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
2990 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
2991 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
2992
2993 /* Setup flooding PGIDs */
2994 for (i = 0; i < ocelot->num_flooding_pgids; i++)
2995 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
2996 ANA_FLOODING_FLD_BROADCAST(PGID_BC) |
2997 ANA_FLOODING_FLD_UNICAST(PGID_UC),
2998 ANA_FLOODING, i);
2999 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
3000 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
3001 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
3002 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
3003 ANA_FLOODING_IPMC);
3004
3005 for (port = 0; port < ocelot->num_phys_ports; port++) {
3006 /* Transmit the frame to the local port. */
3007 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
3008 /* Do not forward BPDU frames to the front ports. */
3009 ocelot_write_gix(ocelot,
3010 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
3011 ANA_PORT_CPU_FWD_BPDU_CFG,
3012 port);
3013 /* Ensure bridging is disabled */
3014 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
3015 }
3016
3017 for_each_nonreserved_multicast_dest_pgid(ocelot, i) {
3018 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
3019
3020 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
3021 }
3022
3023 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE);
3024
3025 /* Allow broadcast and unknown L2 multicast to the CPU. */
3026 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3027 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3028 ANA_PGID_PGID, PGID_MC);
3029 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3030 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3031 ANA_PGID_PGID, PGID_BC);
3032 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
3033 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
3034
3035 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
3036 * registers endianness.
3037 */
3038 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
3039 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
3040 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
3041 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
3042 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
3043 ANA_CPUQ_CFG_CPUQ_LRN(2) |
3044 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
3045 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
3046 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
3047 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
3048 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
3049 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
3050 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
3051 for (i = 0; i < 16; i++)
3052 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
3053 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
3054 ANA_CPUQ_8021_CFG, i);
3055
3056 return 0;
3057
3058err_mm_init:
3059 ocelot_stats_deinit(ocelot);
3060err_stats_init:
3061 destroy_workqueue(ocelot->owq);
3062 return ret;
3063}
3064EXPORT_SYMBOL(ocelot_init);
3065
3066void ocelot_deinit(struct ocelot *ocelot)
3067{
3068 ocelot_stats_deinit(ocelot);
3069 destroy_workqueue(ocelot->owq);
3070}
3071EXPORT_SYMBOL(ocelot_deinit);
3072
3073void ocelot_deinit_port(struct ocelot *ocelot, int port)
3074{
3075 struct ocelot_port *ocelot_port = ocelot->ports[port];
3076
3077 skb_queue_purge(&ocelot_port->tx_skbs);
3078}
3079EXPORT_SYMBOL(ocelot_deinit_port);
3080
3081MODULE_LICENSE("Dual MIT/GPL");
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7#include <linux/dsa/ocelot.h>
8#include <linux/if_bridge.h>
9#include <soc/mscc/ocelot_vcap.h>
10#include "ocelot.h"
11#include "ocelot_vcap.h"
12
13#define TABLE_UPDATE_SLEEP_US 10
14#define TABLE_UPDATE_TIMEOUT_US 100000
15#define OCELOT_RSV_VLAN_RANGE_START 4000
16
17struct ocelot_mact_entry {
18 u8 mac[ETH_ALEN];
19 u16 vid;
20 enum macaccess_entry_type type;
21};
22
23/* Caller must hold &ocelot->mact_lock */
24static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
25{
26 return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
27}
28
29/* Caller must hold &ocelot->mact_lock */
30static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
31{
32 u32 val;
33
34 return readx_poll_timeout(ocelot_mact_read_macaccess,
35 ocelot, val,
36 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) ==
37 MACACCESS_CMD_IDLE,
38 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
39}
40
41/* Caller must hold &ocelot->mact_lock */
42static void ocelot_mact_select(struct ocelot *ocelot,
43 const unsigned char mac[ETH_ALEN],
44 unsigned int vid)
45{
46 u32 macl = 0, mach = 0;
47
48 /* Set the MAC address to handle and the vlan associated in a format
49 * understood by the hardware.
50 */
51 mach |= vid << 16;
52 mach |= mac[0] << 8;
53 mach |= mac[1] << 0;
54 macl |= mac[2] << 24;
55 macl |= mac[3] << 16;
56 macl |= mac[4] << 8;
57 macl |= mac[5] << 0;
58
59 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
60 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
61
62}
63
64static int __ocelot_mact_learn(struct ocelot *ocelot, int port,
65 const unsigned char mac[ETH_ALEN],
66 unsigned int vid, enum macaccess_entry_type type)
67{
68 u32 cmd = ANA_TABLES_MACACCESS_VALID |
69 ANA_TABLES_MACACCESS_DEST_IDX(port) |
70 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
71 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN);
72 unsigned int mc_ports;
73 int err;
74
75 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */
76 if (type == ENTRYTYPE_MACv4)
77 mc_ports = (mac[1] << 8) | mac[2];
78 else if (type == ENTRYTYPE_MACv6)
79 mc_ports = (mac[0] << 8) | mac[1];
80 else
81 mc_ports = 0;
82
83 if (mc_ports & BIT(ocelot->num_phys_ports))
84 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY;
85
86 ocelot_mact_select(ocelot, mac, vid);
87
88 /* Issue a write command */
89 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS);
90
91 err = ocelot_mact_wait_for_completion(ocelot);
92
93 return err;
94}
95
96int ocelot_mact_learn(struct ocelot *ocelot, int port,
97 const unsigned char mac[ETH_ALEN],
98 unsigned int vid, enum macaccess_entry_type type)
99{
100 int ret;
101
102 mutex_lock(&ocelot->mact_lock);
103 ret = __ocelot_mact_learn(ocelot, port, mac, vid, type);
104 mutex_unlock(&ocelot->mact_lock);
105
106 return ret;
107}
108EXPORT_SYMBOL(ocelot_mact_learn);
109
110int ocelot_mact_forget(struct ocelot *ocelot,
111 const unsigned char mac[ETH_ALEN], unsigned int vid)
112{
113 int err;
114
115 mutex_lock(&ocelot->mact_lock);
116
117 ocelot_mact_select(ocelot, mac, vid);
118
119 /* Issue a forget command */
120 ocelot_write(ocelot,
121 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
122 ANA_TABLES_MACACCESS);
123
124 err = ocelot_mact_wait_for_completion(ocelot);
125
126 mutex_unlock(&ocelot->mact_lock);
127
128 return err;
129}
130EXPORT_SYMBOL(ocelot_mact_forget);
131
132int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx,
133 const unsigned char mac[ETH_ALEN],
134 unsigned int vid, enum macaccess_entry_type *type)
135{
136 int val;
137
138 mutex_lock(&ocelot->mact_lock);
139
140 ocelot_mact_select(ocelot, mac, vid);
141
142 /* Issue a read command with MACACCESS_VALID=1. */
143 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID |
144 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
145 ANA_TABLES_MACACCESS);
146
147 if (ocelot_mact_wait_for_completion(ocelot)) {
148 mutex_unlock(&ocelot->mact_lock);
149 return -ETIMEDOUT;
150 }
151
152 /* Read back the entry flags */
153 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
154
155 mutex_unlock(&ocelot->mact_lock);
156
157 if (!(val & ANA_TABLES_MACACCESS_VALID))
158 return -ENOENT;
159
160 *dst_idx = ANA_TABLES_MACACCESS_DEST_IDX_X(val);
161 *type = ANA_TABLES_MACACCESS_ENTRYTYPE_X(val);
162
163 return 0;
164}
165EXPORT_SYMBOL(ocelot_mact_lookup);
166
167int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx,
168 const unsigned char mac[ETH_ALEN],
169 unsigned int vid,
170 enum macaccess_entry_type type,
171 int sfid, int ssid)
172{
173 int ret;
174
175 mutex_lock(&ocelot->mact_lock);
176
177 ocelot_write(ocelot,
178 (sfid < 0 ? 0 : ANA_TABLES_STREAMDATA_SFID_VALID) |
179 ANA_TABLES_STREAMDATA_SFID(sfid) |
180 (ssid < 0 ? 0 : ANA_TABLES_STREAMDATA_SSID_VALID) |
181 ANA_TABLES_STREAMDATA_SSID(ssid),
182 ANA_TABLES_STREAMDATA);
183
184 ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type);
185
186 mutex_unlock(&ocelot->mact_lock);
187
188 return ret;
189}
190EXPORT_SYMBOL(ocelot_mact_learn_streamdata);
191
192static void ocelot_mact_init(struct ocelot *ocelot)
193{
194 /* Configure the learning mode entries attributes:
195 * - Do not copy the frame to the CPU extraction queues.
196 * - Use the vlan and mac_cpoy for dmac lookup.
197 */
198 ocelot_rmw(ocelot, 0,
199 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
200 | ANA_AGENCTRL_LEARN_FWD_KILL
201 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
202 ANA_AGENCTRL);
203
204 /* Clear the MAC table. We are not concurrent with anyone, so
205 * holding &ocelot->mact_lock is pointless.
206 */
207 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
208}
209
210static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
211{
212 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
213 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
214 ANA_PORT_VCAP_S2_CFG, port);
215
216 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA,
217 ANA_PORT_VCAP_CFG, port);
218
219 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN,
220 REW_PORT_CFG_ES0_EN,
221 REW_PORT_CFG, port);
222}
223
224static int ocelot_single_vlan_aware_bridge(struct ocelot *ocelot,
225 struct netlink_ext_ack *extack)
226{
227 struct net_device *bridge = NULL;
228 int port;
229
230 for (port = 0; port < ocelot->num_phys_ports; port++) {
231 struct ocelot_port *ocelot_port = ocelot->ports[port];
232
233 if (!ocelot_port || !ocelot_port->bridge ||
234 !br_vlan_enabled(ocelot_port->bridge))
235 continue;
236
237 if (!bridge) {
238 bridge = ocelot_port->bridge;
239 continue;
240 }
241
242 if (bridge == ocelot_port->bridge)
243 continue;
244
245 NL_SET_ERR_MSG_MOD(extack,
246 "Only one VLAN-aware bridge is supported");
247 return -EBUSY;
248 }
249
250 return 0;
251}
252
253static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
254{
255 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
256}
257
258static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
259{
260 u32 val;
261
262 return readx_poll_timeout(ocelot_vlant_read_vlanaccess,
263 ocelot,
264 val,
265 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) ==
266 ANA_TABLES_VLANACCESS_CMD_IDLE,
267 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
268}
269
270static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
271{
272 /* Select the VID to configure */
273 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
274 ANA_TABLES_VLANTIDX);
275 /* Set the vlan port members mask and issue a write command */
276 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
277 ANA_TABLES_VLANACCESS_CMD_WRITE,
278 ANA_TABLES_VLANACCESS);
279
280 return ocelot_vlant_wait_for_completion(ocelot);
281}
282
283static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port)
284{
285 struct ocelot_bridge_vlan *vlan;
286 int num_untagged = 0;
287
288 list_for_each_entry(vlan, &ocelot->vlans, list) {
289 if (!(vlan->portmask & BIT(port)))
290 continue;
291
292 /* Ignore the VLAN added by ocelot_add_vlan_unaware_pvid(),
293 * because this is never active in hardware at the same time as
294 * the bridge VLANs, which only matter in VLAN-aware mode.
295 */
296 if (vlan->vid >= OCELOT_RSV_VLAN_RANGE_START)
297 continue;
298
299 if (vlan->untagged & BIT(port))
300 num_untagged++;
301 }
302
303 return num_untagged;
304}
305
306static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port)
307{
308 struct ocelot_bridge_vlan *vlan;
309 int num_tagged = 0;
310
311 list_for_each_entry(vlan, &ocelot->vlans, list) {
312 if (!(vlan->portmask & BIT(port)))
313 continue;
314
315 if (!(vlan->untagged & BIT(port)))
316 num_tagged++;
317 }
318
319 return num_tagged;
320}
321
322/* We use native VLAN when we have to mix egress-tagged VLANs with exactly
323 * _one_ egress-untagged VLAN (_the_ native VLAN)
324 */
325static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port)
326{
327 return ocelot_port_num_tagged_vlans(ocelot, port) &&
328 ocelot_port_num_untagged_vlans(ocelot, port) == 1;
329}
330
331static struct ocelot_bridge_vlan *
332ocelot_port_find_native_vlan(struct ocelot *ocelot, int port)
333{
334 struct ocelot_bridge_vlan *vlan;
335
336 list_for_each_entry(vlan, &ocelot->vlans, list)
337 if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port))
338 return vlan;
339
340 return NULL;
341}
342
343/* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable,
344 * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness
345 * state of the port.
346 */
347static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port)
348{
349 struct ocelot_port *ocelot_port = ocelot->ports[port];
350 enum ocelot_port_tag_config tag_cfg;
351 bool uses_native_vlan = false;
352
353 if (ocelot_port->vlan_aware) {
354 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port);
355
356 if (uses_native_vlan)
357 tag_cfg = OCELOT_PORT_TAG_NATIVE;
358 else if (ocelot_port_num_untagged_vlans(ocelot, port))
359 tag_cfg = OCELOT_PORT_TAG_DISABLED;
360 else
361 tag_cfg = OCELOT_PORT_TAG_TRUNK;
362 } else {
363 tag_cfg = OCELOT_PORT_TAG_DISABLED;
364 }
365
366 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg),
367 REW_TAG_CFG_TAG_CFG_M,
368 REW_TAG_CFG, port);
369
370 if (uses_native_vlan) {
371 struct ocelot_bridge_vlan *native_vlan;
372
373 /* Not having a native VLAN is impossible, because
374 * ocelot_port_num_untagged_vlans has returned 1.
375 * So there is no use in checking for NULL here.
376 */
377 native_vlan = ocelot_port_find_native_vlan(ocelot, port);
378
379 ocelot_rmw_gix(ocelot,
380 REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid),
381 REW_PORT_VLAN_CFG_PORT_VID_M,
382 REW_PORT_VLAN_CFG, port);
383 }
384}
385
386int ocelot_bridge_num_find(struct ocelot *ocelot,
387 const struct net_device *bridge)
388{
389 int port;
390
391 for (port = 0; port < ocelot->num_phys_ports; port++) {
392 struct ocelot_port *ocelot_port = ocelot->ports[port];
393
394 if (ocelot_port && ocelot_port->bridge == bridge)
395 return ocelot_port->bridge_num;
396 }
397
398 return -1;
399}
400EXPORT_SYMBOL_GPL(ocelot_bridge_num_find);
401
402static u16 ocelot_vlan_unaware_pvid(struct ocelot *ocelot,
403 const struct net_device *bridge)
404{
405 int bridge_num;
406
407 /* Standalone ports use VID 0 */
408 if (!bridge)
409 return 0;
410
411 bridge_num = ocelot_bridge_num_find(ocelot, bridge);
412 if (WARN_ON(bridge_num < 0))
413 return 0;
414
415 /* VLAN-unaware bridges use a reserved VID going from 4095 downwards */
416 return VLAN_N_VID - bridge_num - 1;
417}
418
419/* Default vlan to clasify for untagged frames (may be zero) */
420static void ocelot_port_set_pvid(struct ocelot *ocelot, int port,
421 const struct ocelot_bridge_vlan *pvid_vlan)
422{
423 struct ocelot_port *ocelot_port = ocelot->ports[port];
424 u16 pvid = ocelot_vlan_unaware_pvid(ocelot, ocelot_port->bridge);
425 u32 val = 0;
426
427 ocelot_port->pvid_vlan = pvid_vlan;
428
429 if (ocelot_port->vlan_aware && pvid_vlan)
430 pvid = pvid_vlan->vid;
431
432 ocelot_rmw_gix(ocelot,
433 ANA_PORT_VLAN_CFG_VLAN_VID(pvid),
434 ANA_PORT_VLAN_CFG_VLAN_VID_M,
435 ANA_PORT_VLAN_CFG, port);
436
437 /* If there's no pvid, we should drop not only untagged traffic (which
438 * happens automatically), but also 802.1p traffic which gets
439 * classified to VLAN 0, but that is always in our RX filter, so it
440 * would get accepted were it not for this setting.
441 */
442 if (!pvid_vlan && ocelot_port->vlan_aware)
443 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
444 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
445
446 ocelot_rmw_gix(ocelot, val,
447 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
448 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA,
449 ANA_PORT_DROP_CFG, port);
450}
451
452static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot,
453 u16 vid)
454{
455 struct ocelot_bridge_vlan *vlan;
456
457 list_for_each_entry(vlan, &ocelot->vlans, list)
458 if (vlan->vid == vid)
459 return vlan;
460
461 return NULL;
462}
463
464static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid,
465 bool untagged)
466{
467 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
468 unsigned long portmask;
469 int err;
470
471 if (vlan) {
472 portmask = vlan->portmask | BIT(port);
473
474 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
475 if (err)
476 return err;
477
478 vlan->portmask = portmask;
479 /* Bridge VLANs can be overwritten with a different
480 * egress-tagging setting, so make sure to override an untagged
481 * with a tagged VID if that's going on.
482 */
483 if (untagged)
484 vlan->untagged |= BIT(port);
485 else
486 vlan->untagged &= ~BIT(port);
487
488 return 0;
489 }
490
491 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
492 if (!vlan)
493 return -ENOMEM;
494
495 portmask = BIT(port);
496
497 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
498 if (err) {
499 kfree(vlan);
500 return err;
501 }
502
503 vlan->vid = vid;
504 vlan->portmask = portmask;
505 if (untagged)
506 vlan->untagged = BIT(port);
507 INIT_LIST_HEAD(&vlan->list);
508 list_add_tail(&vlan->list, &ocelot->vlans);
509
510 return 0;
511}
512
513static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid)
514{
515 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
516 unsigned long portmask;
517 int err;
518
519 if (!vlan)
520 return 0;
521
522 portmask = vlan->portmask & ~BIT(port);
523
524 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
525 if (err)
526 return err;
527
528 vlan->portmask = portmask;
529 if (vlan->portmask)
530 return 0;
531
532 list_del(&vlan->list);
533 kfree(vlan);
534
535 return 0;
536}
537
538static int ocelot_add_vlan_unaware_pvid(struct ocelot *ocelot, int port,
539 const struct net_device *bridge)
540{
541 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
542
543 return ocelot_vlan_member_add(ocelot, port, vid, true);
544}
545
546static int ocelot_del_vlan_unaware_pvid(struct ocelot *ocelot, int port,
547 const struct net_device *bridge)
548{
549 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
550
551 return ocelot_vlan_member_del(ocelot, port, vid);
552}
553
554int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
555 bool vlan_aware, struct netlink_ext_ack *extack)
556{
557 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1];
558 struct ocelot_port *ocelot_port = ocelot->ports[port];
559 struct ocelot_vcap_filter *filter;
560 int err = 0;
561 u32 val;
562
563 list_for_each_entry(filter, &block->rules, list) {
564 if (filter->ingress_port_mask & BIT(port) &&
565 filter->action.vid_replace_ena) {
566 NL_SET_ERR_MSG_MOD(extack,
567 "Cannot change VLAN state with vlan modify rules active");
568 return -EBUSY;
569 }
570 }
571
572 err = ocelot_single_vlan_aware_bridge(ocelot, extack);
573 if (err)
574 return err;
575
576 if (vlan_aware)
577 err = ocelot_del_vlan_unaware_pvid(ocelot, port,
578 ocelot_port->bridge);
579 else if (ocelot_port->bridge)
580 err = ocelot_add_vlan_unaware_pvid(ocelot, port,
581 ocelot_port->bridge);
582 if (err)
583 return err;
584
585 ocelot_port->vlan_aware = vlan_aware;
586
587 if (vlan_aware)
588 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
589 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
590 else
591 val = 0;
592 ocelot_rmw_gix(ocelot, val,
593 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
594 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
595 ANA_PORT_VLAN_CFG, port);
596
597 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan);
598 ocelot_port_manage_port_tag(ocelot, port);
599
600 return 0;
601}
602EXPORT_SYMBOL(ocelot_port_vlan_filtering);
603
604int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
605 bool untagged, struct netlink_ext_ack *extack)
606{
607 if (untagged) {
608 /* We are adding an egress-tagged VLAN */
609 if (ocelot_port_uses_native_vlan(ocelot, port)) {
610 NL_SET_ERR_MSG_MOD(extack,
611 "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN");
612 return -EBUSY;
613 }
614 } else {
615 /* We are adding an egress-tagged VLAN */
616 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) {
617 NL_SET_ERR_MSG_MOD(extack,
618 "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs");
619 return -EBUSY;
620 }
621 }
622
623 if (vid > OCELOT_RSV_VLAN_RANGE_START) {
624 NL_SET_ERR_MSG_MOD(extack,
625 "VLAN range 4000-4095 reserved for VLAN-unaware bridging");
626 return -EBUSY;
627 }
628
629 return 0;
630}
631EXPORT_SYMBOL(ocelot_vlan_prepare);
632
633int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
634 bool untagged)
635{
636 int err;
637
638 /* Ignore VID 0 added to our RX filter by the 8021q module, since
639 * that collides with OCELOT_STANDALONE_PVID and changes it from
640 * egress-untagged to egress-tagged.
641 */
642 if (!vid)
643 return 0;
644
645 err = ocelot_vlan_member_add(ocelot, port, vid, untagged);
646 if (err)
647 return err;
648
649 /* Default ingress vlan classification */
650 if (pvid)
651 ocelot_port_set_pvid(ocelot, port,
652 ocelot_bridge_vlan_find(ocelot, vid));
653
654 /* Untagged egress vlan clasification */
655 ocelot_port_manage_port_tag(ocelot, port);
656
657 return 0;
658}
659EXPORT_SYMBOL(ocelot_vlan_add);
660
661int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
662{
663 struct ocelot_port *ocelot_port = ocelot->ports[port];
664 bool del_pvid = false;
665 int err;
666
667 if (!vid)
668 return 0;
669
670 if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid)
671 del_pvid = true;
672
673 err = ocelot_vlan_member_del(ocelot, port, vid);
674 if (err)
675 return err;
676
677 /* Ingress */
678 if (del_pvid)
679 ocelot_port_set_pvid(ocelot, port, NULL);
680
681 /* Egress */
682 ocelot_port_manage_port_tag(ocelot, port);
683
684 return 0;
685}
686EXPORT_SYMBOL(ocelot_vlan_del);
687
688static void ocelot_vlan_init(struct ocelot *ocelot)
689{
690 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0);
691 u16 port, vid;
692
693 /* Clear VLAN table, by default all ports are members of all VLANs */
694 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
695 ANA_TABLES_VLANACCESS);
696 ocelot_vlant_wait_for_completion(ocelot);
697
698 /* Configure the port VLAN memberships */
699 for (vid = 1; vid < VLAN_N_VID; vid++)
700 ocelot_vlant_set_mask(ocelot, vid, 0);
701
702 /* We need VID 0 to get traffic on standalone ports.
703 * It is added automatically if the 8021q module is loaded, but we
704 * can't rely on that since it might not be.
705 */
706 ocelot_vlant_set_mask(ocelot, OCELOT_STANDALONE_PVID, all_ports);
707
708 /* Set vlan ingress filter mask to all ports but the CPU port by
709 * default.
710 */
711 ocelot_write(ocelot, all_ports, ANA_VLANMASK);
712
713 for (port = 0; port < ocelot->num_phys_ports; port++) {
714 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
715 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
716 }
717}
718
719static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port)
720{
721 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port);
722}
723
724static int ocelot_port_flush(struct ocelot *ocelot, int port)
725{
726 unsigned int pause_ena;
727 int err, val;
728
729 /* Disable dequeuing from the egress queues */
730 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS,
731 QSYS_PORT_MODE_DEQUEUE_DIS,
732 QSYS_PORT_MODE, port);
733
734 /* Disable flow control */
735 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena);
736 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0);
737
738 /* Disable priority flow control */
739 ocelot_fields_write(ocelot, port,
740 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0);
741
742 /* Wait at least the time it takes to receive a frame of maximum length
743 * at the port.
744 * Worst-case delays for 10 kilobyte jumbo frames are:
745 * 8 ms on a 10M port
746 * 800 μs on a 100M port
747 * 80 μs on a 1G port
748 * 32 μs on a 2.5G port
749 */
750 usleep_range(8000, 10000);
751
752 /* Disable half duplex backpressure. */
753 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE,
754 SYS_FRONT_PORT_MODE, port);
755
756 /* Flush the queues associated with the port. */
757 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA,
758 REW_PORT_CFG, port);
759
760 /* Enable dequeuing from the egress queues. */
761 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE,
762 port);
763
764 /* Wait until flushing is complete. */
765 err = read_poll_timeout(ocelot_read_eq_avail, val, !val,
766 100, 2000000, false, ocelot, port);
767
768 /* Clear flushing again. */
769 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port);
770
771 /* Re-enable flow control */
772 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena);
773
774 return err;
775}
776
777void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port,
778 unsigned int link_an_mode,
779 phy_interface_t interface,
780 unsigned long quirks)
781{
782 struct ocelot_port *ocelot_port = ocelot->ports[port];
783 int err;
784
785 ocelot_port->speed = SPEED_UNKNOWN;
786
787 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA,
788 DEV_MAC_ENA_CFG);
789
790 if (ocelot->ops->cut_through_fwd) {
791 mutex_lock(&ocelot->fwd_domain_lock);
792 ocelot->ops->cut_through_fwd(ocelot);
793 mutex_unlock(&ocelot->fwd_domain_lock);
794 }
795
796 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);
797
798 err = ocelot_port_flush(ocelot, port);
799 if (err)
800 dev_err(ocelot->dev, "failed to flush port %d: %d\n",
801 port, err);
802
803 /* Put the port in reset. */
804 if (interface != PHY_INTERFACE_MODE_QSGMII ||
805 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP))
806 ocelot_port_rmwl(ocelot_port,
807 DEV_CLOCK_CFG_MAC_TX_RST |
808 DEV_CLOCK_CFG_MAC_RX_RST,
809 DEV_CLOCK_CFG_MAC_TX_RST |
810 DEV_CLOCK_CFG_MAC_RX_RST,
811 DEV_CLOCK_CFG);
812}
813EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down);
814
815void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port,
816 struct phy_device *phydev,
817 unsigned int link_an_mode,
818 phy_interface_t interface,
819 int speed, int duplex,
820 bool tx_pause, bool rx_pause,
821 unsigned long quirks)
822{
823 struct ocelot_port *ocelot_port = ocelot->ports[port];
824 int mac_speed, mode = 0;
825 u32 mac_fc_cfg;
826
827 ocelot_port->speed = speed;
828
829 /* The MAC might be integrated in systems where the MAC speed is fixed
830 * and it's the PCS who is performing the rate adaptation, so we have
831 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG
832 * (which is also its default value).
833 */
834 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) ||
835 speed == SPEED_1000) {
836 mac_speed = OCELOT_SPEED_1000;
837 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
838 } else if (speed == SPEED_2500) {
839 mac_speed = OCELOT_SPEED_2500;
840 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
841 } else if (speed == SPEED_100) {
842 mac_speed = OCELOT_SPEED_100;
843 } else {
844 mac_speed = OCELOT_SPEED_10;
845 }
846
847 if (duplex == DUPLEX_FULL)
848 mode |= DEV_MAC_MODE_CFG_FDX_ENA;
849
850 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG);
851
852 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and
853 * PORT_RST bits in DEV_CLOCK_CFG.
854 */
855 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed),
856 DEV_CLOCK_CFG);
857
858 switch (speed) {
859 case SPEED_10:
860 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10);
861 break;
862 case SPEED_100:
863 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100);
864 break;
865 case SPEED_1000:
866 case SPEED_2500:
867 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000);
868 break;
869 default:
870 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n",
871 port, speed);
872 return;
873 }
874
875 if (rx_pause)
876 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA;
877
878 if (tx_pause)
879 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA |
880 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
881 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
882 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA;
883
884 /* Flow control. Link speed is only used here to evaluate the time
885 * specification in incoming pause frames.
886 */
887 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port);
888
889 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
890
891 /* Don't attempt to send PAUSE frames on the NPI port, it's broken */
892 if (port != ocelot->npi)
893 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA,
894 tx_pause);
895
896 /* Undo the effects of ocelot_phylink_mac_link_down:
897 * enable MAC module
898 */
899 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
900 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
901
902 /* If the port supports cut-through forwarding, update the masks before
903 * enabling forwarding on the port.
904 */
905 if (ocelot->ops->cut_through_fwd) {
906 mutex_lock(&ocelot->fwd_domain_lock);
907 ocelot->ops->cut_through_fwd(ocelot);
908 mutex_unlock(&ocelot->fwd_domain_lock);
909 }
910
911 /* Core: Enable port for frame transfer */
912 ocelot_fields_write(ocelot, port,
913 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
914}
915EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up);
916
917static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
918 u32 *rval)
919{
920 u32 bytes_valid, val;
921
922 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
923 if (val == XTR_NOT_READY) {
924 if (ifh)
925 return -EIO;
926
927 do {
928 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
929 } while (val == XTR_NOT_READY);
930 }
931
932 switch (val) {
933 case XTR_ABORT:
934 return -EIO;
935 case XTR_EOF_0:
936 case XTR_EOF_1:
937 case XTR_EOF_2:
938 case XTR_EOF_3:
939 case XTR_PRUNED:
940 bytes_valid = XTR_VALID_BYTES(val);
941 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
942 if (val == XTR_ESCAPE)
943 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
944 else
945 *rval = val;
946
947 return bytes_valid;
948 case XTR_ESCAPE:
949 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
950
951 return 4;
952 default:
953 *rval = val;
954
955 return 4;
956 }
957}
958
959static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh)
960{
961 int i, err = 0;
962
963 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) {
964 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]);
965 if (err != 4)
966 return (err < 0) ? err : -EIO;
967 }
968
969 return 0;
970}
971
972void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb,
973 u64 timestamp)
974{
975 struct skb_shared_hwtstamps *shhwtstamps;
976 u64 tod_in_ns, full_ts_in_ns;
977 struct timespec64 ts;
978
979 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
980
981 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec);
982 if ((tod_in_ns & 0xffffffff) < timestamp)
983 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) |
984 timestamp;
985 else
986 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) |
987 timestamp;
988
989 shhwtstamps = skb_hwtstamps(skb);
990 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
991 shhwtstamps->hwtstamp = full_ts_in_ns;
992}
993EXPORT_SYMBOL(ocelot_ptp_rx_timestamp);
994
995int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb)
996{
997 u64 timestamp, src_port, len;
998 u32 xfh[OCELOT_TAG_LEN / 4];
999 struct net_device *dev;
1000 struct sk_buff *skb;
1001 int sz, buf_len;
1002 u32 val, *buf;
1003 int err;
1004
1005 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh);
1006 if (err)
1007 return err;
1008
1009 ocelot_xfh_get_src_port(xfh, &src_port);
1010 ocelot_xfh_get_len(xfh, &len);
1011 ocelot_xfh_get_rew_val(xfh, ×tamp);
1012
1013 if (WARN_ON(src_port >= ocelot->num_phys_ports))
1014 return -EINVAL;
1015
1016 dev = ocelot->ops->port_to_netdev(ocelot, src_port);
1017 if (!dev)
1018 return -EINVAL;
1019
1020 skb = netdev_alloc_skb(dev, len);
1021 if (unlikely(!skb)) {
1022 netdev_err(dev, "Unable to allocate sk_buff\n");
1023 return -ENOMEM;
1024 }
1025
1026 buf_len = len - ETH_FCS_LEN;
1027 buf = (u32 *)skb_put(skb, buf_len);
1028
1029 len = 0;
1030 do {
1031 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1032 if (sz < 0) {
1033 err = sz;
1034 goto out_free_skb;
1035 }
1036 *buf++ = val;
1037 len += sz;
1038 } while (len < buf_len);
1039
1040 /* Read the FCS */
1041 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1042 if (sz < 0) {
1043 err = sz;
1044 goto out_free_skb;
1045 }
1046
1047 /* Update the statistics if part of the FCS was read before */
1048 len -= ETH_FCS_LEN - sz;
1049
1050 if (unlikely(dev->features & NETIF_F_RXFCS)) {
1051 buf = (u32 *)skb_put(skb, ETH_FCS_LEN);
1052 *buf = val;
1053 }
1054
1055 if (ocelot->ptp)
1056 ocelot_ptp_rx_timestamp(ocelot, skb, timestamp);
1057
1058 /* Everything we see on an interface that is in the HW bridge
1059 * has already been forwarded.
1060 */
1061 if (ocelot->ports[src_port]->bridge)
1062 skb->offload_fwd_mark = 1;
1063
1064 skb->protocol = eth_type_trans(skb, dev);
1065
1066 *nskb = skb;
1067
1068 return 0;
1069
1070out_free_skb:
1071 kfree_skb(skb);
1072 return err;
1073}
1074EXPORT_SYMBOL(ocelot_xtr_poll_frame);
1075
1076bool ocelot_can_inject(struct ocelot *ocelot, int grp)
1077{
1078 u32 val = ocelot_read(ocelot, QS_INJ_STATUS);
1079
1080 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))))
1081 return false;
1082 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))
1083 return false;
1084
1085 return true;
1086}
1087EXPORT_SYMBOL(ocelot_can_inject);
1088
1089void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag)
1090{
1091 ocelot_ifh_set_bypass(ifh, 1);
1092 ocelot_ifh_set_dest(ifh, BIT_ULL(port));
1093 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C);
1094 if (vlan_tag)
1095 ocelot_ifh_set_vlan_tci(ifh, vlan_tag);
1096 if (rew_op)
1097 ocelot_ifh_set_rew_op(ifh, rew_op);
1098}
1099EXPORT_SYMBOL(ocelot_ifh_port_set);
1100
1101void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
1102 u32 rew_op, struct sk_buff *skb)
1103{
1104 u32 ifh[OCELOT_TAG_LEN / 4] = {0};
1105 unsigned int i, count, last;
1106
1107 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1108 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
1109
1110 ocelot_ifh_port_set(ifh, port, rew_op, skb_vlan_tag_get(skb));
1111
1112 for (i = 0; i < OCELOT_TAG_LEN / 4; i++)
1113 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp);
1114
1115 count = DIV_ROUND_UP(skb->len, 4);
1116 last = skb->len % 4;
1117 for (i = 0; i < count; i++)
1118 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
1119
1120 /* Add padding */
1121 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
1122 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1123 i++;
1124 }
1125
1126 /* Indicate EOF and valid bytes in last word */
1127 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1128 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
1129 QS_INJ_CTRL_EOF,
1130 QS_INJ_CTRL, grp);
1131
1132 /* Add dummy CRC */
1133 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1134 skb_tx_timestamp(skb);
1135
1136 skb->dev->stats.tx_packets++;
1137 skb->dev->stats.tx_bytes += skb->len;
1138}
1139EXPORT_SYMBOL(ocelot_port_inject_frame);
1140
1141void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp)
1142{
1143 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
1144 ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1145}
1146EXPORT_SYMBOL(ocelot_drain_cpu_queue);
1147
1148int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr,
1149 u16 vid, const struct net_device *bridge)
1150{
1151 if (!vid)
1152 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1153
1154 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED);
1155}
1156EXPORT_SYMBOL(ocelot_fdb_add);
1157
1158int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr,
1159 u16 vid, const struct net_device *bridge)
1160{
1161 if (!vid)
1162 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1163
1164 return ocelot_mact_forget(ocelot, addr, vid);
1165}
1166EXPORT_SYMBOL(ocelot_fdb_del);
1167
1168/* Caller must hold &ocelot->mact_lock */
1169static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col,
1170 struct ocelot_mact_entry *entry)
1171{
1172 u32 val, dst, macl, mach;
1173 char mac[ETH_ALEN];
1174
1175 /* Set row and column to read from */
1176 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
1177 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
1178
1179 /* Issue a read command */
1180 ocelot_write(ocelot,
1181 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
1182 ANA_TABLES_MACACCESS);
1183
1184 if (ocelot_mact_wait_for_completion(ocelot))
1185 return -ETIMEDOUT;
1186
1187 /* Read the entry flags */
1188 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
1189 if (!(val & ANA_TABLES_MACACCESS_VALID))
1190 return -EINVAL;
1191
1192 /* If the entry read has another port configured as its destination,
1193 * do not report it.
1194 */
1195 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
1196 if (dst != port)
1197 return -EINVAL;
1198
1199 /* Get the entry's MAC address and VLAN id */
1200 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
1201 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
1202
1203 mac[0] = (mach >> 8) & 0xff;
1204 mac[1] = (mach >> 0) & 0xff;
1205 mac[2] = (macl >> 24) & 0xff;
1206 mac[3] = (macl >> 16) & 0xff;
1207 mac[4] = (macl >> 8) & 0xff;
1208 mac[5] = (macl >> 0) & 0xff;
1209
1210 entry->vid = (mach >> 16) & 0xfff;
1211 ether_addr_copy(entry->mac, mac);
1212
1213 return 0;
1214}
1215
1216int ocelot_mact_flush(struct ocelot *ocelot, int port)
1217{
1218 int err;
1219
1220 mutex_lock(&ocelot->mact_lock);
1221
1222 /* Program ageing filter for a single port */
1223 ocelot_write(ocelot, ANA_ANAGEFIL_PID_EN | ANA_ANAGEFIL_PID_VAL(port),
1224 ANA_ANAGEFIL);
1225
1226 /* Flushing dynamic FDB entries requires two successive age scans */
1227 ocelot_write(ocelot,
1228 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE),
1229 ANA_TABLES_MACACCESS);
1230
1231 err = ocelot_mact_wait_for_completion(ocelot);
1232 if (err) {
1233 mutex_unlock(&ocelot->mact_lock);
1234 return err;
1235 }
1236
1237 /* And second... */
1238 ocelot_write(ocelot,
1239 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE),
1240 ANA_TABLES_MACACCESS);
1241
1242 err = ocelot_mact_wait_for_completion(ocelot);
1243
1244 /* Restore ageing filter */
1245 ocelot_write(ocelot, 0, ANA_ANAGEFIL);
1246
1247 mutex_unlock(&ocelot->mact_lock);
1248
1249 return err;
1250}
1251EXPORT_SYMBOL_GPL(ocelot_mact_flush);
1252
1253int ocelot_fdb_dump(struct ocelot *ocelot, int port,
1254 dsa_fdb_dump_cb_t *cb, void *data)
1255{
1256 int err = 0;
1257 int i, j;
1258
1259 /* We could take the lock just around ocelot_mact_read, but doing so
1260 * thousands of times in a row seems rather pointless and inefficient.
1261 */
1262 mutex_lock(&ocelot->mact_lock);
1263
1264 /* Loop through all the mac tables entries. */
1265 for (i = 0; i < ocelot->num_mact_rows; i++) {
1266 for (j = 0; j < 4; j++) {
1267 struct ocelot_mact_entry entry;
1268 bool is_static;
1269
1270 err = ocelot_mact_read(ocelot, port, i, j, &entry);
1271 /* If the entry is invalid (wrong port, invalid...),
1272 * skip it.
1273 */
1274 if (err == -EINVAL)
1275 continue;
1276 else if (err)
1277 break;
1278
1279 is_static = (entry.type == ENTRYTYPE_LOCKED);
1280
1281 /* Hide the reserved VLANs used for
1282 * VLAN-unaware bridging.
1283 */
1284 if (entry.vid > OCELOT_RSV_VLAN_RANGE_START)
1285 entry.vid = 0;
1286
1287 err = cb(entry.mac, entry.vid, is_static, data);
1288 if (err)
1289 break;
1290 }
1291 }
1292
1293 mutex_unlock(&ocelot->mact_lock);
1294
1295 return err;
1296}
1297EXPORT_SYMBOL(ocelot_fdb_dump);
1298
1299int ocelot_trap_add(struct ocelot *ocelot, int port,
1300 unsigned long cookie, bool take_ts,
1301 void (*populate)(struct ocelot_vcap_filter *f))
1302{
1303 struct ocelot_vcap_block *block_vcap_is2;
1304 struct ocelot_vcap_filter *trap;
1305 bool new = false;
1306 int err;
1307
1308 block_vcap_is2 = &ocelot->block[VCAP_IS2];
1309
1310 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie,
1311 false);
1312 if (!trap) {
1313 trap = kzalloc(sizeof(*trap), GFP_KERNEL);
1314 if (!trap)
1315 return -ENOMEM;
1316
1317 populate(trap);
1318 trap->prio = 1;
1319 trap->id.cookie = cookie;
1320 trap->id.tc_offload = false;
1321 trap->block_id = VCAP_IS2;
1322 trap->type = OCELOT_VCAP_FILTER_OFFLOAD;
1323 trap->lookup = 0;
1324 trap->action.cpu_copy_ena = true;
1325 trap->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY;
1326 trap->action.port_mask = 0;
1327 trap->take_ts = take_ts;
1328 trap->is_trap = true;
1329 new = true;
1330 }
1331
1332 trap->ingress_port_mask |= BIT(port);
1333
1334 if (new)
1335 err = ocelot_vcap_filter_add(ocelot, trap, NULL);
1336 else
1337 err = ocelot_vcap_filter_replace(ocelot, trap);
1338 if (err) {
1339 trap->ingress_port_mask &= ~BIT(port);
1340 if (!trap->ingress_port_mask)
1341 kfree(trap);
1342 return err;
1343 }
1344
1345 return 0;
1346}
1347
1348int ocelot_trap_del(struct ocelot *ocelot, int port, unsigned long cookie)
1349{
1350 struct ocelot_vcap_block *block_vcap_is2;
1351 struct ocelot_vcap_filter *trap;
1352
1353 block_vcap_is2 = &ocelot->block[VCAP_IS2];
1354
1355 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie,
1356 false);
1357 if (!trap)
1358 return 0;
1359
1360 trap->ingress_port_mask &= ~BIT(port);
1361 if (!trap->ingress_port_mask)
1362 return ocelot_vcap_filter_del(ocelot, trap);
1363
1364 return ocelot_vcap_filter_replace(ocelot, trap);
1365}
1366
1367static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond)
1368{
1369 u32 mask = 0;
1370 int port;
1371
1372 lockdep_assert_held(&ocelot->fwd_domain_lock);
1373
1374 for (port = 0; port < ocelot->num_phys_ports; port++) {
1375 struct ocelot_port *ocelot_port = ocelot->ports[port];
1376
1377 if (!ocelot_port)
1378 continue;
1379
1380 if (ocelot_port->bond == bond)
1381 mask |= BIT(port);
1382 }
1383
1384 return mask;
1385}
1386
1387/* The logical port number of a LAG is equal to the lowest numbered physical
1388 * port ID present in that LAG. It may change if that port ever leaves the LAG.
1389 */
1390int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond)
1391{
1392 int bond_mask = ocelot_get_bond_mask(ocelot, bond);
1393
1394 if (!bond_mask)
1395 return -ENOENT;
1396
1397 return __ffs(bond_mask);
1398}
1399EXPORT_SYMBOL_GPL(ocelot_bond_get_id);
1400
1401/* Returns the mask of user ports assigned to this DSA tag_8021q CPU port.
1402 * Note that when CPU ports are in a LAG, the user ports are assigned to the
1403 * 'primary' CPU port, the one whose physical port number gives the logical
1404 * port number of the LAG.
1405 *
1406 * We leave PGID_SRC poorly configured for the 'secondary' CPU port in the LAG
1407 * (to which no user port is assigned), but it appears that forwarding from
1408 * this secondary CPU port looks at the PGID_SRC associated with the logical
1409 * port ID that it's assigned to, which *is* configured properly.
1410 */
1411static u32 ocelot_dsa_8021q_cpu_assigned_ports(struct ocelot *ocelot,
1412 struct ocelot_port *cpu)
1413{
1414 u32 mask = 0;
1415 int port;
1416
1417 for (port = 0; port < ocelot->num_phys_ports; port++) {
1418 struct ocelot_port *ocelot_port = ocelot->ports[port];
1419
1420 if (!ocelot_port)
1421 continue;
1422
1423 if (ocelot_port->dsa_8021q_cpu == cpu)
1424 mask |= BIT(port);
1425 }
1426
1427 if (cpu->bond)
1428 mask &= ~ocelot_get_bond_mask(ocelot, cpu->bond);
1429
1430 return mask;
1431}
1432
1433/* Returns the DSA tag_8021q CPU port that the given port is assigned to,
1434 * or the bit mask of CPU ports if said CPU port is in a LAG.
1435 */
1436u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port)
1437{
1438 struct ocelot_port *ocelot_port = ocelot->ports[port];
1439 struct ocelot_port *cpu_port = ocelot_port->dsa_8021q_cpu;
1440
1441 if (!cpu_port)
1442 return 0;
1443
1444 if (cpu_port->bond)
1445 return ocelot_get_bond_mask(ocelot, cpu_port->bond);
1446
1447 return BIT(cpu_port->index);
1448}
1449EXPORT_SYMBOL_GPL(ocelot_port_assigned_dsa_8021q_cpu_mask);
1450
1451u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port)
1452{
1453 struct ocelot_port *ocelot_port = ocelot->ports[src_port];
1454 const struct net_device *bridge;
1455 u32 mask = 0;
1456 int port;
1457
1458 if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING)
1459 return 0;
1460
1461 bridge = ocelot_port->bridge;
1462 if (!bridge)
1463 return 0;
1464
1465 for (port = 0; port < ocelot->num_phys_ports; port++) {
1466 ocelot_port = ocelot->ports[port];
1467
1468 if (!ocelot_port)
1469 continue;
1470
1471 if (ocelot_port->stp_state == BR_STATE_FORWARDING &&
1472 ocelot_port->bridge == bridge)
1473 mask |= BIT(port);
1474 }
1475
1476 return mask;
1477}
1478EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask);
1479
1480static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining)
1481{
1482 int port;
1483
1484 lockdep_assert_held(&ocelot->fwd_domain_lock);
1485
1486 /* If cut-through forwarding is supported, update the masks before a
1487 * port joins the forwarding domain, to avoid potential underruns if it
1488 * has the highest speed from the new domain.
1489 */
1490 if (joining && ocelot->ops->cut_through_fwd)
1491 ocelot->ops->cut_through_fwd(ocelot);
1492
1493 /* Apply FWD mask. The loop is needed to add/remove the current port as
1494 * a source for the other ports.
1495 */
1496 for (port = 0; port < ocelot->num_phys_ports; port++) {
1497 struct ocelot_port *ocelot_port = ocelot->ports[port];
1498 unsigned long mask;
1499
1500 if (!ocelot_port) {
1501 /* Unused ports can't send anywhere */
1502 mask = 0;
1503 } else if (ocelot_port->is_dsa_8021q_cpu) {
1504 /* The DSA tag_8021q CPU ports need to be able to
1505 * forward packets to all ports assigned to them.
1506 */
1507 mask = ocelot_dsa_8021q_cpu_assigned_ports(ocelot,
1508 ocelot_port);
1509 } else if (ocelot_port->bridge) {
1510 struct net_device *bond = ocelot_port->bond;
1511
1512 mask = ocelot_get_bridge_fwd_mask(ocelot, port);
1513 mask &= ~BIT(port);
1514
1515 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
1516 port);
1517
1518 if (bond)
1519 mask &= ~ocelot_get_bond_mask(ocelot, bond);
1520 } else {
1521 /* Standalone ports forward only to DSA tag_8021q CPU
1522 * ports (if those exist), or to the hardware CPU port
1523 * module otherwise.
1524 */
1525 mask = ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
1526 port);
1527 }
1528
1529 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port);
1530 }
1531
1532 /* If cut-through forwarding is supported and a port is leaving, there
1533 * is a chance that cut-through was disabled on the other ports due to
1534 * the port which is leaving (it has a higher link speed). We need to
1535 * update the cut-through masks of the remaining ports no earlier than
1536 * after the port has left, to prevent underruns from happening between
1537 * the cut-through update and the forwarding domain update.
1538 */
1539 if (!joining && ocelot->ops->cut_through_fwd)
1540 ocelot->ops->cut_through_fwd(ocelot);
1541}
1542
1543/* Update PGID_CPU which is the destination port mask used for whitelisting
1544 * unicast addresses filtered towards the host. In the normal and NPI modes,
1545 * this points to the analyzer entry for the CPU port module, while in DSA
1546 * tag_8021q mode, it is a bit mask of all active CPU ports.
1547 * PGID_SRC will take care of forwarding a packet from one user port to
1548 * no more than a single CPU port.
1549 */
1550static void ocelot_update_pgid_cpu(struct ocelot *ocelot)
1551{
1552 int pgid_cpu = 0;
1553 int port;
1554
1555 for (port = 0; port < ocelot->num_phys_ports; port++) {
1556 struct ocelot_port *ocelot_port = ocelot->ports[port];
1557
1558 if (!ocelot_port || !ocelot_port->is_dsa_8021q_cpu)
1559 continue;
1560
1561 pgid_cpu |= BIT(port);
1562 }
1563
1564 if (!pgid_cpu)
1565 pgid_cpu = BIT(ocelot->num_phys_ports);
1566
1567 ocelot_write_rix(ocelot, pgid_cpu, ANA_PGID_PGID, PGID_CPU);
1568}
1569
1570void ocelot_port_setup_dsa_8021q_cpu(struct ocelot *ocelot, int cpu)
1571{
1572 struct ocelot_port *cpu_port = ocelot->ports[cpu];
1573 u16 vid;
1574
1575 mutex_lock(&ocelot->fwd_domain_lock);
1576
1577 cpu_port->is_dsa_8021q_cpu = true;
1578
1579 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
1580 ocelot_vlan_member_add(ocelot, cpu, vid, true);
1581
1582 ocelot_update_pgid_cpu(ocelot);
1583
1584 mutex_unlock(&ocelot->fwd_domain_lock);
1585}
1586EXPORT_SYMBOL_GPL(ocelot_port_setup_dsa_8021q_cpu);
1587
1588void ocelot_port_teardown_dsa_8021q_cpu(struct ocelot *ocelot, int cpu)
1589{
1590 struct ocelot_port *cpu_port = ocelot->ports[cpu];
1591 u16 vid;
1592
1593 mutex_lock(&ocelot->fwd_domain_lock);
1594
1595 cpu_port->is_dsa_8021q_cpu = false;
1596
1597 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
1598 ocelot_vlan_member_del(ocelot, cpu_port->index, vid);
1599
1600 ocelot_update_pgid_cpu(ocelot);
1601
1602 mutex_unlock(&ocelot->fwd_domain_lock);
1603}
1604EXPORT_SYMBOL_GPL(ocelot_port_teardown_dsa_8021q_cpu);
1605
1606void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port,
1607 int cpu)
1608{
1609 struct ocelot_port *cpu_port = ocelot->ports[cpu];
1610
1611 mutex_lock(&ocelot->fwd_domain_lock);
1612
1613 ocelot->ports[port]->dsa_8021q_cpu = cpu_port;
1614 ocelot_apply_bridge_fwd_mask(ocelot, true);
1615
1616 mutex_unlock(&ocelot->fwd_domain_lock);
1617}
1618EXPORT_SYMBOL_GPL(ocelot_port_assign_dsa_8021q_cpu);
1619
1620void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port)
1621{
1622 mutex_lock(&ocelot->fwd_domain_lock);
1623
1624 ocelot->ports[port]->dsa_8021q_cpu = NULL;
1625 ocelot_apply_bridge_fwd_mask(ocelot, true);
1626
1627 mutex_unlock(&ocelot->fwd_domain_lock);
1628}
1629EXPORT_SYMBOL_GPL(ocelot_port_unassign_dsa_8021q_cpu);
1630
1631void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
1632{
1633 struct ocelot_port *ocelot_port = ocelot->ports[port];
1634 u32 learn_ena = 0;
1635
1636 mutex_lock(&ocelot->fwd_domain_lock);
1637
1638 ocelot_port->stp_state = state;
1639
1640 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) &&
1641 ocelot_port->learn_ena)
1642 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA;
1643
1644 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA,
1645 ANA_PORT_PORT_CFG, port);
1646
1647 ocelot_apply_bridge_fwd_mask(ocelot, state == BR_STATE_FORWARDING);
1648
1649 mutex_unlock(&ocelot->fwd_domain_lock);
1650}
1651EXPORT_SYMBOL(ocelot_bridge_stp_state_set);
1652
1653void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
1654{
1655 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000);
1656
1657 /* Setting AGE_PERIOD to zero effectively disables automatic aging,
1658 * which is clearly not what our intention is. So avoid that.
1659 */
1660 if (!age_period)
1661 age_period = 1;
1662
1663 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE);
1664}
1665EXPORT_SYMBOL(ocelot_set_ageing_time);
1666
1667static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
1668 const unsigned char *addr,
1669 u16 vid)
1670{
1671 struct ocelot_multicast *mc;
1672
1673 list_for_each_entry(mc, &ocelot->multicast, list) {
1674 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
1675 return mc;
1676 }
1677
1678 return NULL;
1679}
1680
1681static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr)
1682{
1683 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e)
1684 return ENTRYTYPE_MACv4;
1685 if (addr[0] == 0x33 && addr[1] == 0x33)
1686 return ENTRYTYPE_MACv6;
1687 return ENTRYTYPE_LOCKED;
1688}
1689
1690static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index,
1691 unsigned long ports)
1692{
1693 struct ocelot_pgid *pgid;
1694
1695 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL);
1696 if (!pgid)
1697 return ERR_PTR(-ENOMEM);
1698
1699 pgid->ports = ports;
1700 pgid->index = index;
1701 refcount_set(&pgid->refcount, 1);
1702 list_add_tail(&pgid->list, &ocelot->pgids);
1703
1704 return pgid;
1705}
1706
1707static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid)
1708{
1709 if (!refcount_dec_and_test(&pgid->refcount))
1710 return;
1711
1712 list_del(&pgid->list);
1713 kfree(pgid);
1714}
1715
1716static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot,
1717 const struct ocelot_multicast *mc)
1718{
1719 struct ocelot_pgid *pgid;
1720 int index;
1721
1722 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and
1723 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the
1724 * destination mask table (PGID), the destination set is programmed as
1725 * part of the entry MAC address.", and the DEST_IDX is set to 0.
1726 */
1727 if (mc->entry_type == ENTRYTYPE_MACv4 ||
1728 mc->entry_type == ENTRYTYPE_MACv6)
1729 return ocelot_pgid_alloc(ocelot, 0, mc->ports);
1730
1731 list_for_each_entry(pgid, &ocelot->pgids, list) {
1732 /* When searching for a nonreserved multicast PGID, ignore the
1733 * dummy PGID of zero that we have for MACv4/MACv6 entries
1734 */
1735 if (pgid->index && pgid->ports == mc->ports) {
1736 refcount_inc(&pgid->refcount);
1737 return pgid;
1738 }
1739 }
1740
1741 /* Search for a free index in the nonreserved multicast PGID area */
1742 for_each_nonreserved_multicast_dest_pgid(ocelot, index) {
1743 bool used = false;
1744
1745 list_for_each_entry(pgid, &ocelot->pgids, list) {
1746 if (pgid->index == index) {
1747 used = true;
1748 break;
1749 }
1750 }
1751
1752 if (!used)
1753 return ocelot_pgid_alloc(ocelot, index, mc->ports);
1754 }
1755
1756 return ERR_PTR(-ENOSPC);
1757}
1758
1759static void ocelot_encode_ports_to_mdb(unsigned char *addr,
1760 struct ocelot_multicast *mc)
1761{
1762 ether_addr_copy(addr, mc->addr);
1763
1764 if (mc->entry_type == ENTRYTYPE_MACv4) {
1765 addr[0] = 0;
1766 addr[1] = mc->ports >> 8;
1767 addr[2] = mc->ports & 0xff;
1768 } else if (mc->entry_type == ENTRYTYPE_MACv6) {
1769 addr[0] = mc->ports >> 8;
1770 addr[1] = mc->ports & 0xff;
1771 }
1772}
1773
1774int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
1775 const struct switchdev_obj_port_mdb *mdb,
1776 const struct net_device *bridge)
1777{
1778 unsigned char addr[ETH_ALEN];
1779 struct ocelot_multicast *mc;
1780 struct ocelot_pgid *pgid;
1781 u16 vid = mdb->vid;
1782
1783 if (!vid)
1784 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1785
1786 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1787 if (!mc) {
1788 /* New entry */
1789 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
1790 if (!mc)
1791 return -ENOMEM;
1792
1793 mc->entry_type = ocelot_classify_mdb(mdb->addr);
1794 ether_addr_copy(mc->addr, mdb->addr);
1795 mc->vid = vid;
1796
1797 list_add_tail(&mc->list, &ocelot->multicast);
1798 } else {
1799 /* Existing entry. Clean up the current port mask from
1800 * hardware now, because we'll be modifying it.
1801 */
1802 ocelot_pgid_free(ocelot, mc->pgid);
1803 ocelot_encode_ports_to_mdb(addr, mc);
1804 ocelot_mact_forget(ocelot, addr, vid);
1805 }
1806
1807 mc->ports |= BIT(port);
1808
1809 pgid = ocelot_mdb_get_pgid(ocelot, mc);
1810 if (IS_ERR(pgid)) {
1811 dev_err(ocelot->dev,
1812 "Cannot allocate PGID for mdb %pM vid %d\n",
1813 mc->addr, mc->vid);
1814 devm_kfree(ocelot->dev, mc);
1815 return PTR_ERR(pgid);
1816 }
1817 mc->pgid = pgid;
1818
1819 ocelot_encode_ports_to_mdb(addr, mc);
1820
1821 if (mc->entry_type != ENTRYTYPE_MACv4 &&
1822 mc->entry_type != ENTRYTYPE_MACv6)
1823 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
1824 pgid->index);
1825
1826 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
1827 mc->entry_type);
1828}
1829EXPORT_SYMBOL(ocelot_port_mdb_add);
1830
1831int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
1832 const struct switchdev_obj_port_mdb *mdb,
1833 const struct net_device *bridge)
1834{
1835 unsigned char addr[ETH_ALEN];
1836 struct ocelot_multicast *mc;
1837 struct ocelot_pgid *pgid;
1838 u16 vid = mdb->vid;
1839
1840 if (!vid)
1841 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1842
1843 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1844 if (!mc)
1845 return -ENOENT;
1846
1847 ocelot_encode_ports_to_mdb(addr, mc);
1848 ocelot_mact_forget(ocelot, addr, vid);
1849
1850 ocelot_pgid_free(ocelot, mc->pgid);
1851 mc->ports &= ~BIT(port);
1852 if (!mc->ports) {
1853 list_del(&mc->list);
1854 devm_kfree(ocelot->dev, mc);
1855 return 0;
1856 }
1857
1858 /* We have a PGID with fewer ports now */
1859 pgid = ocelot_mdb_get_pgid(ocelot, mc);
1860 if (IS_ERR(pgid))
1861 return PTR_ERR(pgid);
1862 mc->pgid = pgid;
1863
1864 ocelot_encode_ports_to_mdb(addr, mc);
1865
1866 if (mc->entry_type != ENTRYTYPE_MACv4 &&
1867 mc->entry_type != ENTRYTYPE_MACv6)
1868 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
1869 pgid->index);
1870
1871 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
1872 mc->entry_type);
1873}
1874EXPORT_SYMBOL(ocelot_port_mdb_del);
1875
1876int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
1877 struct net_device *bridge, int bridge_num,
1878 struct netlink_ext_ack *extack)
1879{
1880 struct ocelot_port *ocelot_port = ocelot->ports[port];
1881 int err;
1882
1883 err = ocelot_single_vlan_aware_bridge(ocelot, extack);
1884 if (err)
1885 return err;
1886
1887 mutex_lock(&ocelot->fwd_domain_lock);
1888
1889 ocelot_port->bridge = bridge;
1890 ocelot_port->bridge_num = bridge_num;
1891
1892 ocelot_apply_bridge_fwd_mask(ocelot, true);
1893
1894 mutex_unlock(&ocelot->fwd_domain_lock);
1895
1896 if (br_vlan_enabled(bridge))
1897 return 0;
1898
1899 return ocelot_add_vlan_unaware_pvid(ocelot, port, bridge);
1900}
1901EXPORT_SYMBOL(ocelot_port_bridge_join);
1902
1903void ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
1904 struct net_device *bridge)
1905{
1906 struct ocelot_port *ocelot_port = ocelot->ports[port];
1907
1908 mutex_lock(&ocelot->fwd_domain_lock);
1909
1910 if (!br_vlan_enabled(bridge))
1911 ocelot_del_vlan_unaware_pvid(ocelot, port, bridge);
1912
1913 ocelot_port->bridge = NULL;
1914 ocelot_port->bridge_num = -1;
1915
1916 ocelot_port_set_pvid(ocelot, port, NULL);
1917 ocelot_port_manage_port_tag(ocelot, port);
1918 ocelot_apply_bridge_fwd_mask(ocelot, false);
1919
1920 mutex_unlock(&ocelot->fwd_domain_lock);
1921}
1922EXPORT_SYMBOL(ocelot_port_bridge_leave);
1923
1924static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
1925{
1926 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0);
1927 int i, port, lag;
1928
1929 /* Reset destination and aggregation PGIDS */
1930 for_each_unicast_dest_pgid(ocelot, port)
1931 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1932
1933 for_each_aggr_pgid(ocelot, i)
1934 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
1935 ANA_PGID_PGID, i);
1936
1937 /* The visited ports bitmask holds the list of ports offloading any
1938 * bonding interface. Initially we mark all these ports as unvisited,
1939 * then every time we visit a port in this bitmask, we know that it is
1940 * the lowest numbered port, i.e. the one whose logical ID == physical
1941 * port ID == LAG ID. So we mark as visited all further ports in the
1942 * bitmask that are offloading the same bonding interface. This way,
1943 * we set up the aggregation PGIDs only once per bonding interface.
1944 */
1945 for (port = 0; port < ocelot->num_phys_ports; port++) {
1946 struct ocelot_port *ocelot_port = ocelot->ports[port];
1947
1948 if (!ocelot_port || !ocelot_port->bond)
1949 continue;
1950
1951 visited &= ~BIT(port);
1952 }
1953
1954 /* Now, set PGIDs for each active LAG */
1955 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
1956 struct net_device *bond = ocelot->ports[lag]->bond;
1957 int num_active_ports = 0;
1958 unsigned long bond_mask;
1959 u8 aggr_idx[16];
1960
1961 if (!bond || (visited & BIT(lag)))
1962 continue;
1963
1964 bond_mask = ocelot_get_bond_mask(ocelot, bond);
1965
1966 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
1967 struct ocelot_port *ocelot_port = ocelot->ports[port];
1968
1969 // Destination mask
1970 ocelot_write_rix(ocelot, bond_mask,
1971 ANA_PGID_PGID, port);
1972
1973 if (ocelot_port->lag_tx_active)
1974 aggr_idx[num_active_ports++] = port;
1975 }
1976
1977 for_each_aggr_pgid(ocelot, i) {
1978 u32 ac;
1979
1980 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
1981 ac &= ~bond_mask;
1982 /* Don't do division by zero if there was no active
1983 * port. Just make all aggregation codes zero.
1984 */
1985 if (num_active_ports)
1986 ac |= BIT(aggr_idx[i % num_active_ports]);
1987 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
1988 }
1989
1990 /* Mark all ports in the same LAG as visited to avoid applying
1991 * the same config again.
1992 */
1993 for (port = lag; port < ocelot->num_phys_ports; port++) {
1994 struct ocelot_port *ocelot_port = ocelot->ports[port];
1995
1996 if (!ocelot_port)
1997 continue;
1998
1999 if (ocelot_port->bond == bond)
2000 visited |= BIT(port);
2001 }
2002 }
2003}
2004
2005/* When offloading a bonding interface, the switch ports configured under the
2006 * same bond must have the same logical port ID, equal to the physical port ID
2007 * of the lowest numbered physical port in that bond. Otherwise, in standalone/
2008 * bridged mode, each port has a logical port ID equal to its physical port ID.
2009 */
2010static void ocelot_setup_logical_port_ids(struct ocelot *ocelot)
2011{
2012 int port;
2013
2014 for (port = 0; port < ocelot->num_phys_ports; port++) {
2015 struct ocelot_port *ocelot_port = ocelot->ports[port];
2016 struct net_device *bond;
2017
2018 if (!ocelot_port)
2019 continue;
2020
2021 bond = ocelot_port->bond;
2022 if (bond) {
2023 int lag = ocelot_bond_get_id(ocelot, bond);
2024
2025 ocelot_rmw_gix(ocelot,
2026 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
2027 ANA_PORT_PORT_CFG_PORTID_VAL_M,
2028 ANA_PORT_PORT_CFG, port);
2029 } else {
2030 ocelot_rmw_gix(ocelot,
2031 ANA_PORT_PORT_CFG_PORTID_VAL(port),
2032 ANA_PORT_PORT_CFG_PORTID_VAL_M,
2033 ANA_PORT_PORT_CFG, port);
2034 }
2035 }
2036}
2037
2038static int ocelot_migrate_mc(struct ocelot *ocelot, struct ocelot_multicast *mc,
2039 unsigned long from_mask, unsigned long to_mask)
2040{
2041 unsigned char addr[ETH_ALEN];
2042 struct ocelot_pgid *pgid;
2043 u16 vid = mc->vid;
2044
2045 dev_dbg(ocelot->dev,
2046 "Migrating multicast %pM vid %d from port mask 0x%lx to 0x%lx\n",
2047 mc->addr, mc->vid, from_mask, to_mask);
2048
2049 /* First clean up the current port mask from hardware, because
2050 * we'll be modifying it.
2051 */
2052 ocelot_pgid_free(ocelot, mc->pgid);
2053 ocelot_encode_ports_to_mdb(addr, mc);
2054 ocelot_mact_forget(ocelot, addr, vid);
2055
2056 mc->ports &= ~from_mask;
2057 mc->ports |= to_mask;
2058
2059 pgid = ocelot_mdb_get_pgid(ocelot, mc);
2060 if (IS_ERR(pgid)) {
2061 dev_err(ocelot->dev,
2062 "Cannot allocate PGID for mdb %pM vid %d\n",
2063 mc->addr, mc->vid);
2064 devm_kfree(ocelot->dev, mc);
2065 return PTR_ERR(pgid);
2066 }
2067 mc->pgid = pgid;
2068
2069 ocelot_encode_ports_to_mdb(addr, mc);
2070
2071 if (mc->entry_type != ENTRYTYPE_MACv4 &&
2072 mc->entry_type != ENTRYTYPE_MACv6)
2073 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2074 pgid->index);
2075
2076 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2077 mc->entry_type);
2078}
2079
2080int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask,
2081 unsigned long to_mask)
2082{
2083 struct ocelot_multicast *mc;
2084 int err;
2085
2086 list_for_each_entry(mc, &ocelot->multicast, list) {
2087 if (!(mc->ports & from_mask))
2088 continue;
2089
2090 err = ocelot_migrate_mc(ocelot, mc, from_mask, to_mask);
2091 if (err)
2092 return err;
2093 }
2094
2095 return 0;
2096}
2097EXPORT_SYMBOL_GPL(ocelot_migrate_mdbs);
2098
2099/* Documentation for PORTID_VAL says:
2100 * Logical port number for front port. If port is not a member of a LLAG,
2101 * then PORTID must be set to the physical port number.
2102 * If port is a member of a LLAG, then PORTID must be set to the common
2103 * PORTID_VAL used for all member ports of the LLAG.
2104 * The value must not exceed the number of physical ports on the device.
2105 *
2106 * This means we have little choice but to migrate FDB entries pointing towards
2107 * a logical port when that changes.
2108 */
2109static void ocelot_migrate_lag_fdbs(struct ocelot *ocelot,
2110 struct net_device *bond,
2111 int lag)
2112{
2113 struct ocelot_lag_fdb *fdb;
2114 int err;
2115
2116 lockdep_assert_held(&ocelot->fwd_domain_lock);
2117
2118 list_for_each_entry(fdb, &ocelot->lag_fdbs, list) {
2119 if (fdb->bond != bond)
2120 continue;
2121
2122 err = ocelot_mact_forget(ocelot, fdb->addr, fdb->vid);
2123 if (err) {
2124 dev_err(ocelot->dev,
2125 "failed to delete LAG %s FDB %pM vid %d: %pe\n",
2126 bond->name, fdb->addr, fdb->vid, ERR_PTR(err));
2127 }
2128
2129 err = ocelot_mact_learn(ocelot, lag, fdb->addr, fdb->vid,
2130 ENTRYTYPE_LOCKED);
2131 if (err) {
2132 dev_err(ocelot->dev,
2133 "failed to migrate LAG %s FDB %pM vid %d: %pe\n",
2134 bond->name, fdb->addr, fdb->vid, ERR_PTR(err));
2135 }
2136 }
2137}
2138
2139int ocelot_port_lag_join(struct ocelot *ocelot, int port,
2140 struct net_device *bond,
2141 struct netdev_lag_upper_info *info,
2142 struct netlink_ext_ack *extack)
2143{
2144 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
2145 NL_SET_ERR_MSG_MOD(extack,
2146 "Can only offload LAG using hash TX type");
2147 return -EOPNOTSUPP;
2148 }
2149
2150 mutex_lock(&ocelot->fwd_domain_lock);
2151
2152 ocelot->ports[port]->bond = bond;
2153
2154 ocelot_setup_logical_port_ids(ocelot);
2155 ocelot_apply_bridge_fwd_mask(ocelot, true);
2156 ocelot_set_aggr_pgids(ocelot);
2157
2158 mutex_unlock(&ocelot->fwd_domain_lock);
2159
2160 return 0;
2161}
2162EXPORT_SYMBOL(ocelot_port_lag_join);
2163
2164void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
2165 struct net_device *bond)
2166{
2167 int old_lag_id, new_lag_id;
2168
2169 mutex_lock(&ocelot->fwd_domain_lock);
2170
2171 old_lag_id = ocelot_bond_get_id(ocelot, bond);
2172
2173 ocelot->ports[port]->bond = NULL;
2174
2175 ocelot_setup_logical_port_ids(ocelot);
2176 ocelot_apply_bridge_fwd_mask(ocelot, false);
2177 ocelot_set_aggr_pgids(ocelot);
2178
2179 new_lag_id = ocelot_bond_get_id(ocelot, bond);
2180
2181 if (new_lag_id >= 0 && old_lag_id != new_lag_id)
2182 ocelot_migrate_lag_fdbs(ocelot, bond, new_lag_id);
2183
2184 mutex_unlock(&ocelot->fwd_domain_lock);
2185}
2186EXPORT_SYMBOL(ocelot_port_lag_leave);
2187
2188void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active)
2189{
2190 struct ocelot_port *ocelot_port = ocelot->ports[port];
2191
2192 mutex_lock(&ocelot->fwd_domain_lock);
2193
2194 ocelot_port->lag_tx_active = lag_tx_active;
2195
2196 /* Rebalance the LAGs */
2197 ocelot_set_aggr_pgids(ocelot);
2198
2199 mutex_unlock(&ocelot->fwd_domain_lock);
2200}
2201EXPORT_SYMBOL(ocelot_port_lag_change);
2202
2203int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond,
2204 const unsigned char *addr, u16 vid,
2205 const struct net_device *bridge)
2206{
2207 struct ocelot_lag_fdb *fdb;
2208 int lag, err;
2209
2210 fdb = kzalloc(sizeof(*fdb), GFP_KERNEL);
2211 if (!fdb)
2212 return -ENOMEM;
2213
2214 mutex_lock(&ocelot->fwd_domain_lock);
2215
2216 if (!vid)
2217 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2218
2219 ether_addr_copy(fdb->addr, addr);
2220 fdb->vid = vid;
2221 fdb->bond = bond;
2222
2223 lag = ocelot_bond_get_id(ocelot, bond);
2224
2225 err = ocelot_mact_learn(ocelot, lag, addr, vid, ENTRYTYPE_LOCKED);
2226 if (err) {
2227 mutex_unlock(&ocelot->fwd_domain_lock);
2228 kfree(fdb);
2229 return err;
2230 }
2231
2232 list_add_tail(&fdb->list, &ocelot->lag_fdbs);
2233 mutex_unlock(&ocelot->fwd_domain_lock);
2234
2235 return 0;
2236}
2237EXPORT_SYMBOL_GPL(ocelot_lag_fdb_add);
2238
2239int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond,
2240 const unsigned char *addr, u16 vid,
2241 const struct net_device *bridge)
2242{
2243 struct ocelot_lag_fdb *fdb, *tmp;
2244
2245 mutex_lock(&ocelot->fwd_domain_lock);
2246
2247 if (!vid)
2248 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2249
2250 list_for_each_entry_safe(fdb, tmp, &ocelot->lag_fdbs, list) {
2251 if (!ether_addr_equal(fdb->addr, addr) || fdb->vid != vid ||
2252 fdb->bond != bond)
2253 continue;
2254
2255 ocelot_mact_forget(ocelot, addr, vid);
2256 list_del(&fdb->list);
2257 mutex_unlock(&ocelot->fwd_domain_lock);
2258 kfree(fdb);
2259
2260 return 0;
2261 }
2262
2263 mutex_unlock(&ocelot->fwd_domain_lock);
2264
2265 return -ENOENT;
2266}
2267EXPORT_SYMBOL_GPL(ocelot_lag_fdb_del);
2268
2269/* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
2270 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
2271 * In the special case that it's the NPI port that we're configuring, the
2272 * length of the tag and optional prefix needs to be accounted for privately,
2273 * in order to be able to sustain communication at the requested @sdu.
2274 */
2275void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu)
2276{
2277 struct ocelot_port *ocelot_port = ocelot->ports[port];
2278 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN;
2279 int pause_start, pause_stop;
2280 int atop, atop_tot;
2281
2282 if (port == ocelot->npi) {
2283 maxlen += OCELOT_TAG_LEN;
2284
2285 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2286 maxlen += OCELOT_SHORT_PREFIX_LEN;
2287 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2288 maxlen += OCELOT_LONG_PREFIX_LEN;
2289 }
2290
2291 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG);
2292
2293 /* Set Pause watermark hysteresis */
2294 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ;
2295 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ;
2296 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START,
2297 pause_start);
2298 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP,
2299 pause_stop);
2300
2301 /* Tail dropping watermarks */
2302 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) /
2303 OCELOT_BUFFER_CELL_SZ;
2304 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ;
2305 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port);
2306 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG);
2307}
2308EXPORT_SYMBOL(ocelot_port_set_maxlen);
2309
2310int ocelot_get_max_mtu(struct ocelot *ocelot, int port)
2311{
2312 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN;
2313
2314 if (port == ocelot->npi) {
2315 max_mtu -= OCELOT_TAG_LEN;
2316
2317 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2318 max_mtu -= OCELOT_SHORT_PREFIX_LEN;
2319 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2320 max_mtu -= OCELOT_LONG_PREFIX_LEN;
2321 }
2322
2323 return max_mtu;
2324}
2325EXPORT_SYMBOL(ocelot_get_max_mtu);
2326
2327static void ocelot_port_set_learning(struct ocelot *ocelot, int port,
2328 bool enabled)
2329{
2330 struct ocelot_port *ocelot_port = ocelot->ports[port];
2331 u32 val = 0;
2332
2333 if (enabled)
2334 val = ANA_PORT_PORT_CFG_LEARN_ENA;
2335
2336 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA,
2337 ANA_PORT_PORT_CFG, port);
2338
2339 ocelot_port->learn_ena = enabled;
2340}
2341
2342static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port,
2343 bool enabled)
2344{
2345 u32 val = 0;
2346
2347 if (enabled)
2348 val = BIT(port);
2349
2350 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC);
2351}
2352
2353static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port,
2354 bool enabled)
2355{
2356 u32 val = 0;
2357
2358 if (enabled)
2359 val = BIT(port);
2360
2361 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC);
2362 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV4);
2363 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV6);
2364}
2365
2366static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port,
2367 bool enabled)
2368{
2369 u32 val = 0;
2370
2371 if (enabled)
2372 val = BIT(port);
2373
2374 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC);
2375}
2376
2377int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
2378 struct switchdev_brport_flags flags)
2379{
2380 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
2381 BR_BCAST_FLOOD))
2382 return -EINVAL;
2383
2384 return 0;
2385}
2386EXPORT_SYMBOL(ocelot_port_pre_bridge_flags);
2387
2388void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
2389 struct switchdev_brport_flags flags)
2390{
2391 if (flags.mask & BR_LEARNING)
2392 ocelot_port_set_learning(ocelot, port,
2393 !!(flags.val & BR_LEARNING));
2394
2395 if (flags.mask & BR_FLOOD)
2396 ocelot_port_set_ucast_flood(ocelot, port,
2397 !!(flags.val & BR_FLOOD));
2398
2399 if (flags.mask & BR_MCAST_FLOOD)
2400 ocelot_port_set_mcast_flood(ocelot, port,
2401 !!(flags.val & BR_MCAST_FLOOD));
2402
2403 if (flags.mask & BR_BCAST_FLOOD)
2404 ocelot_port_set_bcast_flood(ocelot, port,
2405 !!(flags.val & BR_BCAST_FLOOD));
2406}
2407EXPORT_SYMBOL(ocelot_port_bridge_flags);
2408
2409int ocelot_port_get_default_prio(struct ocelot *ocelot, int port)
2410{
2411 int val = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port);
2412
2413 return ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(val);
2414}
2415EXPORT_SYMBOL_GPL(ocelot_port_get_default_prio);
2416
2417int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio)
2418{
2419 if (prio >= OCELOT_NUM_TC)
2420 return -ERANGE;
2421
2422 ocelot_rmw_gix(ocelot,
2423 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(prio),
2424 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M,
2425 ANA_PORT_QOS_CFG,
2426 port);
2427
2428 return 0;
2429}
2430EXPORT_SYMBOL_GPL(ocelot_port_set_default_prio);
2431
2432int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp)
2433{
2434 int qos_cfg = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port);
2435 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2436
2437 /* Return error if DSCP prioritization isn't enabled */
2438 if (!(qos_cfg & ANA_PORT_QOS_CFG_QOS_DSCP_ENA))
2439 return -EOPNOTSUPP;
2440
2441 if (qos_cfg & ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA) {
2442 dscp = ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(dscp_cfg);
2443 /* Re-read ANA_DSCP_CFG for the translated DSCP */
2444 dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2445 }
2446
2447 /* If the DSCP value is not trusted, the QoS classification falls back
2448 * to VLAN PCP or port-based default.
2449 */
2450 if (!(dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA))
2451 return -EOPNOTSUPP;
2452
2453 return ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg);
2454}
2455EXPORT_SYMBOL_GPL(ocelot_port_get_dscp_prio);
2456
2457int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio)
2458{
2459 int mask, val;
2460
2461 if (prio >= OCELOT_NUM_TC)
2462 return -ERANGE;
2463
2464 /* There is at least one app table priority (this one), so we need to
2465 * make sure DSCP prioritization is enabled on the port.
2466 * Also make sure DSCP translation is disabled
2467 * (dcbnl doesn't support it).
2468 */
2469 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA |
2470 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA;
2471
2472 ocelot_rmw_gix(ocelot, ANA_PORT_QOS_CFG_QOS_DSCP_ENA, mask,
2473 ANA_PORT_QOS_CFG, port);
2474
2475 /* Trust this DSCP value and map it to the given QoS class */
2476 val = ANA_DSCP_CFG_DSCP_TRUST_ENA | ANA_DSCP_CFG_QOS_DSCP_VAL(prio);
2477
2478 ocelot_write_rix(ocelot, val, ANA_DSCP_CFG, dscp);
2479
2480 return 0;
2481}
2482EXPORT_SYMBOL_GPL(ocelot_port_add_dscp_prio);
2483
2484int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio)
2485{
2486 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2487 int mask, i;
2488
2489 /* During a "dcb app replace" command, the new app table entry will be
2490 * added first, then the old one will be deleted. But the hardware only
2491 * supports one QoS class per DSCP value (duh), so if we blindly delete
2492 * the app table entry for this DSCP value, we end up deleting the
2493 * entry with the new priority. Avoid that by checking whether user
2494 * space wants to delete the priority which is currently configured, or
2495 * something else which is no longer current.
2496 */
2497 if (ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg) != prio)
2498 return 0;
2499
2500 /* Untrust this DSCP value */
2501 ocelot_write_rix(ocelot, 0, ANA_DSCP_CFG, dscp);
2502
2503 for (i = 0; i < 64; i++) {
2504 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, i);
2505
2506 /* There are still app table entries on the port, so we need to
2507 * keep DSCP enabled, nothing to do.
2508 */
2509 if (dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA)
2510 return 0;
2511 }
2512
2513 /* Disable DSCP QoS classification if there isn't any trusted
2514 * DSCP value left.
2515 */
2516 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA |
2517 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA;
2518
2519 ocelot_rmw_gix(ocelot, 0, mask, ANA_PORT_QOS_CFG, port);
2520
2521 return 0;
2522}
2523EXPORT_SYMBOL_GPL(ocelot_port_del_dscp_prio);
2524
2525struct ocelot_mirror *ocelot_mirror_get(struct ocelot *ocelot, int to,
2526 struct netlink_ext_ack *extack)
2527{
2528 struct ocelot_mirror *m = ocelot->mirror;
2529
2530 if (m) {
2531 if (m->to != to) {
2532 NL_SET_ERR_MSG_MOD(extack,
2533 "Mirroring already configured towards different egress port");
2534 return ERR_PTR(-EBUSY);
2535 }
2536
2537 refcount_inc(&m->refcount);
2538 return m;
2539 }
2540
2541 m = kzalloc(sizeof(*m), GFP_KERNEL);
2542 if (!m)
2543 return ERR_PTR(-ENOMEM);
2544
2545 m->to = to;
2546 refcount_set(&m->refcount, 1);
2547 ocelot->mirror = m;
2548
2549 /* Program the mirror port to hardware */
2550 ocelot_write(ocelot, BIT(to), ANA_MIRRORPORTS);
2551
2552 return m;
2553}
2554
2555void ocelot_mirror_put(struct ocelot *ocelot)
2556{
2557 struct ocelot_mirror *m = ocelot->mirror;
2558
2559 if (!refcount_dec_and_test(&m->refcount))
2560 return;
2561
2562 ocelot_write(ocelot, 0, ANA_MIRRORPORTS);
2563 ocelot->mirror = NULL;
2564 kfree(m);
2565}
2566
2567int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to,
2568 bool ingress, struct netlink_ext_ack *extack)
2569{
2570 struct ocelot_mirror *m = ocelot_mirror_get(ocelot, to, extack);
2571
2572 if (IS_ERR(m))
2573 return PTR_ERR(m);
2574
2575 if (ingress) {
2576 ocelot_rmw_gix(ocelot, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2577 ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2578 ANA_PORT_PORT_CFG, from);
2579 } else {
2580 ocelot_rmw(ocelot, BIT(from), BIT(from),
2581 ANA_EMIRRORPORTS);
2582 }
2583
2584 return 0;
2585}
2586EXPORT_SYMBOL_GPL(ocelot_port_mirror_add);
2587
2588void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress)
2589{
2590 if (ingress) {
2591 ocelot_rmw_gix(ocelot, 0, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2592 ANA_PORT_PORT_CFG, from);
2593 } else {
2594 ocelot_rmw(ocelot, 0, BIT(from), ANA_EMIRRORPORTS);
2595 }
2596
2597 ocelot_mirror_put(ocelot);
2598}
2599EXPORT_SYMBOL_GPL(ocelot_port_mirror_del);
2600
2601void ocelot_init_port(struct ocelot *ocelot, int port)
2602{
2603 struct ocelot_port *ocelot_port = ocelot->ports[port];
2604
2605 skb_queue_head_init(&ocelot_port->tx_skbs);
2606
2607 /* Basic L2 initialization */
2608
2609 /* Set MAC IFG Gaps
2610 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
2611 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
2612 */
2613 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
2614 DEV_MAC_IFG_CFG);
2615
2616 /* Load seed (0) and set MAC HDX late collision */
2617 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
2618 DEV_MAC_HDX_CFG_SEED_LOAD,
2619 DEV_MAC_HDX_CFG);
2620 mdelay(1);
2621 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
2622 DEV_MAC_HDX_CFG);
2623
2624 /* Set Max Length and maximum tags allowed */
2625 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN);
2626 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
2627 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
2628 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA |
2629 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
2630 DEV_MAC_TAGS_CFG);
2631
2632 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
2633 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
2634 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
2635
2636 /* Enable transmission of pause frames */
2637 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1);
2638
2639 /* Drop frames with multicast source address */
2640 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2641 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2642 ANA_PORT_DROP_CFG, port);
2643
2644 /* Set default VLAN and tag type to 8021Q. */
2645 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
2646 REW_PORT_VLAN_CFG_PORT_TPID_M,
2647 REW_PORT_VLAN_CFG, port);
2648
2649 /* Disable source address learning for standalone mode */
2650 ocelot_port_set_learning(ocelot, port, false);
2651
2652 /* Set the port's initial logical port ID value, enable receiving
2653 * frames on it, and configure the MAC address learning type to
2654 * automatic.
2655 */
2656 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
2657 ANA_PORT_PORT_CFG_RECV_ENA |
2658 ANA_PORT_PORT_CFG_PORTID_VAL(port),
2659 ANA_PORT_PORT_CFG, port);
2660
2661 /* Enable vcap lookups */
2662 ocelot_vcap_enable(ocelot, port);
2663}
2664EXPORT_SYMBOL(ocelot_init_port);
2665
2666/* Configure and enable the CPU port module, which is a set of queues
2667 * accessible through register MMIO, frame DMA or Ethernet (in case
2668 * NPI mode is used).
2669 */
2670static void ocelot_cpu_port_init(struct ocelot *ocelot)
2671{
2672 int cpu = ocelot->num_phys_ports;
2673
2674 /* The unicast destination PGID for the CPU port module is unused */
2675 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
2676 /* Instead set up a multicast destination PGID for traffic copied to
2677 * the CPU. Whitelisted MAC addresses like the port netdevice MAC
2678 * addresses will be copied to the CPU via this PGID.
2679 */
2680 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
2681 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
2682 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
2683 ANA_PORT_PORT_CFG, cpu);
2684
2685 /* Enable CPU port module */
2686 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
2687 /* CPU port Injection/Extraction configuration */
2688 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR,
2689 OCELOT_TAG_PREFIX_NONE);
2690 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR,
2691 OCELOT_TAG_PREFIX_NONE);
2692
2693 /* Configure the CPU port to be VLAN aware */
2694 ocelot_write_gix(ocelot,
2695 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_STANDALONE_PVID) |
2696 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
2697 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
2698 ANA_PORT_VLAN_CFG, cpu);
2699}
2700
2701static void ocelot_detect_features(struct ocelot *ocelot)
2702{
2703 int mmgt, eq_ctrl;
2704
2705 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds
2706 * the number of 240-byte free memory words (aka 4-cell chunks) and not
2707 * 192 bytes as the documentation incorrectly says.
2708 */
2709 mmgt = ocelot_read(ocelot, SYS_MMGT);
2710 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt);
2711
2712 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL);
2713 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl);
2714}
2715
2716int ocelot_init(struct ocelot *ocelot)
2717{
2718 int i, ret;
2719 u32 port;
2720
2721 if (ocelot->ops->reset) {
2722 ret = ocelot->ops->reset(ocelot);
2723 if (ret) {
2724 dev_err(ocelot->dev, "Switch reset failed\n");
2725 return ret;
2726 }
2727 }
2728
2729 mutex_init(&ocelot->ptp_lock);
2730 mutex_init(&ocelot->mact_lock);
2731 mutex_init(&ocelot->fwd_domain_lock);
2732 mutex_init(&ocelot->tas_lock);
2733 spin_lock_init(&ocelot->ptp_clock_lock);
2734 spin_lock_init(&ocelot->ts_id_lock);
2735
2736 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0);
2737 if (!ocelot->owq)
2738 return -ENOMEM;
2739
2740 ret = ocelot_stats_init(ocelot);
2741 if (ret) {
2742 destroy_workqueue(ocelot->owq);
2743 return ret;
2744 }
2745
2746 INIT_LIST_HEAD(&ocelot->multicast);
2747 INIT_LIST_HEAD(&ocelot->pgids);
2748 INIT_LIST_HEAD(&ocelot->vlans);
2749 INIT_LIST_HEAD(&ocelot->lag_fdbs);
2750 ocelot_detect_features(ocelot);
2751 ocelot_mact_init(ocelot);
2752 ocelot_vlan_init(ocelot);
2753 ocelot_vcap_init(ocelot);
2754 ocelot_cpu_port_init(ocelot);
2755
2756 if (ocelot->ops->psfp_init)
2757 ocelot->ops->psfp_init(ocelot);
2758
2759 for (port = 0; port < ocelot->num_phys_ports; port++) {
2760 /* Clear all counters (5 groups) */
2761 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
2762 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
2763 SYS_STAT_CFG);
2764 }
2765
2766 /* Only use S-Tag */
2767 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
2768
2769 /* Aggregation mode */
2770 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
2771 ANA_AGGR_CFG_AC_DMAC_ENA |
2772 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
2773 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA |
2774 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA |
2775 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA,
2776 ANA_AGGR_CFG);
2777
2778 /* Set MAC age time to default value. The entry is aged after
2779 * 2*AGE_PERIOD
2780 */
2781 ocelot_write(ocelot,
2782 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
2783 ANA_AUTOAGE);
2784
2785 /* Disable learning for frames discarded by VLAN ingress filtering */
2786 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
2787
2788 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
2789 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
2790 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
2791
2792 /* Setup flooding PGIDs */
2793 for (i = 0; i < ocelot->num_flooding_pgids; i++)
2794 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
2795 ANA_FLOODING_FLD_BROADCAST(PGID_BC) |
2796 ANA_FLOODING_FLD_UNICAST(PGID_UC),
2797 ANA_FLOODING, i);
2798 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
2799 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
2800 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
2801 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
2802 ANA_FLOODING_IPMC);
2803
2804 for (port = 0; port < ocelot->num_phys_ports; port++) {
2805 /* Transmit the frame to the local port. */
2806 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
2807 /* Do not forward BPDU frames to the front ports. */
2808 ocelot_write_gix(ocelot,
2809 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
2810 ANA_PORT_CPU_FWD_BPDU_CFG,
2811 port);
2812 /* Ensure bridging is disabled */
2813 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
2814 }
2815
2816 for_each_nonreserved_multicast_dest_pgid(ocelot, i) {
2817 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
2818
2819 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
2820 }
2821
2822 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE);
2823
2824 /* Allow broadcast and unknown L2 multicast to the CPU. */
2825 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2826 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2827 ANA_PGID_PGID, PGID_MC);
2828 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2829 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2830 ANA_PGID_PGID, PGID_BC);
2831 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
2832 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
2833
2834 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
2835 * registers endianness.
2836 */
2837 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
2838 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
2839 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
2840 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
2841 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
2842 ANA_CPUQ_CFG_CPUQ_LRN(2) |
2843 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
2844 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
2845 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
2846 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
2847 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
2848 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
2849 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
2850 for (i = 0; i < 16; i++)
2851 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
2852 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
2853 ANA_CPUQ_8021_CFG, i);
2854
2855 return 0;
2856}
2857EXPORT_SYMBOL(ocelot_init);
2858
2859void ocelot_deinit(struct ocelot *ocelot)
2860{
2861 ocelot_stats_deinit(ocelot);
2862 destroy_workqueue(ocelot->owq);
2863}
2864EXPORT_SYMBOL(ocelot_deinit);
2865
2866void ocelot_deinit_port(struct ocelot *ocelot, int port)
2867{
2868 struct ocelot_port *ocelot_port = ocelot->ports[port];
2869
2870 skb_queue_purge(&ocelot_port->tx_skbs);
2871}
2872EXPORT_SYMBOL(ocelot_deinit_port);
2873
2874MODULE_LICENSE("Dual MIT/GPL");