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1/* SPDX-License-Identifier: GPL-2.0+ */
2/* Microchip Sparx5 Switch driver
3 *
4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
5 */
6
7#ifndef __SPARX5_PORT_H__
8#define __SPARX5_PORT_H__
9
10#include "sparx5_main.h"
11
12/* Port PCP rewrite mode */
13#define SPARX5_PORT_REW_TAG_CTRL_CLASSIFIED 0
14#define SPARX5_PORT_REW_TAG_CTRL_DEFAULT 1
15#define SPARX5_PORT_REW_TAG_CTRL_MAPPED 2
16
17/* Port DSCP rewrite mode */
18#define SPARX5_PORT_REW_DSCP_NONE 0
19#define SPARX5_PORT_REW_DSCP_IF_ZERO 1
20#define SPARX5_PORT_REW_DSCP_SELECTED 2
21#define SPARX5_PORT_REW_DSCP_ALL 3
22
23static inline bool sparx5_port_is_2g5(int portno)
24{
25 return portno >= 16 && portno <= 47;
26}
27
28static inline bool sparx5_port_is_5g(int portno)
29{
30 return portno <= 11 || portno == 64;
31}
32
33static inline bool sparx5_port_is_10g(int portno)
34{
35 return (portno >= 12 && portno <= 15) || (portno >= 48 && portno <= 55);
36}
37
38static inline bool sparx5_port_is_25g(int portno)
39{
40 return portno >= 56 && portno <= 63;
41}
42
43static inline u32 sparx5_to_high_dev(int port)
44{
45 if (sparx5_port_is_5g(port))
46 return TARGET_DEV5G;
47 if (sparx5_port_is_10g(port))
48 return TARGET_DEV10G;
49 return TARGET_DEV25G;
50}
51
52static inline u32 sparx5_to_pcs_dev(int port)
53{
54 if (sparx5_port_is_5g(port))
55 return TARGET_PCS5G_BR;
56 if (sparx5_port_is_10g(port))
57 return TARGET_PCS10G_BR;
58 return TARGET_PCS25G_BR;
59}
60
61static inline int sparx5_port_dev_index(int port)
62{
63 if (sparx5_port_is_2g5(port))
64 return port;
65 if (sparx5_port_is_5g(port))
66 return (port <= 11 ? port : 12);
67 if (sparx5_port_is_10g(port))
68 return (port >= 12 && port <= 15) ?
69 port - 12 : port - 44;
70 return (port - 56);
71}
72
73int sparx5_port_init(struct sparx5 *sparx5,
74 struct sparx5_port *spx5_port,
75 struct sparx5_port_config *conf);
76
77int sparx5_port_config(struct sparx5 *sparx5,
78 struct sparx5_port *spx5_port,
79 struct sparx5_port_config *conf);
80
81int sparx5_port_pcs_set(struct sparx5 *sparx5,
82 struct sparx5_port *port,
83 struct sparx5_port_config *conf);
84
85int sparx5_serdes_set(struct sparx5 *sparx5,
86 struct sparx5_port *spx5_port,
87 struct sparx5_port_config *conf);
88
89struct sparx5_port_status {
90 bool link;
91 bool link_down;
92 int speed;
93 bool an_complete;
94 int duplex;
95 int pause;
96};
97
98int sparx5_get_port_status(struct sparx5 *sparx5,
99 struct sparx5_port *port,
100 struct sparx5_port_status *status);
101
102void sparx5_port_enable(struct sparx5_port *port, bool enable);
103int sparx5_port_fwd_urg(struct sparx5 *sparx5, u32 speed);
104
105#define SPARX5_PORT_QOS_PCP_COUNT 8
106#define SPARX5_PORT_QOS_DEI_COUNT 8
107#define SPARX5_PORT_QOS_PCP_DEI_COUNT \
108 (SPARX5_PORT_QOS_PCP_COUNT + SPARX5_PORT_QOS_DEI_COUNT)
109struct sparx5_port_qos_pcp_map {
110 u8 map[SPARX5_PORT_QOS_PCP_DEI_COUNT];
111};
112
113struct sparx5_port_qos_pcp_rewr_map {
114 u16 map[SPX5_PRIOS];
115};
116
117#define SPARX5_PORT_QOS_DP_NUM 4
118struct sparx5_port_qos_dscp_rewr_map {
119 u16 map[SPX5_PRIOS * SPARX5_PORT_QOS_DP_NUM];
120};
121
122#define SPARX5_PORT_QOS_DSCP_COUNT 64
123struct sparx5_port_qos_dscp_map {
124 u8 map[SPARX5_PORT_QOS_DSCP_COUNT];
125};
126
127struct sparx5_port_qos_pcp {
128 struct sparx5_port_qos_pcp_map map;
129 bool qos_enable;
130 bool dp_enable;
131};
132
133struct sparx5_port_qos_pcp_rewr {
134 struct sparx5_port_qos_pcp_rewr_map map;
135 bool enable;
136};
137
138struct sparx5_port_qos_dscp {
139 struct sparx5_port_qos_dscp_map map;
140 bool qos_enable;
141 bool dp_enable;
142};
143
144struct sparx5_port_qos_dscp_rewr {
145 struct sparx5_port_qos_dscp_rewr_map map;
146 bool enable;
147};
148
149struct sparx5_port_qos {
150 struct sparx5_port_qos_pcp pcp;
151 struct sparx5_port_qos_pcp_rewr pcp_rewr;
152 struct sparx5_port_qos_dscp dscp;
153 struct sparx5_port_qos_dscp_rewr dscp_rewr;
154 u8 default_prio;
155};
156
157int sparx5_port_qos_set(struct sparx5_port *port, struct sparx5_port_qos *qos);
158
159int sparx5_port_qos_pcp_set(const struct sparx5_port *port,
160 struct sparx5_port_qos_pcp *qos);
161
162int sparx5_port_qos_pcp_rewr_set(const struct sparx5_port *port,
163 struct sparx5_port_qos_pcp_rewr *qos);
164
165int sparx5_port_qos_dscp_set(const struct sparx5_port *port,
166 struct sparx5_port_qos_dscp *qos);
167
168void sparx5_port_qos_dscp_rewr_mode_set(const struct sparx5_port *port,
169 int mode);
170
171int sparx5_port_qos_dscp_rewr_set(const struct sparx5_port *port,
172 struct sparx5_port_qos_dscp_rewr *qos);
173
174int sparx5_port_qos_default_set(const struct sparx5_port *port,
175 const struct sparx5_port_qos *qos);
176
177#endif /* __SPARX5_PORT_H__ */
1/* SPDX-License-Identifier: GPL-2.0+ */
2/* Microchip Sparx5 Switch driver
3 *
4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
5 */
6
7#ifndef __SPARX5_PORT_H__
8#define __SPARX5_PORT_H__
9
10#include "sparx5_main.h"
11
12static inline bool sparx5_port_is_2g5(int portno)
13{
14 return portno >= 16 && portno <= 47;
15}
16
17static inline bool sparx5_port_is_5g(int portno)
18{
19 return portno <= 11 || portno == 64;
20}
21
22static inline bool sparx5_port_is_10g(int portno)
23{
24 return (portno >= 12 && portno <= 15) || (portno >= 48 && portno <= 55);
25}
26
27static inline bool sparx5_port_is_25g(int portno)
28{
29 return portno >= 56 && portno <= 63;
30}
31
32static inline u32 sparx5_to_high_dev(int port)
33{
34 if (sparx5_port_is_5g(port))
35 return TARGET_DEV5G;
36 if (sparx5_port_is_10g(port))
37 return TARGET_DEV10G;
38 return TARGET_DEV25G;
39}
40
41static inline u32 sparx5_to_pcs_dev(int port)
42{
43 if (sparx5_port_is_5g(port))
44 return TARGET_PCS5G_BR;
45 if (sparx5_port_is_10g(port))
46 return TARGET_PCS10G_BR;
47 return TARGET_PCS25G_BR;
48}
49
50static inline int sparx5_port_dev_index(int port)
51{
52 if (sparx5_port_is_2g5(port))
53 return port;
54 if (sparx5_port_is_5g(port))
55 return (port <= 11 ? port : 12);
56 if (sparx5_port_is_10g(port))
57 return (port >= 12 && port <= 15) ?
58 port - 12 : port - 44;
59 return (port - 56);
60}
61
62int sparx5_port_init(struct sparx5 *sparx5,
63 struct sparx5_port *spx5_port,
64 struct sparx5_port_config *conf);
65
66int sparx5_port_config(struct sparx5 *sparx5,
67 struct sparx5_port *spx5_port,
68 struct sparx5_port_config *conf);
69
70int sparx5_port_pcs_set(struct sparx5 *sparx5,
71 struct sparx5_port *port,
72 struct sparx5_port_config *conf);
73
74int sparx5_serdes_set(struct sparx5 *sparx5,
75 struct sparx5_port *spx5_port,
76 struct sparx5_port_config *conf);
77
78struct sparx5_port_status {
79 bool link;
80 bool link_down;
81 int speed;
82 bool an_complete;
83 int duplex;
84 int pause;
85};
86
87int sparx5_get_port_status(struct sparx5 *sparx5,
88 struct sparx5_port *port,
89 struct sparx5_port_status *status);
90
91void sparx5_port_enable(struct sparx5_port *port, bool enable);
92int sparx5_port_fwd_urg(struct sparx5 *sparx5, u32 speed);
93
94#define SPARX5_PORT_QOS_PCP_COUNT 8
95#define SPARX5_PORT_QOS_DEI_COUNT 8
96#define SPARX5_PORT_QOS_PCP_DEI_COUNT \
97 (SPARX5_PORT_QOS_PCP_COUNT + SPARX5_PORT_QOS_DEI_COUNT)
98struct sparx5_port_qos_pcp_map {
99 u8 map[SPARX5_PORT_QOS_PCP_DEI_COUNT];
100};
101
102#define SPARX5_PORT_QOS_DSCP_COUNT 64
103struct sparx5_port_qos_dscp_map {
104 u8 map[SPARX5_PORT_QOS_DSCP_COUNT];
105};
106
107struct sparx5_port_qos_pcp {
108 struct sparx5_port_qos_pcp_map map;
109 bool qos_enable;
110 bool dp_enable;
111};
112
113struct sparx5_port_qos_dscp {
114 struct sparx5_port_qos_dscp_map map;
115 bool qos_enable;
116 bool dp_enable;
117};
118
119struct sparx5_port_qos {
120 struct sparx5_port_qos_pcp pcp;
121 struct sparx5_port_qos_dscp dscp;
122 u8 default_prio;
123};
124
125int sparx5_port_qos_set(struct sparx5_port *port, struct sparx5_port_qos *qos);
126
127int sparx5_port_qos_pcp_set(const struct sparx5_port *port,
128 struct sparx5_port_qos_pcp *qos);
129
130int sparx5_port_qos_dscp_set(const struct sparx5_port *port,
131 struct sparx5_port_qos_dscp *qos);
132
133int sparx5_port_qos_default_set(const struct sparx5_port *port,
134 const struct sparx5_port_qos *qos);
135
136#endif /* __SPARX5_PORT_H__ */