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1/* SPDX-License-Identifier: GPL-2.0+ */
2/* Copyright (C) 2018 Microchip Technology Inc. */
3
4#ifndef _LAN743X_H
5#define _LAN743X_H
6
7#include <linux/phy.h>
8#include "lan743x_ptp.h"
9
10#define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>"
11#define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver"
12#define DRIVER_NAME "lan743x"
13
14/* Register Definitions */
15#define ID_REV (0x00)
16#define ID_REV_ID_MASK_ (0xFFFF0000)
17#define ID_REV_ID_LAN7430_ (0x74300000)
18#define ID_REV_ID_LAN7431_ (0x74310000)
19#define ID_REV_ID_LAN743X_ (0x74300000)
20#define ID_REV_ID_A011_ (0xA0110000) // PCI11010
21#define ID_REV_ID_A041_ (0xA0410000) // PCI11414
22#define ID_REV_ID_A0X1_ (0xA0010000)
23#define ID_REV_IS_VALID_CHIP_ID_(id_rev) \
24 ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \
25 (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_))
26#define ID_REV_CHIP_REV_MASK_ (0x0000FFFF)
27#define ID_REV_CHIP_REV_A0_ (0x00000000)
28#define ID_REV_CHIP_REV_B0_ (0x00000010)
29
30#define FPGA_REV (0x04)
31#define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF)
32#define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF)
33#define FPGA_SGMII_OP BIT(24)
34
35#define STRAP_READ (0x0C)
36#define STRAP_READ_USE_SGMII_EN_ BIT(22)
37#define STRAP_READ_SGMII_EN_ BIT(6)
38#define STRAP_READ_SGMII_REFCLK_ BIT(5)
39#define STRAP_READ_SGMII_2_5G_ BIT(4)
40#define STRAP_READ_BASE_X_ BIT(3)
41#define STRAP_READ_RGMII_TXC_DELAY_EN_ BIT(2)
42#define STRAP_READ_RGMII_RXC_DELAY_EN_ BIT(1)
43#define STRAP_READ_ADV_PM_DISABLE_ BIT(0)
44
45#define HW_CFG (0x010)
46#define HW_CFG_RST_PROTECT_PCIE_ BIT(19)
47#define HW_CFG_HOT_RESET_DIS_ BIT(15)
48#define HW_CFG_D3_VAUX_OVR_ BIT(14)
49#define HW_CFG_D3_RESET_DIS_ BIT(13)
50#define HW_CFG_RST_PROTECT_ BIT(12)
51#define HW_CFG_RELOAD_TYPE_ALL_ (0x00000FC0)
52#define HW_CFG_EE_OTP_RELOAD_ BIT(4)
53#define HW_CFG_LRST_ BIT(1)
54
55#define PMT_CTL (0x014)
56#define PMT_CTL_ETH_PHY_D3_COLD_OVR_ BIT(27)
57#define PMT_CTL_MAC_D3_RX_CLK_OVR_ BIT(25)
58#define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_ BIT(24)
59#define PMT_CTL_ETH_PHY_D3_OVR_ BIT(23)
60#define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ BIT(18)
61#define PMT_CTL_GPIO_WAKEUP_EN_ BIT(15)
62#define PMT_CTL_EEE_WAKEUP_EN_ BIT(13)
63#define PMT_CTL_READY_ BIT(7)
64#define PMT_CTL_ETH_PHY_RST_ BIT(4)
65#define PMT_CTL_WOL_EN_ BIT(3)
66#define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2)
67#define PMT_CTL_WUPS_MASK_ (0x00000003)
68
69#define DP_SEL (0x024)
70#define DP_SEL_DPRDY_ BIT(31)
71#define DP_SEL_MASK_ (0x0000001F)
72#define DP_SEL_RFE_RAM (0x00000001)
73
74#define DP_SEL_VHF_HASH_LEN (16)
75#define DP_SEL_VHF_VLAN_LEN (128)
76
77#define DP_CMD (0x028)
78#define DP_CMD_WRITE_ (0x00000001)
79
80#define DP_ADDR (0x02C)
81
82#define DP_DATA_0 (0x030)
83
84#define E2P_CMD (0x040)
85#define E2P_CMD_EPC_BUSY_ BIT(31)
86#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000)
87#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000)
88#define E2P_CMD_EPC_CMD_READ_ (0x00000000)
89#define E2P_CMD_EPC_TIMEOUT_ BIT(10)
90#define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF)
91
92#define E2P_DATA (0x044)
93
94/* Hearthstone top level & System Reg Addresses */
95#define ETH_CTRL_REG_ADDR_BASE (0x0000)
96#define ETH_SYS_REG_ADDR_BASE (0x4000)
97#define CONFIG_REG_ADDR_BASE (0x0000)
98#define ETH_EEPROM_REG_ADDR_BASE (0x0E00)
99#define ETH_OTP_REG_ADDR_BASE (0x1000)
100#define GEN_SYS_CONFIG_LOAD_STARTED_REG (0x0078)
101#define ETH_SYS_CONFIG_LOAD_STARTED_REG (ETH_SYS_REG_ADDR_BASE + \
102 CONFIG_REG_ADDR_BASE + \
103 GEN_SYS_CONFIG_LOAD_STARTED_REG)
104#define GEN_SYS_LOAD_STARTED_REG_ETH_ BIT(4)
105#define SYS_LOCK_REG (0x00A0)
106#define SYS_LOCK_REG_MAIN_LOCK_ BIT(7)
107#define SYS_LOCK_REG_GEN_PERI_LOCK_ BIT(5)
108#define SYS_LOCK_REG_SPI_PERI_LOCK_ BIT(4)
109#define SYS_LOCK_REG_SMBUS_PERI_LOCK_ BIT(3)
110#define SYS_LOCK_REG_UART_SS_LOCK_ BIT(2)
111#define SYS_LOCK_REG_ENET_SS_LOCK_ BIT(1)
112#define SYS_LOCK_REG_USB_SS_LOCK_ BIT(0)
113#define ETH_SYSTEM_SYS_LOCK_REG (ETH_SYS_REG_ADDR_BASE + \
114 CONFIG_REG_ADDR_BASE + \
115 SYS_LOCK_REG)
116#define HS_EEPROM_REG_ADDR_BASE (ETH_SYS_REG_ADDR_BASE + \
117 ETH_EEPROM_REG_ADDR_BASE)
118#define HS_E2P_CMD (HS_EEPROM_REG_ADDR_BASE + 0x0000)
119#define HS_E2P_CMD_EPC_BUSY_ BIT(31)
120#define HS_E2P_CMD_EPC_CMD_WRITE_ GENMASK(29, 28)
121#define HS_E2P_CMD_EPC_CMD_READ_ (0x0)
122#define HS_E2P_CMD_EPC_TIMEOUT_ BIT(17)
123#define HS_E2P_CMD_EPC_ADDR_MASK_ GENMASK(15, 0)
124#define HS_E2P_DATA (HS_EEPROM_REG_ADDR_BASE + 0x0004)
125#define HS_E2P_DATA_MASK_ GENMASK(7, 0)
126#define HS_E2P_CFG (HS_EEPROM_REG_ADDR_BASE + 0x0008)
127#define HS_E2P_CFG_I2C_PULSE_MASK_ GENMASK(19, 16)
128#define HS_E2P_CFG_EEPROM_SIZE_SEL_ BIT(12)
129#define HS_E2P_CFG_I2C_BAUD_RATE_MASK_ GENMASK(9, 8)
130#define HS_E2P_CFG_TEST_EEPR_TO_BYP_ BIT(0)
131#define HS_E2P_PAD_CTL (HS_EEPROM_REG_ADDR_BASE + 0x000C)
132
133#define GPIO_CFG0 (0x050)
134#define GPIO_CFG0_GPIO_DIR_BIT_(bit) BIT(16 + (bit))
135#define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit))
136
137#define GPIO_CFG1 (0x054)
138#define GPIO_CFG1_GPIOEN_BIT_(bit) BIT(16 + (bit))
139#define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit))
140
141#define GPIO_CFG2 (0x058)
142#define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit))
143
144#define GPIO_CFG3 (0x05C)
145#define GPIO_CFG3_1588_CH_SEL_BIT_(bit) BIT(16 + (bit))
146#define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit))
147
148#define FCT_RX_CTL (0xAC)
149#define FCT_RX_CTL_EN_(channel) BIT(28 + (channel))
150#define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel))
151#define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel))
152
153#define FCT_TX_CTL (0xC4)
154#define FCT_TX_CTL_EN_(channel) BIT(28 + (channel))
155#define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel))
156#define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel))
157
158#define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2))
159#define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00)
160#define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \
161 ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_)
162#define FCT_FLOW_CTL_REQ_EN_ BIT(7)
163#define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F)
164#define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \
165 ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_)
166
167#define MAC_CR (0x100)
168#define MAC_CR_MII_EN_ BIT(19)
169#define MAC_CR_EEE_EN_ BIT(17)
170#define MAC_CR_ADD_ BIT(12)
171#define MAC_CR_ASD_ BIT(11)
172#define MAC_CR_CNTR_RST_ BIT(5)
173#define MAC_CR_DPX_ BIT(3)
174#define MAC_CR_CFG_H_ BIT(2)
175#define MAC_CR_CFG_L_ BIT(1)
176#define MAC_CR_RST_ BIT(0)
177
178#define MAC_RX (0x104)
179#define MAC_RX_MAX_SIZE_SHIFT_ (16)
180#define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000)
181#define MAC_RX_RXD_ BIT(1)
182#define MAC_RX_RXEN_ BIT(0)
183
184#define MAC_TX (0x108)
185#define MAC_TX_TXD_ BIT(1)
186#define MAC_TX_TXEN_ BIT(0)
187
188#define MAC_FLOW (0x10C)
189#define MAC_FLOW_CR_TX_FCEN_ BIT(30)
190#define MAC_FLOW_CR_RX_FCEN_ BIT(29)
191#define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF)
192
193#define MAC_RX_ADDRH (0x118)
194
195#define MAC_RX_ADDRL (0x11C)
196
197#define MAC_MII_ACC (0x120)
198#define MAC_MII_ACC_MDC_CYCLE_SHIFT_ (16)
199#define MAC_MII_ACC_MDC_CYCLE_MASK_ (0x00070000)
200#define MAC_MII_ACC_MDC_CYCLE_2_5MHZ_ (0)
201#define MAC_MII_ACC_MDC_CYCLE_5MHZ_ (1)
202#define MAC_MII_ACC_MDC_CYCLE_12_5MHZ_ (2)
203#define MAC_MII_ACC_MDC_CYCLE_25MHZ_ (3)
204#define MAC_MII_ACC_MDC_CYCLE_1_25MHZ_ (4)
205#define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11)
206#define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800)
207#define MAC_MII_ACC_MIIRINDA_SHIFT_ (6)
208#define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0)
209#define MAC_MII_ACC_MII_READ_ (0x00000000)
210#define MAC_MII_ACC_MII_WRITE_ (0x00000002)
211#define MAC_MII_ACC_MII_BUSY_ BIT(0)
212
213#define MAC_MII_ACC_MIIMMD_SHIFT_ (6)
214#define MAC_MII_ACC_MIIMMD_MASK_ (0x000007C0)
215#define MAC_MII_ACC_MIICL45_ BIT(3)
216#define MAC_MII_ACC_MIICMD_MASK_ (0x00000006)
217#define MAC_MII_ACC_MIICMD_ADDR_ (0x00000000)
218#define MAC_MII_ACC_MIICMD_WRITE_ (0x00000002)
219#define MAC_MII_ACC_MIICMD_READ_ (0x00000004)
220#define MAC_MII_ACC_MIICMD_READ_INC_ (0x00000006)
221
222#define MAC_MII_DATA (0x124)
223
224#define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130)
225
226#define MAC_WUCSR (0x140)
227#define MAC_MP_SO_EN_ BIT(21)
228#define MAC_WUCSR_RFE_WAKE_EN_ BIT(14)
229#define MAC_WUCSR_PFDA_EN_ BIT(3)
230#define MAC_WUCSR_WAKE_EN_ BIT(2)
231#define MAC_WUCSR_MPEN_ BIT(1)
232#define MAC_WUCSR_BCST_EN_ BIT(0)
233
234#define MAC_WK_SRC (0x144)
235#define MAC_MP_SO_HI (0x148)
236#define MAC_MP_SO_LO (0x14C)
237
238#define MAC_WUF_CFG0 (0x150)
239#define MAC_NUM_OF_WUF_CFG (32)
240#define MAC_WUF_CFG_BEGIN (MAC_WUF_CFG0)
241#define MAC_WUF_CFG(index) (MAC_WUF_CFG_BEGIN + (4 * (index)))
242#define MAC_WUF_CFG_EN_ BIT(31)
243#define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000)
244#define MAC_WUF_CFG_TYPE_ALL_ (0x01000000)
245#define MAC_WUF_CFG_OFFSET_SHIFT_ (16)
246#define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF)
247
248#define MAC_WUF_MASK0_0 (0x200)
249#define MAC_WUF_MASK0_1 (0x204)
250#define MAC_WUF_MASK0_2 (0x208)
251#define MAC_WUF_MASK0_3 (0x20C)
252#define MAC_WUF_MASK0_BEGIN (MAC_WUF_MASK0_0)
253#define MAC_WUF_MASK1_BEGIN (MAC_WUF_MASK0_1)
254#define MAC_WUF_MASK2_BEGIN (MAC_WUF_MASK0_2)
255#define MAC_WUF_MASK3_BEGIN (MAC_WUF_MASK0_3)
256#define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index)))
257#define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index)))
258#define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index)))
259#define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index)))
260
261/* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */
262#define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x)))
263#define RFE_ADDR_FILT_HI_VALID_ BIT(31)
264
265/* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */
266#define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x)))
267
268#define RFE_CTL (0x508)
269#define RFE_CTL_TCP_UDP_COE_ BIT(12)
270#define RFE_CTL_IP_COE_ BIT(11)
271#define RFE_CTL_AB_ BIT(10)
272#define RFE_CTL_AM_ BIT(9)
273#define RFE_CTL_AU_ BIT(8)
274#define RFE_CTL_MCAST_HASH_ BIT(3)
275#define RFE_CTL_DA_PERFECT_ BIT(1)
276
277#define RFE_RSS_CFG (0x554)
278#define RFE_RSS_CFG_UDP_IPV6_EX_ BIT(16)
279#define RFE_RSS_CFG_TCP_IPV6_EX_ BIT(15)
280#define RFE_RSS_CFG_IPV6_EX_ BIT(14)
281#define RFE_RSS_CFG_UDP_IPV6_ BIT(13)
282#define RFE_RSS_CFG_TCP_IPV6_ BIT(12)
283#define RFE_RSS_CFG_IPV6_ BIT(11)
284#define RFE_RSS_CFG_UDP_IPV4_ BIT(10)
285#define RFE_RSS_CFG_TCP_IPV4_ BIT(9)
286#define RFE_RSS_CFG_IPV4_ BIT(8)
287#define RFE_RSS_CFG_VALID_HASH_BITS_ (0x000000E0)
288#define RFE_RSS_CFG_RSS_QUEUE_ENABLE_ BIT(2)
289#define RFE_RSS_CFG_RSS_HASH_STORE_ BIT(1)
290#define RFE_RSS_CFG_RSS_ENABLE_ BIT(0)
291
292#define RFE_HASH_KEY(index) (0x558 + (index << 2))
293
294#define RFE_INDX(index) (0x580 + (index << 2))
295
296#define MAC_WUCSR2 (0x600)
297
298#define SGMII_ACC (0x720)
299#define SGMII_ACC_SGMII_BZY_ BIT(31)
300#define SGMII_ACC_SGMII_WR_ BIT(30)
301#define SGMII_ACC_SGMII_MMD_SHIFT_ (16)
302#define SGMII_ACC_SGMII_MMD_MASK_ GENMASK(20, 16)
303#define SGMII_ACC_SGMII_MMD_VSR_ BIT(15)
304#define SGMII_ACC_SGMII_ADDR_SHIFT_ (0)
305#define SGMII_ACC_SGMII_ADDR_MASK_ GENMASK(15, 0)
306#define SGMII_DATA (0x724)
307#define SGMII_DATA_SHIFT_ (0)
308#define SGMII_DATA_MASK_ GENMASK(15, 0)
309#define SGMII_CTL (0x728)
310#define SGMII_CTL_SGMII_ENABLE_ BIT(31)
311#define SGMII_CTL_LINK_STATUS_SOURCE_ BIT(8)
312#define SGMII_CTL_SGMII_POWER_DN_ BIT(1)
313
314/* Vendor Specific SGMII MMD details */
315#define SR_VSMMD_PCS_ID1 0x0004
316#define SR_VSMMD_PCS_ID2 0x0005
317#define SR_VSMMD_STS 0x0008
318#define SR_VSMMD_CTRL 0x0009
319
320#define VR_MII_DIG_CTRL1 0x8000
321#define VR_MII_DIG_CTRL1_VR_RST_ BIT(15)
322#define VR_MII_DIG_CTRL1_R2TLBE_ BIT(14)
323#define VR_MII_DIG_CTRL1_EN_VSMMD1_ BIT(13)
324#define VR_MII_DIG_CTRL1_CS_EN_ BIT(10)
325#define VR_MII_DIG_CTRL1_MAC_AUTO_SW_ BIT(9)
326#define VR_MII_DIG_CTRL1_INIT_ BIT(8)
327#define VR_MII_DIG_CTRL1_DTXLANED_0_ BIT(4)
328#define VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE_ BIT(3)
329#define VR_MII_DIG_CTRL1_EN_2_5G_MODE_ BIT(2)
330#define VR_MII_DIG_CTRL1_BYP_PWRUP_ BIT(1)
331#define VR_MII_DIG_CTRL1_PHY_MODE_CTRL_ BIT(0)
332#define VR_MII_AN_CTRL 0x8001
333#define VR_MII_AN_CTRL_MII_CTRL_ BIT(8)
334#define VR_MII_AN_CTRL_SGMII_LINK_STS_ BIT(4)
335#define VR_MII_AN_CTRL_TX_CONFIG_ BIT(3)
336#define VR_MII_AN_CTRL_1000BASE_X_ (0)
337#define VR_MII_AN_CTRL_SGMII_MODE_ (2)
338#define VR_MII_AN_CTRL_QSGMII_MODE_ (3)
339#define VR_MII_AN_CTRL_PCS_MODE_SHIFT_ (1)
340#define VR_MII_AN_CTRL_PCS_MODE_MASK_ GENMASK(2, 1)
341#define VR_MII_AN_CTRL_MII_AN_INTR_EN_ BIT(0)
342#define VR_MII_AN_INTR_STS 0x8002
343#define VR_MII_AN_INTR_STS_LINK_UP_ BIT(4)
344#define VR_MII_AN_INTR_STS_SPEED_MASK_ GENMASK(3, 2)
345#define VR_MII_AN_INTR_STS_1000_MBPS_ BIT(3)
346#define VR_MII_AN_INTR_STS_100_MBPS_ BIT(2)
347#define VR_MII_AN_INTR_STS_10_MBPS_ (0)
348#define VR_MII_AN_INTR_STS_FDX_ BIT(1)
349#define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_ BIT(0)
350
351#define VR_MII_LINK_TIMER_CTRL 0x800A
352#define VR_MII_DIG_STS 0x8010
353#define VR_MII_DIG_STS_PSEQ_STATE_MASK_ GENMASK(4, 2)
354#define VR_MII_DIG_STS_PSEQ_STATE_POS_ (2)
355#define VR_MII_GEN2_4_MPLL_CTRL0 0x8078
356#define VR_MII_MPLL_CTRL0_REF_CLK_DIV2_ BIT(12)
357#define VR_MII_MPLL_CTRL0_USE_REFCLK_PAD_ BIT(4)
358#define VR_MII_GEN2_4_MPLL_CTRL1 0x8079
359#define VR_MII_MPLL_CTRL1_MPLL_MULTIPLIER_ GENMASK(6, 0)
360#define VR_MII_BAUD_RATE_3P125GBPS (3125)
361#define VR_MII_BAUD_RATE_1P25GBPS (1250)
362#define VR_MII_MPLL_MULTIPLIER_125 (125)
363#define VR_MII_MPLL_MULTIPLIER_100 (100)
364#define VR_MII_MPLL_MULTIPLIER_50 (50)
365#define VR_MII_MPLL_MULTIPLIER_40 (40)
366#define VR_MII_GEN2_4_MISC_CTRL1 0x809A
367#define VR_MII_CTRL1_RX_RATE_0_MASK_ GENMASK(3, 2)
368#define VR_MII_CTRL1_RX_RATE_0_SHIFT_ (2)
369#define VR_MII_CTRL1_TX_RATE_0_MASK_ GENMASK(1, 0)
370#define VR_MII_MPLL_BAUD_CLK (0)
371#define VR_MII_MPLL_BAUD_CLK_DIV_2 (1)
372#define VR_MII_MPLL_BAUD_CLK_DIV_4 (2)
373
374#define INT_STS (0x780)
375#define INT_BIT_DMA_RX_(channel) BIT(24 + (channel))
376#define INT_BIT_ALL_RX_ (0x0F000000)
377#define INT_BIT_DMA_TX_(channel) BIT(16 + (channel))
378#define INT_BIT_ALL_TX_ (0x000F0000)
379#define INT_BIT_SW_GP_ BIT(9)
380#define INT_BIT_1588_ BIT(7)
381#define INT_BIT_ALL_OTHER_ (INT_BIT_SW_GP_ | INT_BIT_1588_)
382#define INT_BIT_MAS_ BIT(0)
383
384#define INT_SET (0x784)
385
386#define INT_EN_SET (0x788)
387
388#define INT_EN_CLR (0x78C)
389
390#define INT_STS_R2C (0x790)
391
392#define INT_VEC_EN_SET (0x794)
393#define INT_VEC_EN_CLR (0x798)
394#define INT_VEC_EN_AUTO_CLR (0x79C)
395#define INT_VEC_EN_(vector_index) BIT(0 + vector_index)
396
397#define INT_VEC_MAP0 (0x7A0)
398#define INT_VEC_MAP0_RX_VEC_(channel, vector) \
399 (((u32)(vector)) << ((channel) << 2))
400
401#define INT_VEC_MAP1 (0x7A4)
402#define INT_VEC_MAP1_TX_VEC_(channel, vector) \
403 (((u32)(vector)) << ((channel) << 2))
404
405#define INT_VEC_MAP2 (0x7A8)
406
407#define INT_MOD_MAP0 (0x7B0)
408
409#define INT_MOD_MAP1 (0x7B4)
410
411#define INT_MOD_MAP2 (0x7B8)
412
413#define INT_MOD_CFG0 (0x7C0)
414#define INT_MOD_CFG1 (0x7C4)
415#define INT_MOD_CFG2 (0x7C8)
416#define INT_MOD_CFG3 (0x7CC)
417#define INT_MOD_CFG4 (0x7D0)
418#define INT_MOD_CFG5 (0x7D4)
419#define INT_MOD_CFG6 (0x7D8)
420#define INT_MOD_CFG7 (0x7DC)
421#define INT_MOD_CFG8 (0x7E0)
422#define INT_MOD_CFG9 (0x7E4)
423
424#define PTP_CMD_CTL (0x0A00)
425#define PTP_CMD_CTL_PTP_LTC_TARGET_READ_ BIT(13)
426#define PTP_CMD_CTL_PTP_CLK_STP_NSEC_ BIT(6)
427#define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_ BIT(5)
428#define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4)
429#define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3)
430#define PTP_CMD_CTL_PTP_ENABLE_ BIT(2)
431#define PTP_CMD_CTL_PTP_DISABLE_ BIT(1)
432#define PTP_CMD_CTL_PTP_RESET_ BIT(0)
433#define PTP_GENERAL_CONFIG (0x0A04)
434#define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \
435 (0x7 << (1 + ((channel) << 2)))
436#define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0)
437#define PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (1)
438#define PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (2)
439#define PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (3)
440#define PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (4)
441#define PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (5)
442#define PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGGLE_ (6)
443#define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \
444 (((value) & 0x7) << (1 + ((channel) << 2)))
445#define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2))
446
447#define HS_PTP_GENERAL_CONFIG (0x0A04)
448#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \
449 (0xf << (4 + ((channel) << 2)))
450#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0)
451#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_500NS_ (1)
452#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1US_ (2)
453#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_5US_ (3)
454#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (4)
455#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_50US_ (5)
456#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (6)
457#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_500US_ (7)
458#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (8)
459#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_5MS_ (9)
460#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (10)
461#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_50MS_ (11)
462#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100MS_ (12)
463#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (13)
464#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGG_ (14)
465#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_INT_ (15)
466#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \
467 (((value) & 0xf) << (4 + ((channel) << 2)))
468#define HS_PTP_GENERAL_CONFIG_EVENT_POL_X_(channel) (BIT(1 + ((channel) * 2)))
469#define HS_PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) * 2))
470
471#define PTP_INT_STS (0x0A08)
472#define PTP_INT_IO_FE_MASK_ GENMASK(31, 24)
473#define PTP_INT_IO_FE_SHIFT_ (24)
474#define PTP_INT_IO_FE_SET_(channel) BIT(24 + (channel))
475#define PTP_INT_IO_RE_MASK_ GENMASK(23, 16)
476#define PTP_INT_IO_RE_SHIFT_ (16)
477#define PTP_INT_IO_RE_SET_(channel) BIT(16 + (channel))
478#define PTP_INT_TX_TS_OVRFL_INT_ BIT(14)
479#define PTP_INT_TX_SWTS_ERR_INT_ BIT(13)
480#define PTP_INT_TX_TS_INT_ BIT(12)
481#define PTP_INT_RX_TS_OVRFL_INT_ BIT(9)
482#define PTP_INT_RX_TS_INT_ BIT(8)
483#define PTP_INT_TIMER_INT_B_ BIT(1)
484#define PTP_INT_TIMER_INT_A_ BIT(0)
485#define PTP_INT_EN_SET (0x0A0C)
486#define PTP_INT_EN_FE_EN_SET_(channel) BIT(24 + (channel))
487#define PTP_INT_EN_RE_EN_SET_(channel) BIT(16 + (channel))
488#define PTP_INT_EN_TIMER_SET_(channel) BIT(channel)
489#define PTP_INT_EN_CLR (0x0A10)
490#define PTP_INT_EN_FE_EN_CLR_(channel) BIT(24 + (channel))
491#define PTP_INT_EN_RE_EN_CLR_(channel) BIT(16 + (channel))
492#define PTP_INT_BIT_TX_SWTS_ERR_ BIT(13)
493#define PTP_INT_BIT_TX_TS_ BIT(12)
494#define PTP_INT_BIT_TIMER_B_ BIT(1)
495#define PTP_INT_BIT_TIMER_A_ BIT(0)
496
497#define PTP_CLOCK_SEC (0x0A14)
498#define PTP_CLOCK_NS (0x0A18)
499#define PTP_CLOCK_SUBNS (0x0A1C)
500#define PTP_CLOCK_RATE_ADJ (0x0A20)
501#define PTP_CLOCK_RATE_ADJ_DIR_ BIT(31)
502#define PTP_CLOCK_STEP_ADJ (0x0A2C)
503#define PTP_CLOCK_STEP_ADJ_DIR_ BIT(31)
504#define PTP_CLOCK_STEP_ADJ_VALUE_MASK_ (0x3FFFFFFF)
505#define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4))
506#define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4))
507#define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4))
508#define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4))
509#define PTP_LTC_SET_SEC_HI (0x0A50)
510#define PTP_LTC_SET_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0)
511#define PTP_VERSION (0x0A54)
512#define PTP_VERSION_TX_UP_MASK_ GENMASK(31, 24)
513#define PTP_VERSION_TX_LO_MASK_ GENMASK(23, 16)
514#define PTP_VERSION_RX_UP_MASK_ GENMASK(15, 8)
515#define PTP_VERSION_RX_LO_MASK_ GENMASK(7, 0)
516#define PTP_IO_SEL (0x0A58)
517#define PTP_IO_SEL_MASK_ GENMASK(10, 8)
518#define PTP_IO_SEL_SHIFT_ (8)
519#define PTP_LATENCY (0x0A5C)
520#define PTP_LATENCY_TX_SET_(tx_latency) (((u32)(tx_latency)) << 16)
521#define PTP_LATENCY_RX_SET_(rx_latency) \
522 (((u32)(rx_latency)) & 0x0000FFFF)
523#define PTP_CAP_INFO (0x0A60)
524#define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4)
525#define PTP_RX_TS_CFG (0x0A68)
526#define PTP_RX_TS_CFG_EVENT_MSGS_ GENMASK(3, 0)
527
528#define PTP_TX_MOD (0x0AA4)
529#define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ (0x10000000)
530
531#define PTP_TX_MOD2 (0x0AA8)
532#define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_ (0x00000001)
533
534#define PTP_TX_EGRESS_SEC (0x0AAC)
535#define PTP_TX_EGRESS_NS (0x0AB0)
536#define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_ (0xC0000000)
537#define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_ (0x00000000)
538#define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_ (0x40000000)
539#define PTP_TX_EGRESS_NS_TS_NS_MASK_ (0x3FFFFFFF)
540
541#define PTP_TX_MSG_HEADER (0x0AB4)
542#define PTP_TX_MSG_HEADER_MSG_TYPE_ (0x000F0000)
543#define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_ (0x00000000)
544
545#define PTP_TX_CAP_INFO (0x0AB8)
546#define PTP_TX_CAP_INFO_TX_CH_MASK_ GENMASK(1, 0)
547#define PTP_TX_DOMAIN (0x0ABC)
548#define PTP_TX_DOMAIN_MASK_ GENMASK(23, 16)
549#define PTP_TX_DOMAIN_RANGE_EN_ BIT(15)
550#define PTP_TX_DOMAIN_RANGE_MASK_ GENMASK(7, 0)
551#define PTP_TX_SDOID (0x0AC0)
552#define PTP_TX_SDOID_MASK_ GENMASK(23, 16)
553#define PTP_TX_SDOID_RANGE_EN_ BIT(15)
554#define PTP_TX_SDOID_11_0_MASK_ GENMASK(7, 0)
555#define PTP_IO_CAP_CONFIG (0x0AC4)
556#define PTP_IO_CAP_CONFIG_LOCK_FE_(channel) BIT(24 + (channel))
557#define PTP_IO_CAP_CONFIG_LOCK_RE_(channel) BIT(16 + (channel))
558#define PTP_IO_CAP_CONFIG_FE_CAP_EN_(channel) BIT(8 + (channel))
559#define PTP_IO_CAP_CONFIG_RE_CAP_EN_(channel) BIT(0 + (channel))
560#define PTP_IO_RE_LTC_SEC_CAP_X (0x0AC8)
561#define PTP_IO_RE_LTC_NS_CAP_X (0x0ACC)
562#define PTP_IO_FE_LTC_SEC_CAP_X (0x0AD0)
563#define PTP_IO_FE_LTC_NS_CAP_X (0x0AD4)
564#define PTP_IO_EVENT_OUTPUT_CFG (0x0AD8)
565#define PTP_IO_EVENT_OUTPUT_CFG_SEL_(channel) BIT(16 + (channel))
566#define PTP_IO_EVENT_OUTPUT_CFG_EN_(channel) BIT(0 + (channel))
567#define PTP_IO_PIN_CFG (0x0ADC)
568#define PTP_IO_PIN_CFG_OBUF_TYPE_(channel) BIT(0 + (channel))
569#define PTP_LTC_RD_SEC_HI (0x0AF0)
570#define PTP_LTC_RD_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0)
571#define PTP_LTC_RD_SEC_LO (0x0AF4)
572#define PTP_LTC_RD_NS (0x0AF8)
573#define PTP_LTC_RD_NS_29_0_MASK_ GENMASK(29, 0)
574#define PTP_LTC_RD_SUBNS (0x0AFC)
575#define PTP_RX_USER_MAC_HI (0x0B00)
576#define PTP_RX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0)
577#define PTP_RX_USER_MAC_LO (0x0B04)
578#define PTP_RX_USER_IP_ADDR_0 (0x0B20)
579#define PTP_RX_USER_IP_ADDR_1 (0x0B24)
580#define PTP_RX_USER_IP_ADDR_2 (0x0B28)
581#define PTP_RX_USER_IP_ADDR_3 (0x0B2C)
582#define PTP_RX_USER_IP_MASK_0 (0x0B30)
583#define PTP_RX_USER_IP_MASK_1 (0x0B34)
584#define PTP_RX_USER_IP_MASK_2 (0x0B38)
585#define PTP_RX_USER_IP_MASK_3 (0x0B3C)
586#define PTP_TX_USER_MAC_HI (0x0B40)
587#define PTP_TX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0)
588#define PTP_TX_USER_MAC_LO (0x0B44)
589#define PTP_TX_USER_IP_ADDR_0 (0x0B60)
590#define PTP_TX_USER_IP_ADDR_1 (0x0B64)
591#define PTP_TX_USER_IP_ADDR_2 (0x0B68)
592#define PTP_TX_USER_IP_ADDR_3 (0x0B6C)
593#define PTP_TX_USER_IP_MASK_0 (0x0B70)
594#define PTP_TX_USER_IP_MASK_1 (0x0B74)
595#define PTP_TX_USER_IP_MASK_2 (0x0B78)
596#define PTP_TX_USER_IP_MASK_3 (0x0B7C)
597
598#define DMAC_CFG (0xC00)
599#define DMAC_CFG_COAL_EN_ BIT(16)
600#define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000)
601#define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070)
602#define DMAC_CFG_MAX_READ_REQ_SET_(val) \
603 ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_)
604#define DMAC_CFG_MAX_DSPACE_16_ (0x00000000)
605#define DMAC_CFG_MAX_DSPACE_32_ (0x00000001)
606#define DMAC_CFG_MAX_DSPACE_64_ BIT(1)
607#define DMAC_CFG_MAX_DSPACE_128_ (0x00000003)
608
609#define DMAC_COAL_CFG (0xC04)
610#define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000)
611#define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \
612 ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_)
613#define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19)
614#define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18)
615#define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17)
616#define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16)
617#define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00)
618#define DMAC_COAL_CFG_TX_THRES_SET_(val) \
619 ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_)
620#define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF)
621#define DMAC_COAL_CFG_RX_THRES_SET_(val) \
622 (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_)
623
624#define DMAC_OBFF_CFG (0xC08)
625#define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00)
626#define DMAC_OBFF_TX_THRES_SET_(val) \
627 ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_)
628#define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF)
629#define DMAC_OBFF_RX_THRES_SET_(val) \
630 (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_)
631
632#define DMAC_CMD (0xC0C)
633#define DMAC_CMD_SWR_ BIT(31)
634#define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel))
635#define DMAC_CMD_START_T_(channel) BIT(20 + (channel))
636#define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel))
637#define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel))
638#define DMAC_CMD_START_R_(channel) BIT(4 + (channel))
639#define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel))
640
641#define DMAC_INT_STS (0xC10)
642#define DMAC_INT_EN_SET (0xC14)
643#define DMAC_INT_EN_CLR (0xC18)
644#define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel))
645#define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel))
646
647#define RX_CFG_A(channel) (0xC40 + ((channel) << 6))
648#define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30)
649#define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000)
650#define RX_CFG_A_RX_WB_THRES_SET_(val) \
651 ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_)
652#define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000)
653#define RX_CFG_A_RX_PF_THRES_SET_(val) \
654 ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_)
655#define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00)
656#define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \
657 ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_)
658#define RX_CFG_A_RX_HP_WB_EN_ BIT(5)
659
660#define RX_CFG_B(channel) (0xC44 + ((channel) << 6))
661#define RX_CFG_B_TS_ALL_RX_ BIT(29)
662#define RX_CFG_B_TS_DESCR_EN_ BIT(28)
663#define RX_CFG_B_TS_NONE_ 0
664#define RX_CFG_B_TS_MASK_ (0xCFFFFFFF)
665#define RX_CFG_B_RX_PAD_MASK_ (0x03000000)
666#define RX_CFG_B_RX_PAD_0_ (0x00000000)
667#define RX_CFG_B_RX_PAD_2_ (0x02000000)
668#define RX_CFG_B_RDMABL_512_ (0x00040000)
669#define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF)
670
671#define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6))
672
673#define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6))
674
675#define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6))
676
677#define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6))
678
679#define RX_HEAD(channel) (0xC58 + ((channel) << 6))
680
681#define RX_TAIL(channel) (0xC5C + ((channel) << 6))
682#define RX_TAIL_SET_TOP_INT_EN_ BIT(30)
683#define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29)
684
685#define RX_CFG_C(channel) (0xC64 + ((channel) << 6))
686#define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6)
687#define RX_CFG_C_RX_INT_EN_R2C_ BIT(4)
688#define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3)
689#define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007)
690
691#define TX_CFG_A(channel) (0xD40 + ((channel) << 6))
692#define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30)
693#define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000)
694#define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000)
695#define TX_CFG_A_TX_PF_THRES_SET_(value) \
696 ((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_)
697#define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00)
698#define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \
699 ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_)
700#define TX_CFG_A_TX_HP_WB_EN_ BIT(5)
701#define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F)
702#define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \
703 (((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_)
704
705#define TX_CFG_B(channel) (0xD44 + ((channel) << 6))
706#define TX_CFG_B_TDMABL_512_ (0x00040000)
707#define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF)
708
709#define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6))
710
711#define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6))
712
713#define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6))
714
715#define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6))
716
717#define TX_HEAD(channel) (0xD58 + ((channel) << 6))
718
719#define TX_TAIL(channel) (0xD5C + ((channel) << 6))
720#define TX_TAIL_SET_DMAC_INT_EN_ BIT(31)
721#define TX_TAIL_SET_TOP_INT_EN_ BIT(30)
722#define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29)
723
724#define TX_CFG_C(channel) (0xD64 + ((channel) << 6))
725#define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6)
726#define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5)
727#define TX_CFG_C_TX_INT_EN_R2C_ BIT(4)
728#define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3)
729#define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007)
730
731#define OTP_PWR_DN (0x1000)
732#define OTP_PWR_DN_PWRDN_N_ BIT(0)
733
734#define OTP_ADDR_HIGH (0x1004)
735#define OTP_ADDR_LOW (0x1008)
736
737#define OTP_PRGM_DATA (0x1010)
738
739#define OTP_PRGM_MODE (0x1014)
740#define OTP_PRGM_MODE_BYTE_ BIT(0)
741
742#define OTP_READ_DATA (0x1018)
743
744#define OTP_FUNC_CMD (0x1020)
745#define OTP_FUNC_CMD_READ_ BIT(0)
746
747#define OTP_TST_CMD (0x1024)
748#define OTP_TST_CMD_PRGVRFY_ BIT(3)
749
750#define OTP_CMD_GO (0x1028)
751#define OTP_CMD_GO_GO_ BIT(0)
752
753#define OTP_STATUS (0x1030)
754#define OTP_STATUS_BUSY_ BIT(0)
755
756/* Hearthstone OTP block registers */
757#define HS_OTP_BLOCK_BASE (ETH_SYS_REG_ADDR_BASE + \
758 ETH_OTP_REG_ADDR_BASE)
759#define HS_OTP_PWR_DN (HS_OTP_BLOCK_BASE + 0x0)
760#define HS_OTP_ADDR_HIGH (HS_OTP_BLOCK_BASE + 0x4)
761#define HS_OTP_ADDR_LOW (HS_OTP_BLOCK_BASE + 0x8)
762#define HS_OTP_PRGM_DATA (HS_OTP_BLOCK_BASE + 0x10)
763#define HS_OTP_PRGM_MODE (HS_OTP_BLOCK_BASE + 0x14)
764#define HS_OTP_READ_DATA (HS_OTP_BLOCK_BASE + 0x18)
765#define HS_OTP_FUNC_CMD (HS_OTP_BLOCK_BASE + 0x20)
766#define HS_OTP_TST_CMD (HS_OTP_BLOCK_BASE + 0x24)
767#define HS_OTP_CMD_GO (HS_OTP_BLOCK_BASE + 0x28)
768#define HS_OTP_STATUS (HS_OTP_BLOCK_BASE + 0x30)
769
770/* MAC statistics registers */
771#define STAT_RX_FCS_ERRORS (0x1200)
772#define STAT_RX_ALIGNMENT_ERRORS (0x1204)
773#define STAT_RX_FRAGMENT_ERRORS (0x1208)
774#define STAT_RX_JABBER_ERRORS (0x120C)
775#define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210)
776#define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214)
777#define STAT_RX_DROPPED_FRAMES (0x1218)
778#define STAT_RX_UNICAST_BYTE_COUNT (0x121C)
779#define STAT_RX_BROADCAST_BYTE_COUNT (0x1220)
780#define STAT_RX_MULTICAST_BYTE_COUNT (0x1224)
781#define STAT_RX_UNICAST_FRAMES (0x1228)
782#define STAT_RX_BROADCAST_FRAMES (0x122C)
783#define STAT_RX_MULTICAST_FRAMES (0x1230)
784#define STAT_RX_PAUSE_FRAMES (0x1234)
785#define STAT_RX_64_BYTE_FRAMES (0x1238)
786#define STAT_RX_65_127_BYTE_FRAMES (0x123C)
787#define STAT_RX_128_255_BYTE_FRAMES (0x1240)
788#define STAT_RX_256_511_BYTES_FRAMES (0x1244)
789#define STAT_RX_512_1023_BYTE_FRAMES (0x1248)
790#define STAT_RX_1024_1518_BYTE_FRAMES (0x124C)
791#define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250)
792#define STAT_RX_TOTAL_FRAMES (0x1254)
793#define STAT_EEE_RX_LPI_TRANSITIONS (0x1258)
794#define STAT_EEE_RX_LPI_TIME (0x125C)
795#define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C)
796
797#define STAT_TX_FCS_ERRORS (0x1280)
798#define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284)
799#define STAT_TX_CARRIER_ERRORS (0x1288)
800#define STAT_TX_BAD_BYTE_COUNT (0x128C)
801#define STAT_TX_SINGLE_COLLISIONS (0x1290)
802#define STAT_TX_MULTIPLE_COLLISIONS (0x1294)
803#define STAT_TX_EXCESSIVE_COLLISION (0x1298)
804#define STAT_TX_LATE_COLLISIONS (0x129C)
805#define STAT_TX_UNICAST_BYTE_COUNT (0x12A0)
806#define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4)
807#define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8)
808#define STAT_TX_UNICAST_FRAMES (0x12AC)
809#define STAT_TX_BROADCAST_FRAMES (0x12B0)
810#define STAT_TX_MULTICAST_FRAMES (0x12B4)
811#define STAT_TX_PAUSE_FRAMES (0x12B8)
812#define STAT_TX_64_BYTE_FRAMES (0x12BC)
813#define STAT_TX_65_127_BYTE_FRAMES (0x12C0)
814#define STAT_TX_128_255_BYTE_FRAMES (0x12C4)
815#define STAT_TX_256_511_BYTES_FRAMES (0x12C8)
816#define STAT_TX_512_1023_BYTE_FRAMES (0x12CC)
817#define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0)
818#define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4)
819#define STAT_TX_TOTAL_FRAMES (0x12D8)
820#define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC)
821#define STAT_EEE_TX_LPI_TIME (0x12E0)
822#define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC)
823
824/* End of Register definitions */
825
826#define LAN743X_MAX_RX_CHANNELS (4)
827#define LAN743X_MAX_TX_CHANNELS (1)
828#define PCI11X1X_MAX_TX_CHANNELS (4)
829struct lan743x_adapter;
830
831#define LAN743X_USED_RX_CHANNELS (4)
832#define LAN743X_USED_TX_CHANNELS (1)
833#define PCI11X1X_USED_TX_CHANNELS (4)
834#define LAN743X_INT_MOD (400)
835
836#if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS)
837#error Invalid LAN743X_USED_RX_CHANNELS
838#endif
839#if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS)
840#error Invalid LAN743X_USED_TX_CHANNELS
841#endif
842#if (PCI11X1X_USED_TX_CHANNELS > PCI11X1X_MAX_TX_CHANNELS)
843#error Invalid PCI11X1X_USED_TX_CHANNELS
844#endif
845
846/* PCI */
847/* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */
848#define PCI_VENDOR_ID_SMSC PCI_VENDOR_ID_EFAR
849#define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430)
850#define PCI_DEVICE_ID_SMSC_LAN7431 (0x7431)
851#define PCI_DEVICE_ID_SMSC_A011 (0xA011)
852#define PCI_DEVICE_ID_SMSC_A041 (0xA041)
853
854#define PCI_CONFIG_LENGTH (0x1000)
855
856/* CSR */
857#define CSR_LENGTH (0x2000)
858
859#define LAN743X_CSR_FLAG_IS_A0 BIT(0)
860#define LAN743X_CSR_FLAG_IS_B0 BIT(1)
861#define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8)
862
863struct lan743x_csr {
864 u32 flags;
865 u8 __iomem *csr_address;
866 u32 id_rev;
867 u32 fpga_rev;
868};
869
870/* INTERRUPTS */
871typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags);
872
873#define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0)
874#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1)
875#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2)
876#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3)
877#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4)
878#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5)
879#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6)
880#define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7)
881#define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8)
882#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9)
883#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10)
884#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11)
885#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12)
886#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13)
887#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14)
888#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15)
889
890struct lan743x_vector {
891 int irq;
892 u32 flags;
893 struct lan743x_adapter *adapter;
894 int vector_index;
895 u32 int_mask;
896 lan743x_vector_handler handler;
897 void *context;
898};
899
900#define LAN743X_MAX_VECTOR_COUNT (8)
901#define PCI11X1X_MAX_VECTOR_COUNT (16)
902
903struct lan743x_intr {
904 int flags;
905
906 unsigned int irq;
907
908 struct lan743x_vector vector_list[PCI11X1X_MAX_VECTOR_COUNT];
909 int number_of_vectors;
910 bool using_vectors;
911
912 bool software_isr_flag;
913 wait_queue_head_t software_isr_wq;
914};
915
916#define LAN743X_MAX_FRAME_SIZE (9 * 1024)
917
918/* PHY */
919struct lan743x_phy {
920 bool fc_autoneg;
921 u8 fc_request_control;
922};
923
924/* TX */
925struct lan743x_tx_descriptor;
926struct lan743x_tx_buffer_info;
927
928#define GPIO_QUEUE_STARTED (0)
929#define GPIO_TX_FUNCTION (1)
930#define GPIO_TX_COMPLETION (2)
931#define GPIO_TX_FRAGMENT (3)
932
933#define TX_FRAME_FLAG_IN_PROGRESS BIT(0)
934
935#define TX_TS_FLAG_TIMESTAMPING_ENABLED BIT(0)
936#define TX_TS_FLAG_ONE_STEP_SYNC BIT(1)
937
938struct lan743x_tx {
939 struct lan743x_adapter *adapter;
940 u32 ts_flags;
941 u32 vector_flags;
942 int channel_number;
943
944 int ring_size;
945 size_t ring_allocation_size;
946 struct lan743x_tx_descriptor *ring_cpu_ptr;
947 dma_addr_t ring_dma_ptr;
948 /* ring_lock: used to prevent concurrent access to tx ring */
949 spinlock_t ring_lock;
950 u32 frame_flags;
951 u32 frame_first;
952 u32 frame_data0;
953 u32 frame_tail;
954
955 struct lan743x_tx_buffer_info *buffer_info;
956
957 __le32 *head_cpu_ptr;
958 dma_addr_t head_dma_ptr;
959 int last_head;
960 int last_tail;
961
962 struct napi_struct napi;
963 u32 frame_count;
964 u32 rqd_descriptors;
965};
966
967void lan743x_tx_set_timestamping_mode(struct lan743x_tx *tx,
968 bool enable_timestamping,
969 bool enable_onestep_sync);
970
971/* RX */
972struct lan743x_rx_descriptor;
973struct lan743x_rx_buffer_info;
974
975struct lan743x_rx {
976 struct lan743x_adapter *adapter;
977 u32 vector_flags;
978 int channel_number;
979
980 int ring_size;
981 size_t ring_allocation_size;
982 struct lan743x_rx_descriptor *ring_cpu_ptr;
983 dma_addr_t ring_dma_ptr;
984
985 struct lan743x_rx_buffer_info *buffer_info;
986
987 __le32 *head_cpu_ptr;
988 dma_addr_t head_dma_ptr;
989 u32 last_head;
990 u32 last_tail;
991
992 struct napi_struct napi;
993
994 u32 frame_count;
995
996 struct sk_buff *skb_head, *skb_tail;
997};
998
999int lan743x_rx_set_tstamp_mode(struct lan743x_adapter *adapter,
1000 int rx_filter);
1001
1002/* SGMII Link Speed Duplex status */
1003enum lan743x_sgmii_lsd {
1004 POWER_DOWN = 0,
1005 LINK_DOWN,
1006 ANEG_BUSY,
1007 LINK_10HD,
1008 LINK_10FD,
1009 LINK_100HD,
1010 LINK_100FD,
1011 LINK_1000_MASTER,
1012 LINK_1000_SLAVE,
1013 LINK_2500_MASTER,
1014 LINK_2500_SLAVE
1015};
1016
1017struct lan743x_adapter {
1018 struct net_device *netdev;
1019 struct mii_bus *mdiobus;
1020 int msg_enable;
1021#ifdef CONFIG_PM
1022 u32 wolopts;
1023 u8 sopass[SOPASS_MAX];
1024#endif
1025 struct pci_dev *pdev;
1026 struct lan743x_csr csr;
1027 struct lan743x_intr intr;
1028
1029 struct lan743x_gpio gpio;
1030 struct lan743x_ptp ptp;
1031
1032 u8 mac_address[ETH_ALEN];
1033
1034 struct lan743x_phy phy;
1035 struct lan743x_tx tx[PCI11X1X_USED_TX_CHANNELS];
1036 struct lan743x_rx rx[LAN743X_USED_RX_CHANNELS];
1037 bool is_pci11x1x;
1038 bool is_sgmii_en;
1039 /* protect ethernet syslock */
1040 spinlock_t eth_syslock_spinlock;
1041 bool eth_syslock_en;
1042 u32 eth_syslock_acquire_cnt;
1043 struct mutex sgmii_rw_lock;
1044 /* SGMII Link Speed & Duplex status */
1045 enum lan743x_sgmii_lsd sgmii_lsd;
1046 u8 max_tx_channels;
1047 u8 used_tx_channels;
1048 u8 max_vector_count;
1049
1050#define LAN743X_ADAPTER_FLAG_OTP BIT(0)
1051 u32 flags;
1052 u32 hw_cfg;
1053 phy_interface_t phy_interface;
1054};
1055
1056#define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel))
1057
1058#define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index)
1059#define INTR_FLAG_MSI_ENABLED BIT(8)
1060#define INTR_FLAG_MSIX_ENABLED BIT(9)
1061
1062#define MAC_MII_READ 1
1063#define MAC_MII_WRITE 0
1064
1065#define PHY_FLAG_OPENED BIT(0)
1066#define PHY_FLAG_ATTACHED BIT(1)
1067
1068#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1069#define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF))
1070#else
1071#define DMA_ADDR_HIGH32(dma_addr) ((u32)(0))
1072#endif
1073#define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF))
1074#define DMA_DESCRIPTOR_SPACING_16 (16)
1075#define DMA_DESCRIPTOR_SPACING_32 (32)
1076#define DMA_DESCRIPTOR_SPACING_64 (64)
1077#define DMA_DESCRIPTOR_SPACING_128 (128)
1078#define DEFAULT_DMA_DESCRIPTOR_SPACING (DMA_DESCRIPTOR_SPACING_16)
1079
1080#define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \
1081 (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0))
1082#define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0)
1083#define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0)
1084#define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1)
1085#define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1)
1086
1087/* TX Descriptor bits */
1088#define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000)
1089#define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000)
1090#define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000)
1091#define TX_DESC_DATA0_FS_ (0x20000000)
1092#define TX_DESC_DATA0_LS_ (0x10000000)
1093#define TX_DESC_DATA0_EXT_ (0x08000000)
1094#define TX_DESC_DATA0_IOC_ (0x04000000)
1095#define TX_DESC_DATA0_ICE_ (0x00400000)
1096#define TX_DESC_DATA0_IPE_ (0x00200000)
1097#define TX_DESC_DATA0_TPE_ (0x00100000)
1098#define TX_DESC_DATA0_FCS_ (0x00020000)
1099#define TX_DESC_DATA0_TSE_ (0x00010000)
1100#define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF)
1101#define TX_DESC_DATA0_EXT_LSO_ (0x00200000)
1102#define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF)
1103#define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000)
1104
1105struct lan743x_tx_descriptor {
1106 __le32 data0;
1107 __le32 data1;
1108 __le32 data2;
1109 __le32 data3;
1110} __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING);
1111
1112#define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0)
1113#define TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED BIT(1)
1114#define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2)
1115#define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3)
1116struct lan743x_tx_buffer_info {
1117 int flags;
1118 struct sk_buff *skb;
1119 dma_addr_t dma_ptr;
1120 unsigned int buffer_length;
1121};
1122
1123#define LAN743X_TX_RING_SIZE (128)
1124
1125/* OWN bit is set. ie, Descs are owned by RX DMAC */
1126#define RX_DESC_DATA0_OWN_ (0x00008000)
1127/* OWN bit is clear. ie, Descs are owned by host */
1128#define RX_DESC_DATA0_FS_ (0x80000000)
1129#define RX_DESC_DATA0_LS_ (0x40000000)
1130#define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000)
1131#define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0) \
1132 (((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16)
1133#define RX_DESC_DATA0_EXT_ (0x00004000)
1134#define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF)
1135#define RX_DESC_DATA1_STATUS_ICE_ (0x00020000)
1136#define RX_DESC_DATA1_STATUS_TCE_ (0x00010000)
1137#define RX_DESC_DATA1_STATUS_ICSM_ (0x00000001)
1138#define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF)
1139
1140#if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2))
1141#error NET_IP_ALIGN must be 0 or 2
1142#endif
1143
1144#define RX_HEAD_PADDING NET_IP_ALIGN
1145
1146struct lan743x_rx_descriptor {
1147 __le32 data0;
1148 __le32 data1;
1149 __le32 data2;
1150 __le32 data3;
1151} __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING);
1152
1153#define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0)
1154struct lan743x_rx_buffer_info {
1155 int flags;
1156 struct sk_buff *skb;
1157
1158 dma_addr_t dma_ptr;
1159 unsigned int buffer_length;
1160};
1161
1162#define LAN743X_RX_RING_SIZE (128)
1163
1164#define RX_PROCESS_RESULT_NOTHING_TO_DO (0)
1165#define RX_PROCESS_RESULT_BUFFER_RECEIVED (1)
1166
1167u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset);
1168void lan743x_csr_write(struct lan743x_adapter *adapter, int offset, u32 data);
1169int lan743x_hs_syslock_acquire(struct lan743x_adapter *adapter, u16 timeout);
1170void lan743x_hs_syslock_release(struct lan743x_adapter *adapter);
1171void lan743x_mac_flow_ctrl_set_enables(struct lan743x_adapter *adapter,
1172 bool tx_enable, bool rx_enable);
1173int lan743x_sgmii_read(struct lan743x_adapter *adapter, u8 mmd, u16 addr);
1174
1175#endif /* _LAN743X_H */
1/* SPDX-License-Identifier: GPL-2.0+ */
2/* Copyright (C) 2018 Microchip Technology Inc. */
3
4#ifndef _LAN743X_H
5#define _LAN743X_H
6
7#include <linux/phy.h>
8#include "lan743x_ptp.h"
9
10#define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>"
11#define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver"
12#define DRIVER_NAME "lan743x"
13
14/* Register Definitions */
15#define ID_REV (0x00)
16#define ID_REV_ID_MASK_ (0xFFFF0000)
17#define ID_REV_ID_LAN7430_ (0x74300000)
18#define ID_REV_ID_LAN7431_ (0x74310000)
19#define ID_REV_ID_LAN743X_ (0x74300000)
20#define ID_REV_ID_A011_ (0xA0110000) // PCI11010
21#define ID_REV_ID_A041_ (0xA0410000) // PCI11414
22#define ID_REV_ID_A0X1_ (0xA0010000)
23#define ID_REV_IS_VALID_CHIP_ID_(id_rev) \
24 ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \
25 (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_))
26#define ID_REV_CHIP_REV_MASK_ (0x0000FFFF)
27#define ID_REV_CHIP_REV_A0_ (0x00000000)
28#define ID_REV_CHIP_REV_B0_ (0x00000010)
29
30#define FPGA_REV (0x04)
31#define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF)
32#define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF)
33#define FPGA_SGMII_OP BIT(24)
34
35#define STRAP_READ (0x0C)
36#define STRAP_READ_USE_SGMII_EN_ BIT(22)
37#define STRAP_READ_SGMII_EN_ BIT(6)
38#define STRAP_READ_SGMII_REFCLK_ BIT(5)
39#define STRAP_READ_SGMII_2_5G_ BIT(4)
40#define STRAP_READ_BASE_X_ BIT(3)
41#define STRAP_READ_RGMII_TXC_DELAY_EN_ BIT(2)
42#define STRAP_READ_RGMII_RXC_DELAY_EN_ BIT(1)
43#define STRAP_READ_ADV_PM_DISABLE_ BIT(0)
44
45#define HW_CFG (0x010)
46#define HW_CFG_RST_PROTECT_PCIE_ BIT(19)
47#define HW_CFG_HOT_RESET_DIS_ BIT(15)
48#define HW_CFG_D3_VAUX_OVR_ BIT(14)
49#define HW_CFG_D3_RESET_DIS_ BIT(13)
50#define HW_CFG_RST_PROTECT_ BIT(12)
51#define HW_CFG_RELOAD_TYPE_ALL_ (0x00000FC0)
52#define HW_CFG_EE_OTP_RELOAD_ BIT(4)
53#define HW_CFG_LRST_ BIT(1)
54
55#define PMT_CTL (0x014)
56#define PMT_CTL_ETH_PHY_D3_COLD_OVR_ BIT(27)
57#define PMT_CTL_MAC_D3_RX_CLK_OVR_ BIT(25)
58#define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_ BIT(24)
59#define PMT_CTL_ETH_PHY_D3_OVR_ BIT(23)
60#define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ BIT(18)
61#define PMT_CTL_GPIO_WAKEUP_EN_ BIT(15)
62#define PMT_CTL_EEE_WAKEUP_EN_ BIT(13)
63#define PMT_CTL_READY_ BIT(7)
64#define PMT_CTL_ETH_PHY_RST_ BIT(4)
65#define PMT_CTL_WOL_EN_ BIT(3)
66#define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2)
67#define PMT_CTL_WUPS_MASK_ (0x00000003)
68
69#define DP_SEL (0x024)
70#define DP_SEL_DPRDY_ BIT(31)
71#define DP_SEL_MASK_ (0x0000001F)
72#define DP_SEL_RFE_RAM (0x00000001)
73
74#define DP_SEL_VHF_HASH_LEN (16)
75#define DP_SEL_VHF_VLAN_LEN (128)
76
77#define DP_CMD (0x028)
78#define DP_CMD_WRITE_ (0x00000001)
79
80#define DP_ADDR (0x02C)
81
82#define DP_DATA_0 (0x030)
83
84#define E2P_CMD (0x040)
85#define E2P_CMD_EPC_BUSY_ BIT(31)
86#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000)
87#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000)
88#define E2P_CMD_EPC_CMD_READ_ (0x00000000)
89#define E2P_CMD_EPC_TIMEOUT_ BIT(10)
90#define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF)
91
92#define E2P_DATA (0x044)
93
94/* Hearthstone top level & System Reg Addresses */
95#define ETH_CTRL_REG_ADDR_BASE (0x0000)
96#define ETH_SYS_REG_ADDR_BASE (0x4000)
97#define CONFIG_REG_ADDR_BASE (0x0000)
98#define ETH_EEPROM_REG_ADDR_BASE (0x0E00)
99#define ETH_OTP_REG_ADDR_BASE (0x1000)
100#define GEN_SYS_CONFIG_LOAD_STARTED_REG (0x0078)
101#define ETH_SYS_CONFIG_LOAD_STARTED_REG (ETH_SYS_REG_ADDR_BASE + \
102 CONFIG_REG_ADDR_BASE + \
103 GEN_SYS_CONFIG_LOAD_STARTED_REG)
104#define GEN_SYS_LOAD_STARTED_REG_ETH_ BIT(4)
105#define SYS_LOCK_REG (0x00A0)
106#define SYS_LOCK_REG_MAIN_LOCK_ BIT(7)
107#define SYS_LOCK_REG_GEN_PERI_LOCK_ BIT(5)
108#define SYS_LOCK_REG_SPI_PERI_LOCK_ BIT(4)
109#define SYS_LOCK_REG_SMBUS_PERI_LOCK_ BIT(3)
110#define SYS_LOCK_REG_UART_SS_LOCK_ BIT(2)
111#define SYS_LOCK_REG_ENET_SS_LOCK_ BIT(1)
112#define SYS_LOCK_REG_USB_SS_LOCK_ BIT(0)
113#define ETH_SYSTEM_SYS_LOCK_REG (ETH_SYS_REG_ADDR_BASE + \
114 CONFIG_REG_ADDR_BASE + \
115 SYS_LOCK_REG)
116#define HS_EEPROM_REG_ADDR_BASE (ETH_SYS_REG_ADDR_BASE + \
117 ETH_EEPROM_REG_ADDR_BASE)
118#define HS_E2P_CMD (HS_EEPROM_REG_ADDR_BASE + 0x0000)
119#define HS_E2P_CMD_EPC_BUSY_ BIT(31)
120#define HS_E2P_CMD_EPC_CMD_WRITE_ GENMASK(29, 28)
121#define HS_E2P_CMD_EPC_CMD_READ_ (0x0)
122#define HS_E2P_CMD_EPC_TIMEOUT_ BIT(17)
123#define HS_E2P_CMD_EPC_ADDR_MASK_ GENMASK(15, 0)
124#define HS_E2P_DATA (HS_EEPROM_REG_ADDR_BASE + 0x0004)
125#define HS_E2P_DATA_MASK_ GENMASK(7, 0)
126#define HS_E2P_CFG (HS_EEPROM_REG_ADDR_BASE + 0x0008)
127#define HS_E2P_CFG_I2C_PULSE_MASK_ GENMASK(19, 16)
128#define HS_E2P_CFG_EEPROM_SIZE_SEL_ BIT(12)
129#define HS_E2P_CFG_I2C_BAUD_RATE_MASK_ GENMASK(9, 8)
130#define HS_E2P_CFG_TEST_EEPR_TO_BYP_ BIT(0)
131#define HS_E2P_PAD_CTL (HS_EEPROM_REG_ADDR_BASE + 0x000C)
132
133#define GPIO_CFG0 (0x050)
134#define GPIO_CFG0_GPIO_DIR_BIT_(bit) BIT(16 + (bit))
135#define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit))
136
137#define GPIO_CFG1 (0x054)
138#define GPIO_CFG1_GPIOEN_BIT_(bit) BIT(16 + (bit))
139#define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit))
140
141#define GPIO_CFG2 (0x058)
142#define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit))
143
144#define GPIO_CFG3 (0x05C)
145#define GPIO_CFG3_1588_CH_SEL_BIT_(bit) BIT(16 + (bit))
146#define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit))
147
148#define FCT_RX_CTL (0xAC)
149#define FCT_RX_CTL_EN_(channel) BIT(28 + (channel))
150#define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel))
151#define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel))
152
153#define FCT_TX_CTL (0xC4)
154#define FCT_TX_CTL_EN_(channel) BIT(28 + (channel))
155#define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel))
156#define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel))
157
158#define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2))
159#define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00)
160#define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \
161 ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_)
162#define FCT_FLOW_CTL_REQ_EN_ BIT(7)
163#define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F)
164#define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \
165 ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_)
166
167#define MAC_CR (0x100)
168#define MAC_CR_MII_EN_ BIT(19)
169#define MAC_CR_EEE_EN_ BIT(17)
170#define MAC_CR_ADD_ BIT(12)
171#define MAC_CR_ASD_ BIT(11)
172#define MAC_CR_CNTR_RST_ BIT(5)
173#define MAC_CR_DPX_ BIT(3)
174#define MAC_CR_CFG_H_ BIT(2)
175#define MAC_CR_CFG_L_ BIT(1)
176#define MAC_CR_RST_ BIT(0)
177
178#define MAC_RX (0x104)
179#define MAC_RX_MAX_SIZE_SHIFT_ (16)
180#define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000)
181#define MAC_RX_RXD_ BIT(1)
182#define MAC_RX_RXEN_ BIT(0)
183
184#define MAC_TX (0x108)
185#define MAC_TX_TXD_ BIT(1)
186#define MAC_TX_TXEN_ BIT(0)
187
188#define MAC_FLOW (0x10C)
189#define MAC_FLOW_CR_TX_FCEN_ BIT(30)
190#define MAC_FLOW_CR_RX_FCEN_ BIT(29)
191#define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF)
192
193#define MAC_RX_ADDRH (0x118)
194
195#define MAC_RX_ADDRL (0x11C)
196
197#define MAC_MII_ACC (0x120)
198#define MAC_MII_ACC_MDC_CYCLE_SHIFT_ (16)
199#define MAC_MII_ACC_MDC_CYCLE_MASK_ (0x00070000)
200#define MAC_MII_ACC_MDC_CYCLE_2_5MHZ_ (0)
201#define MAC_MII_ACC_MDC_CYCLE_5MHZ_ (1)
202#define MAC_MII_ACC_MDC_CYCLE_12_5MHZ_ (2)
203#define MAC_MII_ACC_MDC_CYCLE_25MHZ_ (3)
204#define MAC_MII_ACC_MDC_CYCLE_1_25MHZ_ (4)
205#define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11)
206#define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800)
207#define MAC_MII_ACC_MIIRINDA_SHIFT_ (6)
208#define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0)
209#define MAC_MII_ACC_MII_READ_ (0x00000000)
210#define MAC_MII_ACC_MII_WRITE_ (0x00000002)
211#define MAC_MII_ACC_MII_BUSY_ BIT(0)
212
213#define MAC_MII_ACC_MIIMMD_SHIFT_ (6)
214#define MAC_MII_ACC_MIIMMD_MASK_ (0x000007C0)
215#define MAC_MII_ACC_MIICL45_ BIT(3)
216#define MAC_MII_ACC_MIICMD_MASK_ (0x00000006)
217#define MAC_MII_ACC_MIICMD_ADDR_ (0x00000000)
218#define MAC_MII_ACC_MIICMD_WRITE_ (0x00000002)
219#define MAC_MII_ACC_MIICMD_READ_ (0x00000004)
220#define MAC_MII_ACC_MIICMD_READ_INC_ (0x00000006)
221
222#define MAC_MII_DATA (0x124)
223
224#define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130)
225
226#define MAC_WUCSR (0x140)
227#define MAC_MP_SO_EN_ BIT(21)
228#define MAC_WUCSR_RFE_WAKE_EN_ BIT(14)
229#define MAC_WUCSR_PFDA_EN_ BIT(3)
230#define MAC_WUCSR_WAKE_EN_ BIT(2)
231#define MAC_WUCSR_MPEN_ BIT(1)
232#define MAC_WUCSR_BCST_EN_ BIT(0)
233
234#define MAC_WK_SRC (0x144)
235#define MAC_MP_SO_HI (0x148)
236#define MAC_MP_SO_LO (0x14C)
237
238#define MAC_WUF_CFG0 (0x150)
239#define MAC_NUM_OF_WUF_CFG (32)
240#define MAC_WUF_CFG_BEGIN (MAC_WUF_CFG0)
241#define MAC_WUF_CFG(index) (MAC_WUF_CFG_BEGIN + (4 * (index)))
242#define MAC_WUF_CFG_EN_ BIT(31)
243#define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000)
244#define MAC_WUF_CFG_TYPE_ALL_ (0x01000000)
245#define MAC_WUF_CFG_OFFSET_SHIFT_ (16)
246#define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF)
247
248#define MAC_WUF_MASK0_0 (0x200)
249#define MAC_WUF_MASK0_1 (0x204)
250#define MAC_WUF_MASK0_2 (0x208)
251#define MAC_WUF_MASK0_3 (0x20C)
252#define MAC_WUF_MASK0_BEGIN (MAC_WUF_MASK0_0)
253#define MAC_WUF_MASK1_BEGIN (MAC_WUF_MASK0_1)
254#define MAC_WUF_MASK2_BEGIN (MAC_WUF_MASK0_2)
255#define MAC_WUF_MASK3_BEGIN (MAC_WUF_MASK0_3)
256#define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index)))
257#define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index)))
258#define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index)))
259#define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index)))
260
261/* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */
262#define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x)))
263#define RFE_ADDR_FILT_HI_VALID_ BIT(31)
264
265/* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */
266#define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x)))
267
268#define RFE_CTL (0x508)
269#define RFE_CTL_TCP_UDP_COE_ BIT(12)
270#define RFE_CTL_IP_COE_ BIT(11)
271#define RFE_CTL_AB_ BIT(10)
272#define RFE_CTL_AM_ BIT(9)
273#define RFE_CTL_AU_ BIT(8)
274#define RFE_CTL_MCAST_HASH_ BIT(3)
275#define RFE_CTL_DA_PERFECT_ BIT(1)
276
277#define RFE_RSS_CFG (0x554)
278#define RFE_RSS_CFG_UDP_IPV6_EX_ BIT(16)
279#define RFE_RSS_CFG_TCP_IPV6_EX_ BIT(15)
280#define RFE_RSS_CFG_IPV6_EX_ BIT(14)
281#define RFE_RSS_CFG_UDP_IPV6_ BIT(13)
282#define RFE_RSS_CFG_TCP_IPV6_ BIT(12)
283#define RFE_RSS_CFG_IPV6_ BIT(11)
284#define RFE_RSS_CFG_UDP_IPV4_ BIT(10)
285#define RFE_RSS_CFG_TCP_IPV4_ BIT(9)
286#define RFE_RSS_CFG_IPV4_ BIT(8)
287#define RFE_RSS_CFG_VALID_HASH_BITS_ (0x000000E0)
288#define RFE_RSS_CFG_RSS_QUEUE_ENABLE_ BIT(2)
289#define RFE_RSS_CFG_RSS_HASH_STORE_ BIT(1)
290#define RFE_RSS_CFG_RSS_ENABLE_ BIT(0)
291
292#define RFE_HASH_KEY(index) (0x558 + (index << 2))
293
294#define RFE_INDX(index) (0x580 + (index << 2))
295
296#define MAC_WUCSR2 (0x600)
297
298#define SGMII_ACC (0x720)
299#define SGMII_ACC_SGMII_BZY_ BIT(31)
300#define SGMII_ACC_SGMII_WR_ BIT(30)
301#define SGMII_ACC_SGMII_MMD_SHIFT_ (16)
302#define SGMII_ACC_SGMII_MMD_MASK_ GENMASK(20, 16)
303#define SGMII_ACC_SGMII_MMD_VSR_ BIT(15)
304#define SGMII_ACC_SGMII_ADDR_SHIFT_ (0)
305#define SGMII_ACC_SGMII_ADDR_MASK_ GENMASK(15, 0)
306#define SGMII_DATA (0x724)
307#define SGMII_DATA_SHIFT_ (0)
308#define SGMII_DATA_MASK_ GENMASK(15, 0)
309#define SGMII_CTL (0x728)
310#define SGMII_CTL_SGMII_ENABLE_ BIT(31)
311#define SGMII_CTL_LINK_STATUS_SOURCE_ BIT(8)
312#define SGMII_CTL_SGMII_POWER_DN_ BIT(1)
313
314/* Vendor Specific SGMII MMD details */
315#define SR_VSMMD_PCS_ID1 0x0004
316#define SR_VSMMD_PCS_ID2 0x0005
317#define SR_VSMMD_STS 0x0008
318#define SR_VSMMD_CTRL 0x0009
319
320#define VR_MII_DIG_CTRL1 0x8000
321#define VR_MII_DIG_CTRL1_VR_RST_ BIT(15)
322#define VR_MII_DIG_CTRL1_R2TLBE_ BIT(14)
323#define VR_MII_DIG_CTRL1_EN_VSMMD1_ BIT(13)
324#define VR_MII_DIG_CTRL1_CS_EN_ BIT(10)
325#define VR_MII_DIG_CTRL1_MAC_AUTO_SW_ BIT(9)
326#define VR_MII_DIG_CTRL1_INIT_ BIT(8)
327#define VR_MII_DIG_CTRL1_DTXLANED_0_ BIT(4)
328#define VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE_ BIT(3)
329#define VR_MII_DIG_CTRL1_EN_2_5G_MODE_ BIT(2)
330#define VR_MII_DIG_CTRL1_BYP_PWRUP_ BIT(1)
331#define VR_MII_DIG_CTRL1_PHY_MODE_CTRL_ BIT(0)
332#define VR_MII_AN_CTRL 0x8001
333#define VR_MII_AN_CTRL_MII_CTRL_ BIT(8)
334#define VR_MII_AN_CTRL_SGMII_LINK_STS_ BIT(4)
335#define VR_MII_AN_CTRL_TX_CONFIG_ BIT(3)
336#define VR_MII_AN_CTRL_1000BASE_X_ (0)
337#define VR_MII_AN_CTRL_SGMII_MODE_ (2)
338#define VR_MII_AN_CTRL_QSGMII_MODE_ (3)
339#define VR_MII_AN_CTRL_PCS_MODE_SHIFT_ (1)
340#define VR_MII_AN_CTRL_PCS_MODE_MASK_ GENMASK(2, 1)
341#define VR_MII_AN_CTRL_MII_AN_INTR_EN_ BIT(0)
342#define VR_MII_AN_INTR_STS 0x8002
343#define VR_MII_AN_INTR_STS_LINK_UP_ BIT(4)
344#define VR_MII_AN_INTR_STS_SPEED_MASK_ GENMASK(3, 2)
345#define VR_MII_AN_INTR_STS_1000_MBPS_ BIT(3)
346#define VR_MII_AN_INTR_STS_100_MBPS_ BIT(2)
347#define VR_MII_AN_INTR_STS_10_MBPS_ (0)
348#define VR_MII_AN_INTR_STS_FDX_ BIT(1)
349#define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_ BIT(0)
350
351#define VR_MII_LINK_TIMER_CTRL 0x800A
352#define VR_MII_DIG_STS 0x8010
353#define VR_MII_DIG_STS_PSEQ_STATE_MASK_ GENMASK(4, 2)
354#define VR_MII_DIG_STS_PSEQ_STATE_POS_ (2)
355#define VR_MII_GEN2_4_MPLL_CTRL0 0x8078
356#define VR_MII_MPLL_CTRL0_REF_CLK_DIV2_ BIT(12)
357#define VR_MII_MPLL_CTRL0_USE_REFCLK_PAD_ BIT(4)
358#define VR_MII_GEN2_4_MPLL_CTRL1 0x8079
359#define VR_MII_MPLL_CTRL1_MPLL_MULTIPLIER_ GENMASK(6, 0)
360#define VR_MII_BAUD_RATE_3P125GBPS (3125)
361#define VR_MII_BAUD_RATE_1P25GBPS (1250)
362#define VR_MII_MPLL_MULTIPLIER_125 (125)
363#define VR_MII_MPLL_MULTIPLIER_100 (100)
364#define VR_MII_MPLL_MULTIPLIER_50 (50)
365#define VR_MII_MPLL_MULTIPLIER_40 (40)
366#define VR_MII_GEN2_4_MISC_CTRL1 0x809A
367#define VR_MII_CTRL1_RX_RATE_0_MASK_ GENMASK(3, 2)
368#define VR_MII_CTRL1_RX_RATE_0_SHIFT_ (2)
369#define VR_MII_CTRL1_TX_RATE_0_MASK_ GENMASK(1, 0)
370#define VR_MII_MPLL_BAUD_CLK (0)
371#define VR_MII_MPLL_BAUD_CLK_DIV_2 (1)
372#define VR_MII_MPLL_BAUD_CLK_DIV_4 (2)
373
374#define INT_STS (0x780)
375#define INT_BIT_DMA_RX_(channel) BIT(24 + (channel))
376#define INT_BIT_ALL_RX_ (0x0F000000)
377#define INT_BIT_DMA_TX_(channel) BIT(16 + (channel))
378#define INT_BIT_ALL_TX_ (0x000F0000)
379#define INT_BIT_SW_GP_ BIT(9)
380#define INT_BIT_1588_ BIT(7)
381#define INT_BIT_ALL_OTHER_ (INT_BIT_SW_GP_ | INT_BIT_1588_)
382#define INT_BIT_MAS_ BIT(0)
383
384#define INT_SET (0x784)
385
386#define INT_EN_SET (0x788)
387
388#define INT_EN_CLR (0x78C)
389
390#define INT_STS_R2C (0x790)
391
392#define INT_VEC_EN_SET (0x794)
393#define INT_VEC_EN_CLR (0x798)
394#define INT_VEC_EN_AUTO_CLR (0x79C)
395#define INT_VEC_EN_(vector_index) BIT(0 + vector_index)
396
397#define INT_VEC_MAP0 (0x7A0)
398#define INT_VEC_MAP0_RX_VEC_(channel, vector) \
399 (((u32)(vector)) << ((channel) << 2))
400
401#define INT_VEC_MAP1 (0x7A4)
402#define INT_VEC_MAP1_TX_VEC_(channel, vector) \
403 (((u32)(vector)) << ((channel) << 2))
404
405#define INT_VEC_MAP2 (0x7A8)
406
407#define INT_MOD_MAP0 (0x7B0)
408
409#define INT_MOD_MAP1 (0x7B4)
410
411#define INT_MOD_MAP2 (0x7B8)
412
413#define INT_MOD_CFG0 (0x7C0)
414#define INT_MOD_CFG1 (0x7C4)
415#define INT_MOD_CFG2 (0x7C8)
416#define INT_MOD_CFG3 (0x7CC)
417#define INT_MOD_CFG4 (0x7D0)
418#define INT_MOD_CFG5 (0x7D4)
419#define INT_MOD_CFG6 (0x7D8)
420#define INT_MOD_CFG7 (0x7DC)
421#define INT_MOD_CFG8 (0x7E0)
422#define INT_MOD_CFG9 (0x7E4)
423
424#define PTP_CMD_CTL (0x0A00)
425#define PTP_CMD_CTL_PTP_LTC_TARGET_READ_ BIT(13)
426#define PTP_CMD_CTL_PTP_CLK_STP_NSEC_ BIT(6)
427#define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_ BIT(5)
428#define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4)
429#define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3)
430#define PTP_CMD_CTL_PTP_ENABLE_ BIT(2)
431#define PTP_CMD_CTL_PTP_DISABLE_ BIT(1)
432#define PTP_CMD_CTL_PTP_RESET_ BIT(0)
433#define PTP_GENERAL_CONFIG (0x0A04)
434#define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \
435 (0x7 << (1 + ((channel) << 2)))
436#define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0)
437#define PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (1)
438#define PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (2)
439#define PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (3)
440#define PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (4)
441#define PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (5)
442#define PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGGLE_ (6)
443#define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \
444 (((value) & 0x7) << (1 + ((channel) << 2)))
445#define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2))
446
447#define HS_PTP_GENERAL_CONFIG (0x0A04)
448#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \
449 (0xf << (4 + ((channel) << 2)))
450#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0)
451#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_500NS_ (1)
452#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1US_ (2)
453#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_5US_ (3)
454#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (4)
455#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_50US_ (5)
456#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (6)
457#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_500US_ (7)
458#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (8)
459#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_5MS_ (9)
460#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (10)
461#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_50MS_ (11)
462#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100MS_ (12)
463#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (13)
464#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGG_ (14)
465#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_INT_ (15)
466#define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \
467 (((value) & 0xf) << (4 + ((channel) << 2)))
468#define HS_PTP_GENERAL_CONFIG_EVENT_POL_X_(channel) (BIT(1 + ((channel) * 2)))
469#define HS_PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) * 2))
470
471#define PTP_INT_STS (0x0A08)
472#define PTP_INT_IO_FE_MASK_ GENMASK(31, 24)
473#define PTP_INT_IO_FE_SHIFT_ (24)
474#define PTP_INT_IO_FE_SET_(channel) BIT(24 + (channel))
475#define PTP_INT_IO_RE_MASK_ GENMASK(23, 16)
476#define PTP_INT_IO_RE_SHIFT_ (16)
477#define PTP_INT_IO_RE_SET_(channel) BIT(16 + (channel))
478#define PTP_INT_TX_TS_OVRFL_INT_ BIT(14)
479#define PTP_INT_TX_SWTS_ERR_INT_ BIT(13)
480#define PTP_INT_TX_TS_INT_ BIT(12)
481#define PTP_INT_RX_TS_OVRFL_INT_ BIT(9)
482#define PTP_INT_RX_TS_INT_ BIT(8)
483#define PTP_INT_TIMER_INT_B_ BIT(1)
484#define PTP_INT_TIMER_INT_A_ BIT(0)
485#define PTP_INT_EN_SET (0x0A0C)
486#define PTP_INT_EN_FE_EN_SET_(channel) BIT(24 + (channel))
487#define PTP_INT_EN_RE_EN_SET_(channel) BIT(16 + (channel))
488#define PTP_INT_EN_TIMER_SET_(channel) BIT(channel)
489#define PTP_INT_EN_CLR (0x0A10)
490#define PTP_INT_EN_FE_EN_CLR_(channel) BIT(24 + (channel))
491#define PTP_INT_EN_RE_EN_CLR_(channel) BIT(16 + (channel))
492#define PTP_INT_BIT_TX_SWTS_ERR_ BIT(13)
493#define PTP_INT_BIT_TX_TS_ BIT(12)
494#define PTP_INT_BIT_TIMER_B_ BIT(1)
495#define PTP_INT_BIT_TIMER_A_ BIT(0)
496
497#define PTP_CLOCK_SEC (0x0A14)
498#define PTP_CLOCK_NS (0x0A18)
499#define PTP_CLOCK_SUBNS (0x0A1C)
500#define PTP_CLOCK_RATE_ADJ (0x0A20)
501#define PTP_CLOCK_RATE_ADJ_DIR_ BIT(31)
502#define PTP_CLOCK_STEP_ADJ (0x0A2C)
503#define PTP_CLOCK_STEP_ADJ_DIR_ BIT(31)
504#define PTP_CLOCK_STEP_ADJ_VALUE_MASK_ (0x3FFFFFFF)
505#define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4))
506#define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4))
507#define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4))
508#define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4))
509#define PTP_LTC_SET_SEC_HI (0x0A50)
510#define PTP_LTC_SET_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0)
511#define PTP_VERSION (0x0A54)
512#define PTP_VERSION_TX_UP_MASK_ GENMASK(31, 24)
513#define PTP_VERSION_TX_LO_MASK_ GENMASK(23, 16)
514#define PTP_VERSION_RX_UP_MASK_ GENMASK(15, 8)
515#define PTP_VERSION_RX_LO_MASK_ GENMASK(7, 0)
516#define PTP_IO_SEL (0x0A58)
517#define PTP_IO_SEL_MASK_ GENMASK(10, 8)
518#define PTP_IO_SEL_SHIFT_ (8)
519#define PTP_LATENCY (0x0A5C)
520#define PTP_LATENCY_TX_SET_(tx_latency) (((u32)(tx_latency)) << 16)
521#define PTP_LATENCY_RX_SET_(rx_latency) \
522 (((u32)(rx_latency)) & 0x0000FFFF)
523#define PTP_CAP_INFO (0x0A60)
524#define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4)
525
526#define PTP_TX_MOD (0x0AA4)
527#define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ (0x10000000)
528
529#define PTP_TX_MOD2 (0x0AA8)
530#define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_ (0x00000001)
531
532#define PTP_TX_EGRESS_SEC (0x0AAC)
533#define PTP_TX_EGRESS_NS (0x0AB0)
534#define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_ (0xC0000000)
535#define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_ (0x00000000)
536#define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_ (0x40000000)
537#define PTP_TX_EGRESS_NS_TS_NS_MASK_ (0x3FFFFFFF)
538
539#define PTP_TX_MSG_HEADER (0x0AB4)
540#define PTP_TX_MSG_HEADER_MSG_TYPE_ (0x000F0000)
541#define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_ (0x00000000)
542
543#define PTP_TX_CAP_INFO (0x0AB8)
544#define PTP_TX_CAP_INFO_TX_CH_MASK_ GENMASK(1, 0)
545#define PTP_TX_DOMAIN (0x0ABC)
546#define PTP_TX_DOMAIN_MASK_ GENMASK(23, 16)
547#define PTP_TX_DOMAIN_RANGE_EN_ BIT(15)
548#define PTP_TX_DOMAIN_RANGE_MASK_ GENMASK(7, 0)
549#define PTP_TX_SDOID (0x0AC0)
550#define PTP_TX_SDOID_MASK_ GENMASK(23, 16)
551#define PTP_TX_SDOID_RANGE_EN_ BIT(15)
552#define PTP_TX_SDOID_11_0_MASK_ GENMASK(7, 0)
553#define PTP_IO_CAP_CONFIG (0x0AC4)
554#define PTP_IO_CAP_CONFIG_LOCK_FE_(channel) BIT(24 + (channel))
555#define PTP_IO_CAP_CONFIG_LOCK_RE_(channel) BIT(16 + (channel))
556#define PTP_IO_CAP_CONFIG_FE_CAP_EN_(channel) BIT(8 + (channel))
557#define PTP_IO_CAP_CONFIG_RE_CAP_EN_(channel) BIT(0 + (channel))
558#define PTP_IO_RE_LTC_SEC_CAP_X (0x0AC8)
559#define PTP_IO_RE_LTC_NS_CAP_X (0x0ACC)
560#define PTP_IO_FE_LTC_SEC_CAP_X (0x0AD0)
561#define PTP_IO_FE_LTC_NS_CAP_X (0x0AD4)
562#define PTP_IO_EVENT_OUTPUT_CFG (0x0AD8)
563#define PTP_IO_EVENT_OUTPUT_CFG_SEL_(channel) BIT(16 + (channel))
564#define PTP_IO_EVENT_OUTPUT_CFG_EN_(channel) BIT(0 + (channel))
565#define PTP_IO_PIN_CFG (0x0ADC)
566#define PTP_IO_PIN_CFG_OBUF_TYPE_(channel) BIT(0 + (channel))
567#define PTP_LTC_RD_SEC_HI (0x0AF0)
568#define PTP_LTC_RD_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0)
569#define PTP_LTC_RD_SEC_LO (0x0AF4)
570#define PTP_LTC_RD_NS (0x0AF8)
571#define PTP_LTC_RD_NS_29_0_MASK_ GENMASK(29, 0)
572#define PTP_LTC_RD_SUBNS (0x0AFC)
573#define PTP_RX_USER_MAC_HI (0x0B00)
574#define PTP_RX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0)
575#define PTP_RX_USER_MAC_LO (0x0B04)
576#define PTP_RX_USER_IP_ADDR_0 (0x0B20)
577#define PTP_RX_USER_IP_ADDR_1 (0x0B24)
578#define PTP_RX_USER_IP_ADDR_2 (0x0B28)
579#define PTP_RX_USER_IP_ADDR_3 (0x0B2C)
580#define PTP_RX_USER_IP_MASK_0 (0x0B30)
581#define PTP_RX_USER_IP_MASK_1 (0x0B34)
582#define PTP_RX_USER_IP_MASK_2 (0x0B38)
583#define PTP_RX_USER_IP_MASK_3 (0x0B3C)
584#define PTP_TX_USER_MAC_HI (0x0B40)
585#define PTP_TX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0)
586#define PTP_TX_USER_MAC_LO (0x0B44)
587#define PTP_TX_USER_IP_ADDR_0 (0x0B60)
588#define PTP_TX_USER_IP_ADDR_1 (0x0B64)
589#define PTP_TX_USER_IP_ADDR_2 (0x0B68)
590#define PTP_TX_USER_IP_ADDR_3 (0x0B6C)
591#define PTP_TX_USER_IP_MASK_0 (0x0B70)
592#define PTP_TX_USER_IP_MASK_1 (0x0B74)
593#define PTP_TX_USER_IP_MASK_2 (0x0B78)
594#define PTP_TX_USER_IP_MASK_3 (0x0B7C)
595
596#define DMAC_CFG (0xC00)
597#define DMAC_CFG_COAL_EN_ BIT(16)
598#define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000)
599#define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070)
600#define DMAC_CFG_MAX_READ_REQ_SET_(val) \
601 ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_)
602#define DMAC_CFG_MAX_DSPACE_16_ (0x00000000)
603#define DMAC_CFG_MAX_DSPACE_32_ (0x00000001)
604#define DMAC_CFG_MAX_DSPACE_64_ BIT(1)
605#define DMAC_CFG_MAX_DSPACE_128_ (0x00000003)
606
607#define DMAC_COAL_CFG (0xC04)
608#define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000)
609#define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \
610 ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_)
611#define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19)
612#define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18)
613#define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17)
614#define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16)
615#define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00)
616#define DMAC_COAL_CFG_TX_THRES_SET_(val) \
617 ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_)
618#define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF)
619#define DMAC_COAL_CFG_RX_THRES_SET_(val) \
620 (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_)
621
622#define DMAC_OBFF_CFG (0xC08)
623#define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00)
624#define DMAC_OBFF_TX_THRES_SET_(val) \
625 ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_)
626#define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF)
627#define DMAC_OBFF_RX_THRES_SET_(val) \
628 (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_)
629
630#define DMAC_CMD (0xC0C)
631#define DMAC_CMD_SWR_ BIT(31)
632#define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel))
633#define DMAC_CMD_START_T_(channel) BIT(20 + (channel))
634#define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel))
635#define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel))
636#define DMAC_CMD_START_R_(channel) BIT(4 + (channel))
637#define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel))
638
639#define DMAC_INT_STS (0xC10)
640#define DMAC_INT_EN_SET (0xC14)
641#define DMAC_INT_EN_CLR (0xC18)
642#define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel))
643#define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel))
644
645#define RX_CFG_A(channel) (0xC40 + ((channel) << 6))
646#define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30)
647#define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000)
648#define RX_CFG_A_RX_WB_THRES_SET_(val) \
649 ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_)
650#define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000)
651#define RX_CFG_A_RX_PF_THRES_SET_(val) \
652 ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_)
653#define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00)
654#define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \
655 ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_)
656#define RX_CFG_A_RX_HP_WB_EN_ BIT(5)
657
658#define RX_CFG_B(channel) (0xC44 + ((channel) << 6))
659#define RX_CFG_B_TS_ALL_RX_ BIT(29)
660#define RX_CFG_B_RX_PAD_MASK_ (0x03000000)
661#define RX_CFG_B_RX_PAD_0_ (0x00000000)
662#define RX_CFG_B_RX_PAD_2_ (0x02000000)
663#define RX_CFG_B_RDMABL_512_ (0x00040000)
664#define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF)
665
666#define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6))
667
668#define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6))
669
670#define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6))
671
672#define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6))
673
674#define RX_HEAD(channel) (0xC58 + ((channel) << 6))
675
676#define RX_TAIL(channel) (0xC5C + ((channel) << 6))
677#define RX_TAIL_SET_TOP_INT_EN_ BIT(30)
678#define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29)
679
680#define RX_CFG_C(channel) (0xC64 + ((channel) << 6))
681#define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6)
682#define RX_CFG_C_RX_INT_EN_R2C_ BIT(4)
683#define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3)
684#define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007)
685
686#define TX_CFG_A(channel) (0xD40 + ((channel) << 6))
687#define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30)
688#define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000)
689#define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000)
690#define TX_CFG_A_TX_PF_THRES_SET_(value) \
691 ((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_)
692#define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00)
693#define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \
694 ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_)
695#define TX_CFG_A_TX_HP_WB_EN_ BIT(5)
696#define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F)
697#define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \
698 (((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_)
699
700#define TX_CFG_B(channel) (0xD44 + ((channel) << 6))
701#define TX_CFG_B_TDMABL_512_ (0x00040000)
702#define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF)
703
704#define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6))
705
706#define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6))
707
708#define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6))
709
710#define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6))
711
712#define TX_HEAD(channel) (0xD58 + ((channel) << 6))
713
714#define TX_TAIL(channel) (0xD5C + ((channel) << 6))
715#define TX_TAIL_SET_DMAC_INT_EN_ BIT(31)
716#define TX_TAIL_SET_TOP_INT_EN_ BIT(30)
717#define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29)
718
719#define TX_CFG_C(channel) (0xD64 + ((channel) << 6))
720#define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6)
721#define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5)
722#define TX_CFG_C_TX_INT_EN_R2C_ BIT(4)
723#define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3)
724#define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007)
725
726#define OTP_PWR_DN (0x1000)
727#define OTP_PWR_DN_PWRDN_N_ BIT(0)
728
729#define OTP_ADDR_HIGH (0x1004)
730#define OTP_ADDR_LOW (0x1008)
731
732#define OTP_PRGM_DATA (0x1010)
733
734#define OTP_PRGM_MODE (0x1014)
735#define OTP_PRGM_MODE_BYTE_ BIT(0)
736
737#define OTP_READ_DATA (0x1018)
738
739#define OTP_FUNC_CMD (0x1020)
740#define OTP_FUNC_CMD_READ_ BIT(0)
741
742#define OTP_TST_CMD (0x1024)
743#define OTP_TST_CMD_PRGVRFY_ BIT(3)
744
745#define OTP_CMD_GO (0x1028)
746#define OTP_CMD_GO_GO_ BIT(0)
747
748#define OTP_STATUS (0x1030)
749#define OTP_STATUS_BUSY_ BIT(0)
750
751/* Hearthstone OTP block registers */
752#define HS_OTP_BLOCK_BASE (ETH_SYS_REG_ADDR_BASE + \
753 ETH_OTP_REG_ADDR_BASE)
754#define HS_OTP_PWR_DN (HS_OTP_BLOCK_BASE + 0x0)
755#define HS_OTP_ADDR_HIGH (HS_OTP_BLOCK_BASE + 0x4)
756#define HS_OTP_ADDR_LOW (HS_OTP_BLOCK_BASE + 0x8)
757#define HS_OTP_PRGM_DATA (HS_OTP_BLOCK_BASE + 0x10)
758#define HS_OTP_PRGM_MODE (HS_OTP_BLOCK_BASE + 0x14)
759#define HS_OTP_READ_DATA (HS_OTP_BLOCK_BASE + 0x18)
760#define HS_OTP_FUNC_CMD (HS_OTP_BLOCK_BASE + 0x20)
761#define HS_OTP_TST_CMD (HS_OTP_BLOCK_BASE + 0x24)
762#define HS_OTP_CMD_GO (HS_OTP_BLOCK_BASE + 0x28)
763#define HS_OTP_STATUS (HS_OTP_BLOCK_BASE + 0x30)
764
765/* MAC statistics registers */
766#define STAT_RX_FCS_ERRORS (0x1200)
767#define STAT_RX_ALIGNMENT_ERRORS (0x1204)
768#define STAT_RX_FRAGMENT_ERRORS (0x1208)
769#define STAT_RX_JABBER_ERRORS (0x120C)
770#define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210)
771#define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214)
772#define STAT_RX_DROPPED_FRAMES (0x1218)
773#define STAT_RX_UNICAST_BYTE_COUNT (0x121C)
774#define STAT_RX_BROADCAST_BYTE_COUNT (0x1220)
775#define STAT_RX_MULTICAST_BYTE_COUNT (0x1224)
776#define STAT_RX_UNICAST_FRAMES (0x1228)
777#define STAT_RX_BROADCAST_FRAMES (0x122C)
778#define STAT_RX_MULTICAST_FRAMES (0x1230)
779#define STAT_RX_PAUSE_FRAMES (0x1234)
780#define STAT_RX_64_BYTE_FRAMES (0x1238)
781#define STAT_RX_65_127_BYTE_FRAMES (0x123C)
782#define STAT_RX_128_255_BYTE_FRAMES (0x1240)
783#define STAT_RX_256_511_BYTES_FRAMES (0x1244)
784#define STAT_RX_512_1023_BYTE_FRAMES (0x1248)
785#define STAT_RX_1024_1518_BYTE_FRAMES (0x124C)
786#define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250)
787#define STAT_RX_TOTAL_FRAMES (0x1254)
788#define STAT_EEE_RX_LPI_TRANSITIONS (0x1258)
789#define STAT_EEE_RX_LPI_TIME (0x125C)
790#define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C)
791
792#define STAT_TX_FCS_ERRORS (0x1280)
793#define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284)
794#define STAT_TX_CARRIER_ERRORS (0x1288)
795#define STAT_TX_BAD_BYTE_COUNT (0x128C)
796#define STAT_TX_SINGLE_COLLISIONS (0x1290)
797#define STAT_TX_MULTIPLE_COLLISIONS (0x1294)
798#define STAT_TX_EXCESSIVE_COLLISION (0x1298)
799#define STAT_TX_LATE_COLLISIONS (0x129C)
800#define STAT_TX_UNICAST_BYTE_COUNT (0x12A0)
801#define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4)
802#define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8)
803#define STAT_TX_UNICAST_FRAMES (0x12AC)
804#define STAT_TX_BROADCAST_FRAMES (0x12B0)
805#define STAT_TX_MULTICAST_FRAMES (0x12B4)
806#define STAT_TX_PAUSE_FRAMES (0x12B8)
807#define STAT_TX_64_BYTE_FRAMES (0x12BC)
808#define STAT_TX_65_127_BYTE_FRAMES (0x12C0)
809#define STAT_TX_128_255_BYTE_FRAMES (0x12C4)
810#define STAT_TX_256_511_BYTES_FRAMES (0x12C8)
811#define STAT_TX_512_1023_BYTE_FRAMES (0x12CC)
812#define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0)
813#define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4)
814#define STAT_TX_TOTAL_FRAMES (0x12D8)
815#define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC)
816#define STAT_EEE_TX_LPI_TIME (0x12E0)
817#define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC)
818
819/* End of Register definitions */
820
821#define LAN743X_MAX_RX_CHANNELS (4)
822#define LAN743X_MAX_TX_CHANNELS (1)
823#define PCI11X1X_MAX_TX_CHANNELS (4)
824struct lan743x_adapter;
825
826#define LAN743X_USED_RX_CHANNELS (4)
827#define LAN743X_USED_TX_CHANNELS (1)
828#define PCI11X1X_USED_TX_CHANNELS (4)
829#define LAN743X_INT_MOD (400)
830
831#if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS)
832#error Invalid LAN743X_USED_RX_CHANNELS
833#endif
834#if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS)
835#error Invalid LAN743X_USED_TX_CHANNELS
836#endif
837#if (PCI11X1X_USED_TX_CHANNELS > PCI11X1X_MAX_TX_CHANNELS)
838#error Invalid PCI11X1X_USED_TX_CHANNELS
839#endif
840
841/* PCI */
842/* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */
843#define PCI_VENDOR_ID_SMSC PCI_VENDOR_ID_EFAR
844#define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430)
845#define PCI_DEVICE_ID_SMSC_LAN7431 (0x7431)
846#define PCI_DEVICE_ID_SMSC_A011 (0xA011)
847#define PCI_DEVICE_ID_SMSC_A041 (0xA041)
848
849#define PCI_CONFIG_LENGTH (0x1000)
850
851/* CSR */
852#define CSR_LENGTH (0x2000)
853
854#define LAN743X_CSR_FLAG_IS_A0 BIT(0)
855#define LAN743X_CSR_FLAG_IS_B0 BIT(1)
856#define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8)
857
858struct lan743x_csr {
859 u32 flags;
860 u8 __iomem *csr_address;
861 u32 id_rev;
862 u32 fpga_rev;
863};
864
865/* INTERRUPTS */
866typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags);
867
868#define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0)
869#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1)
870#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2)
871#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3)
872#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4)
873#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5)
874#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6)
875#define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7)
876#define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8)
877#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9)
878#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10)
879#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11)
880#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12)
881#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13)
882#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14)
883#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15)
884
885struct lan743x_vector {
886 int irq;
887 u32 flags;
888 struct lan743x_adapter *adapter;
889 int vector_index;
890 u32 int_mask;
891 lan743x_vector_handler handler;
892 void *context;
893};
894
895#define LAN743X_MAX_VECTOR_COUNT (8)
896#define PCI11X1X_MAX_VECTOR_COUNT (16)
897
898struct lan743x_intr {
899 int flags;
900
901 unsigned int irq;
902
903 struct lan743x_vector vector_list[PCI11X1X_MAX_VECTOR_COUNT];
904 int number_of_vectors;
905 bool using_vectors;
906
907 bool software_isr_flag;
908 wait_queue_head_t software_isr_wq;
909};
910
911#define LAN743X_MAX_FRAME_SIZE (9 * 1024)
912
913/* PHY */
914struct lan743x_phy {
915 bool fc_autoneg;
916 u8 fc_request_control;
917};
918
919/* TX */
920struct lan743x_tx_descriptor;
921struct lan743x_tx_buffer_info;
922
923#define GPIO_QUEUE_STARTED (0)
924#define GPIO_TX_FUNCTION (1)
925#define GPIO_TX_COMPLETION (2)
926#define GPIO_TX_FRAGMENT (3)
927
928#define TX_FRAME_FLAG_IN_PROGRESS BIT(0)
929
930#define TX_TS_FLAG_TIMESTAMPING_ENABLED BIT(0)
931#define TX_TS_FLAG_ONE_STEP_SYNC BIT(1)
932
933struct lan743x_tx {
934 struct lan743x_adapter *adapter;
935 u32 ts_flags;
936 u32 vector_flags;
937 int channel_number;
938
939 int ring_size;
940 size_t ring_allocation_size;
941 struct lan743x_tx_descriptor *ring_cpu_ptr;
942 dma_addr_t ring_dma_ptr;
943 /* ring_lock: used to prevent concurrent access to tx ring */
944 spinlock_t ring_lock;
945 u32 frame_flags;
946 u32 frame_first;
947 u32 frame_data0;
948 u32 frame_tail;
949
950 struct lan743x_tx_buffer_info *buffer_info;
951
952 __le32 *head_cpu_ptr;
953 dma_addr_t head_dma_ptr;
954 int last_head;
955 int last_tail;
956
957 struct napi_struct napi;
958 u32 frame_count;
959 u32 rqd_descriptors;
960};
961
962void lan743x_tx_set_timestamping_mode(struct lan743x_tx *tx,
963 bool enable_timestamping,
964 bool enable_onestep_sync);
965
966/* RX */
967struct lan743x_rx_descriptor;
968struct lan743x_rx_buffer_info;
969
970struct lan743x_rx {
971 struct lan743x_adapter *adapter;
972 u32 vector_flags;
973 int channel_number;
974
975 int ring_size;
976 size_t ring_allocation_size;
977 struct lan743x_rx_descriptor *ring_cpu_ptr;
978 dma_addr_t ring_dma_ptr;
979
980 struct lan743x_rx_buffer_info *buffer_info;
981
982 __le32 *head_cpu_ptr;
983 dma_addr_t head_dma_ptr;
984 u32 last_head;
985 u32 last_tail;
986
987 struct napi_struct napi;
988
989 u32 frame_count;
990
991 struct sk_buff *skb_head, *skb_tail;
992};
993
994/* SGMII Link Speed Duplex status */
995enum lan743x_sgmii_lsd {
996 POWER_DOWN = 0,
997 LINK_DOWN,
998 ANEG_BUSY,
999 LINK_10HD,
1000 LINK_10FD,
1001 LINK_100HD,
1002 LINK_100FD,
1003 LINK_1000_MASTER,
1004 LINK_1000_SLAVE,
1005 LINK_2500_MASTER,
1006 LINK_2500_SLAVE
1007};
1008
1009struct lan743x_adapter {
1010 struct net_device *netdev;
1011 struct mii_bus *mdiobus;
1012 int msg_enable;
1013#ifdef CONFIG_PM
1014 u32 wolopts;
1015 u8 sopass[SOPASS_MAX];
1016#endif
1017 struct pci_dev *pdev;
1018 struct lan743x_csr csr;
1019 struct lan743x_intr intr;
1020
1021 struct lan743x_gpio gpio;
1022 struct lan743x_ptp ptp;
1023
1024 u8 mac_address[ETH_ALEN];
1025
1026 struct lan743x_phy phy;
1027 struct lan743x_tx tx[PCI11X1X_USED_TX_CHANNELS];
1028 struct lan743x_rx rx[LAN743X_USED_RX_CHANNELS];
1029 bool is_pci11x1x;
1030 bool is_sgmii_en;
1031 /* protect ethernet syslock */
1032 spinlock_t eth_syslock_spinlock;
1033 bool eth_syslock_en;
1034 u32 eth_syslock_acquire_cnt;
1035 struct mutex sgmii_rw_lock;
1036 /* SGMII Link Speed & Duplex status */
1037 enum lan743x_sgmii_lsd sgmii_lsd;
1038 u8 max_tx_channels;
1039 u8 used_tx_channels;
1040 u8 max_vector_count;
1041
1042#define LAN743X_ADAPTER_FLAG_OTP BIT(0)
1043 u32 flags;
1044 u32 hw_cfg;
1045};
1046
1047#define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel))
1048
1049#define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index)
1050#define INTR_FLAG_MSI_ENABLED BIT(8)
1051#define INTR_FLAG_MSIX_ENABLED BIT(9)
1052
1053#define MAC_MII_READ 1
1054#define MAC_MII_WRITE 0
1055
1056#define PHY_FLAG_OPENED BIT(0)
1057#define PHY_FLAG_ATTACHED BIT(1)
1058
1059#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1060#define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF))
1061#else
1062#define DMA_ADDR_HIGH32(dma_addr) ((u32)(0))
1063#endif
1064#define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF))
1065#define DMA_DESCRIPTOR_SPACING_16 (16)
1066#define DMA_DESCRIPTOR_SPACING_32 (32)
1067#define DMA_DESCRIPTOR_SPACING_64 (64)
1068#define DMA_DESCRIPTOR_SPACING_128 (128)
1069#define DEFAULT_DMA_DESCRIPTOR_SPACING (L1_CACHE_BYTES)
1070
1071#define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \
1072 (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0))
1073#define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0)
1074#define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0)
1075#define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1)
1076#define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1)
1077
1078/* TX Descriptor bits */
1079#define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000)
1080#define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000)
1081#define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000)
1082#define TX_DESC_DATA0_FS_ (0x20000000)
1083#define TX_DESC_DATA0_LS_ (0x10000000)
1084#define TX_DESC_DATA0_EXT_ (0x08000000)
1085#define TX_DESC_DATA0_IOC_ (0x04000000)
1086#define TX_DESC_DATA0_ICE_ (0x00400000)
1087#define TX_DESC_DATA0_IPE_ (0x00200000)
1088#define TX_DESC_DATA0_TPE_ (0x00100000)
1089#define TX_DESC_DATA0_FCS_ (0x00020000)
1090#define TX_DESC_DATA0_TSE_ (0x00010000)
1091#define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF)
1092#define TX_DESC_DATA0_EXT_LSO_ (0x00200000)
1093#define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF)
1094#define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000)
1095
1096struct lan743x_tx_descriptor {
1097 __le32 data0;
1098 __le32 data1;
1099 __le32 data2;
1100 __le32 data3;
1101} __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING);
1102
1103#define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0)
1104#define TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED BIT(1)
1105#define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2)
1106#define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3)
1107struct lan743x_tx_buffer_info {
1108 int flags;
1109 struct sk_buff *skb;
1110 dma_addr_t dma_ptr;
1111 unsigned int buffer_length;
1112};
1113
1114#define LAN743X_TX_RING_SIZE (128)
1115
1116/* OWN bit is set. ie, Descs are owned by RX DMAC */
1117#define RX_DESC_DATA0_OWN_ (0x00008000)
1118/* OWN bit is clear. ie, Descs are owned by host */
1119#define RX_DESC_DATA0_FS_ (0x80000000)
1120#define RX_DESC_DATA0_LS_ (0x40000000)
1121#define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000)
1122#define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0) \
1123 (((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16)
1124#define RX_DESC_DATA0_EXT_ (0x00004000)
1125#define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF)
1126#define RX_DESC_DATA1_STATUS_ICE_ (0x00020000)
1127#define RX_DESC_DATA1_STATUS_TCE_ (0x00010000)
1128#define RX_DESC_DATA1_STATUS_ICSM_ (0x00000001)
1129#define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF)
1130
1131#if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2))
1132#error NET_IP_ALIGN must be 0 or 2
1133#endif
1134
1135#define RX_HEAD_PADDING NET_IP_ALIGN
1136
1137struct lan743x_rx_descriptor {
1138 __le32 data0;
1139 __le32 data1;
1140 __le32 data2;
1141 __le32 data3;
1142} __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING);
1143
1144#define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0)
1145struct lan743x_rx_buffer_info {
1146 int flags;
1147 struct sk_buff *skb;
1148
1149 dma_addr_t dma_ptr;
1150 unsigned int buffer_length;
1151};
1152
1153#define LAN743X_RX_RING_SIZE (128)
1154
1155#define RX_PROCESS_RESULT_NOTHING_TO_DO (0)
1156#define RX_PROCESS_RESULT_BUFFER_RECEIVED (1)
1157
1158u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset);
1159void lan743x_csr_write(struct lan743x_adapter *adapter, int offset, u32 data);
1160int lan743x_hs_syslock_acquire(struct lan743x_adapter *adapter, u16 timeout);
1161void lan743x_hs_syslock_release(struct lan743x_adapter *adapter);
1162void lan743x_mac_flow_ctrl_set_enables(struct lan743x_adapter *adapter,
1163 bool tx_enable, bool rx_enable);
1164int lan743x_sgmii_read(struct lan743x_adapter *adapter, u8 mmd, u16 addr);
1165
1166#endif /* _LAN743X_H */